1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 * 29 * Copyright (c) 2011 The FreeBSD Foundation 30 * All rights reserved. 31 * 32 * This software was developed by Konstantin Belousov under sponsorship from 33 * the FreeBSD Foundation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/mplock2.h> 58 59 #include <linux/i2c.h> 60 #include <linux/export.h> 61 #include <drm/drmP.h> 62 #include "intel_drv.h" 63 #include <drm/i915_drm.h> 64 #include "i915_drv.h" 65 66 #include <bus/iicbus/iic.h> 67 #include <bus/iicbus/iiconf.h> 68 #include <bus/iicbus/iicbus.h> 69 #include "iicbus_if.h" 70 #include "iicbb_if.h" 71 72 enum disp_clk { 73 CDCLK, 74 CZCLK 75 }; 76 77 struct gmbus_port { 78 const char *name; 79 int reg; 80 }; 81 82 static const struct gmbus_port gmbus_ports[] = { 83 { "ssc", GPIOB }, 84 { "vga", GPIOA }, 85 { "panel", GPIOC }, 86 { "dpc", GPIOD }, 87 { "dpb", GPIOE }, 88 { "dpd", GPIOF }, 89 }; 90 91 /* Intel GPIO access functions */ 92 93 #define I2C_RISEFALL_TIME 10 94 95 static int get_disp_clk_div(struct drm_i915_private *dev_priv, 96 enum disp_clk clk) 97 { 98 u32 reg_val; 99 int clk_ratio; 100 101 reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO); 102 103 if (clk == CDCLK) 104 clk_ratio = 105 ((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1; 106 else 107 clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1; 108 109 return clk_ratio; 110 } 111 112 static void gmbus_set_freq(struct drm_i915_private *dev_priv) 113 { 114 int vco, gmbus_freq = 0, cdclk_div; 115 116 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); 117 118 vco = valleyview_get_vco(dev_priv); 119 120 /* Get the CDCLK divide ratio */ 121 cdclk_div = get_disp_clk_div(dev_priv, CDCLK); 122 123 /* 124 * Program the gmbus_freq based on the cdclk frequency. 125 * BSpec erroneously claims we should aim for 4MHz, but 126 * in fact 1MHz is the correct frequency. 127 */ 128 if (cdclk_div) 129 gmbus_freq = (vco << 1) / cdclk_div; 130 131 if (WARN_ON(gmbus_freq == 0)) 132 return; 133 134 I915_WRITE(GMBUSFREQ_VLV, gmbus_freq); 135 } 136 137 void 138 intel_i2c_reset(struct drm_device *dev) 139 { 140 struct drm_i915_private *dev_priv = dev->dev_private; 141 142 /* 143 * In BIOS-less system, program the correct gmbus frequency 144 * before reading edid. 145 */ 146 if (IS_VALLEYVIEW(dev)) 147 gmbus_set_freq(dev_priv); 148 149 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); 150 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); 151 } 152 153 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) 154 { 155 u32 val; 156 157 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 158 if (!IS_PINEVIEW(dev_priv->dev)) 159 return; 160 161 val = I915_READ(DSPCLK_GATE_D); 162 if (enable) 163 val |= DPCUNIT_CLOCK_GATE_DISABLE; 164 else 165 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 166 I915_WRITE(DSPCLK_GATE_D, val); 167 } 168 169 static u32 get_reserved(device_t idev) 170 { 171 struct intel_iic_softc *sc = device_get_softc(idev); 172 struct drm_device *dev = sc->drm_dev; 173 struct drm_i915_private *dev_priv; 174 u32 reserved = 0; 175 176 dev_priv = dev->dev_private; 177 178 /* On most chips, these bits must be preserved in software. */ 179 if (!IS_I830(dev) && !IS_845G(dev)) 180 reserved = I915_READ_NOTRACE(sc->reg) & 181 (GPIO_DATA_PULLUP_DISABLE | 182 GPIO_CLOCK_PULLUP_DISABLE); 183 184 return reserved; 185 } 186 187 static int get_clock(device_t idev) 188 { 189 struct intel_iic_softc *sc; 190 struct drm_i915_private *dev_priv; 191 u32 reserved; 192 193 sc = device_get_softc(idev); 194 dev_priv = sc->drm_dev->dev_private; 195 196 reserved = get_reserved(idev); 197 198 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK); 199 I915_WRITE_NOTRACE(sc->reg, reserved); 200 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0); 201 } 202 203 static int get_data(device_t idev) 204 { 205 struct intel_iic_softc *sc; 206 struct drm_i915_private *dev_priv; 207 u32 reserved; 208 209 sc = device_get_softc(idev); 210 dev_priv = sc->drm_dev->dev_private; 211 212 reserved = get_reserved(idev); 213 214 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK); 215 I915_WRITE_NOTRACE(sc->reg, reserved); 216 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0); 217 } 218 219 static int 220 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr) 221 { 222 struct intel_iic_softc *sc; 223 struct drm_device *dev; 224 225 sc = device_get_softc(idev); 226 dev = sc->drm_dev; 227 228 intel_i2c_reset(dev); 229 return (0); 230 } 231 232 static void set_clock(device_t idev, int val) 233 { 234 struct intel_iic_softc *sc; 235 struct drm_i915_private *dev_priv; 236 u32 clock_bits, reserved; 237 238 sc = device_get_softc(idev); 239 dev_priv = sc->drm_dev->dev_private; 240 241 reserved = get_reserved(idev); 242 if (val) 243 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 244 else 245 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 246 GPIO_CLOCK_VAL_MASK; 247 248 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits); 249 POSTING_READ(sc->reg); 250 } 251 252 static void set_data(device_t idev, int val) 253 { 254 struct intel_iic_softc *sc; 255 struct drm_i915_private *dev_priv; 256 u32 reserved; 257 u32 data_bits; 258 259 sc = device_get_softc(idev); 260 dev_priv = sc->drm_dev->dev_private; 261 262 reserved = get_reserved(idev); 263 264 if (val) 265 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 266 else 267 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 268 GPIO_DATA_VAL_MASK; 269 270 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits); 271 POSTING_READ(sc->reg); 272 } 273 274 static const char *gpio_names[GMBUS_NUM_PORTS] = { 275 "ssc", 276 "vga", 277 "panel", 278 "dpc", 279 "dpb", 280 "dpd", 281 }; 282 283 static int 284 intel_gpio_setup(device_t idev) 285 { 286 static const int map_pin_to_reg[] = { 287 0, 288 GPIOB, 289 GPIOA, 290 GPIOC, 291 GPIOD, 292 GPIOE, 293 GPIOF, 294 0 295 }; 296 297 struct intel_iic_softc *sc; 298 struct drm_i915_private *dev_priv; 299 int pin; 300 301 sc = device_get_softc(idev); 302 sc->drm_dev = device_get_softc(device_get_parent(idev)); 303 dev_priv = sc->drm_dev->dev_private; 304 pin = device_get_unit(idev); 305 306 ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]); 307 device_set_desc(idev, sc->name); 308 309 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 310 sc->reg = dev_priv->gpio_mmio_base + map_pin_to_reg[pin + 1]; 311 312 /* add generic bit-banging code */ 313 sc->iic_dev = device_add_child(idev, "iicbb", -1); 314 if (sc->iic_dev == NULL) 315 return (ENXIO); 316 device_quiet(sc->iic_dev); 317 bus_generic_attach(idev); 318 319 return (0); 320 } 321 322 static int 323 intel_i2c_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs) 324 { 325 device_t bridge_dev; 326 struct intel_iic_softc *sc; 327 struct drm_i915_private *dev_priv; 328 int ret; 329 int i; 330 331 bridge_dev = device_get_parent(device_get_parent(idev)); 332 sc = device_get_softc(bridge_dev); 333 dev_priv = sc->drm_dev->dev_private; 334 335 intel_i2c_reset(sc->drm_dev); 336 intel_i2c_quirk_set(dev_priv, true); 337 IICBB_SETSDA(bridge_dev, 1); 338 IICBB_SETSCL(bridge_dev, 1); 339 DELAY(I2C_RISEFALL_TIME); 340 341 for (i = 0; i < nmsgs - 1; i++) { 342 /* force use of repeated start instead of default stop+start */ 343 msgs[i].flags |= IIC_M_NOSTOP; 344 } 345 ret = iicbus_transfer(idev, msgs, nmsgs); 346 IICBB_SETSDA(bridge_dev, 1); 347 IICBB_SETSCL(bridge_dev, 1); 348 intel_i2c_quirk_set(dev_priv, false); 349 350 return (ret); 351 } 352 353 static int 354 gmbus_wait_hw_status(struct drm_i915_private *dev_priv, 355 u32 gmbus2_status, 356 u32 gmbus4_irq_en) 357 { 358 int i; 359 int reg_offset = dev_priv->gpio_mmio_base; 360 u32 gmbus2 = 0; 361 DEFINE_WAIT(wait); 362 363 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 364 gmbus4_irq_en = 0; 365 366 /* Important: The hw handles only the first bit, so set only one! Since 367 * we also need to check for NAKs besides the hw ready/idle signal, we 368 * need to wake up periodically and check that ourselves. */ 369 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); 370 371 for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { 372 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, 373 TASK_UNINTERRUPTIBLE); 374 375 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); 376 if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) 377 break; 378 379 schedule_timeout(1); 380 } 381 finish_wait(&dev_priv->gmbus_wait_queue, &wait); 382 383 I915_WRITE(GMBUS4 + reg_offset, 0); 384 385 if (gmbus2 & GMBUS_SATOER) 386 return -ENXIO; 387 if (gmbus2 & gmbus2_status) 388 return 0; 389 return -ETIMEDOUT; 390 } 391 392 static int 393 gmbus_wait_idle(struct drm_i915_private *dev_priv) 394 { 395 int ret; 396 int reg_offset = dev_priv->gpio_mmio_base; 397 398 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) 399 400 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 401 return wait_for(C, 10); 402 403 /* Important: The hw handles only the first bit, so set only one! */ 404 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); 405 406 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 407 msecs_to_jiffies_timeout(10)); 408 409 I915_WRITE(GMBUS4 + reg_offset, 0); 410 411 if (ret) 412 return 0; 413 else 414 return -ETIMEDOUT; 415 #undef C 416 } 417 418 static int 419 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 420 u32 gmbus1_index) 421 { 422 int reg_offset = dev_priv->gpio_mmio_base; 423 u16 len = msg->len; 424 u8 *buf = msg->buf; 425 426 I915_WRITE(GMBUS1 + reg_offset, 427 gmbus1_index | 428 GMBUS_CYCLE_WAIT | 429 (len << GMBUS_BYTE_COUNT_SHIFT) | 430 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 431 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 432 while (len) { 433 int ret; 434 u32 val, loop = 0; 435 436 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 437 GMBUS_HW_RDY_EN); 438 if (ret) 439 return ret; 440 441 val = I915_READ(GMBUS3 + reg_offset); 442 do { 443 *buf++ = val & 0xff; 444 val >>= 8; 445 } while (--len && ++loop < 4); 446 } 447 448 return 0; 449 } 450 451 static int 452 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) 453 { 454 int reg_offset = dev_priv->gpio_mmio_base; 455 u16 len = msg->len; 456 u8 *buf = msg->buf; 457 u32 val, loop; 458 459 val = loop = 0; 460 while (len && loop < 4) { 461 val |= *buf++ << (8 * loop++); 462 len -= 1; 463 } 464 465 I915_WRITE(GMBUS3 + reg_offset, val); 466 I915_WRITE(GMBUS1 + reg_offset, 467 GMBUS_CYCLE_WAIT | 468 (msg->len << GMBUS_BYTE_COUNT_SHIFT) | 469 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 470 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 471 while (len) { 472 int ret; 473 474 val = loop = 0; 475 do { 476 val |= *buf++ << (8 * loop); 477 } while (--len && ++loop < 4); 478 479 I915_WRITE(GMBUS3 + reg_offset, val); 480 481 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 482 GMBUS_HW_RDY_EN); 483 if (ret) 484 return ret; 485 } 486 return 0; 487 } 488 489 /* 490 * The gmbus controller can combine a 1 or 2 byte write with a read that 491 * immediately follows it by using an "INDEX" cycle. 492 */ 493 static bool 494 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) 495 { 496 return (i + 1 < num && 497 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && 498 (msgs[i + 1].flags & I2C_M_RD)); 499 } 500 501 static int 502 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) 503 { 504 int reg_offset = dev_priv->gpio_mmio_base; 505 u32 gmbus1_index = 0; 506 u32 gmbus5 = 0; 507 int ret; 508 509 if (msgs[0].len == 2) 510 gmbus5 = GMBUS_2BYTE_INDEX_EN | 511 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 512 if (msgs[0].len == 1) 513 gmbus1_index = GMBUS_CYCLE_INDEX | 514 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 515 516 /* GMBUS5 holds 16-bit index */ 517 if (gmbus5) 518 I915_WRITE(GMBUS5 + reg_offset, gmbus5); 519 520 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); 521 522 /* Clear GMBUS5 after each index transfer */ 523 if (gmbus5) 524 I915_WRITE(GMBUS5 + reg_offset, 0); 525 526 return ret; 527 } 528 529 static int 530 gmbus_xfer(struct device *adapter, 531 struct i2c_msg *msgs, 532 int num) 533 { 534 struct intel_iic_softc *sc; 535 struct drm_i915_private *dev_priv; 536 int i, reg_offset, unit; 537 int ret = 0; 538 539 sc = device_get_softc(adapter); 540 dev_priv = sc->drm_dev->dev_private; 541 unit = device_get_unit(adapter); 542 543 mutex_lock(&dev_priv->gmbus_mutex); 544 545 if (sc->force_bit_dev) { 546 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 547 goto out; 548 } 549 550 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; 551 552 I915_WRITE(GMBUS0 + reg_offset, sc->reg0); 553 554 for (i = 0; i < num; i++) { 555 if (gmbus_is_index_read(msgs, i, num)) { 556 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); 557 i += 1; /* set i to the index of the read xfer */ 558 } else if (msgs[i].flags & I2C_M_RD) { 559 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); 560 } else { 561 ret = gmbus_xfer_write(dev_priv, &msgs[i]); 562 } 563 564 if (ret == -ETIMEDOUT) 565 goto timeout; 566 if (ret == -ENXIO) 567 goto clear_err; 568 569 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, 570 GMBUS_HW_WAIT_EN); 571 if (ret == -ENXIO) 572 goto clear_err; 573 if (ret) 574 goto timeout; 575 } 576 577 /* Generate a STOP condition on the bus. Note that gmbus can't generata 578 * a STOP on the very first cycle. To simplify the code we 579 * unconditionally generate the STOP condition with an additional gmbus 580 * cycle. */ 581 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 582 583 /* Mark the GMBUS interface as disabled after waiting for idle. 584 * We will re-enable it at the start of the next xfer, 585 * till then let it sleep. 586 */ 587 if (gmbus_wait_idle(dev_priv)) { 588 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 589 sc->name); 590 ret = -ETIMEDOUT; 591 } 592 I915_WRITE(GMBUS0 + reg_offset, 0); 593 ret = ret ?: i; 594 goto timeout; /* XXX: should be out */ 595 596 clear_err: 597 /* 598 * Wait for bus to IDLE before clearing NAK. 599 * If we clear the NAK while bus is still active, then it will stay 600 * active and the next transaction may fail. 601 * 602 * If no ACK is received during the address phase of a transaction, the 603 * adapter must report -ENXIO. It is not clear what to return if no ACK 604 * is received at other times. But we have to be careful to not return 605 * spurious -ENXIO because that will prevent i2c and drm edid functions 606 * from retrying. So return -ENXIO only when gmbus properly quiescents - 607 * timing out seems to happen when there _is_ a ddc chip present, but 608 * it's slow responding and only answers on the 2nd retry. 609 */ 610 ret = -ENXIO; 611 if (gmbus_wait_idle(dev_priv)) { 612 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 613 sc->name); 614 ret = -ETIMEDOUT; 615 } 616 617 /* Toggle the Software Clear Interrupt bit. This has the effect 618 * of resetting the GMBUS controller and so clearing the 619 * BUS_ERROR raised by the slave's NAK. 620 */ 621 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); 622 I915_WRITE(GMBUS1 + reg_offset, 0); 623 I915_WRITE(GMBUS0 + reg_offset, 0); 624 625 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 626 sc->name, msgs[i].slave, 627 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 628 629 goto out; 630 631 timeout: 632 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 633 sc->name, sc->reg0 & 0xff); 634 I915_WRITE(GMBUS0 + reg_offset, 0); 635 636 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ 637 sc->force_bit_dev = true; 638 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 639 640 out: 641 mutex_unlock(&dev_priv->gmbus_mutex); 642 return ret; 643 } 644 645 struct device *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 646 unsigned port) 647 { 648 WARN_ON(!intel_gmbus_is_port_valid(port)); 649 /* -1 to map pin pair to gmbus index */ 650 return (intel_gmbus_is_port_valid(port)) ? 651 dev_priv->gmbus[port-1] : NULL; 652 } 653 654 void 655 intel_gmbus_set_speed(device_t idev, int speed) 656 { 657 struct intel_iic_softc *sc; 658 659 sc = device_get_softc(device_get_parent(idev)); 660 661 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed; 662 } 663 664 void 665 intel_gmbus_force_bit(device_t idev, bool force_bit) 666 { 667 struct intel_iic_softc *sc; 668 669 sc = device_get_softc(device_get_parent(idev)); 670 sc->force_bit_dev += force_bit ? 1 : -1; 671 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 672 force_bit ? "en" : "dis", sc->name, 673 sc->force_bit_dev); 674 } 675 676 static int 677 intel_gmbus_probe(device_t dev) 678 { 679 680 return (BUS_PROBE_SPECIFIC); 681 } 682 683 static int 684 intel_gmbus_attach(device_t idev) 685 { 686 struct drm_i915_private *dev_priv; 687 struct intel_iic_softc *sc; 688 int pin; 689 690 sc = device_get_softc(idev); 691 sc->drm_dev = device_get_softc(device_get_parent(idev)); 692 dev_priv = sc->drm_dev->dev_private; 693 pin = device_get_unit(idev); 694 695 ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]); 696 device_set_desc(idev, sc->name); 697 698 /* By default use a conservative clock rate */ 699 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 700 701 /* XXX force bit banging until GMBUS is fully debugged */ 702 if (IS_GEN2(sc->drm_dev)) { 703 sc->force_bit_dev = true; 704 } 705 706 /* add bus interface device */ 707 sc->iic_dev = device_add_child(idev, "iicbus", -1); 708 if (sc->iic_dev == NULL) 709 return (ENXIO); 710 device_quiet(sc->iic_dev); 711 bus_generic_attach(idev); 712 713 return (0); 714 } 715 716 static int 717 intel_gmbus_detach(device_t idev) 718 { 719 struct intel_iic_softc *sc; 720 struct drm_i915_private *dev_priv; 721 device_t child; 722 int u; 723 724 sc = device_get_softc(idev); 725 u = device_get_unit(idev); 726 dev_priv = sc->drm_dev->dev_private; 727 728 child = sc->iic_dev; 729 bus_generic_detach(idev); 730 if (child != NULL) 731 device_delete_child(idev, child); 732 733 return (0); 734 } 735 736 static int 737 intel_iicbb_probe(device_t dev) 738 { 739 740 return (BUS_PROBE_DEFAULT); 741 } 742 743 static int 744 intel_iicbb_detach(device_t idev) 745 { 746 struct intel_iic_softc *sc; 747 device_t child; 748 749 sc = device_get_softc(idev); 750 child = sc->iic_dev; 751 bus_generic_detach(idev); 752 if (child) 753 device_delete_child(idev, child); 754 return (0); 755 } 756 757 static device_method_t intel_gmbus_methods[] = { 758 DEVMETHOD(device_probe, intel_gmbus_probe), 759 DEVMETHOD(device_attach, intel_gmbus_attach), 760 DEVMETHOD(device_detach, intel_gmbus_detach), 761 DEVMETHOD(iicbus_reset, intel_iicbus_reset), 762 DEVMETHOD(iicbus_transfer, gmbus_xfer), 763 DEVMETHOD_END 764 }; 765 static driver_t intel_gmbus_driver = { 766 "intel_gmbus", 767 intel_gmbus_methods, 768 sizeof(struct intel_iic_softc) 769 }; 770 static devclass_t intel_gmbus_devclass; 771 DRIVER_MODULE_ORDERED(intel_gmbus, drm, intel_gmbus_driver, 772 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST); 773 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, NULL, NULL); 774 775 static device_method_t intel_iicbb_methods[] = { 776 DEVMETHOD(device_probe, intel_iicbb_probe), 777 DEVMETHOD(device_attach, intel_gpio_setup), 778 DEVMETHOD(device_detach, intel_iicbb_detach), 779 780 DEVMETHOD(bus_add_child, bus_generic_add_child), 781 DEVMETHOD(bus_print_child, bus_generic_print_child), 782 783 DEVMETHOD(iicbb_callback, iicbus_null_callback), 784 DEVMETHOD(iicbb_reset, intel_iicbus_reset), 785 DEVMETHOD(iicbb_setsda, set_data), 786 DEVMETHOD(iicbb_setscl, set_clock), 787 DEVMETHOD(iicbb_getsda, get_data), 788 DEVMETHOD(iicbb_getscl, get_clock), 789 DEVMETHOD_END 790 }; 791 static driver_t intel_iicbb_driver = { 792 "intel_iicbb", 793 intel_iicbb_methods, 794 sizeof(struct intel_iic_softc) 795 }; 796 static devclass_t intel_iicbb_devclass; 797 DRIVER_MODULE_ORDERED(intel_iicbb, drm, intel_iicbb_driver, 798 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST); 799 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, NULL, NULL); 800 801 static void intel_teardown_gmbus_m(struct drm_device *dev, int m); 802 803 int 804 intel_setup_gmbus(struct drm_device *dev) 805 { 806 struct drm_i915_private *dev_priv = dev->dev_private; 807 device_t iic_dev; 808 int i, ret; 809 810 if (HAS_PCH_NOP(dev)) 811 return 0; 812 else if (HAS_PCH_SPLIT(dev)) 813 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; 814 else if (IS_VALLEYVIEW(dev)) 815 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 816 else 817 dev_priv->gpio_mmio_base = 0; 818 819 lockinit(&dev_priv->gmbus_mutex, "gmbus", 0, LK_CANRECURSE); 820 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 821 822 dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 823 M_DRM, M_WAITOK | M_ZERO); 824 dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 825 M_DRM, M_WAITOK | M_ZERO); 826 dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 827 M_DRM, M_WAITOK | M_ZERO); 828 dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 829 M_DRM, M_WAITOK | M_ZERO); 830 831 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 832 /* 833 * Initialized bbbus_bridge before gmbus_bridge, since 834 * gmbus may decide to force quirk transfer in the 835 * attachment code. 836 */ 837 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev, 838 "intel_iicbb", i); 839 if (dev_priv->bbbus_bridge[i] == NULL) { 840 DRM_ERROR("bbbus bridge %d creation failed\n", i); 841 ret = ENXIO; 842 goto err; 843 } 844 device_quiet(dev_priv->bbbus_bridge[i]); 845 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]); 846 if (ret != 0) { 847 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i, 848 ret); 849 goto err; 850 } 851 852 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb", 853 -1); 854 if (iic_dev == NULL) { 855 DRM_ERROR("bbbus bridge doesn't have iicbb child\n"); 856 goto err; 857 } 858 iic_dev = device_find_child(iic_dev, "iicbus", -1); 859 if (iic_dev == NULL) { 860 DRM_ERROR( 861 "bbbus bridge doesn't have iicbus grandchild\n"); 862 goto err; 863 } 864 865 dev_priv->bbbus[i] = iic_dev; 866 867 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev, 868 "intel_gmbus", i); 869 if (dev_priv->gmbus_bridge[i] == NULL) { 870 DRM_ERROR("gmbus bridge %d creation failed\n", i); 871 ret = ENXIO; 872 goto err; 873 } 874 device_quiet(dev_priv->gmbus_bridge[i]); 875 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]); 876 if (ret != 0) { 877 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i, 878 ret); 879 ret = ENXIO; 880 goto err; 881 } 882 883 iic_dev = device_find_child(dev_priv->gmbus_bridge[i], 884 "iicbus", -1); 885 if (iic_dev == NULL) { 886 DRM_ERROR("gmbus bridge doesn't have iicbus child\n"); 887 goto err; 888 } 889 dev_priv->gmbus[i] = iic_dev; 890 891 intel_i2c_reset(dev); 892 } 893 894 return (0); 895 896 err: 897 intel_teardown_gmbus_m(dev, i); 898 return (ret); 899 } 900 901 static void 902 intel_teardown_gmbus_m(struct drm_device *dev, int m) 903 { 904 struct drm_i915_private *dev_priv; 905 906 dev_priv = dev->dev_private; 907 908 drm_free(dev_priv->gmbus, M_DRM); 909 dev_priv->gmbus = NULL; 910 drm_free(dev_priv->bbbus, M_DRM); 911 dev_priv->bbbus = NULL; 912 drm_free(dev_priv->gmbus_bridge, M_DRM); 913 dev_priv->gmbus_bridge = NULL; 914 drm_free(dev_priv->bbbus_bridge, M_DRM); 915 dev_priv->bbbus_bridge = NULL; 916 lockuninit(&dev_priv->gmbus_mutex); 917 } 918 919 void 920 intel_teardown_gmbus(struct drm_device *dev) 921 { 922 923 get_mplock(); 924 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS); 925 rel_mplock(); 926 } 927