1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 #include <linux/i2c.h> 30 #include <linux/i2c-algo-bit.h> 31 #include <linux/export.h> 32 #include <drm/drmP.h> 33 #include "intel_drv.h" 34 #include <drm/i915_drm.h> 35 #include "i915_drv.h" 36 37 struct gmbus_pin { 38 const char *name; 39 i915_reg_t reg; 40 }; 41 42 /* Map gmbus pin pairs to names and registers. */ 43 static const struct gmbus_pin gmbus_pins[] = { 44 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 45 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 46 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 47 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 48 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 49 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 50 }; 51 52 static const struct gmbus_pin gmbus_pins_bdw[] = { 53 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 54 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 55 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 56 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 57 }; 58 59 static const struct gmbus_pin gmbus_pins_skl[] = { 60 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 61 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 62 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 63 }; 64 65 static const struct gmbus_pin gmbus_pins_bxt[] = { 66 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 67 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 68 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 69 }; 70 71 /* pin is expected to be valid */ 72 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, 73 unsigned int pin) 74 { 75 if (IS_BROXTON(dev_priv)) 76 return &gmbus_pins_bxt[pin]; 77 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 78 return &gmbus_pins_skl[pin]; 79 else if (IS_BROADWELL(dev_priv)) 80 return &gmbus_pins_bdw[pin]; 81 else 82 return &gmbus_pins[pin]; 83 } 84 85 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 86 unsigned int pin) 87 { 88 unsigned int size; 89 90 if (IS_BROXTON(dev_priv)) 91 size = ARRAY_SIZE(gmbus_pins_bxt); 92 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 93 size = ARRAY_SIZE(gmbus_pins_skl); 94 else if (IS_BROADWELL(dev_priv)) 95 size = ARRAY_SIZE(gmbus_pins_bdw); 96 else 97 size = ARRAY_SIZE(gmbus_pins); 98 99 return pin < size && 100 i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); 101 } 102 103 /* Intel GPIO access functions */ 104 105 #define I2C_RISEFALL_TIME 10 106 107 static inline struct intel_gmbus * 108 to_intel_gmbus(struct i2c_adapter *i2c) 109 { 110 return container_of(i2c, struct intel_gmbus, adapter); 111 } 112 113 void 114 intel_i2c_reset(struct drm_device *dev) 115 { 116 struct drm_i915_private *dev_priv = to_i915(dev); 117 118 I915_WRITE(GMBUS0, 0); 119 I915_WRITE(GMBUS4, 0); 120 } 121 122 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) 123 { 124 u32 val; 125 126 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 127 if (!IS_PINEVIEW(dev_priv)) 128 return; 129 130 val = I915_READ(DSPCLK_GATE_D); 131 if (enable) 132 val |= DPCUNIT_CLOCK_GATE_DISABLE; 133 else 134 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 135 I915_WRITE(DSPCLK_GATE_D, val); 136 } 137 138 static u32 get_reserved(struct intel_gmbus *bus) 139 { 140 struct drm_i915_private *dev_priv = bus->dev_priv; 141 u32 reserved = 0; 142 143 /* On most chips, these bits must be preserved in software. */ 144 if (!IS_I830(dev_priv) && !IS_845G(dev_priv)) 145 reserved = I915_READ_NOTRACE(bus->gpio_reg) & 146 (GPIO_DATA_PULLUP_DISABLE | 147 GPIO_CLOCK_PULLUP_DISABLE); 148 149 return reserved; 150 } 151 152 static int get_clock(void *data) 153 { 154 struct intel_gmbus *bus = data; 155 struct drm_i915_private *dev_priv = bus->dev_priv; 156 u32 reserved = get_reserved(bus); 157 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 158 I915_WRITE_NOTRACE(bus->gpio_reg, reserved); 159 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 160 } 161 162 static int get_data(void *data) 163 { 164 struct intel_gmbus *bus = data; 165 struct drm_i915_private *dev_priv = bus->dev_priv; 166 u32 reserved = get_reserved(bus); 167 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 168 I915_WRITE_NOTRACE(bus->gpio_reg, reserved); 169 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 170 } 171 172 static void set_clock(void *data, int state_high) 173 { 174 struct intel_gmbus *bus = data; 175 struct drm_i915_private *dev_priv = bus->dev_priv; 176 u32 reserved = get_reserved(bus); 177 u32 clock_bits; 178 179 if (state_high) 180 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 181 else 182 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 183 GPIO_CLOCK_VAL_MASK; 184 185 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); 186 POSTING_READ(bus->gpio_reg); 187 } 188 189 static void set_data(void *data, int state_high) 190 { 191 struct intel_gmbus *bus = data; 192 struct drm_i915_private *dev_priv = bus->dev_priv; 193 u32 reserved = get_reserved(bus); 194 u32 data_bits; 195 196 if (state_high) 197 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 198 else 199 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 200 GPIO_DATA_VAL_MASK; 201 202 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); 203 POSTING_READ(bus->gpio_reg); 204 } 205 206 static int 207 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 208 { 209 struct intel_gmbus *bus = container_of(adapter, 210 struct intel_gmbus, 211 adapter); 212 struct drm_i915_private *dev_priv = bus->dev_priv; 213 214 intel_i2c_reset(&dev_priv->drm); 215 intel_i2c_quirk_set(dev_priv, true); 216 set_data(bus, 1); 217 set_clock(bus, 1); 218 udelay(I2C_RISEFALL_TIME); 219 return 0; 220 } 221 222 static void 223 intel_gpio_post_xfer(struct i2c_adapter *adapter) 224 { 225 struct intel_gmbus *bus = container_of(adapter, 226 struct intel_gmbus, 227 adapter); 228 struct drm_i915_private *dev_priv = bus->dev_priv; 229 230 set_data(bus, 1); 231 set_clock(bus, 1); 232 intel_i2c_quirk_set(dev_priv, false); 233 } 234 235 static void 236 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) 237 { 238 struct drm_i915_private *dev_priv = bus->dev_priv; 239 struct i2c_algo_bit_data *algo; 240 241 algo = &bus->bit_algo; 242 243 bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + 244 i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); 245 bus->adapter.algo_data = algo; 246 algo->setsda = set_data; 247 algo->setscl = set_clock; 248 algo->getsda = get_data; 249 algo->getscl = get_clock; 250 algo->pre_xfer = intel_gpio_pre_xfer; 251 algo->post_xfer = intel_gpio_post_xfer; 252 algo->udelay = I2C_RISEFALL_TIME; 253 algo->timeout = usecs_to_jiffies(2200); 254 algo->data = bus; 255 } 256 257 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 258 { 259 DEFINE_WAIT(wait); 260 u32 gmbus2; 261 int ret; 262 263 /* Important: The hw handles only the first bit, so set only one! Since 264 * we also need to check for NAKs besides the hw ready/idle signal, we 265 * need to wake up periodically and check that ourselves. 266 */ 267 if (!HAS_GMBUS_IRQ(dev_priv)) 268 irq_en = 0; 269 270 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 271 I915_WRITE_FW(GMBUS4, irq_en); 272 273 status |= GMBUS_SATOER; 274 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); 275 if (ret) 276 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); 277 278 I915_WRITE_FW(GMBUS4, 0); 279 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 280 281 if (gmbus2 & GMBUS_SATOER) 282 return -ENXIO; 283 284 return ret; 285 } 286 287 static int 288 gmbus_wait_idle(struct drm_i915_private *dev_priv) 289 { 290 DEFINE_WAIT(wait); 291 u32 irq_enable; 292 int ret; 293 294 /* Important: The hw handles only the first bit, so set only one! */ 295 irq_enable = 0; 296 if (HAS_GMBUS_IRQ(dev_priv)) 297 irq_enable = GMBUS_IDLE_EN; 298 299 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 300 I915_WRITE_FW(GMBUS4, irq_enable); 301 302 ret = intel_wait_for_register_fw(dev_priv, 303 GMBUS2, GMBUS_ACTIVE, 0, 304 10); 305 306 I915_WRITE_FW(GMBUS4, 0); 307 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 308 309 return ret; 310 } 311 312 static int 313 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 314 unsigned short addr, u8 *buf, unsigned int len, 315 u32 gmbus1_index) 316 { 317 I915_WRITE_FW(GMBUS1, 318 gmbus1_index | 319 GMBUS_CYCLE_WAIT | 320 (len << GMBUS_BYTE_COUNT_SHIFT) | 321 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 322 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 323 while (len) { 324 int ret; 325 u32 val, loop = 0; 326 327 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 328 if (ret) 329 return ret; 330 331 val = I915_READ_FW(GMBUS3); 332 do { 333 *buf++ = val & 0xff; 334 val >>= 8; 335 } while (--len && ++loop < 4); 336 } 337 338 return 0; 339 } 340 341 static int 342 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 343 u32 gmbus1_index) 344 { 345 u8 *buf = msg->buf; 346 unsigned int rx_size = msg->len; 347 unsigned int len; 348 int ret; 349 350 do { 351 len = min(rx_size, GMBUS_BYTE_COUNT_MAX); 352 353 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, 354 buf, len, gmbus1_index); 355 if (ret) 356 return ret; 357 358 rx_size -= len; 359 buf += len; 360 } while (rx_size != 0); 361 362 return 0; 363 } 364 365 static int 366 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 367 unsigned short addr, u8 *buf, unsigned int len) 368 { 369 unsigned int chunk_size = len; 370 u32 val, loop; 371 372 val = loop = 0; 373 while (len && loop < 4) { 374 val |= *buf++ << (8 * loop++); 375 len -= 1; 376 } 377 378 I915_WRITE_FW(GMBUS3, val); 379 I915_WRITE_FW(GMBUS1, 380 GMBUS_CYCLE_WAIT | 381 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | 382 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 383 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 384 while (len) { 385 int ret; 386 387 val = loop = 0; 388 do { 389 val |= *buf++ << (8 * loop); 390 } while (--len && ++loop < 4); 391 392 I915_WRITE_FW(GMBUS3, val); 393 394 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 395 if (ret) 396 return ret; 397 } 398 399 return 0; 400 } 401 402 static int 403 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) 404 { 405 u8 *buf = msg->buf; 406 unsigned int tx_size = msg->len; 407 unsigned int len; 408 int ret; 409 410 do { 411 len = min(tx_size, GMBUS_BYTE_COUNT_MAX); 412 413 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); 414 if (ret) 415 return ret; 416 417 buf += len; 418 tx_size -= len; 419 } while (tx_size != 0); 420 421 return 0; 422 } 423 424 /* 425 * The gmbus controller can combine a 1 or 2 byte write with a read that 426 * immediately follows it by using an "INDEX" cycle. 427 */ 428 static bool 429 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) 430 { 431 return (i + 1 < num && 432 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && 433 (msgs[i + 1].flags & I2C_M_RD)); 434 } 435 436 static int 437 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) 438 { 439 u32 gmbus1_index = 0; 440 u32 gmbus5 = 0; 441 int ret; 442 443 if (msgs[0].len == 2) 444 gmbus5 = GMBUS_2BYTE_INDEX_EN | 445 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 446 if (msgs[0].len == 1) 447 gmbus1_index = GMBUS_CYCLE_INDEX | 448 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 449 450 /* GMBUS5 holds 16-bit index */ 451 if (gmbus5) 452 I915_WRITE_FW(GMBUS5, gmbus5); 453 454 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); 455 456 /* Clear GMBUS5 after each index transfer */ 457 if (gmbus5) 458 I915_WRITE_FW(GMBUS5, 0); 459 460 return ret; 461 } 462 463 static int 464 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 465 { 466 struct intel_gmbus *bus = container_of(adapter, 467 struct intel_gmbus, 468 adapter); 469 struct drm_i915_private *dev_priv = bus->dev_priv; 470 int i = 0, inc, try = 0; 471 int ret = 0; 472 473 retry: 474 I915_WRITE_FW(GMBUS0, bus->reg0); 475 476 for (; i < num; i += inc) { 477 inc = 1; 478 if (gmbus_is_index_read(msgs, i, num)) { 479 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); 480 inc = 2; /* an index read is two msgs */ 481 } else if (msgs[i].flags & I2C_M_RD) { 482 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); 483 } else { 484 ret = gmbus_xfer_write(dev_priv, &msgs[i]); 485 } 486 487 if (!ret) 488 ret = gmbus_wait(dev_priv, 489 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 490 if (ret == -ETIMEDOUT) 491 goto timeout; 492 else if (ret) 493 goto clear_err; 494 } 495 496 /* Generate a STOP condition on the bus. Note that gmbus can't generata 497 * a STOP on the very first cycle. To simplify the code we 498 * unconditionally generate the STOP condition with an additional gmbus 499 * cycle. */ 500 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 501 502 /* Mark the GMBUS interface as disabled after waiting for idle. 503 * We will re-enable it at the start of the next xfer, 504 * till then let it sleep. 505 */ 506 if (gmbus_wait_idle(dev_priv)) { 507 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 508 adapter->name); 509 ret = -ETIMEDOUT; 510 } 511 I915_WRITE_FW(GMBUS0, 0); 512 ret = ret ?: i; 513 goto out; 514 515 clear_err: 516 /* 517 * Wait for bus to IDLE before clearing NAK. 518 * If we clear the NAK while bus is still active, then it will stay 519 * active and the next transaction may fail. 520 * 521 * If no ACK is received during the address phase of a transaction, the 522 * adapter must report -ENXIO. It is not clear what to return if no ACK 523 * is received at other times. But we have to be careful to not return 524 * spurious -ENXIO because that will prevent i2c and drm edid functions 525 * from retrying. So return -ENXIO only when gmbus properly quiescents - 526 * timing out seems to happen when there _is_ a ddc chip present, but 527 * it's slow responding and only answers on the 2nd retry. 528 */ 529 ret = -ENXIO; 530 if (gmbus_wait_idle(dev_priv)) { 531 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 532 adapter->name); 533 ret = -ETIMEDOUT; 534 } 535 536 /* Toggle the Software Clear Interrupt bit. This has the effect 537 * of resetting the GMBUS controller and so clearing the 538 * BUS_ERROR raised by the slave's NAK. 539 */ 540 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); 541 I915_WRITE_FW(GMBUS1, 0); 542 I915_WRITE_FW(GMBUS0, 0); 543 544 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 545 adapter->name, msgs[i].addr, 546 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 547 548 /* 549 * Passive adapters sometimes NAK the first probe. Retry the first 550 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 551 * has retries internally. See also the retry loop in 552 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 553 */ 554 if (ret == -ENXIO && i == 0 && try++ == 0) { 555 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", 556 adapter->name); 557 goto retry; 558 } 559 560 goto out; 561 562 timeout: 563 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 564 bus->adapter.name, bus->reg0 & 0xff); 565 I915_WRITE_FW(GMBUS0, 0); 566 567 /* 568 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 569 * instead. Use EAGAIN to have i2c core retry. 570 */ 571 ret = -EAGAIN; 572 573 out: 574 return ret; 575 } 576 577 static int 578 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 579 { 580 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus, 581 adapter); 582 struct drm_i915_private *dev_priv = bus->dev_priv; 583 int ret; 584 585 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 586 mutex_lock(&dev_priv->gmbus_mutex); 587 588 if (bus->force_bit) { 589 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 590 if (ret < 0) 591 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 592 } else { 593 ret = do_gmbus_xfer(adapter, msgs, num); 594 if (ret == -EAGAIN) 595 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 596 } 597 598 mutex_unlock(&dev_priv->gmbus_mutex); 599 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); 600 601 return ret; 602 } 603 604 static u32 gmbus_func(struct i2c_adapter *adapter) 605 { 606 return i2c_bit_algo.functionality(adapter) & 607 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 608 /* I2C_FUNC_10BIT_ADDR | */ 609 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 610 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 611 } 612 613 static const struct i2c_algorithm gmbus_algorithm = { 614 .master_xfer = gmbus_xfer, 615 .functionality = gmbus_func 616 }; 617 618 /** 619 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 620 * @dev: DRM device 621 */ 622 int intel_setup_gmbus(struct drm_device *dev) 623 { 624 struct drm_i915_private *dev_priv = to_i915(dev); 625 struct pci_dev *pdev = dev_priv->drm.pdev; 626 struct intel_gmbus *bus; 627 unsigned int pin; 628 int ret; 629 630 if (HAS_PCH_NOP(dev_priv)) 631 return 0; 632 633 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 634 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 635 else if (!HAS_GMCH_DISPLAY(dev_priv)) 636 dev_priv->gpio_mmio_base = 637 i915_mmio_reg_offset(PCH_GPIOA) - 638 i915_mmio_reg_offset(GPIOA); 639 640 lockinit(&dev_priv->gmbus_mutex, "gmbus", 0, LK_CANRECURSE); 641 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 642 643 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 644 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 645 continue; 646 647 bus = &dev_priv->gmbus[pin]; 648 649 #if 0 650 bus->adapter.owner = THIS_MODULE; 651 bus->adapter.class = I2C_CLASS_DDC; 652 #endif 653 ksnprintf(bus->adapter.name, 654 sizeof(bus->adapter.name), 655 "i915 gmbus %s", 656 get_gmbus_pin(dev_priv, pin)->name); 657 658 bus->adapter.dev.parent = &pdev->dev; 659 bus->dev_priv = dev_priv; 660 661 bus->adapter.algo = &gmbus_algorithm; 662 663 /* 664 * We wish to retry with bit banging 665 * after a timed out GMBUS attempt. 666 */ 667 bus->adapter.retries = 1; 668 669 /* By default use a conservative clock rate */ 670 bus->reg0 = pin | GMBUS_RATE_100KHZ; 671 672 /* gmbus seems to be broken on i830 */ 673 if (IS_I830(dev_priv)) 674 bus->force_bit = 1; 675 676 intel_gpio_setup(bus, pin); 677 678 ret = i2c_add_adapter(&bus->adapter); 679 if (ret) 680 goto err; 681 } 682 683 intel_i2c_reset(&dev_priv->drm); 684 685 return 0; 686 687 err: 688 while (pin--) { 689 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 690 continue; 691 692 bus = &dev_priv->gmbus[pin]; 693 i2c_del_adapter(&bus->adapter); 694 } 695 return ret; 696 } 697 698 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 699 unsigned int pin) 700 { 701 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) 702 return NULL; 703 704 return &dev_priv->gmbus[pin].adapter; 705 } 706 707 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) 708 { 709 struct intel_gmbus *bus = to_intel_gmbus(adapter); 710 711 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 712 } 713 714 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 715 { 716 struct intel_gmbus *bus = to_intel_gmbus(adapter); 717 struct drm_i915_private *dev_priv = bus->dev_priv; 718 719 mutex_lock(&dev_priv->gmbus_mutex); 720 721 bus->force_bit += force_bit ? 1 : -1; 722 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 723 force_bit ? "en" : "dis", adapter->name, 724 bus->force_bit); 725 726 mutex_unlock(&dev_priv->gmbus_mutex); 727 } 728 729 void intel_teardown_gmbus(struct drm_device *dev) 730 { 731 struct drm_i915_private *dev_priv = to_i915(dev); 732 struct intel_gmbus *bus; 733 unsigned int pin; 734 735 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 736 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 737 continue; 738 739 bus = &dev_priv->gmbus[pin]; 740 i2c_del_adapter(&bus->adapter); 741 } 742 } 743