1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 * 29 * Copyright (c) 2011 The FreeBSD Foundation 30 * All rights reserved. 31 * 32 * This software was developed by Konstantin Belousov under sponsorship from 33 * the FreeBSD Foundation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 */ 56 57 #include <sys/mplock2.h> 58 59 #include <linux/i2c.h> 60 #include <linux/export.h> 61 #include <drm/drmP.h> 62 #include "intel_drv.h" 63 #include <drm/i915_drm.h> 64 #include "i915_drv.h" 65 66 #include <bus/iicbus/iic.h> 67 #include <bus/iicbus/iiconf.h> 68 #include <bus/iicbus/iicbus.h> 69 #include "iicbus_if.h" 70 #include "iicbb_if.h" 71 72 enum disp_clk { 73 CDCLK, 74 CZCLK 75 }; 76 77 struct gmbus_port { 78 const char *name; 79 int reg; 80 }; 81 82 static const struct gmbus_port gmbus_ports[] = { 83 { "ssc", GPIOB }, 84 { "vga", GPIOA }, 85 { "panel", GPIOC }, 86 { "dpc", GPIOD }, 87 { "dpb", GPIOE }, 88 { "dpd", GPIOF }, 89 }; 90 91 /* Intel GPIO access functions */ 92 93 #define I2C_RISEFALL_TIME 10 94 95 static int get_disp_clk_div(struct drm_i915_private *dev_priv, 96 enum disp_clk clk) 97 { 98 u32 reg_val; 99 int clk_ratio; 100 101 reg_val = I915_READ(CZCLK_CDCLK_FREQ_RATIO); 102 103 if (clk == CDCLK) 104 clk_ratio = 105 ((reg_val & CDCLK_FREQ_MASK) >> CDCLK_FREQ_SHIFT) + 1; 106 else 107 clk_ratio = (reg_val & CZCLK_FREQ_MASK) + 1; 108 109 return clk_ratio; 110 } 111 112 static void gmbus_set_freq(struct drm_i915_private *dev_priv) 113 { 114 int vco, gmbus_freq = 0, cdclk_div; 115 116 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); 117 118 vco = valleyview_get_vco(dev_priv); 119 120 /* Get the CDCLK divide ratio */ 121 cdclk_div = get_disp_clk_div(dev_priv, CDCLK); 122 123 /* 124 * Program the gmbus_freq based on the cdclk frequency. 125 * BSpec erroneously claims we should aim for 4MHz, but 126 * in fact 1MHz is the correct frequency. 127 */ 128 if (cdclk_div) 129 gmbus_freq = (vco << 1) / cdclk_div; 130 131 if (WARN_ON(gmbus_freq == 0)) 132 return; 133 134 I915_WRITE(GMBUSFREQ_VLV, gmbus_freq); 135 } 136 137 void 138 intel_i2c_reset(struct drm_device *dev) 139 { 140 struct drm_i915_private *dev_priv = dev->dev_private; 141 142 /* 143 * In BIOS-less system, program the correct gmbus frequency 144 * before reading edid. 145 */ 146 if (IS_VALLEYVIEW(dev)) 147 gmbus_set_freq(dev_priv); 148 149 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); 150 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); 151 } 152 153 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) 154 { 155 u32 val; 156 157 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 158 if (!IS_PINEVIEW(dev_priv->dev)) 159 return; 160 161 val = I915_READ(DSPCLK_GATE_D); 162 if (enable) 163 val |= DPCUNIT_CLOCK_GATE_DISABLE; 164 else 165 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 166 I915_WRITE(DSPCLK_GATE_D, val); 167 } 168 169 static u32 get_reserved(device_t idev) 170 { 171 struct intel_iic_softc *sc = device_get_softc(idev); 172 struct drm_device *dev = sc->drm_dev; 173 struct drm_i915_private *dev_priv; 174 u32 reserved = 0; 175 176 dev_priv = dev->dev_private; 177 178 /* On most chips, these bits must be preserved in software. */ 179 if (!IS_I830(dev) && !IS_845G(dev)) 180 reserved = I915_READ_NOTRACE(sc->reg) & 181 (GPIO_DATA_PULLUP_DISABLE | 182 GPIO_CLOCK_PULLUP_DISABLE); 183 184 return reserved; 185 } 186 187 static int get_clock(device_t idev) 188 { 189 struct intel_iic_softc *sc; 190 struct drm_i915_private *dev_priv; 191 u32 reserved; 192 193 sc = device_get_softc(idev); 194 dev_priv = sc->drm_dev->dev_private; 195 196 reserved = get_reserved(idev); 197 198 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK); 199 I915_WRITE_NOTRACE(sc->reg, reserved); 200 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0); 201 } 202 203 static int get_data(device_t idev) 204 { 205 struct intel_iic_softc *sc; 206 struct drm_i915_private *dev_priv; 207 u32 reserved; 208 209 sc = device_get_softc(idev); 210 dev_priv = sc->drm_dev->dev_private; 211 212 reserved = get_reserved(idev); 213 214 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK); 215 I915_WRITE_NOTRACE(sc->reg, reserved); 216 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0); 217 } 218 219 static int 220 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr) 221 { 222 struct intel_iic_softc *sc; 223 struct drm_device *dev; 224 225 sc = device_get_softc(idev); 226 dev = sc->drm_dev; 227 228 intel_i2c_reset(dev); 229 return (0); 230 } 231 232 static void set_clock(device_t idev, int val) 233 { 234 struct intel_iic_softc *sc; 235 struct drm_i915_private *dev_priv; 236 u32 clock_bits, reserved; 237 238 sc = device_get_softc(idev); 239 dev_priv = sc->drm_dev->dev_private; 240 241 reserved = get_reserved(idev); 242 if (val) 243 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 244 else 245 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 246 GPIO_CLOCK_VAL_MASK; 247 248 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits); 249 POSTING_READ(sc->reg); 250 } 251 252 static void set_data(device_t idev, int val) 253 { 254 struct intel_iic_softc *sc; 255 struct drm_i915_private *dev_priv; 256 u32 reserved; 257 u32 data_bits; 258 259 sc = device_get_softc(idev); 260 dev_priv = sc->drm_dev->dev_private; 261 262 reserved = get_reserved(idev); 263 if (val) 264 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 265 else 266 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 267 GPIO_DATA_VAL_MASK; 268 269 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits); 270 POSTING_READ(sc->reg); 271 } 272 273 static const char *gpio_names[GMBUS_NUM_PORTS] = { 274 "ssc", 275 "vga", 276 "panel", 277 "dpc", 278 "dpb", 279 "dpd", 280 }; 281 282 static int 283 intel_gpio_setup(device_t idev) 284 { 285 static const int map_pin_to_reg[] = { 286 0, 287 GPIOB, 288 GPIOA, 289 GPIOC, 290 GPIOD, 291 GPIOE, 292 GPIOF, 293 0 294 }; 295 296 struct intel_iic_softc *sc; 297 struct drm_i915_private *dev_priv; 298 int pin; 299 300 sc = device_get_softc(idev); 301 sc->drm_dev = device_get_softc(device_get_parent(idev)); 302 dev_priv = sc->drm_dev->dev_private; 303 pin = device_get_unit(idev); 304 305 ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]); 306 device_set_desc(idev, sc->name); 307 308 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 309 sc->reg = map_pin_to_reg[pin + 1]; 310 if (HAS_PCH_SPLIT(dev_priv->dev)) 311 sc->reg += PCH_GPIOA - GPIOA; 312 313 /* add generic bit-banging code */ 314 sc->iic_dev = device_add_child(idev, "iicbb", -1); 315 if (sc->iic_dev == NULL) 316 return (ENXIO); 317 device_quiet(sc->iic_dev); 318 bus_generic_attach(idev); 319 320 return (0); 321 } 322 323 static int 324 intel_i2c_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs) 325 { 326 device_t bridge_dev; 327 struct intel_iic_softc *sc; 328 struct drm_i915_private *dev_priv; 329 int ret; 330 int i; 331 332 bridge_dev = device_get_parent(device_get_parent(idev)); 333 sc = device_get_softc(bridge_dev); 334 dev_priv = sc->drm_dev->dev_private; 335 336 intel_i2c_reset(sc->drm_dev); 337 intel_i2c_quirk_set(dev_priv, true); 338 IICBB_SETSDA(bridge_dev, 1); 339 IICBB_SETSCL(bridge_dev, 1); 340 DELAY(I2C_RISEFALL_TIME); 341 342 for (i = 0; i < nmsgs - 1; i++) { 343 /* force use of repeated start instead of default stop+start */ 344 msgs[i].flags |= IIC_M_NOSTOP; 345 } 346 ret = iicbus_transfer(idev, msgs, nmsgs); 347 IICBB_SETSDA(bridge_dev, 1); 348 IICBB_SETSCL(bridge_dev, 1); 349 intel_i2c_quirk_set(dev_priv, false); 350 351 return (ret); 352 } 353 354 static int 355 gmbus_wait_hw_status(struct drm_i915_private *dev_priv, 356 u32 gmbus2_status, 357 u32 gmbus4_irq_en) 358 { 359 int i; 360 int reg_offset = dev_priv->gpio_mmio_base; 361 u32 gmbus2 = 0; 362 DEFINE_WAIT(wait); 363 364 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 365 gmbus4_irq_en = 0; 366 367 /* Important: The hw handles only the first bit, so set only one! Since 368 * we also need to check for NAKs besides the hw ready/idle signal, we 369 * need to wake up periodically and check that ourselves. */ 370 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); 371 372 for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { 373 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, 374 TASK_UNINTERRUPTIBLE); 375 376 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); 377 if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) 378 break; 379 380 schedule_timeout(1); 381 } 382 finish_wait(&dev_priv->gmbus_wait_queue, &wait); 383 384 I915_WRITE(GMBUS4 + reg_offset, 0); 385 386 if (gmbus2 & GMBUS_SATOER) 387 return -ENXIO; 388 if (gmbus2 & gmbus2_status) 389 return 0; 390 return -ETIMEDOUT; 391 } 392 393 static int 394 gmbus_wait_idle(struct drm_i915_private *dev_priv) 395 { 396 int ret; 397 int reg_offset = dev_priv->gpio_mmio_base; 398 399 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) 400 401 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 402 return wait_for(C, 10); 403 404 /* Important: The hw handles only the first bit, so set only one! */ 405 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); 406 407 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 408 msecs_to_jiffies_timeout(10)); 409 410 I915_WRITE(GMBUS4 + reg_offset, 0); 411 412 if (ret) 413 return 0; 414 else 415 return -ETIMEDOUT; 416 #undef C 417 } 418 419 static int 420 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 421 u32 gmbus1_index) 422 { 423 int reg_offset = dev_priv->gpio_mmio_base; 424 u16 len = msg->len; 425 u8 *buf = msg->buf; 426 427 I915_WRITE(GMBUS1 + reg_offset, 428 gmbus1_index | 429 GMBUS_CYCLE_WAIT | 430 (len << GMBUS_BYTE_COUNT_SHIFT) | 431 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 432 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 433 while (len) { 434 int ret; 435 u32 val, loop = 0; 436 437 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 438 GMBUS_HW_RDY_EN); 439 if (ret) 440 return ret; 441 442 val = I915_READ(GMBUS3 + reg_offset); 443 do { 444 *buf++ = val & 0xff; 445 val >>= 8; 446 } while (--len && ++loop < 4); 447 } 448 449 return 0; 450 } 451 452 static int 453 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) 454 { 455 int reg_offset = dev_priv->gpio_mmio_base; 456 u16 len = msg->len; 457 u8 *buf = msg->buf; 458 u32 val, loop; 459 460 val = loop = 0; 461 while (len && loop < 4) { 462 val |= *buf++ << (8 * loop++); 463 len -= 1; 464 } 465 466 I915_WRITE(GMBUS3 + reg_offset, val); 467 I915_WRITE(GMBUS1 + reg_offset, 468 GMBUS_CYCLE_WAIT | 469 (msg->len << GMBUS_BYTE_COUNT_SHIFT) | 470 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 471 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 472 while (len) { 473 int ret; 474 475 val = loop = 0; 476 do { 477 val |= *buf++ << (8 * loop); 478 } while (--len && ++loop < 4); 479 480 I915_WRITE(GMBUS3 + reg_offset, val); 481 482 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 483 GMBUS_HW_RDY_EN); 484 if (ret) 485 return ret; 486 } 487 return 0; 488 } 489 490 /* 491 * The gmbus controller can combine a 1 or 2 byte write with a read that 492 * immediately follows it by using an "INDEX" cycle. 493 */ 494 static bool 495 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) 496 { 497 return (i + 1 < num && 498 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && 499 (msgs[i + 1].flags & I2C_M_RD)); 500 } 501 502 static int 503 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) 504 { 505 int reg_offset = dev_priv->gpio_mmio_base; 506 u32 gmbus1_index = 0; 507 u32 gmbus5 = 0; 508 int ret; 509 510 if (msgs[0].len == 2) 511 gmbus5 = GMBUS_2BYTE_INDEX_EN | 512 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 513 if (msgs[0].len == 1) 514 gmbus1_index = GMBUS_CYCLE_INDEX | 515 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 516 517 /* GMBUS5 holds 16-bit index */ 518 if (gmbus5) 519 I915_WRITE(GMBUS5 + reg_offset, gmbus5); 520 521 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); 522 523 /* Clear GMBUS5 after each index transfer */ 524 if (gmbus5) 525 I915_WRITE(GMBUS5 + reg_offset, 0); 526 527 return ret; 528 } 529 530 static int 531 gmbus_xfer(struct device *adapter, 532 struct i2c_msg *msgs, 533 int num) 534 { 535 struct intel_iic_softc *sc; 536 struct drm_i915_private *dev_priv; 537 int i, reg_offset, unit; 538 int ret = 0; 539 540 sc = device_get_softc(adapter); 541 dev_priv = sc->drm_dev->dev_private; 542 unit = device_get_unit(adapter); 543 544 mutex_lock(&dev_priv->gmbus_mutex); 545 546 if (sc->force_bit_dev) { 547 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 548 goto out; 549 } 550 551 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; 552 553 I915_WRITE(GMBUS0 + reg_offset, sc->reg0); 554 555 for (i = 0; i < num; i++) { 556 if (gmbus_is_index_read(msgs, i, num)) { 557 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); 558 i += 1; /* set i to the index of the read xfer */ 559 } else if (msgs[i].flags & I2C_M_RD) { 560 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); 561 } else { 562 ret = gmbus_xfer_write(dev_priv, &msgs[i]); 563 } 564 565 if (ret == -ETIMEDOUT) 566 goto timeout; 567 if (ret == -ENXIO) 568 goto clear_err; 569 570 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, 571 GMBUS_HW_WAIT_EN); 572 if (ret == -ENXIO) 573 goto clear_err; 574 if (ret) 575 goto timeout; 576 } 577 578 /* Generate a STOP condition on the bus. Note that gmbus can't generata 579 * a STOP on the very first cycle. To simplify the code we 580 * unconditionally generate the STOP condition with an additional gmbus 581 * cycle. */ 582 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 583 584 /* Mark the GMBUS interface as disabled after waiting for idle. 585 * We will re-enable it at the start of the next xfer, 586 * till then let it sleep. 587 */ 588 if (gmbus_wait_idle(dev_priv)) { 589 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 590 sc->name); 591 ret = -ETIMEDOUT; 592 } 593 I915_WRITE(GMBUS0 + reg_offset, 0); 594 ret = ret ?: i; 595 goto timeout; /* XXX: should be out */ 596 597 clear_err: 598 /* 599 * Wait for bus to IDLE before clearing NAK. 600 * If we clear the NAK while bus is still active, then it will stay 601 * active and the next transaction may fail. 602 * 603 * If no ACK is received during the address phase of a transaction, the 604 * adapter must report -ENXIO. It is not clear what to return if no ACK 605 * is received at other times. But we have to be careful to not return 606 * spurious -ENXIO because that will prevent i2c and drm edid functions 607 * from retrying. So return -ENXIO only when gmbus properly quiescents - 608 * timing out seems to happen when there _is_ a ddc chip present, but 609 * it's slow responding and only answers on the 2nd retry. 610 */ 611 ret = -ENXIO; 612 if (gmbus_wait_idle(dev_priv)) { 613 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 614 sc->name); 615 ret = -ETIMEDOUT; 616 } 617 618 /* Toggle the Software Clear Interrupt bit. This has the effect 619 * of resetting the GMBUS controller and so clearing the 620 * BUS_ERROR raised by the slave's NAK. 621 */ 622 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); 623 I915_WRITE(GMBUS1 + reg_offset, 0); 624 I915_WRITE(GMBUS0 + reg_offset, 0); 625 626 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 627 sc->name, msgs[i].slave, 628 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 629 630 goto out; 631 632 timeout: 633 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 634 sc->name, sc->reg0 & 0xff); 635 I915_WRITE(GMBUS0 + reg_offset, 0); 636 637 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ 638 sc->force_bit_dev = true; 639 ret = intel_i2c_quirk_xfer(dev_priv->bbbus[unit], msgs, num); 640 641 out: 642 mutex_unlock(&dev_priv->gmbus_mutex); 643 return ret; 644 } 645 646 struct device *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 647 unsigned port) 648 { 649 WARN_ON(!intel_gmbus_is_port_valid(port)); 650 /* -1 to map pin pair to gmbus index */ 651 return (intel_gmbus_is_port_valid(port)) ? 652 dev_priv->gmbus[port-1] : NULL; 653 } 654 655 void 656 intel_gmbus_set_speed(device_t idev, int speed) 657 { 658 struct intel_iic_softc *sc; 659 660 sc = device_get_softc(device_get_parent(idev)); 661 662 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed; 663 } 664 665 void 666 intel_gmbus_force_bit(device_t idev, bool force_bit) 667 { 668 struct intel_iic_softc *sc; 669 670 sc = device_get_softc(device_get_parent(idev)); 671 sc->force_bit_dev += force_bit ? 1 : -1; 672 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 673 force_bit ? "en" : "dis", sc->name, 674 sc->force_bit_dev); 675 } 676 677 static int 678 intel_gmbus_probe(device_t dev) 679 { 680 681 return (BUS_PROBE_SPECIFIC); 682 } 683 684 static int 685 intel_gmbus_attach(device_t idev) 686 { 687 struct drm_i915_private *dev_priv; 688 struct intel_iic_softc *sc; 689 int pin; 690 691 sc = device_get_softc(idev); 692 sc->drm_dev = device_get_softc(device_get_parent(idev)); 693 dev_priv = sc->drm_dev->dev_private; 694 pin = device_get_unit(idev); 695 696 ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]); 697 device_set_desc(idev, sc->name); 698 699 /* By default use a conservative clock rate */ 700 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 701 702 /* XXX force bit banging until GMBUS is fully debugged */ 703 if (IS_GEN2(sc->drm_dev)) { 704 sc->force_bit_dev = true; 705 } 706 707 /* add bus interface device */ 708 sc->iic_dev = device_add_child(idev, "iicbus", -1); 709 if (sc->iic_dev == NULL) 710 return (ENXIO); 711 device_quiet(sc->iic_dev); 712 bus_generic_attach(idev); 713 714 return (0); 715 } 716 717 static int 718 intel_gmbus_detach(device_t idev) 719 { 720 struct intel_iic_softc *sc; 721 struct drm_i915_private *dev_priv; 722 device_t child; 723 int u; 724 725 sc = device_get_softc(idev); 726 u = device_get_unit(idev); 727 dev_priv = sc->drm_dev->dev_private; 728 729 child = sc->iic_dev; 730 bus_generic_detach(idev); 731 if (child != NULL) 732 device_delete_child(idev, child); 733 734 return (0); 735 } 736 737 static int 738 intel_iicbb_probe(device_t dev) 739 { 740 741 return (BUS_PROBE_DEFAULT); 742 } 743 744 static int 745 intel_iicbb_detach(device_t idev) 746 { 747 struct intel_iic_softc *sc; 748 device_t child; 749 750 sc = device_get_softc(idev); 751 child = sc->iic_dev; 752 bus_generic_detach(idev); 753 if (child) 754 device_delete_child(idev, child); 755 return (0); 756 } 757 758 static device_method_t intel_gmbus_methods[] = { 759 DEVMETHOD(device_probe, intel_gmbus_probe), 760 DEVMETHOD(device_attach, intel_gmbus_attach), 761 DEVMETHOD(device_detach, intel_gmbus_detach), 762 DEVMETHOD(iicbus_reset, intel_iicbus_reset), 763 DEVMETHOD(iicbus_transfer, gmbus_xfer), 764 DEVMETHOD_END 765 }; 766 static driver_t intel_gmbus_driver = { 767 "intel_gmbus", 768 intel_gmbus_methods, 769 sizeof(struct intel_iic_softc) 770 }; 771 static devclass_t intel_gmbus_devclass; 772 DRIVER_MODULE_ORDERED(intel_gmbus, drm, intel_gmbus_driver, 773 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST); 774 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, NULL, NULL); 775 776 static device_method_t intel_iicbb_methods[] = { 777 DEVMETHOD(device_probe, intel_iicbb_probe), 778 DEVMETHOD(device_attach, intel_gpio_setup), 779 DEVMETHOD(device_detach, intel_iicbb_detach), 780 781 DEVMETHOD(bus_add_child, bus_generic_add_child), 782 DEVMETHOD(bus_print_child, bus_generic_print_child), 783 784 DEVMETHOD(iicbb_callback, iicbus_null_callback), 785 DEVMETHOD(iicbb_reset, intel_iicbus_reset), 786 DEVMETHOD(iicbb_setsda, set_data), 787 DEVMETHOD(iicbb_setscl, set_clock), 788 DEVMETHOD(iicbb_getsda, get_data), 789 DEVMETHOD(iicbb_getscl, get_clock), 790 DEVMETHOD_END 791 }; 792 static driver_t intel_iicbb_driver = { 793 "intel_iicbb", 794 intel_iicbb_methods, 795 sizeof(struct intel_iic_softc) 796 }; 797 static devclass_t intel_iicbb_devclass; 798 DRIVER_MODULE_ORDERED(intel_iicbb, drm, intel_iicbb_driver, 799 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST); 800 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, NULL, NULL); 801 802 static void intel_teardown_gmbus_m(struct drm_device *dev, int m); 803 804 int 805 intel_setup_gmbus(struct drm_device *dev) 806 { 807 struct drm_i915_private *dev_priv = dev->dev_private; 808 device_t iic_dev; 809 int i, ret; 810 811 if (HAS_PCH_NOP(dev)) 812 return 0; 813 else if (HAS_PCH_SPLIT(dev)) 814 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; 815 else if (IS_VALLEYVIEW(dev)) 816 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 817 else 818 dev_priv->gpio_mmio_base = 0; 819 820 lockinit(&dev_priv->gmbus_mutex, "gmbus", 0, LK_CANRECURSE); 821 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 822 823 dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 824 M_DRM, M_WAITOK | M_ZERO); 825 dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 826 M_DRM, M_WAITOK | M_ZERO); 827 dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 828 M_DRM, M_WAITOK | M_ZERO); 829 dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 830 M_DRM, M_WAITOK | M_ZERO); 831 832 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 833 /* 834 * Initialized bbbus_bridge before gmbus_bridge, since 835 * gmbus may decide to force quirk transfer in the 836 * attachment code. 837 */ 838 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev, 839 "intel_iicbb", i); 840 if (dev_priv->bbbus_bridge[i] == NULL) { 841 DRM_ERROR("bbbus bridge %d creation failed\n", i); 842 ret = ENXIO; 843 goto err; 844 } 845 device_quiet(dev_priv->bbbus_bridge[i]); 846 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]); 847 if (ret != 0) { 848 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i, 849 ret); 850 goto err; 851 } 852 853 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb", 854 -1); 855 if (iic_dev == NULL) { 856 DRM_ERROR("bbbus bridge doesn't have iicbb child\n"); 857 goto err; 858 } 859 iic_dev = device_find_child(iic_dev, "iicbus", -1); 860 if (iic_dev == NULL) { 861 DRM_ERROR( 862 "bbbus bridge doesn't have iicbus grandchild\n"); 863 goto err; 864 } 865 866 dev_priv->bbbus[i] = iic_dev; 867 868 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev, 869 "intel_gmbus", i); 870 if (dev_priv->gmbus_bridge[i] == NULL) { 871 DRM_ERROR("gmbus bridge %d creation failed\n", i); 872 ret = ENXIO; 873 goto err; 874 } 875 device_quiet(dev_priv->gmbus_bridge[i]); 876 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]); 877 if (ret != 0) { 878 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i, 879 ret); 880 ret = ENXIO; 881 goto err; 882 } 883 884 iic_dev = device_find_child(dev_priv->gmbus_bridge[i], 885 "iicbus", -1); 886 if (iic_dev == NULL) { 887 DRM_ERROR("gmbus bridge doesn't have iicbus child\n"); 888 goto err; 889 } 890 dev_priv->gmbus[i] = iic_dev; 891 892 intel_i2c_reset(dev); 893 } 894 895 return (0); 896 897 err: 898 intel_teardown_gmbus_m(dev, i); 899 return (ret); 900 } 901 902 static void 903 intel_teardown_gmbus_m(struct drm_device *dev, int m) 904 { 905 struct drm_i915_private *dev_priv; 906 907 dev_priv = dev->dev_private; 908 909 drm_free(dev_priv->gmbus, M_DRM); 910 dev_priv->gmbus = NULL; 911 drm_free(dev_priv->bbbus, M_DRM); 912 dev_priv->bbbus = NULL; 913 drm_free(dev_priv->gmbus_bridge, M_DRM); 914 dev_priv->gmbus_bridge = NULL; 915 drm_free(dev_priv->bbbus_bridge, M_DRM); 916 dev_priv->bbbus_bridge = NULL; 917 lockuninit(&dev_priv->gmbus_mutex); 918 } 919 920 void 921 intel_teardown_gmbus(struct drm_device *dev) 922 { 923 924 get_mplock(); 925 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS); 926 rel_mplock(); 927 } 928