1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 * 29 * Copyright (c) 2011 The FreeBSD Foundation 30 * All rights reserved. 31 * 32 * This software was developed by Konstantin Belousov under sponsorship from 33 * the FreeBSD Foundation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 * 56 * $FreeBSD: head/sys/dev/drm2/i915/intel_iic.c 249041 2013-04-03 08:27:35Z dumbbell $ 57 */ 58 59 #include <sys/mplock2.h> 60 61 #include <drm/drmP.h> 62 #include <drm/i915_drm.h> 63 #include "i915_drv.h" 64 #include "intel_drv.h" 65 #include <bus/iicbus/iic.h> 66 #include <bus/iicbus/iiconf.h> 67 #include <bus/iicbus/iicbus.h> 68 #include "iicbus_if.h" 69 #include "iicbb_if.h" 70 71 static int intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs); 72 static void intel_teardown_gmbus_m(struct drm_device *dev, int m); 73 74 /* Intel GPIO access functions */ 75 76 #define I2C_RISEFALL_TIME 10 77 78 static void 79 intel_iic_quirk_set(struct drm_i915_private *dev_priv, bool enable) 80 { 81 u32 val; 82 83 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 84 if (!IS_PINEVIEW(dev_priv->dev)) 85 return; 86 87 val = I915_READ(DSPCLK_GATE_D); 88 if (enable) 89 val |= DPCUNIT_CLOCK_GATE_DISABLE; 90 else 91 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 92 I915_WRITE(DSPCLK_GATE_D, val); 93 } 94 95 static u32 96 intel_iic_get_reserved(device_t idev) 97 { 98 struct intel_iic_softc *sc; 99 struct drm_device *dev; 100 struct drm_i915_private *dev_priv; 101 u32 reserved; 102 103 sc = device_get_softc(idev); 104 dev = sc->drm_dev; 105 dev_priv = dev->dev_private; 106 107 if (!IS_I830(dev) && !IS_845G(dev)) { 108 reserved = I915_READ_NOTRACE(sc->reg) & 109 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); 110 } else { 111 reserved = 0; 112 } 113 114 return (reserved); 115 } 116 117 void 118 intel_i2c_reset(struct drm_device *dev) 119 { 120 struct drm_i915_private *dev_priv; 121 122 dev_priv = dev->dev_private; 123 if (HAS_PCH_SPLIT(dev)) 124 I915_WRITE(PCH_GMBUS0, 0); 125 else 126 I915_WRITE(GMBUS0, 0); 127 } 128 129 static int 130 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr) 131 { 132 struct intel_iic_softc *sc; 133 struct drm_device *dev; 134 135 sc = device_get_softc(idev); 136 dev = sc->drm_dev; 137 138 intel_i2c_reset(dev); 139 return (0); 140 } 141 142 static void 143 intel_iicbb_setsda(device_t idev, int val) 144 { 145 struct intel_iic_softc *sc; 146 struct drm_i915_private *dev_priv; 147 u32 reserved; 148 u32 data_bits; 149 150 sc = device_get_softc(idev); 151 dev_priv = sc->drm_dev->dev_private; 152 153 reserved = intel_iic_get_reserved(idev); 154 if (val) 155 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 156 else 157 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 158 GPIO_DATA_VAL_MASK; 159 160 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits); 161 POSTING_READ(sc->reg); 162 } 163 164 static void 165 intel_iicbb_setscl(device_t idev, int val) 166 { 167 struct intel_iic_softc *sc; 168 struct drm_i915_private *dev_priv; 169 u32 clock_bits, reserved; 170 171 sc = device_get_softc(idev); 172 dev_priv = sc->drm_dev->dev_private; 173 174 reserved = intel_iic_get_reserved(idev); 175 if (val) 176 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 177 else 178 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 179 GPIO_CLOCK_VAL_MASK; 180 181 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits); 182 POSTING_READ(sc->reg); 183 } 184 185 static int 186 intel_iicbb_getsda(device_t idev) 187 { 188 struct intel_iic_softc *sc; 189 struct drm_i915_private *dev_priv; 190 u32 reserved; 191 192 sc = device_get_softc(idev); 193 dev_priv = sc->drm_dev->dev_private; 194 195 reserved = intel_iic_get_reserved(idev); 196 197 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK); 198 I915_WRITE_NOTRACE(sc->reg, reserved); 199 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0); 200 } 201 202 static int 203 intel_iicbb_getscl(device_t idev) 204 { 205 struct intel_iic_softc *sc; 206 struct drm_i915_private *dev_priv; 207 u32 reserved; 208 209 sc = device_get_softc(idev); 210 dev_priv = sc->drm_dev->dev_private; 211 212 reserved = intel_iic_get_reserved(idev); 213 214 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK); 215 I915_WRITE_NOTRACE(sc->reg, reserved); 216 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0); 217 } 218 219 static int 220 intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs) 221 { 222 struct intel_iic_softc *sc; 223 struct drm_i915_private *dev_priv; 224 u8 *buf; 225 int error, i, reg_offset, unit; 226 u32 val, loop; 227 u16 len; 228 229 sc = device_get_softc(idev); 230 dev_priv = sc->drm_dev->dev_private; 231 unit = device_get_unit(idev); 232 233 lockmgr(&dev_priv->gmbus_mutex, LK_EXCLUSIVE); 234 if (sc->force_bit_dev) { 235 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs); 236 goto out; 237 } 238 239 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; 240 241 I915_WRITE(GMBUS0 + reg_offset, sc->reg0); 242 243 for (i = 0; i < nmsgs; i++) { 244 len = msgs[i].len; 245 buf = msgs[i].buf; 246 247 if ((msgs[i].flags & IIC_M_RD) != 0) { 248 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT | 249 (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) | 250 (len << GMBUS_BYTE_COUNT_SHIFT) | 251 (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 252 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 253 POSTING_READ(GMBUS2 + reg_offset); 254 do { 255 loop = 0; 256 257 if (_intel_wait_for(sc->drm_dev, 258 (I915_READ(GMBUS2 + reg_offset) & 259 (GMBUS_SATOER | GMBUS_HW_RDY)) != 0, 260 50, 1, "915gbr")) 261 goto timeout; 262 if ((I915_READ(GMBUS2 + reg_offset) & 263 GMBUS_SATOER) != 0) 264 goto clear_err; 265 266 val = I915_READ(GMBUS3 + reg_offset); 267 do { 268 *buf++ = val & 0xff; 269 val >>= 8; 270 } while (--len != 0 && ++loop < 4); 271 } while (len != 0); 272 } else { 273 val = loop = 0; 274 do { 275 val |= *buf++ << (8 * loop); 276 } while (--len != 0 && ++loop < 4); 277 278 I915_WRITE(GMBUS3 + reg_offset, val); 279 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT | 280 (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) | 281 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) | 282 (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 283 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 284 POSTING_READ(GMBUS2+reg_offset); 285 286 while (len != 0) { 287 if (_intel_wait_for(sc->drm_dev, 288 (I915_READ(GMBUS2 + reg_offset) & 289 (GMBUS_SATOER | GMBUS_HW_RDY)) != 0, 290 50, 1, "915gbw")) 291 goto timeout; 292 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) 293 goto clear_err; 294 295 val = loop = 0; 296 do { 297 val |= *buf++ << (8 * loop); 298 } while (--len != 0 && ++loop < 4); 299 300 I915_WRITE(GMBUS3 + reg_offset, val); 301 POSTING_READ(GMBUS2 + reg_offset); 302 } 303 } 304 305 if (i + 1 < nmsgs && _intel_wait_for(sc->drm_dev, 306 (I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | 307 GMBUS_HW_WAIT_PHASE)) != 0, 308 50, 1, "915gbh")) 309 goto timeout; 310 if ((I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) != 0) 311 goto clear_err; 312 } 313 314 error = 0; 315 done: 316 /* Mark the GMBUS interface as disabled after waiting for idle. 317 * We will re-enable it at the start of the next xfer, 318 * till then let it sleep. 319 */ 320 if (_intel_wait_for(dev, 321 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 322 10, 1, "915gbu")) 323 DRM_INFO("GMBUS timed out waiting for idle\n"); 324 I915_WRITE(GMBUS0 + reg_offset, 0); 325 out: 326 lockmgr(&dev_priv->gmbus_mutex, LK_RELEASE); 327 return (error); 328 329 clear_err: 330 /* Toggle the Software Clear Interrupt bit. This has the effect 331 * of resetting the GMBUS controller and so clearing the 332 * BUS_ERROR raised by the slave's NAK. 333 */ 334 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); 335 I915_WRITE(GMBUS1 + reg_offset, 0); 336 error = EIO; 337 goto done; 338 339 timeout: 340 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n", 341 sc->reg0 & 0xff, sc->name); 342 I915_WRITE(GMBUS0 + reg_offset, 0); 343 344 /* 345 * Hardware may not support GMBUS over these pins? 346 * Try GPIO bitbanging instead. 347 */ 348 sc->force_bit_dev = true; 349 350 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs); 351 goto out; 352 } 353 354 struct device *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 355 unsigned port) 356 { 357 WARN_ON(!intel_gmbus_is_port_valid(port)); 358 /* -1 to map pin pair to gmbus index */ 359 return (intel_gmbus_is_port_valid(port)) ? 360 dev_priv->gmbus[port-1] : NULL; 361 } 362 363 void 364 intel_gmbus_set_speed(device_t idev, int speed) 365 { 366 struct intel_iic_softc *sc; 367 368 sc = device_get_softc(device_get_parent(idev)); 369 370 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed; 371 } 372 373 void 374 intel_gmbus_force_bit(device_t idev, bool force_bit) 375 { 376 struct intel_iic_softc *sc; 377 378 sc = device_get_softc(device_get_parent(idev)); 379 sc->force_bit_dev = force_bit; 380 } 381 382 static int 383 intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs) 384 { 385 device_t bridge_dev; 386 struct intel_iic_softc *sc; 387 struct drm_i915_private *dev_priv; 388 int ret; 389 int i; 390 391 bridge_dev = device_get_parent(device_get_parent(idev)); 392 sc = device_get_softc(bridge_dev); 393 dev_priv = sc->drm_dev->dev_private; 394 395 intel_i2c_reset(sc->drm_dev); 396 intel_iic_quirk_set(dev_priv, true); 397 IICBB_SETSDA(bridge_dev, 1); 398 IICBB_SETSCL(bridge_dev, 1); 399 DELAY(I2C_RISEFALL_TIME); 400 401 for (i = 0; i < nmsgs - 1; i++) { 402 /* force use of repeated start instead of default stop+start */ 403 msgs[i].flags |= IIC_M_NOSTOP; 404 } 405 ret = iicbus_transfer(idev, msgs, nmsgs); 406 IICBB_SETSDA(bridge_dev, 1); 407 IICBB_SETSCL(bridge_dev, 1); 408 intel_iic_quirk_set(dev_priv, false); 409 410 return (ret); 411 } 412 413 static const char *gpio_names[GMBUS_NUM_PORTS] = { 414 "ssc", 415 "vga", 416 "panel", 417 "dpc", 418 "dpb", 419 "dpd", 420 }; 421 422 static int 423 intel_gmbus_probe(device_t dev) 424 { 425 426 return (BUS_PROBE_SPECIFIC); 427 } 428 429 static int 430 intel_gmbus_attach(device_t idev) 431 { 432 struct drm_i915_private *dev_priv; 433 struct intel_iic_softc *sc; 434 int pin; 435 436 sc = device_get_softc(idev); 437 sc->drm_dev = device_get_softc(device_get_parent(idev)); 438 dev_priv = sc->drm_dev->dev_private; 439 pin = device_get_unit(idev); 440 441 ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]); 442 device_set_desc(idev, sc->name); 443 444 /* By default use a conservative clock rate */ 445 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 446 447 /* XXX force bit banging until GMBUS is fully debugged */ 448 if (IS_GEN2(sc->drm_dev)) { 449 sc->force_bit_dev = true; 450 } 451 452 /* add bus interface device */ 453 sc->iic_dev = device_add_child(idev, "iicbus", -1); 454 if (sc->iic_dev == NULL) 455 return (ENXIO); 456 device_quiet(sc->iic_dev); 457 bus_generic_attach(idev); 458 459 return (0); 460 } 461 462 static int 463 intel_gmbus_detach(device_t idev) 464 { 465 struct intel_iic_softc *sc; 466 struct drm_i915_private *dev_priv; 467 device_t child; 468 int u; 469 470 sc = device_get_softc(idev); 471 u = device_get_unit(idev); 472 dev_priv = sc->drm_dev->dev_private; 473 474 child = sc->iic_dev; 475 bus_generic_detach(idev); 476 if (child != NULL) 477 device_delete_child(idev, child); 478 479 return (0); 480 } 481 482 static int 483 intel_iicbb_probe(device_t dev) 484 { 485 486 return (BUS_PROBE_DEFAULT); 487 } 488 489 static int 490 intel_iicbb_attach(device_t idev) 491 { 492 static const int map_pin_to_reg[] = { 493 0, 494 GPIOB, 495 GPIOA, 496 GPIOC, 497 GPIOD, 498 GPIOE, 499 GPIOF, 500 0 501 }; 502 503 struct intel_iic_softc *sc; 504 struct drm_i915_private *dev_priv; 505 int pin; 506 507 sc = device_get_softc(idev); 508 sc->drm_dev = device_get_softc(device_get_parent(idev)); 509 dev_priv = sc->drm_dev->dev_private; 510 pin = device_get_unit(idev); 511 512 ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]); 513 device_set_desc(idev, sc->name); 514 515 sc->reg0 = (pin + 1) | GMBUS_RATE_100KHZ; 516 sc->reg = map_pin_to_reg[pin + 1]; 517 if (HAS_PCH_SPLIT(dev_priv->dev)) 518 sc->reg += PCH_GPIOA - GPIOA; 519 520 /* add generic bit-banging code */ 521 sc->iic_dev = device_add_child(idev, "iicbb", -1); 522 if (sc->iic_dev == NULL) 523 return (ENXIO); 524 device_quiet(sc->iic_dev); 525 bus_generic_attach(idev); 526 527 return (0); 528 } 529 530 static int 531 intel_iicbb_detach(device_t idev) 532 { 533 struct intel_iic_softc *sc; 534 device_t child; 535 536 sc = device_get_softc(idev); 537 child = sc->iic_dev; 538 bus_generic_detach(idev); 539 if (child) 540 device_delete_child(idev, child); 541 return (0); 542 } 543 544 static device_method_t intel_gmbus_methods[] = { 545 DEVMETHOD(device_probe, intel_gmbus_probe), 546 DEVMETHOD(device_attach, intel_gmbus_attach), 547 DEVMETHOD(device_detach, intel_gmbus_detach), 548 DEVMETHOD(iicbus_reset, intel_iicbus_reset), 549 DEVMETHOD(iicbus_transfer, intel_gmbus_transfer), 550 DEVMETHOD_END 551 }; 552 static driver_t intel_gmbus_driver = { 553 "intel_gmbus", 554 intel_gmbus_methods, 555 sizeof(struct intel_iic_softc) 556 }; 557 static devclass_t intel_gmbus_devclass; 558 DRIVER_MODULE_ORDERED(intel_gmbus, drm, intel_gmbus_driver, 559 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST); 560 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, NULL, NULL); 561 562 static device_method_t intel_iicbb_methods[] = { 563 DEVMETHOD(device_probe, intel_iicbb_probe), 564 DEVMETHOD(device_attach, intel_iicbb_attach), 565 DEVMETHOD(device_detach, intel_iicbb_detach), 566 567 DEVMETHOD(bus_add_child, bus_generic_add_child), 568 DEVMETHOD(bus_print_child, bus_generic_print_child), 569 570 DEVMETHOD(iicbb_callback, iicbus_null_callback), 571 DEVMETHOD(iicbb_reset, intel_iicbus_reset), 572 DEVMETHOD(iicbb_setsda, intel_iicbb_setsda), 573 DEVMETHOD(iicbb_setscl, intel_iicbb_setscl), 574 DEVMETHOD(iicbb_getsda, intel_iicbb_getsda), 575 DEVMETHOD(iicbb_getscl, intel_iicbb_getscl), 576 DEVMETHOD_END 577 }; 578 static driver_t intel_iicbb_driver = { 579 "intel_iicbb", 580 intel_iicbb_methods, 581 sizeof(struct intel_iic_softc) 582 }; 583 static devclass_t intel_iicbb_devclass; 584 DRIVER_MODULE_ORDERED(intel_iicbb, drm, intel_iicbb_driver, 585 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST); 586 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, NULL, NULL); 587 588 int 589 intel_setup_gmbus(struct drm_device *dev) 590 { 591 struct drm_i915_private *dev_priv; 592 device_t iic_dev; 593 int i, ret; 594 595 dev_priv = dev->dev_private; 596 lockinit(&dev_priv->gmbus_mutex, "gmbus", 0, LK_CANRECURSE); 597 dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 598 M_DRM, M_WAITOK | M_ZERO); 599 dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 600 M_DRM, M_WAITOK | M_ZERO); 601 dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 602 M_DRM, M_WAITOK | M_ZERO); 603 dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 604 M_DRM, M_WAITOK | M_ZERO); 605 606 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 607 /* 608 * Initialized bbbus_bridge before gmbus_bridge, since 609 * gmbus may decide to force quirk transfer in the 610 * attachment code. 611 */ 612 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev, 613 "intel_iicbb", i); 614 if (dev_priv->bbbus_bridge[i] == NULL) { 615 DRM_ERROR("bbbus bridge %d creation failed\n", i); 616 ret = ENXIO; 617 goto err; 618 } 619 device_quiet(dev_priv->bbbus_bridge[i]); 620 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]); 621 if (ret != 0) { 622 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i, 623 ret); 624 goto err; 625 } 626 627 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb", 628 -1); 629 if (iic_dev == NULL) { 630 DRM_ERROR("bbbus bridge doesn't have iicbb child\n"); 631 goto err; 632 } 633 iic_dev = device_find_child(iic_dev, "iicbus", -1); 634 if (iic_dev == NULL) { 635 DRM_ERROR( 636 "bbbus bridge doesn't have iicbus grandchild\n"); 637 goto err; 638 } 639 640 dev_priv->bbbus[i] = iic_dev; 641 642 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev, 643 "intel_gmbus", i); 644 if (dev_priv->gmbus_bridge[i] == NULL) { 645 DRM_ERROR("gmbus bridge %d creation failed\n", i); 646 ret = ENXIO; 647 goto err; 648 } 649 device_quiet(dev_priv->gmbus_bridge[i]); 650 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]); 651 if (ret != 0) { 652 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i, 653 ret); 654 ret = ENXIO; 655 goto err; 656 } 657 658 iic_dev = device_find_child(dev_priv->gmbus_bridge[i], 659 "iicbus", -1); 660 if (iic_dev == NULL) { 661 DRM_ERROR("gmbus bridge doesn't have iicbus child\n"); 662 goto err; 663 } 664 dev_priv->gmbus[i] = iic_dev; 665 666 intel_i2c_reset(dev); 667 } 668 669 return (0); 670 671 err: 672 intel_teardown_gmbus_m(dev, i); 673 return (ret); 674 } 675 676 static void 677 intel_teardown_gmbus_m(struct drm_device *dev, int m) 678 { 679 struct drm_i915_private *dev_priv; 680 681 dev_priv = dev->dev_private; 682 683 drm_free(dev_priv->gmbus, M_DRM); 684 dev_priv->gmbus = NULL; 685 drm_free(dev_priv->bbbus, M_DRM); 686 dev_priv->bbbus = NULL; 687 drm_free(dev_priv->gmbus_bridge, M_DRM); 688 dev_priv->gmbus_bridge = NULL; 689 drm_free(dev_priv->bbbus_bridge, M_DRM); 690 dev_priv->bbbus_bridge = NULL; 691 lockuninit(&dev_priv->gmbus_mutex); 692 } 693 694 void 695 intel_teardown_gmbus(struct drm_device *dev) 696 { 697 698 get_mplock(); 699 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS); 700 rel_mplock(); 701 } 702