1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * Michel Thierry <michel.thierry@intel.com> 26 * Thomas Daniel <thomas.daniel@intel.com> 27 * Oscar Mateo <oscar.mateo@intel.com> 28 * 29 */ 30 31 /** 32 * DOC: Logical Rings, Logical Ring Contexts and Execlists 33 * 34 * Motivation: 35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". 36 * These expanded contexts enable a number of new abilities, especially 37 * "Execlists" (also implemented in this file). 38 * 39 * One of the main differences with the legacy HW contexts is that logical 40 * ring contexts incorporate many more things to the context's state, like 41 * PDPs or ringbuffer control registers: 42 * 43 * The reason why PDPs are included in the context is straightforward: as 44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs 45 * contained there mean you don't need to do a ppgtt->switch_mm yourself, 46 * instead, the GPU will do it for you on the context switch. 47 * 48 * But, what about the ringbuffer control registers (head, tail, etc..)? 49 * shouldn't we just need a set of those per engine command streamer? This is 50 * where the name "Logical Rings" starts to make sense: by virtualizing the 51 * rings, the engine cs shifts to a new "ring buffer" with every context 52 * switch. When you want to submit a workload to the GPU you: A) choose your 53 * context, B) find its appropriate virtualized ring, C) write commands to it 54 * and then, finally, D) tell the GPU to switch to that context. 55 * 56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch 57 * to a contexts is via a context execution list, ergo "Execlists". 58 * 59 * LRC implementation: 60 * Regarding the creation of contexts, we have: 61 * 62 * - One global default context. 63 * - One local default context for each opened fd. 64 * - One local extra context for each context create ioctl call. 65 * 66 * Now that ringbuffers belong per-context (and not per-engine, like before) 67 * and that contexts are uniquely tied to a given engine (and not reusable, 68 * like before) we need: 69 * 70 * - One ringbuffer per-engine inside each context. 71 * - One backing object per-engine inside each context. 72 * 73 * The global default context starts its life with these new objects fully 74 * allocated and populated. The local default context for each opened fd is 75 * more complex, because we don't know at creation time which engine is going 76 * to use them. To handle this, we have implemented a deferred creation of LR 77 * contexts: 78 * 79 * The local context starts its life as a hollow or blank holder, that only 80 * gets populated for a given engine once we receive an execbuffer. If later 81 * on we receive another execbuffer ioctl for the same context but a different 82 * engine, we allocate/populate a new ringbuffer and context backing object and 83 * so on. 84 * 85 * Finally, regarding local contexts created using the ioctl call: as they are 86 * only allowed with the render ring, we can allocate & populate them right 87 * away (no need to defer anything, at least for now). 88 * 89 * Execlists implementation: 90 * Execlists are the new method by which, on gen8+ hardware, workloads are 91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method). 92 * This method works as follows: 93 * 94 * When a request is committed, its commands (the BB start and any leading or 95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer 96 * for the appropriate context. The tail pointer in the hardware context is not 97 * updated at this time, but instead, kept by the driver in the ringbuffer 98 * structure. A structure representing this request is added to a request queue 99 * for the appropriate engine: this structure contains a copy of the context's 100 * tail after the request was written to the ring buffer and a pointer to the 101 * context itself. 102 * 103 * If the engine's request queue was empty before the request was added, the 104 * queue is processed immediately. Otherwise the queue will be processed during 105 * a context switch interrupt. In any case, elements on the queue will get sent 106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a 107 * globally unique 20-bits submission ID. 108 * 109 * When execution of a request completes, the GPU updates the context status 110 * buffer with a context complete event and generates a context switch interrupt. 111 * During the interrupt handling, the driver examines the events in the buffer: 112 * for each context complete event, if the announced ID matches that on the head 113 * of the request queue, then that request is retired and removed from the queue. 114 * 115 * After processing, if any requests were retired and the queue is not empty 116 * then a new execution list can be submitted. The two requests at the front of 117 * the queue are next to be submitted but since a context may not occur twice in 118 * an execution list, if subsequent requests have the same ID as the first then 119 * the two requests must be combined. This is done simply by discarding requests 120 * at the head of the queue until either only one requests is left (in which case 121 * we use a NULL second context) or the first two requests have unique IDs. 122 * 123 * By always executing the first two requests in the queue the driver ensures 124 * that the GPU is kept as busy as possible. In the case where a single context 125 * completes but a second context is still executing, the request for this second 126 * context will be at the head of the queue when we remove the first one. This 127 * request will then be resubmitted along with a new request for a different context, 128 * which will cause the hardware to continue executing the second request and queue 129 * the new request (the GPU detects the condition of a context getting preempted 130 * with the same context and optimizes the context switch flow by not doing 131 * preemption, but just sampling the new tail pointer). 132 * 133 */ 134 135 #include <drm/drmP.h> 136 #include <drm/i915_drm.h> 137 #include "i915_drv.h" 138 #include "intel_drv.h" 139 140 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 141 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) 142 143 #define GEN8_LR_CONTEXT_ALIGN 4096 144 145 #define RING_EXECLIST_QFULL (1 << 0x2) 146 #define RING_EXECLIST1_VALID (1 << 0x3) 147 #define RING_EXECLIST0_VALID (1 << 0x4) 148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) 149 #define RING_EXECLIST1_ACTIVE (1 << 0x11) 150 #define RING_EXECLIST0_ACTIVE (1 << 0x12) 151 152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) 153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) 154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) 155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) 156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4) 157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) 158 159 #define CTX_LRI_HEADER_0 0x01 160 #define CTX_CONTEXT_CONTROL 0x02 161 #define CTX_RING_HEAD 0x04 162 #define CTX_RING_TAIL 0x06 163 #define CTX_RING_BUFFER_START 0x08 164 #define CTX_RING_BUFFER_CONTROL 0x0a 165 #define CTX_BB_HEAD_U 0x0c 166 #define CTX_BB_HEAD_L 0x0e 167 #define CTX_BB_STATE 0x10 168 #define CTX_SECOND_BB_HEAD_U 0x12 169 #define CTX_SECOND_BB_HEAD_L 0x14 170 #define CTX_SECOND_BB_STATE 0x16 171 #define CTX_BB_PER_CTX_PTR 0x18 172 #define CTX_RCS_INDIRECT_CTX 0x1a 173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c 174 #define CTX_LRI_HEADER_1 0x21 175 #define CTX_CTX_TIMESTAMP 0x22 176 #define CTX_PDP3_UDW 0x24 177 #define CTX_PDP3_LDW 0x26 178 #define CTX_PDP2_UDW 0x28 179 #define CTX_PDP2_LDW 0x2a 180 #define CTX_PDP1_UDW 0x2c 181 #define CTX_PDP1_LDW 0x2e 182 #define CTX_PDP0_UDW 0x30 183 #define CTX_PDP0_LDW 0x32 184 #define CTX_LRI_HEADER_2 0x41 185 #define CTX_R_PWR_CLK_STATE 0x42 186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 187 188 #define GEN8_CTX_VALID (1<<0) 189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) 190 #define GEN8_CTX_FORCE_RESTORE (1<<2) 191 #define GEN8_CTX_L3LLC_COHERENT (1<<5) 192 #define GEN8_CTX_PRIVILEGE (1<<8) 193 enum { 194 ADVANCED_CONTEXT = 0, 195 LEGACY_CONTEXT, 196 ADVANCED_AD_CONTEXT, 197 LEGACY_64B_CONTEXT 198 }; 199 #define GEN8_CTX_MODE_SHIFT 3 200 enum { 201 FAULT_AND_HANG = 0, 202 FAULT_AND_HALT, /* Debug only */ 203 FAULT_AND_STREAM, 204 FAULT_AND_CONTINUE /* Unsupported */ 205 }; 206 #define GEN8_CTX_ID_SHIFT 32 207 208 /** 209 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists 210 * @dev: DRM device. 211 * @enable_execlists: value of i915.enable_execlists module parameter. 212 * 213 * Only certain platforms support Execlists (the prerequisites being 214 * support for Logical Ring Contexts and Aliasing PPGTT or better), 215 * and only when enabled via module parameter. 216 * 217 * Return: 1 if Execlists is supported and has to be enabled. 218 */ 219 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) 220 { 221 WARN_ON(i915.enable_ppgtt == -1); 222 223 if (enable_execlists == 0) 224 return 0; 225 226 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && 227 i915.use_mmio_flip >= 0) 228 return 1; 229 230 return 0; 231 } 232 233 /** 234 * intel_execlists_ctx_id() - get the Execlists Context ID 235 * @ctx_obj: Logical Ring Context backing object. 236 * 237 * Do not confuse with ctx->id! Unfortunately we have a name overload 238 * here: the old context ID we pass to userspace as a handler so that 239 * they can refer to a context, and the new context ID we pass to the 240 * ELSP so that the GPU can inform us of the context status via 241 * interrupts. 242 * 243 * Return: 20-bits globally unique context ID. 244 */ 245 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) 246 { 247 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); 248 249 /* LRCA is required to be 4K aligned so the more significant 20 bits 250 * are globally unique */ 251 return lrca >> 12; 252 } 253 254 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_object *ctx_obj) 255 { 256 uint64_t desc; 257 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); 258 259 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); 260 261 desc = GEN8_CTX_VALID; 262 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; 263 desc |= GEN8_CTX_L3LLC_COHERENT; 264 desc |= GEN8_CTX_PRIVILEGE; 265 desc |= lrca; 266 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; 267 268 /* TODO: WaDisableLiteRestore when we start using semaphore 269 * signalling between Command Streamers */ 270 /* desc |= GEN8_CTX_FORCE_RESTORE; */ 271 272 return desc; 273 } 274 275 static void execlists_elsp_write(struct intel_engine_cs *ring, 276 struct drm_i915_gem_object *ctx_obj0, 277 struct drm_i915_gem_object *ctx_obj1) 278 { 279 struct drm_i915_private *dev_priv = ring->dev->dev_private; 280 uint64_t temp = 0; 281 uint32_t desc[4]; 282 283 /* XXX: You must always write both descriptors in the order below. */ 284 if (ctx_obj1) 285 temp = execlists_ctx_descriptor(ctx_obj1); 286 else 287 temp = 0; 288 desc[1] = (u32)(temp >> 32); 289 desc[0] = (u32)temp; 290 291 temp = execlists_ctx_descriptor(ctx_obj0); 292 desc[3] = (u32)(temp >> 32); 293 desc[2] = (u32)temp; 294 295 /* Set Force Wakeup bit to prevent GT from entering C6 while ELSP writes 296 * are in progress. 297 * 298 * The other problem is that we can't just call gen6_gt_force_wake_get() 299 * because that function calls intel_runtime_pm_get(), which might sleep. 300 * Instead, we do the runtime_pm_get/put when creating/destroying requests. 301 */ 302 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 303 if (IS_CHERRYVIEW(dev_priv->dev)) { 304 if (dev_priv->uncore.fw_rendercount++ == 0) 305 dev_priv->uncore.funcs.force_wake_get(dev_priv, 306 FORCEWAKE_RENDER); 307 if (dev_priv->uncore.fw_mediacount++ == 0) 308 dev_priv->uncore.funcs.force_wake_get(dev_priv, 309 FORCEWAKE_MEDIA); 310 } else { 311 if (dev_priv->uncore.forcewake_count++ == 0) 312 dev_priv->uncore.funcs.force_wake_get(dev_priv, 313 FORCEWAKE_ALL); 314 } 315 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 316 317 I915_WRITE(RING_ELSP(ring), desc[1]); 318 I915_WRITE(RING_ELSP(ring), desc[0]); 319 I915_WRITE(RING_ELSP(ring), desc[3]); 320 /* The context is automatically loaded after the following */ 321 I915_WRITE(RING_ELSP(ring), desc[2]); 322 323 /* ELSP is a wo register, so use another nearby reg for posting instead */ 324 POSTING_READ(RING_EXECLIST_STATUS(ring)); 325 326 /* Release Force Wakeup (see the big comment above). */ 327 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 328 if (IS_CHERRYVIEW(dev_priv->dev)) { 329 if (--dev_priv->uncore.fw_rendercount == 0) 330 dev_priv->uncore.funcs.force_wake_put(dev_priv, 331 FORCEWAKE_RENDER); 332 if (--dev_priv->uncore.fw_mediacount == 0) 333 dev_priv->uncore.funcs.force_wake_put(dev_priv, 334 FORCEWAKE_MEDIA); 335 } else { 336 if (--dev_priv->uncore.forcewake_count == 0) 337 dev_priv->uncore.funcs.force_wake_put(dev_priv, 338 FORCEWAKE_ALL); 339 } 340 341 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 342 } 343 344 static int execlists_ctx_write_tail(struct drm_i915_gem_object *ctx_obj, u32 tail) 345 { 346 struct vm_page *page; 347 uint32_t *reg_state; 348 349 page = i915_gem_object_get_page(ctx_obj, 1); 350 reg_state = kmap_atomic(page); 351 352 reg_state[CTX_RING_TAIL+1] = tail; 353 354 kunmap_atomic(reg_state); 355 356 return 0; 357 } 358 359 static int execlists_submit_context(struct intel_engine_cs *ring, 360 struct intel_context *to0, u32 tail0, 361 struct intel_context *to1, u32 tail1) 362 { 363 struct drm_i915_gem_object *ctx_obj0; 364 struct drm_i915_gem_object *ctx_obj1 = NULL; 365 366 ctx_obj0 = to0->engine[ring->id].state; 367 BUG_ON(!ctx_obj0); 368 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); 369 370 execlists_ctx_write_tail(ctx_obj0, tail0); 371 372 if (to1) { 373 ctx_obj1 = to1->engine[ring->id].state; 374 BUG_ON(!ctx_obj1); 375 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); 376 377 execlists_ctx_write_tail(ctx_obj1, tail1); 378 } 379 380 execlists_elsp_write(ring, ctx_obj0, ctx_obj1); 381 382 return 0; 383 } 384 385 static void execlists_context_unqueue(struct intel_engine_cs *ring) 386 { 387 struct intel_ctx_submit_request *req0 = NULL, *req1 = NULL; 388 struct intel_ctx_submit_request *cursor = NULL, *tmp = NULL; 389 struct drm_i915_private *dev_priv = ring->dev->dev_private; 390 391 assert_spin_locked(&ring->execlist_lock); 392 393 if (list_empty(&ring->execlist_queue)) 394 return; 395 396 /* Try to read in pairs */ 397 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, 398 execlist_link) { 399 if (!req0) { 400 req0 = cursor; 401 } else if (req0->ctx == cursor->ctx) { 402 /* Same ctx: ignore first request, as second request 403 * will update tail past first request's workload */ 404 cursor->elsp_submitted = req0->elsp_submitted; 405 list_del(&req0->execlist_link); 406 queue_work(dev_priv->wq, &req0->work); 407 req0 = cursor; 408 } else { 409 req1 = cursor; 410 break; 411 } 412 } 413 414 WARN_ON(req1 && req1->elsp_submitted); 415 416 WARN_ON(execlists_submit_context(ring, req0->ctx, req0->tail, 417 req1 ? req1->ctx : NULL, 418 req1 ? req1->tail : 0)); 419 420 req0->elsp_submitted++; 421 if (req1) 422 req1->elsp_submitted++; 423 } 424 425 static bool execlists_check_remove_request(struct intel_engine_cs *ring, 426 u32 request_id) 427 { 428 struct drm_i915_private *dev_priv = ring->dev->dev_private; 429 struct intel_ctx_submit_request *head_req; 430 431 assert_spin_locked(&ring->execlist_lock); 432 433 head_req = list_first_entry_or_null(&ring->execlist_queue, 434 struct intel_ctx_submit_request, 435 execlist_link); 436 437 if (head_req != NULL) { 438 struct drm_i915_gem_object *ctx_obj = 439 head_req->ctx->engine[ring->id].state; 440 if (intel_execlists_ctx_id(ctx_obj) == request_id) { 441 WARN(head_req->elsp_submitted == 0, 442 "Never submitted head request\n"); 443 444 if (--head_req->elsp_submitted <= 0) { 445 list_del(&head_req->execlist_link); 446 queue_work(dev_priv->wq, &head_req->work); 447 return true; 448 } 449 } 450 } 451 452 return false; 453 } 454 455 /** 456 * intel_execlists_handle_ctx_events() - handle Context Switch interrupts 457 * @ring: Engine Command Streamer to handle. 458 * 459 * Check the unread Context Status Buffers and manage the submission of new 460 * contexts to the ELSP accordingly. 461 */ 462 void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring) 463 { 464 struct drm_i915_private *dev_priv = ring->dev->dev_private; 465 u32 status_pointer; 466 u8 read_pointer; 467 u8 write_pointer; 468 u32 status; 469 u32 status_id; 470 u32 submit_contexts = 0; 471 472 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); 473 474 read_pointer = ring->next_context_status_buffer; 475 write_pointer = status_pointer & 0x07; 476 if (read_pointer > write_pointer) 477 write_pointer += 6; 478 479 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 480 481 while (read_pointer < write_pointer) { 482 read_pointer++; 483 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 484 (read_pointer % 6) * 8); 485 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 486 (read_pointer % 6) * 8 + 4); 487 488 if (status & GEN8_CTX_STATUS_PREEMPTED) { 489 if (status & GEN8_CTX_STATUS_LITE_RESTORE) { 490 if (execlists_check_remove_request(ring, status_id)) 491 WARN(1, "Lite Restored request removed from queue\n"); 492 } else 493 WARN(1, "Preemption without Lite Restore\n"); 494 } 495 496 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || 497 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { 498 if (execlists_check_remove_request(ring, status_id)) 499 submit_contexts++; 500 } 501 } 502 503 if (submit_contexts != 0) 504 execlists_context_unqueue(ring); 505 506 lockmgr(&ring->execlist_lock, LK_RELEASE); 507 508 WARN(submit_contexts > 2, "More than two context complete events?\n"); 509 ring->next_context_status_buffer = write_pointer % 6; 510 511 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), 512 ((u32)ring->next_context_status_buffer & 0x07) << 8); 513 } 514 515 static void execlists_free_request_task(struct work_struct *work) 516 { 517 struct intel_ctx_submit_request *req = 518 container_of(work, struct intel_ctx_submit_request, work); 519 struct drm_device *dev = req->ring->dev; 520 struct drm_i915_private *dev_priv = dev->dev_private; 521 522 intel_runtime_pm_put(dev_priv); 523 524 mutex_lock(&dev->struct_mutex); 525 i915_gem_context_unreference(req->ctx); 526 mutex_unlock(&dev->struct_mutex); 527 528 kfree(req); 529 } 530 531 static int execlists_context_queue(struct intel_engine_cs *ring, 532 struct intel_context *to, 533 u32 tail) 534 { 535 struct intel_ctx_submit_request *req = NULL, *cursor; 536 struct drm_i915_private *dev_priv = ring->dev->dev_private; 537 int num_elements = 0; 538 539 req = kzalloc(sizeof(*req), GFP_KERNEL); 540 if (req == NULL) 541 return -ENOMEM; 542 req->ctx = to; 543 i915_gem_context_reference(req->ctx); 544 req->ring = ring; 545 req->tail = tail; 546 INIT_WORK(&req->work, execlists_free_request_task); 547 548 intel_runtime_pm_get(dev_priv); 549 550 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 551 552 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) 553 if (++num_elements > 2) 554 break; 555 556 if (num_elements > 2) { 557 struct intel_ctx_submit_request *tail_req; 558 559 tail_req = list_last_entry(&ring->execlist_queue, 560 struct intel_ctx_submit_request, 561 execlist_link); 562 563 if (to == tail_req->ctx) { 564 WARN(tail_req->elsp_submitted != 0, 565 "More than 2 already-submitted reqs queued\n"); 566 list_del(&tail_req->execlist_link); 567 queue_work(dev_priv->wq, &tail_req->work); 568 } 569 } 570 571 list_add_tail(&req->execlist_link, &ring->execlist_queue); 572 if (num_elements == 0) 573 execlists_context_unqueue(ring); 574 575 lockmgr(&ring->execlist_lock, LK_RELEASE); 576 577 return 0; 578 } 579 580 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf) 581 { 582 struct intel_engine_cs *ring = ringbuf->ring; 583 uint32_t flush_domains; 584 int ret; 585 586 flush_domains = 0; 587 if (ring->gpu_caches_dirty) 588 flush_domains = I915_GEM_GPU_DOMAINS; 589 590 ret = ring->emit_flush(ringbuf, I915_GEM_GPU_DOMAINS, flush_domains); 591 if (ret) 592 return ret; 593 594 ring->gpu_caches_dirty = false; 595 return 0; 596 } 597 598 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, 599 struct list_head *vmas) 600 { 601 struct intel_engine_cs *ring = ringbuf->ring; 602 struct i915_vma *vma; 603 uint32_t flush_domains = 0; 604 bool flush_chipset = false; 605 int ret; 606 607 list_for_each_entry(vma, vmas, exec_list) { 608 struct drm_i915_gem_object *obj = vma->obj; 609 610 ret = i915_gem_object_sync(obj, ring); 611 if (ret) 612 return ret; 613 614 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) 615 flush_chipset |= i915_gem_clflush_object(obj, false); 616 617 flush_domains |= obj->base.write_domain; 618 } 619 620 if (flush_domains & I915_GEM_DOMAIN_GTT) 621 wmb(); 622 623 /* Unconditionally invalidate gpu caches and ensure that we do flush 624 * any residual writes from the previous batch. 625 */ 626 return logical_ring_invalidate_all_caches(ringbuf); 627 } 628 629 /** 630 * execlists_submission() - submit a batchbuffer for execution, Execlists style 631 * @dev: DRM device. 632 * @file: DRM file. 633 * @ring: Engine Command Streamer to submit to. 634 * @ctx: Context to employ for this submission. 635 * @args: execbuffer call arguments. 636 * @vmas: list of vmas. 637 * @batch_obj: the batchbuffer to submit. 638 * @exec_start: batchbuffer start virtual address pointer. 639 * @flags: translated execbuffer call flags. 640 * 641 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts 642 * away the submission details of the execbuffer ioctl call. 643 * 644 * Return: non-zero if the submission fails. 645 */ 646 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, 647 struct intel_engine_cs *ring, 648 struct intel_context *ctx, 649 struct drm_i915_gem_execbuffer2 *args, 650 struct list_head *vmas, 651 struct drm_i915_gem_object *batch_obj, 652 u64 exec_start, u32 flags) 653 { 654 struct drm_i915_private *dev_priv = dev->dev_private; 655 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 656 int instp_mode; 657 u32 instp_mask; 658 int ret; 659 660 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; 661 instp_mask = I915_EXEC_CONSTANTS_MASK; 662 switch (instp_mode) { 663 case I915_EXEC_CONSTANTS_REL_GENERAL: 664 case I915_EXEC_CONSTANTS_ABSOLUTE: 665 case I915_EXEC_CONSTANTS_REL_SURFACE: 666 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { 667 DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); 668 return -EINVAL; 669 } 670 671 if (instp_mode != dev_priv->relative_constants_mode) { 672 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { 673 DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); 674 return -EINVAL; 675 } 676 677 /* The HW changed the meaning on this bit on gen6 */ 678 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; 679 } 680 break; 681 default: 682 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); 683 return -EINVAL; 684 } 685 686 if (args->num_cliprects != 0) { 687 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); 688 return -EINVAL; 689 } else { 690 if (args->DR4 == 0xffffffff) { 691 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); 692 args->DR4 = 0; 693 } 694 695 if (args->DR1 || args->DR4 || args->cliprects_ptr) { 696 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); 697 return -EINVAL; 698 } 699 } 700 701 if (args->flags & I915_EXEC_GEN7_SOL_RESET) { 702 DRM_DEBUG("sol reset is gen7 only\n"); 703 return -EINVAL; 704 } 705 706 ret = execlists_move_to_gpu(ringbuf, vmas); 707 if (ret) 708 return ret; 709 710 if (ring == &dev_priv->ring[RCS] && 711 instp_mode != dev_priv->relative_constants_mode) { 712 ret = intel_logical_ring_begin(ringbuf, 4); 713 if (ret) 714 return ret; 715 716 intel_logical_ring_emit(ringbuf, MI_NOOP); 717 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); 718 intel_logical_ring_emit(ringbuf, INSTPM); 719 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); 720 intel_logical_ring_advance(ringbuf); 721 722 dev_priv->relative_constants_mode = instp_mode; 723 } 724 725 ret = ring->emit_bb_start(ringbuf, exec_start, flags); 726 if (ret) 727 return ret; 728 729 i915_gem_execbuffer_move_to_active(vmas, ring); 730 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); 731 732 return 0; 733 } 734 735 void intel_logical_ring_stop(struct intel_engine_cs *ring) 736 { 737 struct drm_i915_private *dev_priv = ring->dev->dev_private; 738 int ret; 739 740 if (!intel_ring_initialized(ring)) 741 return; 742 743 ret = intel_ring_idle(ring); 744 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) 745 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", 746 ring->name, ret); 747 748 /* TODO: Is this correct with Execlists enabled? */ 749 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); 750 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { 751 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); 752 return; 753 } 754 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); 755 } 756 757 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf) 758 { 759 struct intel_engine_cs *ring = ringbuf->ring; 760 int ret; 761 762 if (!ring->gpu_caches_dirty) 763 return 0; 764 765 ret = ring->emit_flush(ringbuf, 0, I915_GEM_GPU_DOMAINS); 766 if (ret) 767 return ret; 768 769 ring->gpu_caches_dirty = false; 770 return 0; 771 } 772 773 /** 774 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload 775 * @ringbuf: Logical Ringbuffer to advance. 776 * 777 * The tail is updated in our logical ringbuffer struct, not in the actual context. What 778 * really happens during submission is that the context and current tail will be placed 779 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that 780 * point, the tail *inside* the context is updated and the ELSP written to. 781 */ 782 void intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf) 783 { 784 struct intel_engine_cs *ring = ringbuf->ring; 785 struct intel_context *ctx = ringbuf->FIXME_lrc_ctx; 786 787 intel_logical_ring_advance(ringbuf); 788 789 if (intel_ring_stopped(ring)) 790 return; 791 792 execlists_context_queue(ring, ctx, ringbuf->tail); 793 } 794 795 static int logical_ring_alloc_seqno(struct intel_engine_cs *ring, 796 struct intel_context *ctx) 797 { 798 if (ring->outstanding_lazy_seqno) 799 return 0; 800 801 if (ring->preallocated_lazy_request == NULL) { 802 struct drm_i915_gem_request *request; 803 804 request = kmalloc(sizeof(*request), M_DRM, M_WAITOK); 805 if (request == NULL) 806 return -ENOMEM; 807 808 /* Hold a reference to the context this request belongs to 809 * (we will need it when the time comes to emit/retire the 810 * request). 811 */ 812 request->ctx = ctx; 813 i915_gem_context_reference(request->ctx); 814 815 ring->preallocated_lazy_request = request; 816 } 817 818 return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno); 819 } 820 821 static int logical_ring_wait_request(struct intel_ringbuffer *ringbuf, 822 int bytes) 823 { 824 struct intel_engine_cs *ring = ringbuf->ring; 825 struct drm_i915_gem_request *request; 826 u32 seqno = 0; 827 int ret; 828 829 if (ringbuf->last_retired_head != -1) { 830 ringbuf->head = ringbuf->last_retired_head; 831 ringbuf->last_retired_head = -1; 832 833 ringbuf->space = intel_ring_space(ringbuf); 834 if (ringbuf->space >= bytes) 835 return 0; 836 } 837 838 list_for_each_entry(request, &ring->request_list, list) { 839 if (__intel_ring_space(request->tail, ringbuf->tail, 840 ringbuf->size) >= bytes) { 841 seqno = request->seqno; 842 break; 843 } 844 } 845 846 if (seqno == 0) 847 return -ENOSPC; 848 849 ret = i915_wait_seqno(ring, seqno); 850 if (ret) 851 return ret; 852 853 i915_gem_retire_requests_ring(ring); 854 ringbuf->head = ringbuf->last_retired_head; 855 ringbuf->last_retired_head = -1; 856 857 ringbuf->space = intel_ring_space(ringbuf); 858 return 0; 859 } 860 861 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, 862 int bytes) 863 { 864 struct intel_engine_cs *ring = ringbuf->ring; 865 struct drm_device *dev = ring->dev; 866 struct drm_i915_private *dev_priv = dev->dev_private; 867 unsigned long end; 868 int ret; 869 870 ret = logical_ring_wait_request(ringbuf, bytes); 871 if (ret != -ENOSPC) 872 return ret; 873 874 /* Force the context submission in case we have been skipping it */ 875 intel_logical_ring_advance_and_submit(ringbuf); 876 877 /* With GEM the hangcheck timer should kick us out of the loop, 878 * leaving it early runs the risk of corrupting GEM state (due 879 * to running on almost untested codepaths). But on resume 880 * timers don't work yet, so prevent a complete hang in that 881 * case by choosing an insanely large timeout. */ 882 end = jiffies + 60 * HZ; 883 884 do { 885 ringbuf->head = I915_READ_HEAD(ring); 886 ringbuf->space = intel_ring_space(ringbuf); 887 if (ringbuf->space >= bytes) { 888 ret = 0; 889 break; 890 } 891 892 msleep(1); 893 894 if (dev_priv->mm.interruptible && signal_pending(curthread->td_lwp)) { 895 ret = -ERESTARTSYS; 896 break; 897 } 898 899 ret = i915_gem_check_wedge(&dev_priv->gpu_error, 900 dev_priv->mm.interruptible); 901 if (ret) 902 break; 903 904 if (time_after(jiffies, end)) { 905 ret = -EBUSY; 906 break; 907 } 908 } while (1); 909 910 return ret; 911 } 912 913 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf) 914 { 915 uint32_t __iomem *virt; 916 int rem = ringbuf->size - ringbuf->tail; 917 918 if (ringbuf->space < rem) { 919 int ret = logical_ring_wait_for_space(ringbuf, rem); 920 921 if (ret) 922 return ret; 923 } 924 925 virt = (unsigned int *)((char *)ringbuf->virtual_start + ringbuf->tail); 926 rem /= 4; 927 while (rem--) 928 iowrite32(MI_NOOP, virt++); 929 930 ringbuf->tail = 0; 931 ringbuf->space = intel_ring_space(ringbuf); 932 933 return 0; 934 } 935 936 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, int bytes) 937 { 938 int ret; 939 940 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { 941 ret = logical_ring_wrap_buffer(ringbuf); 942 if (unlikely(ret)) 943 return ret; 944 } 945 946 if (unlikely(ringbuf->space < bytes)) { 947 ret = logical_ring_wait_for_space(ringbuf, bytes); 948 if (unlikely(ret)) 949 return ret; 950 } 951 952 return 0; 953 } 954 955 /** 956 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands 957 * 958 * @ringbuf: Logical ringbuffer. 959 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. 960 * 961 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to 962 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that 963 * and also preallocates a request (every workload submission is still mediated through 964 * requests, same as it did with legacy ringbuffer submission). 965 * 966 * Return: non-zero if the ringbuffer is not ready to be written to. 967 */ 968 int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, int num_dwords) 969 { 970 struct intel_engine_cs *ring = ringbuf->ring; 971 struct drm_device *dev = ring->dev; 972 struct drm_i915_private *dev_priv = dev->dev_private; 973 int ret; 974 975 ret = i915_gem_check_wedge(&dev_priv->gpu_error, 976 dev_priv->mm.interruptible); 977 if (ret) 978 return ret; 979 980 ret = logical_ring_prepare(ringbuf, num_dwords * sizeof(uint32_t)); 981 if (ret) 982 return ret; 983 984 /* Preallocate the olr before touching the ring */ 985 ret = logical_ring_alloc_seqno(ring, ringbuf->FIXME_lrc_ctx); 986 if (ret) 987 return ret; 988 989 ringbuf->space -= num_dwords * sizeof(uint32_t); 990 return 0; 991 } 992 993 static int gen8_init_common_ring(struct intel_engine_cs *ring) 994 { 995 struct drm_device *dev = ring->dev; 996 struct drm_i915_private *dev_priv = dev->dev_private; 997 998 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); 999 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); 1000 1001 I915_WRITE(RING_MODE_GEN7(ring), 1002 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | 1003 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); 1004 POSTING_READ(RING_MODE_GEN7(ring)); 1005 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); 1006 1007 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); 1008 1009 return 0; 1010 } 1011 1012 static int gen8_init_render_ring(struct intel_engine_cs *ring) 1013 { 1014 struct drm_device *dev = ring->dev; 1015 struct drm_i915_private *dev_priv = dev->dev_private; 1016 int ret; 1017 1018 ret = gen8_init_common_ring(ring); 1019 if (ret) 1020 return ret; 1021 1022 /* We need to disable the AsyncFlip performance optimisations in order 1023 * to use MI_WAIT_FOR_EVENT within the CS. It should already be 1024 * programmed to '1' on all products. 1025 * 1026 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv 1027 */ 1028 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); 1029 1030 ret = intel_init_pipe_control(ring); 1031 if (ret) 1032 return ret; 1033 1034 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); 1035 1036 return ret; 1037 } 1038 1039 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, 1040 u64 offset, unsigned flags) 1041 { 1042 bool ppgtt = !(flags & I915_DISPATCH_SECURE); 1043 int ret; 1044 1045 ret = intel_logical_ring_begin(ringbuf, 4); 1046 if (ret) 1047 return ret; 1048 1049 /* FIXME(BDW): Address space and security selectors. */ 1050 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); 1051 intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); 1052 intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); 1053 intel_logical_ring_emit(ringbuf, MI_NOOP); 1054 intel_logical_ring_advance(ringbuf); 1055 1056 return 0; 1057 } 1058 1059 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) 1060 { 1061 struct drm_device *dev = ring->dev; 1062 struct drm_i915_private *dev_priv = dev->dev_private; 1063 1064 if (!dev->irq_enabled) 1065 return false; 1066 1067 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1068 if (ring->irq_refcount++ == 0) { 1069 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); 1070 POSTING_READ(RING_IMR(ring->mmio_base)); 1071 } 1072 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1073 1074 return true; 1075 } 1076 1077 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) 1078 { 1079 struct drm_device *dev = ring->dev; 1080 struct drm_i915_private *dev_priv = dev->dev_private; 1081 1082 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1083 if (--ring->irq_refcount == 0) { 1084 I915_WRITE_IMR(ring, ~ring->irq_keep_mask); 1085 POSTING_READ(RING_IMR(ring->mmio_base)); 1086 } 1087 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1088 } 1089 1090 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, 1091 u32 invalidate_domains, 1092 u32 unused) 1093 { 1094 struct intel_engine_cs *ring = ringbuf->ring; 1095 struct drm_device *dev = ring->dev; 1096 struct drm_i915_private *dev_priv = dev->dev_private; 1097 uint32_t cmd; 1098 int ret; 1099 1100 ret = intel_logical_ring_begin(ringbuf, 4); 1101 if (ret) 1102 return ret; 1103 1104 cmd = MI_FLUSH_DW + 1; 1105 1106 if (ring == &dev_priv->ring[VCS]) { 1107 if (invalidate_domains & I915_GEM_GPU_DOMAINS) 1108 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | 1109 MI_FLUSH_DW_STORE_INDEX | 1110 MI_FLUSH_DW_OP_STOREDW; 1111 } else { 1112 if (invalidate_domains & I915_GEM_DOMAIN_RENDER) 1113 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | 1114 MI_FLUSH_DW_OP_STOREDW; 1115 } 1116 1117 intel_logical_ring_emit(ringbuf, cmd); 1118 intel_logical_ring_emit(ringbuf, 1119 I915_GEM_HWS_SCRATCH_ADDR | 1120 MI_FLUSH_DW_USE_GTT); 1121 intel_logical_ring_emit(ringbuf, 0); /* upper addr */ 1122 intel_logical_ring_emit(ringbuf, 0); /* value */ 1123 intel_logical_ring_advance(ringbuf); 1124 1125 return 0; 1126 } 1127 1128 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, 1129 u32 invalidate_domains, 1130 u32 flush_domains) 1131 { 1132 struct intel_engine_cs *ring = ringbuf->ring; 1133 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; 1134 u32 flags = 0; 1135 int ret; 1136 1137 flags |= PIPE_CONTROL_CS_STALL; 1138 1139 if (flush_domains) { 1140 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 1141 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 1142 } 1143 1144 if (invalidate_domains) { 1145 flags |= PIPE_CONTROL_TLB_INVALIDATE; 1146 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 1147 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 1148 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 1149 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 1150 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 1151 flags |= PIPE_CONTROL_QW_WRITE; 1152 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 1153 } 1154 1155 ret = intel_logical_ring_begin(ringbuf, 6); 1156 if (ret) 1157 return ret; 1158 1159 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); 1160 intel_logical_ring_emit(ringbuf, flags); 1161 intel_logical_ring_emit(ringbuf, scratch_addr); 1162 intel_logical_ring_emit(ringbuf, 0); 1163 intel_logical_ring_emit(ringbuf, 0); 1164 intel_logical_ring_emit(ringbuf, 0); 1165 intel_logical_ring_advance(ringbuf); 1166 1167 return 0; 1168 } 1169 1170 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) 1171 { 1172 return intel_read_status_page(ring, I915_GEM_HWS_INDEX); 1173 } 1174 1175 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) 1176 { 1177 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); 1178 } 1179 1180 static int gen8_emit_request(struct intel_ringbuffer *ringbuf) 1181 { 1182 struct intel_engine_cs *ring = ringbuf->ring; 1183 u32 cmd; 1184 int ret; 1185 1186 ret = intel_logical_ring_begin(ringbuf, 6); 1187 if (ret) 1188 return ret; 1189 1190 cmd = MI_STORE_DWORD_IMM_GEN8; 1191 cmd |= MI_GLOBAL_GTT; 1192 1193 intel_logical_ring_emit(ringbuf, cmd); 1194 intel_logical_ring_emit(ringbuf, 1195 (ring->status_page.gfx_addr + 1196 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); 1197 intel_logical_ring_emit(ringbuf, 0); 1198 intel_logical_ring_emit(ringbuf, ring->outstanding_lazy_seqno); 1199 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); 1200 intel_logical_ring_emit(ringbuf, MI_NOOP); 1201 intel_logical_ring_advance_and_submit(ringbuf); 1202 1203 return 0; 1204 } 1205 1206 /** 1207 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer 1208 * 1209 * @ring: Engine Command Streamer. 1210 * 1211 */ 1212 void intel_logical_ring_cleanup(struct intel_engine_cs *ring) 1213 { 1214 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1215 1216 if (!intel_ring_initialized(ring)) 1217 return; 1218 1219 intel_logical_ring_stop(ring); 1220 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); 1221 ring->preallocated_lazy_request = NULL; 1222 ring->outstanding_lazy_seqno = 0; 1223 1224 if (ring->cleanup) 1225 ring->cleanup(ring); 1226 1227 i915_cmd_parser_fini_ring(ring); 1228 1229 if (ring->status_page.obj) { 1230 kunmap(ring->status_page.obj->pages[0]); 1231 ring->status_page.obj = NULL; 1232 } 1233 } 1234 1235 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) 1236 { 1237 int ret; 1238 1239 /* Intentionally left blank. */ 1240 ring->buffer = NULL; 1241 1242 ring->dev = dev; 1243 INIT_LIST_HEAD(&ring->active_list); 1244 INIT_LIST_HEAD(&ring->request_list); 1245 init_waitqueue_head(&ring->irq_queue); 1246 1247 INIT_LIST_HEAD(&ring->execlist_queue); 1248 lockinit(&ring->execlist_lock, "i915el", 0, LK_CANRECURSE); 1249 ring->next_context_status_buffer = 0; 1250 1251 ret = i915_cmd_parser_init_ring(ring); 1252 if (ret) 1253 return ret; 1254 1255 if (ring->init) { 1256 ret = ring->init(ring); 1257 if (ret) 1258 return ret; 1259 } 1260 1261 ret = intel_lr_context_deferred_create(ring->default_context, ring); 1262 1263 return ret; 1264 } 1265 1266 static int logical_render_ring_init(struct drm_device *dev) 1267 { 1268 struct drm_i915_private *dev_priv = dev->dev_private; 1269 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; 1270 1271 ring->name = "render ring"; 1272 ring->id = RCS; 1273 ring->mmio_base = RENDER_RING_BASE; 1274 ring->irq_enable_mask = 1275 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; 1276 ring->irq_keep_mask = 1277 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; 1278 if (HAS_L3_DPF(dev)) 1279 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; 1280 1281 ring->init = gen8_init_render_ring; 1282 ring->cleanup = intel_fini_pipe_control; 1283 ring->get_seqno = gen8_get_seqno; 1284 ring->set_seqno = gen8_set_seqno; 1285 ring->emit_request = gen8_emit_request; 1286 ring->emit_flush = gen8_emit_flush_render; 1287 ring->irq_get = gen8_logical_ring_get_irq; 1288 ring->irq_put = gen8_logical_ring_put_irq; 1289 ring->emit_bb_start = gen8_emit_bb_start; 1290 1291 return logical_ring_init(dev, ring); 1292 } 1293 1294 static int logical_bsd_ring_init(struct drm_device *dev) 1295 { 1296 struct drm_i915_private *dev_priv = dev->dev_private; 1297 struct intel_engine_cs *ring = &dev_priv->ring[VCS]; 1298 1299 ring->name = "bsd ring"; 1300 ring->id = VCS; 1301 ring->mmio_base = GEN6_BSD_RING_BASE; 1302 ring->irq_enable_mask = 1303 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; 1304 ring->irq_keep_mask = 1305 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; 1306 1307 ring->init = gen8_init_common_ring; 1308 ring->get_seqno = gen8_get_seqno; 1309 ring->set_seqno = gen8_set_seqno; 1310 ring->emit_request = gen8_emit_request; 1311 ring->emit_flush = gen8_emit_flush; 1312 ring->irq_get = gen8_logical_ring_get_irq; 1313 ring->irq_put = gen8_logical_ring_put_irq; 1314 ring->emit_bb_start = gen8_emit_bb_start; 1315 1316 return logical_ring_init(dev, ring); 1317 } 1318 1319 static int logical_bsd2_ring_init(struct drm_device *dev) 1320 { 1321 struct drm_i915_private *dev_priv = dev->dev_private; 1322 struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; 1323 1324 ring->name = "bds2 ring"; 1325 ring->id = VCS2; 1326 ring->mmio_base = GEN8_BSD2_RING_BASE; 1327 ring->irq_enable_mask = 1328 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; 1329 ring->irq_keep_mask = 1330 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; 1331 1332 ring->init = gen8_init_common_ring; 1333 ring->get_seqno = gen8_get_seqno; 1334 ring->set_seqno = gen8_set_seqno; 1335 ring->emit_request = gen8_emit_request; 1336 ring->emit_flush = gen8_emit_flush; 1337 ring->irq_get = gen8_logical_ring_get_irq; 1338 ring->irq_put = gen8_logical_ring_put_irq; 1339 ring->emit_bb_start = gen8_emit_bb_start; 1340 1341 return logical_ring_init(dev, ring); 1342 } 1343 1344 static int logical_blt_ring_init(struct drm_device *dev) 1345 { 1346 struct drm_i915_private *dev_priv = dev->dev_private; 1347 struct intel_engine_cs *ring = &dev_priv->ring[BCS]; 1348 1349 ring->name = "blitter ring"; 1350 ring->id = BCS; 1351 ring->mmio_base = BLT_RING_BASE; 1352 ring->irq_enable_mask = 1353 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; 1354 ring->irq_keep_mask = 1355 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; 1356 1357 ring->init = gen8_init_common_ring; 1358 ring->get_seqno = gen8_get_seqno; 1359 ring->set_seqno = gen8_set_seqno; 1360 ring->emit_request = gen8_emit_request; 1361 ring->emit_flush = gen8_emit_flush; 1362 ring->irq_get = gen8_logical_ring_get_irq; 1363 ring->irq_put = gen8_logical_ring_put_irq; 1364 ring->emit_bb_start = gen8_emit_bb_start; 1365 1366 return logical_ring_init(dev, ring); 1367 } 1368 1369 static int logical_vebox_ring_init(struct drm_device *dev) 1370 { 1371 struct drm_i915_private *dev_priv = dev->dev_private; 1372 struct intel_engine_cs *ring = &dev_priv->ring[VECS]; 1373 1374 ring->name = "video enhancement ring"; 1375 ring->id = VECS; 1376 ring->mmio_base = VEBOX_RING_BASE; 1377 ring->irq_enable_mask = 1378 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; 1379 ring->irq_keep_mask = 1380 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; 1381 1382 ring->init = gen8_init_common_ring; 1383 ring->get_seqno = gen8_get_seqno; 1384 ring->set_seqno = gen8_set_seqno; 1385 ring->emit_request = gen8_emit_request; 1386 ring->emit_flush = gen8_emit_flush; 1387 ring->irq_get = gen8_logical_ring_get_irq; 1388 ring->irq_put = gen8_logical_ring_put_irq; 1389 ring->emit_bb_start = gen8_emit_bb_start; 1390 1391 return logical_ring_init(dev, ring); 1392 } 1393 1394 /** 1395 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers 1396 * @dev: DRM device. 1397 * 1398 * This function inits the engines for an Execlists submission style (the equivalent in the 1399 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for 1400 * those engines that are present in the hardware. 1401 * 1402 * Return: non-zero if the initialization failed. 1403 */ 1404 int intel_logical_rings_init(struct drm_device *dev) 1405 { 1406 struct drm_i915_private *dev_priv = dev->dev_private; 1407 int ret; 1408 1409 ret = logical_render_ring_init(dev); 1410 if (ret) 1411 return ret; 1412 1413 if (HAS_BSD(dev)) { 1414 ret = logical_bsd_ring_init(dev); 1415 if (ret) 1416 goto cleanup_render_ring; 1417 } 1418 1419 if (HAS_BLT(dev)) { 1420 ret = logical_blt_ring_init(dev); 1421 if (ret) 1422 goto cleanup_bsd_ring; 1423 } 1424 1425 if (HAS_VEBOX(dev)) { 1426 ret = logical_vebox_ring_init(dev); 1427 if (ret) 1428 goto cleanup_blt_ring; 1429 } 1430 1431 if (HAS_BSD2(dev)) { 1432 ret = logical_bsd2_ring_init(dev); 1433 if (ret) 1434 goto cleanup_vebox_ring; 1435 } 1436 1437 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); 1438 if (ret) 1439 goto cleanup_bsd2_ring; 1440 1441 return 0; 1442 1443 cleanup_bsd2_ring: 1444 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); 1445 cleanup_vebox_ring: 1446 intel_logical_ring_cleanup(&dev_priv->ring[VECS]); 1447 cleanup_blt_ring: 1448 intel_logical_ring_cleanup(&dev_priv->ring[BCS]); 1449 cleanup_bsd_ring: 1450 intel_logical_ring_cleanup(&dev_priv->ring[VCS]); 1451 cleanup_render_ring: 1452 intel_logical_ring_cleanup(&dev_priv->ring[RCS]); 1453 1454 return ret; 1455 } 1456 1457 int intel_lr_context_render_state_init(struct intel_engine_cs *ring, 1458 struct intel_context *ctx) 1459 { 1460 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 1461 struct render_state so; 1462 struct drm_i915_file_private *file_priv = ctx->file_priv; 1463 struct drm_file *file = file_priv ? file_priv->file : NULL; 1464 int ret; 1465 1466 ret = i915_gem_render_state_prepare(ring, &so); 1467 if (ret) 1468 return ret; 1469 1470 if (so.rodata == NULL) 1471 return 0; 1472 1473 ret = ring->emit_bb_start(ringbuf, 1474 so.ggtt_offset, 1475 I915_DISPATCH_SECURE); 1476 if (ret) 1477 goto out; 1478 1479 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring); 1480 1481 ret = __i915_add_request(ring, file, so.obj, NULL); 1482 /* intel_logical_ring_add_request moves object to inactive if it 1483 * fails */ 1484 out: 1485 i915_gem_render_state_fini(&so); 1486 return ret; 1487 } 1488 1489 static int 1490 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, 1491 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) 1492 { 1493 struct drm_device *dev = ring->dev; 1494 struct drm_i915_private *dev_priv = dev->dev_private; 1495 struct drm_i915_gem_object *ring_obj = ringbuf->obj; 1496 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; 1497 struct vm_page *page; 1498 uint32_t *reg_state; 1499 int ret; 1500 1501 if (!ppgtt) 1502 ppgtt = dev_priv->mm.aliasing_ppgtt; 1503 1504 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); 1505 if (ret) { 1506 DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); 1507 return ret; 1508 } 1509 1510 ret = i915_gem_object_get_pages(ctx_obj); 1511 if (ret) { 1512 DRM_DEBUG_DRIVER("Could not get object pages\n"); 1513 return ret; 1514 } 1515 1516 i915_gem_object_pin_pages(ctx_obj); 1517 1518 /* The second page of the context object contains some fields which must 1519 * be set up prior to the first execution. */ 1520 page = i915_gem_object_get_page(ctx_obj, 1); 1521 reg_state = kmap_atomic(page); 1522 1523 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM 1524 * commands followed by (reg, value) pairs. The values we are setting here are 1525 * only for the first context restore: on a subsequent save, the GPU will 1526 * recreate this batchbuffer with new values (including all the missing 1527 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ 1528 if (ring->id == RCS) 1529 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); 1530 else 1531 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); 1532 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; 1533 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); 1534 reg_state[CTX_CONTEXT_CONTROL+1] = 1535 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT); 1536 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); 1537 reg_state[CTX_RING_HEAD+1] = 0; 1538 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); 1539 reg_state[CTX_RING_TAIL+1] = 0; 1540 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); 1541 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); 1542 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); 1543 reg_state[CTX_RING_BUFFER_CONTROL+1] = 1544 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; 1545 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; 1546 reg_state[CTX_BB_HEAD_U+1] = 0; 1547 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; 1548 reg_state[CTX_BB_HEAD_L+1] = 0; 1549 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; 1550 reg_state[CTX_BB_STATE+1] = (1<<5); 1551 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; 1552 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; 1553 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; 1554 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; 1555 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; 1556 reg_state[CTX_SECOND_BB_STATE+1] = 0; 1557 if (ring->id == RCS) { 1558 /* TODO: according to BSpec, the register state context 1559 * for CHV does not have these. OTOH, these registers do 1560 * exist in CHV. I'm waiting for a clarification */ 1561 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; 1562 reg_state[CTX_BB_PER_CTX_PTR+1] = 0; 1563 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; 1564 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; 1565 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; 1566 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; 1567 } 1568 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); 1569 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; 1570 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; 1571 reg_state[CTX_CTX_TIMESTAMP+1] = 0; 1572 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); 1573 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); 1574 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); 1575 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); 1576 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); 1577 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); 1578 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); 1579 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); 1580 reg_state[CTX_PDP3_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[3]); 1581 reg_state[CTX_PDP3_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[3]); 1582 reg_state[CTX_PDP2_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[2]); 1583 reg_state[CTX_PDP2_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[2]); 1584 reg_state[CTX_PDP1_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[1]); 1585 reg_state[CTX_PDP1_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[1]); 1586 reg_state[CTX_PDP0_UDW+1] = upper_32_bits(ppgtt->pd_dma_addr[0]); 1587 reg_state[CTX_PDP0_LDW+1] = lower_32_bits(ppgtt->pd_dma_addr[0]); 1588 if (ring->id == RCS) { 1589 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); 1590 reg_state[CTX_R_PWR_CLK_STATE] = 0x20c8; 1591 reg_state[CTX_R_PWR_CLK_STATE+1] = 0; 1592 } 1593 1594 kunmap_atomic(reg_state); 1595 1596 ctx_obj->dirty = 1; 1597 set_page_dirty(page); 1598 i915_gem_object_unpin_pages(ctx_obj); 1599 1600 return 0; 1601 } 1602 1603 /** 1604 * intel_lr_context_free() - free the LRC specific bits of a context 1605 * @ctx: the LR context to free. 1606 * 1607 * The real context freeing is done in i915_gem_context_free: this only 1608 * takes care of the bits that are LRC related: the per-engine backing 1609 * objects and the logical ringbuffer. 1610 */ 1611 void intel_lr_context_free(struct intel_context *ctx) 1612 { 1613 int i; 1614 1615 for (i = 0; i < I915_NUM_RINGS; i++) { 1616 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; 1617 struct intel_ringbuffer *ringbuf = ctx->engine[i].ringbuf; 1618 1619 if (ctx_obj) { 1620 intel_destroy_ringbuffer_obj(ringbuf); 1621 kfree(ringbuf); 1622 i915_gem_object_ggtt_unpin(ctx_obj); 1623 drm_gem_object_unreference(&ctx_obj->base); 1624 } 1625 } 1626 } 1627 1628 static uint32_t get_lr_context_size(struct intel_engine_cs *ring) 1629 { 1630 int ret = 0; 1631 1632 WARN_ON(INTEL_INFO(ring->dev)->gen != 8); 1633 1634 switch (ring->id) { 1635 case RCS: 1636 ret = GEN8_LR_CONTEXT_RENDER_SIZE; 1637 break; 1638 case VCS: 1639 case BCS: 1640 case VECS: 1641 case VCS2: 1642 ret = GEN8_LR_CONTEXT_OTHER_SIZE; 1643 break; 1644 } 1645 1646 return ret; 1647 } 1648 1649 /** 1650 * intel_lr_context_deferred_create() - create the LRC specific bits of a context 1651 * @ctx: LR context to create. 1652 * @ring: engine to be used with the context. 1653 * 1654 * This function can be called more than once, with different engines, if we plan 1655 * to use the context with them. The context backing objects and the ringbuffers 1656 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why 1657 * the creation is a deferred call: it's better to make sure first that we need to use 1658 * a given ring with the context. 1659 * 1660 * Return: non-zero on eror. 1661 */ 1662 int intel_lr_context_deferred_create(struct intel_context *ctx, 1663 struct intel_engine_cs *ring) 1664 { 1665 struct drm_device *dev = ring->dev; 1666 struct drm_i915_gem_object *ctx_obj; 1667 uint32_t context_size; 1668 struct intel_ringbuffer *ringbuf; 1669 int ret; 1670 1671 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); 1672 if (ctx->engine[ring->id].state) 1673 return 0; 1674 1675 context_size = round_up(get_lr_context_size(ring), 4096); 1676 1677 ctx_obj = i915_gem_alloc_context_obj(dev, context_size); 1678 if (IS_ERR(ctx_obj)) { 1679 ret = PTR_ERR(ctx_obj); 1680 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed: %d\n", ret); 1681 return ret; 1682 } 1683 1684 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); 1685 if (ret) { 1686 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", ret); 1687 drm_gem_object_unreference(&ctx_obj->base); 1688 return ret; 1689 } 1690 1691 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); 1692 if (!ringbuf) { 1693 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", 1694 ring->name); 1695 i915_gem_object_ggtt_unpin(ctx_obj); 1696 drm_gem_object_unreference(&ctx_obj->base); 1697 ret = -ENOMEM; 1698 return ret; 1699 } 1700 1701 ringbuf->ring = ring; 1702 ringbuf->FIXME_lrc_ctx = ctx; 1703 1704 ringbuf->size = 32 * PAGE_SIZE; 1705 ringbuf->effective_size = ringbuf->size; 1706 ringbuf->head = 0; 1707 ringbuf->tail = 0; 1708 ringbuf->space = ringbuf->size; 1709 ringbuf->last_retired_head = -1; 1710 1711 /* TODO: For now we put this in the mappable region so that we can reuse 1712 * the existing ringbuffer code which ioremaps it. When we start 1713 * creating many contexts, this will no longer work and we must switch 1714 * to a kmapish interface. 1715 */ 1716 ret = intel_alloc_ringbuffer_obj(dev, ringbuf); 1717 if (ret) { 1718 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer obj %s: %d\n", 1719 ring->name, ret); 1720 goto error; 1721 } 1722 1723 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); 1724 if (ret) { 1725 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); 1726 intel_destroy_ringbuffer_obj(ringbuf); 1727 goto error; 1728 } 1729 1730 ctx->engine[ring->id].ringbuf = ringbuf; 1731 ctx->engine[ring->id].state = ctx_obj; 1732 1733 if (ctx == ring->default_context) { 1734 /* The status page is offset 0 from the default context object 1735 * in LRC mode. */ 1736 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(ctx_obj); 1737 ring->status_page.page_addr = 1738 kmap(ctx_obj->pages[0]); 1739 if (ring->status_page.page_addr == NULL) 1740 return -ENOMEM; 1741 ring->status_page.obj = ctx_obj; 1742 } 1743 1744 if (ring->id == RCS && !ctx->rcs_initialized) { 1745 ret = intel_lr_context_render_state_init(ring, ctx); 1746 if (ret) { 1747 DRM_ERROR("Init render state failed: %d\n", ret); 1748 ctx->engine[ring->id].ringbuf = NULL; 1749 ctx->engine[ring->id].state = NULL; 1750 intel_destroy_ringbuffer_obj(ringbuf); 1751 goto error; 1752 } 1753 ctx->rcs_initialized = true; 1754 } 1755 1756 return 0; 1757 1758 error: 1759 kfree(ringbuf); 1760 i915_gem_object_ggtt_unpin(ctx_obj); 1761 drm_gem_object_unreference(&ctx_obj->base); 1762 return ret; 1763 } 1764