1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * Michel Thierry <michel.thierry@intel.com> 26 * Thomas Daniel <thomas.daniel@intel.com> 27 * Oscar Mateo <oscar.mateo@intel.com> 28 * 29 */ 30 31 /** 32 * DOC: Logical Rings, Logical Ring Contexts and Execlists 33 * 34 * Motivation: 35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". 36 * These expanded contexts enable a number of new abilities, especially 37 * "Execlists" (also implemented in this file). 38 * 39 * One of the main differences with the legacy HW contexts is that logical 40 * ring contexts incorporate many more things to the context's state, like 41 * PDPs or ringbuffer control registers: 42 * 43 * The reason why PDPs are included in the context is straightforward: as 44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs 45 * contained there mean you don't need to do a ppgtt->switch_mm yourself, 46 * instead, the GPU will do it for you on the context switch. 47 * 48 * But, what about the ringbuffer control registers (head, tail, etc..)? 49 * shouldn't we just need a set of those per engine command streamer? This is 50 * where the name "Logical Rings" starts to make sense: by virtualizing the 51 * rings, the engine cs shifts to a new "ring buffer" with every context 52 * switch. When you want to submit a workload to the GPU you: A) choose your 53 * context, B) find its appropriate virtualized ring, C) write commands to it 54 * and then, finally, D) tell the GPU to switch to that context. 55 * 56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch 57 * to a contexts is via a context execution list, ergo "Execlists". 58 * 59 * LRC implementation: 60 * Regarding the creation of contexts, we have: 61 * 62 * - One global default context. 63 * - One local default context for each opened fd. 64 * - One local extra context for each context create ioctl call. 65 * 66 * Now that ringbuffers belong per-context (and not per-engine, like before) 67 * and that contexts are uniquely tied to a given engine (and not reusable, 68 * like before) we need: 69 * 70 * - One ringbuffer per-engine inside each context. 71 * - One backing object per-engine inside each context. 72 * 73 * The global default context starts its life with these new objects fully 74 * allocated and populated. The local default context for each opened fd is 75 * more complex, because we don't know at creation time which engine is going 76 * to use them. To handle this, we have implemented a deferred creation of LR 77 * contexts: 78 * 79 * The local context starts its life as a hollow or blank holder, that only 80 * gets populated for a given engine once we receive an execbuffer. If later 81 * on we receive another execbuffer ioctl for the same context but a different 82 * engine, we allocate/populate a new ringbuffer and context backing object and 83 * so on. 84 * 85 * Finally, regarding local contexts created using the ioctl call: as they are 86 * only allowed with the render ring, we can allocate & populate them right 87 * away (no need to defer anything, at least for now). 88 * 89 * Execlists implementation: 90 * Execlists are the new method by which, on gen8+ hardware, workloads are 91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method). 92 * This method works as follows: 93 * 94 * When a request is committed, its commands (the BB start and any leading or 95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer 96 * for the appropriate context. The tail pointer in the hardware context is not 97 * updated at this time, but instead, kept by the driver in the ringbuffer 98 * structure. A structure representing this request is added to a request queue 99 * for the appropriate engine: this structure contains a copy of the context's 100 * tail after the request was written to the ring buffer and a pointer to the 101 * context itself. 102 * 103 * If the engine's request queue was empty before the request was added, the 104 * queue is processed immediately. Otherwise the queue will be processed during 105 * a context switch interrupt. In any case, elements on the queue will get sent 106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a 107 * globally unique 20-bits submission ID. 108 * 109 * When execution of a request completes, the GPU updates the context status 110 * buffer with a context complete event and generates a context switch interrupt. 111 * During the interrupt handling, the driver examines the events in the buffer: 112 * for each context complete event, if the announced ID matches that on the head 113 * of the request queue, then that request is retired and removed from the queue. 114 * 115 * After processing, if any requests were retired and the queue is not empty 116 * then a new execution list can be submitted. The two requests at the front of 117 * the queue are next to be submitted but since a context may not occur twice in 118 * an execution list, if subsequent requests have the same ID as the first then 119 * the two requests must be combined. This is done simply by discarding requests 120 * at the head of the queue until either only one requests is left (in which case 121 * we use a NULL second context) or the first two requests have unique IDs. 122 * 123 * By always executing the first two requests in the queue the driver ensures 124 * that the GPU is kept as busy as possible. In the case where a single context 125 * completes but a second context is still executing, the request for this second 126 * context will be at the head of the queue when we remove the first one. This 127 * request will then be resubmitted along with a new request for a different context, 128 * which will cause the hardware to continue executing the second request and queue 129 * the new request (the GPU detects the condition of a context getting preempted 130 * with the same context and optimizes the context switch flow by not doing 131 * preemption, but just sampling the new tail pointer). 132 * 133 */ 134 135 #include <drm/drmP.h> 136 #include <drm/i915_drm.h> 137 #include "i915_drv.h" 138 #include "intel_drv.h" 139 #include "intel_mocs.h" 140 141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) 144 145 #define RING_EXECLIST_QFULL (1 << 0x2) 146 #define RING_EXECLIST1_VALID (1 << 0x3) 147 #define RING_EXECLIST0_VALID (1 << 0x4) 148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) 149 #define RING_EXECLIST1_ACTIVE (1 << 0x11) 150 #define RING_EXECLIST0_ACTIVE (1 << 0x12) 151 152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) 153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) 154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) 155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) 156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4) 157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) 158 159 #define CTX_LRI_HEADER_0 0x01 160 #define CTX_CONTEXT_CONTROL 0x02 161 #define CTX_RING_HEAD 0x04 162 #define CTX_RING_TAIL 0x06 163 #define CTX_RING_BUFFER_START 0x08 164 #define CTX_RING_BUFFER_CONTROL 0x0a 165 #define CTX_BB_HEAD_U 0x0c 166 #define CTX_BB_HEAD_L 0x0e 167 #define CTX_BB_STATE 0x10 168 #define CTX_SECOND_BB_HEAD_U 0x12 169 #define CTX_SECOND_BB_HEAD_L 0x14 170 #define CTX_SECOND_BB_STATE 0x16 171 #define CTX_BB_PER_CTX_PTR 0x18 172 #define CTX_RCS_INDIRECT_CTX 0x1a 173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c 174 #define CTX_LRI_HEADER_1 0x21 175 #define CTX_CTX_TIMESTAMP 0x22 176 #define CTX_PDP3_UDW 0x24 177 #define CTX_PDP3_LDW 0x26 178 #define CTX_PDP2_UDW 0x28 179 #define CTX_PDP2_LDW 0x2a 180 #define CTX_PDP1_UDW 0x2c 181 #define CTX_PDP1_LDW 0x2e 182 #define CTX_PDP0_UDW 0x30 183 #define CTX_PDP0_LDW 0x32 184 #define CTX_LRI_HEADER_2 0x41 185 #define CTX_R_PWR_CLK_STATE 0x42 186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 187 188 #define GEN8_CTX_VALID (1<<0) 189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) 190 #define GEN8_CTX_FORCE_RESTORE (1<<2) 191 #define GEN8_CTX_L3LLC_COHERENT (1<<5) 192 #define GEN8_CTX_PRIVILEGE (1<<8) 193 194 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ 195 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ 196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ 197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ 198 } 199 200 enum { 201 ADVANCED_CONTEXT = 0, 202 LEGACY_CONTEXT, 203 ADVANCED_AD_CONTEXT, 204 LEGACY_64B_CONTEXT 205 }; 206 #define GEN8_CTX_MODE_SHIFT 3 207 enum { 208 FAULT_AND_HANG = 0, 209 FAULT_AND_HALT, /* Debug only */ 210 FAULT_AND_STREAM, 211 FAULT_AND_CONTINUE /* Unsupported */ 212 }; 213 #define GEN8_CTX_ID_SHIFT 32 214 #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 215 216 static int intel_lr_context_pin(struct drm_i915_gem_request *rq); 217 218 /** 219 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists 220 * @dev: DRM device. 221 * @enable_execlists: value of i915.enable_execlists module parameter. 222 * 223 * Only certain platforms support Execlists (the prerequisites being 224 * support for Logical Ring Contexts and Aliasing PPGTT or better). 225 * 226 * Return: 1 if Execlists is supported and has to be enabled. 227 */ 228 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) 229 { 230 WARN_ON(i915.enable_ppgtt == -1); 231 232 if (INTEL_INFO(dev)->gen >= 9) 233 return 1; 234 235 if (enable_execlists == 0) 236 return 0; 237 238 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && 239 i915.use_mmio_flip >= 0) 240 return 1; 241 242 return 0; 243 } 244 245 /** 246 * intel_execlists_ctx_id() - get the Execlists Context ID 247 * @ctx_obj: Logical Ring Context backing object. 248 * 249 * Do not confuse with ctx->id! Unfortunately we have a name overload 250 * here: the old context ID we pass to userspace as a handler so that 251 * they can refer to a context, and the new context ID we pass to the 252 * ELSP so that the GPU can inform us of the context status via 253 * interrupts. 254 * 255 * Return: 20-bits globally unique context ID. 256 */ 257 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) 258 { 259 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); 260 261 /* LRCA is required to be 4K aligned so the more significant 20 bits 262 * are globally unique */ 263 return lrca >> 12; 264 } 265 266 static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request *rq) 267 { 268 struct intel_engine_cs *ring = rq->ring; 269 struct drm_device *dev = ring->dev; 270 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; 271 uint64_t desc; 272 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); 273 274 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); 275 276 desc = GEN8_CTX_VALID; 277 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; 278 if (IS_GEN8(ctx_obj->base.dev)) 279 desc |= GEN8_CTX_L3LLC_COHERENT; 280 desc |= GEN8_CTX_PRIVILEGE; 281 desc |= lrca; 282 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; 283 284 /* TODO: WaDisableLiteRestore when we start using semaphore 285 * signalling between Command Streamers */ 286 /* desc |= GEN8_CTX_FORCE_RESTORE; */ 287 288 /* WaEnableForceRestoreInCtxtDescForVCS:skl */ 289 if (IS_GEN9(dev) && 290 INTEL_REVID(dev) <= SKL_REVID_B0 && 291 (ring->id == BCS || ring->id == VCS || 292 ring->id == VECS || ring->id == VCS2)) 293 desc |= GEN8_CTX_FORCE_RESTORE; 294 295 return desc; 296 } 297 298 static void execlists_elsp_write(struct drm_i915_gem_request *rq0, 299 struct drm_i915_gem_request *rq1) 300 { 301 302 struct intel_engine_cs *ring = rq0->ring; 303 struct drm_device *dev = ring->dev; 304 struct drm_i915_private *dev_priv = dev->dev_private; 305 uint64_t desc[2]; 306 307 if (rq1) { 308 desc[1] = execlists_ctx_descriptor(rq1); 309 rq1->elsp_submitted++; 310 } else { 311 desc[1] = 0; 312 } 313 314 desc[0] = execlists_ctx_descriptor(rq0); 315 rq0->elsp_submitted++; 316 317 /* You must always write both descriptors in the order below. */ 318 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 319 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); 320 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1])); 321 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1])); 322 323 I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0])); 324 /* The context is automatically loaded after the following */ 325 I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0])); 326 327 /* ELSP is a wo register, use another nearby reg for posting */ 328 POSTING_READ_FW(RING_EXECLIST_STATUS(ring)); 329 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); 330 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 331 } 332 333 static int execlists_update_context(struct drm_i915_gem_request *rq) 334 { 335 struct intel_engine_cs *ring = rq->ring; 336 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; 337 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; 338 struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj; 339 struct vm_page *page; 340 uint32_t *reg_state; 341 342 BUG_ON(!ctx_obj); 343 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj)); 344 WARN_ON(!i915_gem_obj_is_pinned(rb_obj)); 345 346 page = i915_gem_object_get_page(ctx_obj, 1); 347 reg_state = kmap_atomic(page); 348 349 reg_state[CTX_RING_TAIL+1] = rq->tail; 350 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj); 351 352 /* True PPGTT with dynamic page allocation: update PDP registers and 353 * point the unallocated PDPs to the scratch page 354 */ 355 if (ppgtt) { 356 ASSIGN_CTX_PDP(ppgtt, reg_state, 3); 357 ASSIGN_CTX_PDP(ppgtt, reg_state, 2); 358 ASSIGN_CTX_PDP(ppgtt, reg_state, 1); 359 ASSIGN_CTX_PDP(ppgtt, reg_state, 0); 360 } 361 362 kunmap_atomic(reg_state); 363 364 return 0; 365 } 366 367 static void execlists_submit_requests(struct drm_i915_gem_request *rq0, 368 struct drm_i915_gem_request *rq1) 369 { 370 execlists_update_context(rq0); 371 372 if (rq1) 373 execlists_update_context(rq1); 374 375 execlists_elsp_write(rq0, rq1); 376 } 377 378 static void execlists_context_unqueue(struct intel_engine_cs *ring) 379 { 380 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; 381 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL; 382 383 assert_spin_locked(&ring->execlist_lock); 384 385 /* 386 * If irqs are not active generate a warning as batches that finish 387 * without the irqs may get lost and a GPU Hang may occur. 388 */ 389 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private)); 390 391 if (list_empty(&ring->execlist_queue)) 392 return; 393 394 /* Try to read in pairs */ 395 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, 396 execlist_link) { 397 if (!req0) { 398 req0 = cursor; 399 } else if (req0->ctx == cursor->ctx) { 400 /* Same ctx: ignore first request, as second request 401 * will update tail past first request's workload */ 402 cursor->elsp_submitted = req0->elsp_submitted; 403 list_del(&req0->execlist_link); 404 list_add_tail(&req0->execlist_link, 405 &ring->execlist_retired_req_list); 406 req0 = cursor; 407 } else { 408 req1 = cursor; 409 break; 410 } 411 } 412 413 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) { 414 /* 415 * WaIdleLiteRestore: make sure we never cause a lite 416 * restore with HEAD==TAIL 417 */ 418 if (req0->elsp_submitted) { 419 /* 420 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL 421 * as we resubmit the request. See gen8_emit_request() 422 * for where we prepare the padding after the end of the 423 * request. 424 */ 425 struct intel_ringbuffer *ringbuf; 426 427 ringbuf = req0->ctx->engine[ring->id].ringbuf; 428 req0->tail += 8; 429 req0->tail &= ringbuf->size - 1; 430 } 431 } 432 433 WARN_ON(req1 && req1->elsp_submitted); 434 435 execlists_submit_requests(req0, req1); 436 } 437 438 static bool execlists_check_remove_request(struct intel_engine_cs *ring, 439 u32 request_id) 440 { 441 struct drm_i915_gem_request *head_req; 442 443 assert_spin_locked(&ring->execlist_lock); 444 445 head_req = list_first_entry_or_null(&ring->execlist_queue, 446 struct drm_i915_gem_request, 447 execlist_link); 448 449 if (head_req != NULL) { 450 struct drm_i915_gem_object *ctx_obj = 451 head_req->ctx->engine[ring->id].state; 452 if (intel_execlists_ctx_id(ctx_obj) == request_id) { 453 WARN(head_req->elsp_submitted == 0, 454 "Never submitted head request\n"); 455 456 if (--head_req->elsp_submitted <= 0) { 457 list_del(&head_req->execlist_link); 458 list_add_tail(&head_req->execlist_link, 459 &ring->execlist_retired_req_list); 460 return true; 461 } 462 } 463 } 464 465 return false; 466 } 467 468 /** 469 * intel_lrc_irq_handler() - handle Context Switch interrupts 470 * @ring: Engine Command Streamer to handle. 471 * 472 * Check the unread Context Status Buffers and manage the submission of new 473 * contexts to the ELSP accordingly. 474 */ 475 void intel_lrc_irq_handler(struct intel_engine_cs *ring) 476 { 477 struct drm_i915_private *dev_priv = ring->dev->dev_private; 478 u32 status_pointer; 479 u8 read_pointer; 480 u8 write_pointer; 481 u32 status; 482 u32 status_id; 483 u32 submit_contexts = 0; 484 485 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); 486 487 read_pointer = ring->next_context_status_buffer; 488 write_pointer = status_pointer & GEN8_CSB_PTR_MASK; 489 if (read_pointer > write_pointer) 490 write_pointer += GEN8_CSB_ENTRIES; 491 492 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 493 494 while (read_pointer < write_pointer) { 495 read_pointer++; 496 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 497 (read_pointer % GEN8_CSB_ENTRIES) * 8); 498 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 499 (read_pointer % GEN8_CSB_ENTRIES) * 8 + 4); 500 501 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) 502 continue; 503 504 if (status & GEN8_CTX_STATUS_PREEMPTED) { 505 if (status & GEN8_CTX_STATUS_LITE_RESTORE) { 506 if (execlists_check_remove_request(ring, status_id)) 507 WARN(1, "Lite Restored request removed from queue\n"); 508 } else 509 WARN(1, "Preemption without Lite Restore\n"); 510 } 511 512 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || 513 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { 514 if (execlists_check_remove_request(ring, status_id)) 515 submit_contexts++; 516 } 517 } 518 519 if (submit_contexts != 0) 520 execlists_context_unqueue(ring); 521 522 lockmgr(&ring->execlist_lock, LK_RELEASE); 523 524 WARN(submit_contexts > 2, "More than two context complete events?\n"); 525 ring->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES; 526 527 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), 528 _MASKED_FIELD(GEN8_CSB_PTR_MASK << 8, 529 ((u32)ring->next_context_status_buffer & 530 GEN8_CSB_PTR_MASK) << 8)); 531 } 532 533 static int execlists_context_queue(struct drm_i915_gem_request *request) 534 { 535 struct intel_engine_cs *ring = request->ring; 536 struct drm_i915_gem_request *cursor; 537 int num_elements = 0; 538 539 if (request->ctx != ring->default_context) 540 intel_lr_context_pin(request); 541 542 i915_gem_request_reference(request); 543 544 request->tail = request->ringbuf->tail; 545 546 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 547 548 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) 549 if (++num_elements > 2) 550 break; 551 552 if (num_elements > 2) { 553 struct drm_i915_gem_request *tail_req; 554 555 tail_req = list_last_entry(&ring->execlist_queue, 556 struct drm_i915_gem_request, 557 execlist_link); 558 559 if (request->ctx == tail_req->ctx) { 560 WARN(tail_req->elsp_submitted != 0, 561 "More than 2 already-submitted reqs queued\n"); 562 list_del(&tail_req->execlist_link); 563 list_add_tail(&tail_req->execlist_link, 564 &ring->execlist_retired_req_list); 565 } 566 } 567 568 list_add_tail(&request->execlist_link, &ring->execlist_queue); 569 if (num_elements == 0) 570 execlists_context_unqueue(ring); 571 572 lockmgr(&ring->execlist_lock, LK_RELEASE); 573 574 return 0; 575 } 576 577 static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) 578 { 579 struct intel_engine_cs *ring = req->ring; 580 uint32_t flush_domains; 581 int ret; 582 583 flush_domains = 0; 584 if (ring->gpu_caches_dirty) 585 flush_domains = I915_GEM_GPU_DOMAINS; 586 587 ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); 588 if (ret) 589 return ret; 590 591 ring->gpu_caches_dirty = false; 592 return 0; 593 } 594 595 static int execlists_move_to_gpu(struct drm_i915_gem_request *req, 596 struct list_head *vmas) 597 { 598 const unsigned other_rings = ~intel_ring_flag(req->ring); 599 struct i915_vma *vma; 600 uint32_t flush_domains = 0; 601 bool flush_chipset = false; 602 int ret; 603 604 list_for_each_entry(vma, vmas, exec_list) { 605 struct drm_i915_gem_object *obj = vma->obj; 606 607 if (obj->active & other_rings) { 608 ret = i915_gem_object_sync(obj, req->ring, &req); 609 if (ret) 610 return ret; 611 } 612 613 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) 614 flush_chipset |= i915_gem_clflush_object(obj, false); 615 616 flush_domains |= obj->base.write_domain; 617 } 618 619 if (flush_domains & I915_GEM_DOMAIN_GTT) 620 wmb(); 621 622 /* Unconditionally invalidate gpu caches and ensure that we do flush 623 * any residual writes from the previous batch. 624 */ 625 return logical_ring_invalidate_all_caches(req); 626 } 627 628 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) 629 { 630 int ret; 631 632 request->ringbuf = request->ctx->engine[request->ring->id].ringbuf; 633 634 if (request->ctx != request->ring->default_context) { 635 ret = intel_lr_context_pin(request); 636 if (ret) 637 return ret; 638 } 639 640 return 0; 641 } 642 643 static int logical_ring_wait_for_space(struct drm_i915_gem_request *req, 644 int bytes) 645 { 646 struct intel_ringbuffer *ringbuf = req->ringbuf; 647 struct intel_engine_cs *ring = req->ring; 648 struct drm_i915_gem_request *target; 649 unsigned space; 650 int ret; 651 652 if (intel_ring_space(ringbuf) >= bytes) 653 return 0; 654 655 /* The whole point of reserving space is to not wait! */ 656 WARN_ON(ringbuf->reserved_in_use); 657 658 list_for_each_entry(target, &ring->request_list, list) { 659 /* 660 * The request queue is per-engine, so can contain requests 661 * from multiple ringbuffers. Here, we must ignore any that 662 * aren't from the ringbuffer we're considering. 663 */ 664 if (target->ringbuf != ringbuf) 665 continue; 666 667 /* Would completion of this request free enough space? */ 668 space = __intel_ring_space(target->postfix, ringbuf->tail, 669 ringbuf->size); 670 if (space >= bytes) 671 break; 672 } 673 674 if (WARN_ON(&target->list == &ring->request_list)) 675 return -ENOSPC; 676 677 ret = i915_wait_request(target); 678 if (ret) 679 return ret; 680 681 ringbuf->space = space; 682 return 0; 683 } 684 685 /* 686 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload 687 * @request: Request to advance the logical ringbuffer of. 688 * 689 * The tail is updated in our logical ringbuffer struct, not in the actual context. What 690 * really happens during submission is that the context and current tail will be placed 691 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that 692 * point, the tail *inside* the context is updated and the ELSP written to. 693 */ 694 static void 695 intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) 696 { 697 struct intel_engine_cs *ring = request->ring; 698 699 intel_logical_ring_advance(request->ringbuf); 700 701 if (intel_ring_stopped(ring)) 702 return; 703 704 execlists_context_queue(request); 705 } 706 707 static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) 708 { 709 uint32_t __iomem *virt; 710 int rem = ringbuf->size - ringbuf->tail; 711 712 virt = (uint32_t *)(ringbuf->virtual_start + ringbuf->tail); 713 rem /= 4; 714 while (rem--) 715 iowrite32(MI_NOOP, virt++); 716 717 ringbuf->tail = 0; 718 intel_ring_update_space(ringbuf); 719 } 720 721 static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) 722 { 723 struct intel_ringbuffer *ringbuf = req->ringbuf; 724 int remain_usable = ringbuf->effective_size - ringbuf->tail; 725 int remain_actual = ringbuf->size - ringbuf->tail; 726 int ret, total_bytes, wait_bytes = 0; 727 bool need_wrap = false; 728 729 if (ringbuf->reserved_in_use) 730 total_bytes = bytes; 731 else 732 total_bytes = bytes + ringbuf->reserved_size; 733 734 if (unlikely(bytes > remain_usable)) { 735 /* 736 * Not enough space for the basic request. So need to flush 737 * out the remainder and then wait for base + reserved. 738 */ 739 wait_bytes = remain_actual + total_bytes; 740 need_wrap = true; 741 } else { 742 if (unlikely(total_bytes > remain_usable)) { 743 /* 744 * The base request will fit but the reserved space 745 * falls off the end. So only need to to wait for the 746 * reserved size after flushing out the remainder. 747 */ 748 wait_bytes = remain_actual + ringbuf->reserved_size; 749 need_wrap = true; 750 } else if (total_bytes > ringbuf->space) { 751 /* No wrapping required, just waiting. */ 752 wait_bytes = total_bytes; 753 } 754 } 755 756 if (wait_bytes) { 757 ret = logical_ring_wait_for_space(req, wait_bytes); 758 if (unlikely(ret)) 759 return ret; 760 761 if (need_wrap) 762 __wrap_ring_buffer(ringbuf); 763 } 764 765 return 0; 766 } 767 768 /** 769 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands 770 * 771 * @request: The request to start some new work for 772 * @ctx: Logical ring context whose ringbuffer is being prepared. 773 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. 774 * 775 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to 776 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that 777 * and also preallocates a request (every workload submission is still mediated through 778 * requests, same as it did with legacy ringbuffer submission). 779 * 780 * Return: non-zero if the ringbuffer is not ready to be written to. 781 */ 782 int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords) 783 { 784 struct drm_i915_private *dev_priv; 785 int ret; 786 787 WARN_ON(req == NULL); 788 dev_priv = req->ring->dev->dev_private; 789 790 ret = i915_gem_check_wedge(&dev_priv->gpu_error, 791 dev_priv->mm.interruptible); 792 if (ret) 793 return ret; 794 795 ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t)); 796 if (ret) 797 return ret; 798 799 req->ringbuf->space -= num_dwords * sizeof(uint32_t); 800 return 0; 801 } 802 803 int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request) 804 { 805 /* 806 * The first call merely notes the reserve request and is common for 807 * all back ends. The subsequent localised _begin() call actually 808 * ensures that the reservation is available. Without the begin, if 809 * the request creator immediately submitted the request without 810 * adding any commands to it then there might not actually be 811 * sufficient room for the submission commands. 812 */ 813 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); 814 815 return intel_logical_ring_begin(request, 0); 816 } 817 818 /** 819 * execlists_submission() - submit a batchbuffer for execution, Execlists style 820 * @dev: DRM device. 821 * @file: DRM file. 822 * @ring: Engine Command Streamer to submit to. 823 * @ctx: Context to employ for this submission. 824 * @args: execbuffer call arguments. 825 * @vmas: list of vmas. 826 * @batch_obj: the batchbuffer to submit. 827 * @exec_start: batchbuffer start virtual address pointer. 828 * @dispatch_flags: translated execbuffer call flags. 829 * 830 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts 831 * away the submission details of the execbuffer ioctl call. 832 * 833 * Return: non-zero if the submission fails. 834 */ 835 int intel_execlists_submission(struct i915_execbuffer_params *params, 836 struct drm_i915_gem_execbuffer2 *args, 837 struct list_head *vmas) 838 { 839 struct drm_device *dev = params->dev; 840 struct intel_engine_cs *ring = params->ring; 841 struct drm_i915_private *dev_priv = dev->dev_private; 842 struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf; 843 u64 exec_start; 844 int instp_mode; 845 u32 instp_mask; 846 int ret; 847 848 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; 849 instp_mask = I915_EXEC_CONSTANTS_MASK; 850 switch (instp_mode) { 851 case I915_EXEC_CONSTANTS_REL_GENERAL: 852 case I915_EXEC_CONSTANTS_ABSOLUTE: 853 case I915_EXEC_CONSTANTS_REL_SURFACE: 854 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { 855 DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); 856 return -EINVAL; 857 } 858 859 if (instp_mode != dev_priv->relative_constants_mode) { 860 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { 861 DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); 862 return -EINVAL; 863 } 864 865 /* The HW changed the meaning on this bit on gen6 */ 866 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; 867 } 868 break; 869 default: 870 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); 871 return -EINVAL; 872 } 873 874 if (args->num_cliprects != 0) { 875 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); 876 return -EINVAL; 877 } else { 878 if (args->DR4 == 0xffffffff) { 879 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); 880 args->DR4 = 0; 881 } 882 883 if (args->DR1 || args->DR4 || args->cliprects_ptr) { 884 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); 885 return -EINVAL; 886 } 887 } 888 889 if (args->flags & I915_EXEC_GEN7_SOL_RESET) { 890 DRM_DEBUG("sol reset is gen7 only\n"); 891 return -EINVAL; 892 } 893 894 ret = execlists_move_to_gpu(params->request, vmas); 895 if (ret) 896 return ret; 897 898 if (ring == &dev_priv->ring[RCS] && 899 instp_mode != dev_priv->relative_constants_mode) { 900 ret = intel_logical_ring_begin(params->request, 4); 901 if (ret) 902 return ret; 903 904 intel_logical_ring_emit(ringbuf, MI_NOOP); 905 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); 906 intel_logical_ring_emit(ringbuf, INSTPM); 907 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); 908 intel_logical_ring_advance(ringbuf); 909 910 dev_priv->relative_constants_mode = instp_mode; 911 } 912 913 exec_start = params->batch_obj_vm_offset + 914 args->batch_start_offset; 915 916 ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags); 917 if (ret) 918 return ret; 919 920 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); 921 922 i915_gem_execbuffer_move_to_active(vmas, params->request); 923 i915_gem_execbuffer_retire_commands(params); 924 925 return 0; 926 } 927 928 void intel_execlists_retire_requests(struct intel_engine_cs *ring) 929 { 930 struct drm_i915_gem_request *req, *tmp; 931 struct list_head retired_list; 932 933 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 934 if (list_empty(&ring->execlist_retired_req_list)) 935 return; 936 937 INIT_LIST_HEAD(&retired_list); 938 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 939 list_replace_init(&ring->execlist_retired_req_list, &retired_list); 940 lockmgr(&ring->execlist_lock, LK_RELEASE); 941 942 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { 943 struct intel_context *ctx = req->ctx; 944 struct drm_i915_gem_object *ctx_obj = 945 ctx->engine[ring->id].state; 946 947 if (ctx_obj && (ctx != ring->default_context)) 948 intel_lr_context_unpin(req); 949 list_del(&req->execlist_link); 950 i915_gem_request_unreference(req); 951 } 952 } 953 954 void intel_logical_ring_stop(struct intel_engine_cs *ring) 955 { 956 struct drm_i915_private *dev_priv = ring->dev->dev_private; 957 int ret; 958 959 if (!intel_ring_initialized(ring)) 960 return; 961 962 ret = intel_ring_idle(ring); 963 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) 964 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", 965 ring->name, ret); 966 967 /* TODO: Is this correct with Execlists enabled? */ 968 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); 969 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { 970 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); 971 return; 972 } 973 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); 974 } 975 976 int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) 977 { 978 struct intel_engine_cs *ring = req->ring; 979 int ret; 980 981 if (!ring->gpu_caches_dirty) 982 return 0; 983 984 ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); 985 if (ret) 986 return ret; 987 988 ring->gpu_caches_dirty = false; 989 return 0; 990 } 991 992 static int intel_lr_context_pin(struct drm_i915_gem_request *rq) 993 { 994 struct intel_engine_cs *ring = rq->ring; 995 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; 996 struct intel_ringbuffer *ringbuf = rq->ringbuf; 997 int ret = 0; 998 999 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 1000 if (rq->ctx->engine[ring->id].pin_count++ == 0) { 1001 ret = i915_gem_obj_ggtt_pin(ctx_obj, 1002 GEN8_LR_CONTEXT_ALIGN, 0); 1003 if (ret) 1004 goto reset_pin_count; 1005 1006 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); 1007 if (ret) 1008 goto unpin_ctx_obj; 1009 1010 ctx_obj->dirty = true; 1011 } 1012 1013 return ret; 1014 1015 unpin_ctx_obj: 1016 i915_gem_object_ggtt_unpin(ctx_obj); 1017 reset_pin_count: 1018 rq->ctx->engine[ring->id].pin_count = 0; 1019 1020 return ret; 1021 } 1022 1023 void intel_lr_context_unpin(struct drm_i915_gem_request *rq) 1024 { 1025 struct intel_engine_cs *ring = rq->ring; 1026 struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; 1027 struct intel_ringbuffer *ringbuf = rq->ringbuf; 1028 1029 if (ctx_obj) { 1030 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 1031 if (--rq->ctx->engine[ring->id].pin_count == 0) { 1032 intel_unpin_ringbuffer_obj(ringbuf); 1033 i915_gem_object_ggtt_unpin(ctx_obj); 1034 } 1035 } 1036 } 1037 1038 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) 1039 { 1040 int ret, i; 1041 struct intel_engine_cs *ring = req->ring; 1042 struct intel_ringbuffer *ringbuf = req->ringbuf; 1043 struct drm_device *dev = ring->dev; 1044 struct drm_i915_private *dev_priv = dev->dev_private; 1045 struct i915_workarounds *w = &dev_priv->workarounds; 1046 1047 if (WARN_ON_ONCE(w->count == 0)) 1048 return 0; 1049 1050 ring->gpu_caches_dirty = true; 1051 ret = logical_ring_flush_all_caches(req); 1052 if (ret) 1053 return ret; 1054 1055 ret = intel_logical_ring_begin(req, w->count * 2 + 2); 1056 if (ret) 1057 return ret; 1058 1059 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); 1060 for (i = 0; i < w->count; i++) { 1061 intel_logical_ring_emit(ringbuf, w->reg[i].addr); 1062 intel_logical_ring_emit(ringbuf, w->reg[i].value); 1063 } 1064 intel_logical_ring_emit(ringbuf, MI_NOOP); 1065 1066 intel_logical_ring_advance(ringbuf); 1067 1068 ring->gpu_caches_dirty = true; 1069 ret = logical_ring_flush_all_caches(req); 1070 if (ret) 1071 return ret; 1072 1073 return 0; 1074 } 1075 1076 #define wa_ctx_emit(batch, index, cmd) \ 1077 do { \ 1078 int __index = (index)++; \ 1079 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ 1080 return -ENOSPC; \ 1081 } \ 1082 batch[__index] = (cmd); \ 1083 } while (0) 1084 1085 1086 /* 1087 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after 1088 * PIPE_CONTROL instruction. This is required for the flush to happen correctly 1089 * but there is a slight complication as this is applied in WA batch where the 1090 * values are only initialized once so we cannot take register value at the 1091 * beginning and reuse it further; hence we save its value to memory, upload a 1092 * constant value with bit21 set and then we restore it back with the saved value. 1093 * To simplify the WA, a constant value is formed by using the default value 1094 * of this register. This shouldn't be a problem because we are only modifying 1095 * it for a short period and this batch in non-premptible. We can ofcourse 1096 * use additional instructions that read the actual value of the register 1097 * at that time and set our bit of interest but it makes the WA complicated. 1098 * 1099 * This WA is also required for Gen9 so extracting as a function avoids 1100 * code duplication. 1101 */ 1102 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring, 1103 uint32_t *const batch, 1104 uint32_t index) 1105 { 1106 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); 1107 1108 /* 1109 * WaDisableLSQCROPERFforOCL:skl 1110 * This WA is implemented in skl_init_clock_gating() but since 1111 * this batch updates GEN8_L3SQCREG4 with default value we need to 1112 * set this bit here to retain the WA during flush. 1113 */ 1114 if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0) 1115 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; 1116 1117 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8(1) | 1118 MI_SRM_LRM_GLOBAL_GTT)); 1119 wa_ctx_emit(batch, index, GEN8_L3SQCREG4); 1120 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256); 1121 wa_ctx_emit(batch, index, 0); 1122 1123 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); 1124 wa_ctx_emit(batch, index, GEN8_L3SQCREG4); 1125 wa_ctx_emit(batch, index, l3sqc4_flush); 1126 1127 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); 1128 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | 1129 PIPE_CONTROL_DC_FLUSH_ENABLE)); 1130 wa_ctx_emit(batch, index, 0); 1131 wa_ctx_emit(batch, index, 0); 1132 wa_ctx_emit(batch, index, 0); 1133 wa_ctx_emit(batch, index, 0); 1134 1135 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8(1) | 1136 MI_SRM_LRM_GLOBAL_GTT)); 1137 wa_ctx_emit(batch, index, GEN8_L3SQCREG4); 1138 wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256); 1139 wa_ctx_emit(batch, index, 0); 1140 1141 return index; 1142 } 1143 1144 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, 1145 uint32_t offset, 1146 uint32_t start_alignment) 1147 { 1148 return wa_ctx->offset = ALIGN(offset, start_alignment); 1149 } 1150 1151 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, 1152 uint32_t offset, 1153 uint32_t size_alignment) 1154 { 1155 wa_ctx->size = offset - wa_ctx->offset; 1156 1157 WARN(wa_ctx->size % size_alignment, 1158 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", 1159 wa_ctx->size, size_alignment); 1160 return 0; 1161 } 1162 1163 /** 1164 * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA 1165 * 1166 * @ring: only applicable for RCS 1167 * @wa_ctx: structure representing wa_ctx 1168 * offset: specifies start of the batch, should be cache-aligned. This is updated 1169 * with the offset value received as input. 1170 * size: size of the batch in DWORDS but HW expects in terms of cachelines 1171 * @batch: page in which WA are loaded 1172 * @offset: This field specifies the start of the batch, it should be 1173 * cache-aligned otherwise it is adjusted accordingly. 1174 * Typically we only have one indirect_ctx and per_ctx batch buffer which are 1175 * initialized at the beginning and shared across all contexts but this field 1176 * helps us to have multiple batches at different offsets and select them based 1177 * on a criteria. At the moment this batch always start at the beginning of the page 1178 * and at this point we don't have multiple wa_ctx batch buffers. 1179 * 1180 * The number of WA applied are not known at the beginning; we use this field 1181 * to return the no of DWORDS written. 1182 * 1183 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END 1184 * so it adds NOOPs as padding to make it cacheline aligned. 1185 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together 1186 * makes a complete batch buffer. 1187 * 1188 * Return: non-zero if we exceed the PAGE_SIZE limit. 1189 */ 1190 1191 static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, 1192 struct i915_wa_ctx_bb *wa_ctx, 1193 uint32_t *const batch, 1194 uint32_t *offset) 1195 { 1196 uint32_t scratch_addr; 1197 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); 1198 1199 /* WaDisableCtxRestoreArbitration:bdw,chv */ 1200 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); 1201 1202 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ 1203 if (IS_BROADWELL(ring->dev)) { 1204 index = gen8_emit_flush_coherentl3_wa(ring, batch, index); 1205 if (index < 0) 1206 return index; 1207 } 1208 1209 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ 1210 /* Actual scratch location is at 128 bytes offset */ 1211 scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES; 1212 1213 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); 1214 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | 1215 PIPE_CONTROL_GLOBAL_GTT_IVB | 1216 PIPE_CONTROL_CS_STALL | 1217 PIPE_CONTROL_QW_WRITE)); 1218 wa_ctx_emit(batch, index, scratch_addr); 1219 wa_ctx_emit(batch, index, 0); 1220 wa_ctx_emit(batch, index, 0); 1221 wa_ctx_emit(batch, index, 0); 1222 1223 /* Pad to end of cacheline */ 1224 while (index % CACHELINE_DWORDS) 1225 wa_ctx_emit(batch, index, MI_NOOP); 1226 1227 /* 1228 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because 1229 * execution depends on the length specified in terms of cache lines 1230 * in the register CTX_RCS_INDIRECT_CTX 1231 */ 1232 1233 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); 1234 } 1235 1236 /** 1237 * gen8_init_perctx_bb() - initialize per ctx batch with WA 1238 * 1239 * @ring: only applicable for RCS 1240 * @wa_ctx: structure representing wa_ctx 1241 * offset: specifies start of the batch, should be cache-aligned. 1242 * size: size of the batch in DWORDS but HW expects in terms of cachelines 1243 * @batch: page in which WA are loaded 1244 * @offset: This field specifies the start of this batch. 1245 * This batch is started immediately after indirect_ctx batch. Since we ensure 1246 * that indirect_ctx ends on a cacheline this batch is aligned automatically. 1247 * 1248 * The number of DWORDS written are returned using this field. 1249 * 1250 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding 1251 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. 1252 */ 1253 static int gen8_init_perctx_bb(struct intel_engine_cs *ring, 1254 struct i915_wa_ctx_bb *wa_ctx, 1255 uint32_t *const batch, 1256 uint32_t *offset) 1257 { 1258 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); 1259 1260 /* WaDisableCtxRestoreArbitration:bdw,chv */ 1261 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); 1262 1263 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); 1264 1265 return wa_ctx_end(wa_ctx, *offset = index, 1); 1266 } 1267 1268 static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, 1269 struct i915_wa_ctx_bb *wa_ctx, 1270 uint32_t *const batch, 1271 uint32_t *offset) 1272 { 1273 int ret; 1274 struct drm_device *dev = ring->dev; 1275 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); 1276 1277 /* WaDisableCtxRestoreArbitration:skl,bxt */ 1278 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || 1279 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) 1280 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); 1281 1282 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ 1283 ret = gen8_emit_flush_coherentl3_wa(ring, batch, index); 1284 if (ret < 0) 1285 return ret; 1286 index = ret; 1287 1288 /* Pad to end of cacheline */ 1289 while (index % CACHELINE_DWORDS) 1290 wa_ctx_emit(batch, index, MI_NOOP); 1291 1292 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); 1293 } 1294 1295 static int gen9_init_perctx_bb(struct intel_engine_cs *ring, 1296 struct i915_wa_ctx_bb *wa_ctx, 1297 uint32_t *const batch, 1298 uint32_t *offset) 1299 { 1300 struct drm_device *dev = ring->dev; 1301 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); 1302 1303 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ 1304 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || 1305 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) { 1306 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); 1307 wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); 1308 wa_ctx_emit(batch, index, 1309 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); 1310 wa_ctx_emit(batch, index, MI_NOOP); 1311 } 1312 1313 /* WaDisableCtxRestoreArbitration:skl,bxt */ 1314 if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || 1315 (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) 1316 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); 1317 1318 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); 1319 1320 return wa_ctx_end(wa_ctx, *offset = index, 1); 1321 } 1322 1323 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size) 1324 { 1325 int ret; 1326 1327 ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size)); 1328 if (!ring->wa_ctx.obj) { 1329 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); 1330 return -ENOMEM; 1331 } 1332 1333 ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0); 1334 if (ret) { 1335 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", 1336 ret); 1337 drm_gem_object_unreference(&ring->wa_ctx.obj->base); 1338 return ret; 1339 } 1340 1341 return 0; 1342 } 1343 1344 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring) 1345 { 1346 if (ring->wa_ctx.obj) { 1347 i915_gem_object_ggtt_unpin(ring->wa_ctx.obj); 1348 drm_gem_object_unreference(&ring->wa_ctx.obj->base); 1349 ring->wa_ctx.obj = NULL; 1350 } 1351 } 1352 1353 static int intel_init_workaround_bb(struct intel_engine_cs *ring) 1354 { 1355 int ret; 1356 uint32_t *batch; 1357 uint32_t offset; 1358 struct vm_page *page; 1359 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; 1360 1361 WARN_ON(ring->id != RCS); 1362 1363 /* update this when WA for higher Gen are added */ 1364 if (INTEL_INFO(ring->dev)->gen > 9) { 1365 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", 1366 INTEL_INFO(ring->dev)->gen); 1367 return 0; 1368 } 1369 1370 /* some WA perform writes to scratch page, ensure it is valid */ 1371 if (ring->scratch.obj == NULL) { 1372 DRM_ERROR("scratch page not allocated for %s\n", ring->name); 1373 return -EINVAL; 1374 } 1375 1376 ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE); 1377 if (ret) { 1378 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); 1379 return ret; 1380 } 1381 1382 page = i915_gem_object_get_page(wa_ctx->obj, 0); 1383 batch = kmap_atomic(page); 1384 offset = 0; 1385 1386 if (INTEL_INFO(ring->dev)->gen == 8) { 1387 ret = gen8_init_indirectctx_bb(ring, 1388 &wa_ctx->indirect_ctx, 1389 batch, 1390 &offset); 1391 if (ret) 1392 goto out; 1393 1394 ret = gen8_init_perctx_bb(ring, 1395 &wa_ctx->per_ctx, 1396 batch, 1397 &offset); 1398 if (ret) 1399 goto out; 1400 } else if (INTEL_INFO(ring->dev)->gen == 9) { 1401 ret = gen9_init_indirectctx_bb(ring, 1402 &wa_ctx->indirect_ctx, 1403 batch, 1404 &offset); 1405 if (ret) 1406 goto out; 1407 1408 ret = gen9_init_perctx_bb(ring, 1409 &wa_ctx->per_ctx, 1410 batch, 1411 &offset); 1412 if (ret) 1413 goto out; 1414 } 1415 1416 out: 1417 kunmap_atomic(batch); 1418 if (ret) 1419 lrc_destroy_wa_ctx_obj(ring); 1420 1421 return ret; 1422 } 1423 1424 static int gen8_init_common_ring(struct intel_engine_cs *ring) 1425 { 1426 struct drm_device *dev = ring->dev; 1427 struct drm_i915_private *dev_priv = dev->dev_private; 1428 u8 next_context_status_buffer_hw; 1429 1430 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); 1431 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); 1432 1433 if (ring->status_page.obj) { 1434 I915_WRITE(RING_HWS_PGA(ring->mmio_base), 1435 (u32)ring->status_page.gfx_addr); 1436 POSTING_READ(RING_HWS_PGA(ring->mmio_base)); 1437 } 1438 1439 I915_WRITE(RING_MODE_GEN7(ring), 1440 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | 1441 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); 1442 POSTING_READ(RING_MODE_GEN7(ring)); 1443 1444 /* 1445 * Instead of resetting the Context Status Buffer (CSB) read pointer to 1446 * zero, we need to read the write pointer from hardware and use its 1447 * value because "this register is power context save restored". 1448 * Effectively, these states have been observed: 1449 * 1450 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) | 1451 * BDW | CSB regs not reset | CSB regs reset | 1452 * CHT | CSB regs not reset | CSB regs not reset | 1453 */ 1454 next_context_status_buffer_hw = (I915_READ(RING_CONTEXT_STATUS_PTR(ring)) 1455 & GEN8_CSB_PTR_MASK); 1456 1457 /* 1458 * When the CSB registers are reset (also after power-up / gpu reset), 1459 * CSB write pointer is set to all 1's, which is not valid, use '5' in 1460 * this special case, so the first element read is CSB[0]. 1461 */ 1462 if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK) 1463 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1); 1464 1465 ring->next_context_status_buffer = next_context_status_buffer_hw; 1466 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); 1467 1468 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); 1469 1470 return 0; 1471 } 1472 1473 static int gen8_init_render_ring(struct intel_engine_cs *ring) 1474 { 1475 struct drm_device *dev = ring->dev; 1476 struct drm_i915_private *dev_priv = dev->dev_private; 1477 int ret; 1478 1479 ret = gen8_init_common_ring(ring); 1480 if (ret) 1481 return ret; 1482 1483 /* We need to disable the AsyncFlip performance optimisations in order 1484 * to use MI_WAIT_FOR_EVENT within the CS. It should already be 1485 * programmed to '1' on all products. 1486 * 1487 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv 1488 */ 1489 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); 1490 1491 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); 1492 1493 return init_workarounds_ring(ring); 1494 } 1495 1496 static int gen9_init_render_ring(struct intel_engine_cs *ring) 1497 { 1498 int ret; 1499 1500 ret = gen8_init_common_ring(ring); 1501 if (ret) 1502 return ret; 1503 1504 return init_workarounds_ring(ring); 1505 } 1506 1507 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) 1508 { 1509 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; 1510 struct intel_engine_cs *ring = req->ring; 1511 struct intel_ringbuffer *ringbuf = req->ringbuf; 1512 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; 1513 int i, ret; 1514 1515 ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2); 1516 if (ret) 1517 return ret; 1518 1519 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); 1520 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { 1521 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); 1522 1523 intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i)); 1524 intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); 1525 intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i)); 1526 intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); 1527 } 1528 1529 intel_logical_ring_emit(ringbuf, MI_NOOP); 1530 intel_logical_ring_advance(ringbuf); 1531 1532 return 0; 1533 } 1534 1535 static int gen8_emit_bb_start(struct drm_i915_gem_request *req, 1536 u64 offset, unsigned dispatch_flags) 1537 { 1538 struct intel_ringbuffer *ringbuf = req->ringbuf; 1539 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); 1540 int ret; 1541 1542 /* Don't rely in hw updating PDPs, specially in lite-restore. 1543 * Ideally, we should set Force PD Restore in ctx descriptor, 1544 * but we can't. Force Restore would be a second option, but 1545 * it is unsafe in case of lite-restore (because the ctx is 1546 * not idle). */ 1547 if (req->ctx->ppgtt && 1548 (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) { 1549 ret = intel_logical_ring_emit_pdps(req); 1550 if (ret) 1551 return ret; 1552 1553 req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring); 1554 } 1555 1556 ret = intel_logical_ring_begin(req, 4); 1557 if (ret) 1558 return ret; 1559 1560 /* FIXME(BDW): Address space and security selectors. */ 1561 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | 1562 (ppgtt<<8) | 1563 (dispatch_flags & I915_DISPATCH_RS ? 1564 MI_BATCH_RESOURCE_STREAMER : 0)); 1565 intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); 1566 intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); 1567 intel_logical_ring_emit(ringbuf, MI_NOOP); 1568 intel_logical_ring_advance(ringbuf); 1569 1570 return 0; 1571 } 1572 1573 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) 1574 { 1575 struct drm_device *dev = ring->dev; 1576 struct drm_i915_private *dev_priv = dev->dev_private; 1577 1578 if (WARN_ON(!intel_irqs_enabled(dev_priv))) 1579 return false; 1580 1581 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1582 if (ring->irq_refcount++ == 0) { 1583 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); 1584 POSTING_READ(RING_IMR(ring->mmio_base)); 1585 } 1586 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1587 1588 return true; 1589 } 1590 1591 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) 1592 { 1593 struct drm_device *dev = ring->dev; 1594 struct drm_i915_private *dev_priv = dev->dev_private; 1595 1596 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1597 if (--ring->irq_refcount == 0) { 1598 I915_WRITE_IMR(ring, ~ring->irq_keep_mask); 1599 POSTING_READ(RING_IMR(ring->mmio_base)); 1600 } 1601 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1602 } 1603 1604 static int gen8_emit_flush(struct drm_i915_gem_request *request, 1605 u32 invalidate_domains, 1606 u32 unused) 1607 { 1608 struct intel_ringbuffer *ringbuf = request->ringbuf; 1609 struct intel_engine_cs *ring = ringbuf->ring; 1610 struct drm_device *dev = ring->dev; 1611 struct drm_i915_private *dev_priv = dev->dev_private; 1612 uint32_t cmd; 1613 int ret; 1614 1615 ret = intel_logical_ring_begin(request, 4); 1616 if (ret) 1617 return ret; 1618 1619 cmd = MI_FLUSH_DW + 1; 1620 1621 /* We always require a command barrier so that subsequent 1622 * commands, such as breadcrumb interrupts, are strictly ordered 1623 * wrt the contents of the write cache being flushed to memory 1624 * (and thus being coherent from the CPU). 1625 */ 1626 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 1627 1628 if (invalidate_domains & I915_GEM_GPU_DOMAINS) { 1629 cmd |= MI_INVALIDATE_TLB; 1630 if (ring == &dev_priv->ring[VCS]) 1631 cmd |= MI_INVALIDATE_BSD; 1632 } 1633 1634 intel_logical_ring_emit(ringbuf, cmd); 1635 intel_logical_ring_emit(ringbuf, 1636 I915_GEM_HWS_SCRATCH_ADDR | 1637 MI_FLUSH_DW_USE_GTT); 1638 intel_logical_ring_emit(ringbuf, 0); /* upper addr */ 1639 intel_logical_ring_emit(ringbuf, 0); /* value */ 1640 intel_logical_ring_advance(ringbuf); 1641 1642 return 0; 1643 } 1644 1645 static int gen8_emit_flush_render(struct drm_i915_gem_request *request, 1646 u32 invalidate_domains, 1647 u32 flush_domains) 1648 { 1649 struct intel_ringbuffer *ringbuf = request->ringbuf; 1650 struct intel_engine_cs *ring = ringbuf->ring; 1651 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; 1652 bool vf_flush_wa; 1653 u32 flags = 0; 1654 int ret; 1655 1656 flags |= PIPE_CONTROL_CS_STALL; 1657 1658 if (flush_domains) { 1659 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 1660 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 1661 flags |= PIPE_CONTROL_FLUSH_ENABLE; 1662 } 1663 1664 if (invalidate_domains) { 1665 flags |= PIPE_CONTROL_TLB_INVALIDATE; 1666 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 1667 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 1668 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 1669 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 1670 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 1671 flags |= PIPE_CONTROL_QW_WRITE; 1672 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 1673 } 1674 1675 /* 1676 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe 1677 * control. 1678 */ 1679 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && 1680 flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; 1681 1682 ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6); 1683 if (ret) 1684 return ret; 1685 1686 if (vf_flush_wa) { 1687 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); 1688 intel_logical_ring_emit(ringbuf, 0); 1689 intel_logical_ring_emit(ringbuf, 0); 1690 intel_logical_ring_emit(ringbuf, 0); 1691 intel_logical_ring_emit(ringbuf, 0); 1692 intel_logical_ring_emit(ringbuf, 0); 1693 } 1694 1695 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); 1696 intel_logical_ring_emit(ringbuf, flags); 1697 intel_logical_ring_emit(ringbuf, scratch_addr); 1698 intel_logical_ring_emit(ringbuf, 0); 1699 intel_logical_ring_emit(ringbuf, 0); 1700 intel_logical_ring_emit(ringbuf, 0); 1701 intel_logical_ring_advance(ringbuf); 1702 1703 return 0; 1704 } 1705 1706 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) 1707 { 1708 return intel_read_status_page(ring, I915_GEM_HWS_INDEX); 1709 } 1710 1711 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) 1712 { 1713 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); 1714 } 1715 1716 static int gen8_emit_request(struct drm_i915_gem_request *request) 1717 { 1718 struct intel_ringbuffer *ringbuf = request->ringbuf; 1719 struct intel_engine_cs *ring = ringbuf->ring; 1720 u32 cmd; 1721 int ret; 1722 1723 /* 1724 * Reserve space for 2 NOOPs at the end of each request to be 1725 * used as a workaround for not being allowed to do lite 1726 * restore with HEAD==TAIL (WaIdleLiteRestore). 1727 */ 1728 ret = intel_logical_ring_begin(request, 8); 1729 if (ret) 1730 return ret; 1731 1732 cmd = MI_STORE_DWORD_IMM_GEN4; 1733 cmd |= MI_GLOBAL_GTT; 1734 1735 intel_logical_ring_emit(ringbuf, cmd); 1736 intel_logical_ring_emit(ringbuf, 1737 (ring->status_page.gfx_addr + 1738 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); 1739 intel_logical_ring_emit(ringbuf, 0); 1740 intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); 1741 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); 1742 intel_logical_ring_emit(ringbuf, MI_NOOP); 1743 intel_logical_ring_advance_and_submit(request); 1744 1745 /* 1746 * Here we add two extra NOOPs as padding to avoid 1747 * lite restore of a context with HEAD==TAIL. 1748 */ 1749 intel_logical_ring_emit(ringbuf, MI_NOOP); 1750 intel_logical_ring_emit(ringbuf, MI_NOOP); 1751 intel_logical_ring_advance(ringbuf); 1752 1753 return 0; 1754 } 1755 1756 static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) 1757 { 1758 struct render_state so; 1759 int ret; 1760 1761 ret = i915_gem_render_state_prepare(req->ring, &so); 1762 if (ret) 1763 return ret; 1764 1765 if (so.rodata == NULL) 1766 return 0; 1767 1768 ret = req->ring->emit_bb_start(req, so.ggtt_offset, 1769 I915_DISPATCH_SECURE); 1770 if (ret) 1771 goto out; 1772 1773 ret = req->ring->emit_bb_start(req, 1774 (so.ggtt_offset + so.aux_batch_offset), 1775 I915_DISPATCH_SECURE); 1776 if (ret) 1777 goto out; 1778 1779 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); 1780 1781 out: 1782 i915_gem_render_state_fini(&so); 1783 return ret; 1784 } 1785 1786 static int gen8_init_rcs_context(struct drm_i915_gem_request *req) 1787 { 1788 int ret; 1789 1790 ret = intel_logical_ring_workarounds_emit(req); 1791 if (ret) 1792 return ret; 1793 1794 ret = intel_rcs_context_init_mocs(req); 1795 /* 1796 * Failing to program the MOCS is non-fatal.The system will not 1797 * run at peak performance. So generate an error and carry on. 1798 */ 1799 if (ret) 1800 DRM_ERROR("MOCS failed to program: expect performance issues.\n"); 1801 1802 return intel_lr_context_render_state_init(req); 1803 } 1804 1805 /** 1806 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer 1807 * 1808 * @ring: Engine Command Streamer. 1809 * 1810 */ 1811 void intel_logical_ring_cleanup(struct intel_engine_cs *ring) 1812 { 1813 struct drm_i915_private *dev_priv; 1814 1815 if (!intel_ring_initialized(ring)) 1816 return; 1817 1818 dev_priv = ring->dev->dev_private; 1819 1820 intel_logical_ring_stop(ring); 1821 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); 1822 1823 if (ring->cleanup) 1824 ring->cleanup(ring); 1825 1826 i915_cmd_parser_fini_ring(ring); 1827 i915_gem_batch_pool_fini(&ring->batch_pool); 1828 1829 if (ring->status_page.obj) { 1830 kunmap(sg_page(ring->status_page.obj->pages->sgl)); 1831 ring->status_page.obj = NULL; 1832 } 1833 1834 lrc_destroy_wa_ctx_obj(ring); 1835 } 1836 1837 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) 1838 { 1839 int ret; 1840 1841 /* Intentionally left blank. */ 1842 ring->buffer = NULL; 1843 1844 ring->dev = dev; 1845 INIT_LIST_HEAD(&ring->active_list); 1846 INIT_LIST_HEAD(&ring->request_list); 1847 i915_gem_batch_pool_init(dev, &ring->batch_pool); 1848 init_waitqueue_head(&ring->irq_queue); 1849 1850 INIT_LIST_HEAD(&ring->execlist_queue); 1851 INIT_LIST_HEAD(&ring->execlist_retired_req_list); 1852 lockinit(&ring->execlist_lock, "i915el", 0, LK_CANRECURSE); 1853 1854 ret = i915_cmd_parser_init_ring(ring); 1855 if (ret) 1856 return ret; 1857 1858 ret = intel_lr_context_deferred_create(ring->default_context, ring); 1859 1860 return ret; 1861 } 1862 1863 static int logical_render_ring_init(struct drm_device *dev) 1864 { 1865 struct drm_i915_private *dev_priv = dev->dev_private; 1866 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; 1867 int ret; 1868 1869 ring->name = "render ring"; 1870 ring->id = RCS; 1871 ring->mmio_base = RENDER_RING_BASE; 1872 ring->irq_enable_mask = 1873 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; 1874 ring->irq_keep_mask = 1875 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; 1876 if (HAS_L3_DPF(dev)) 1877 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; 1878 1879 if (INTEL_INFO(dev)->gen >= 9) 1880 ring->init_hw = gen9_init_render_ring; 1881 else 1882 ring->init_hw = gen8_init_render_ring; 1883 ring->init_context = gen8_init_rcs_context; 1884 ring->cleanup = intel_fini_pipe_control; 1885 ring->get_seqno = gen8_get_seqno; 1886 ring->set_seqno = gen8_set_seqno; 1887 ring->emit_request = gen8_emit_request; 1888 ring->emit_flush = gen8_emit_flush_render; 1889 ring->irq_get = gen8_logical_ring_get_irq; 1890 ring->irq_put = gen8_logical_ring_put_irq; 1891 ring->emit_bb_start = gen8_emit_bb_start; 1892 1893 ring->dev = dev; 1894 1895 ret = intel_init_pipe_control(ring); 1896 if (ret) 1897 return ret; 1898 1899 ret = intel_init_workaround_bb(ring); 1900 if (ret) { 1901 /* 1902 * We continue even if we fail to initialize WA batch 1903 * because we only expect rare glitches but nothing 1904 * critical to prevent us from using GPU 1905 */ 1906 DRM_ERROR("WA batch buffer initialization failed: %d\n", 1907 ret); 1908 } 1909 1910 ret = logical_ring_init(dev, ring); 1911 if (ret) { 1912 lrc_destroy_wa_ctx_obj(ring); 1913 } 1914 1915 return ret; 1916 } 1917 1918 static int logical_bsd_ring_init(struct drm_device *dev) 1919 { 1920 struct drm_i915_private *dev_priv = dev->dev_private; 1921 struct intel_engine_cs *ring = &dev_priv->ring[VCS]; 1922 1923 ring->name = "bsd ring"; 1924 ring->id = VCS; 1925 ring->mmio_base = GEN6_BSD_RING_BASE; 1926 ring->irq_enable_mask = 1927 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; 1928 ring->irq_keep_mask = 1929 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; 1930 1931 ring->init_hw = gen8_init_common_ring; 1932 ring->get_seqno = gen8_get_seqno; 1933 ring->set_seqno = gen8_set_seqno; 1934 ring->emit_request = gen8_emit_request; 1935 ring->emit_flush = gen8_emit_flush; 1936 ring->irq_get = gen8_logical_ring_get_irq; 1937 ring->irq_put = gen8_logical_ring_put_irq; 1938 ring->emit_bb_start = gen8_emit_bb_start; 1939 1940 return logical_ring_init(dev, ring); 1941 } 1942 1943 static int logical_bsd2_ring_init(struct drm_device *dev) 1944 { 1945 struct drm_i915_private *dev_priv = dev->dev_private; 1946 struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; 1947 1948 ring->name = "bds2 ring"; 1949 ring->id = VCS2; 1950 ring->mmio_base = GEN8_BSD2_RING_BASE; 1951 ring->irq_enable_mask = 1952 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; 1953 ring->irq_keep_mask = 1954 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; 1955 1956 ring->init_hw = gen8_init_common_ring; 1957 ring->get_seqno = gen8_get_seqno; 1958 ring->set_seqno = gen8_set_seqno; 1959 ring->emit_request = gen8_emit_request; 1960 ring->emit_flush = gen8_emit_flush; 1961 ring->irq_get = gen8_logical_ring_get_irq; 1962 ring->irq_put = gen8_logical_ring_put_irq; 1963 ring->emit_bb_start = gen8_emit_bb_start; 1964 1965 return logical_ring_init(dev, ring); 1966 } 1967 1968 static int logical_blt_ring_init(struct drm_device *dev) 1969 { 1970 struct drm_i915_private *dev_priv = dev->dev_private; 1971 struct intel_engine_cs *ring = &dev_priv->ring[BCS]; 1972 1973 ring->name = "blitter ring"; 1974 ring->id = BCS; 1975 ring->mmio_base = BLT_RING_BASE; 1976 ring->irq_enable_mask = 1977 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; 1978 ring->irq_keep_mask = 1979 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; 1980 1981 ring->init_hw = gen8_init_common_ring; 1982 ring->get_seqno = gen8_get_seqno; 1983 ring->set_seqno = gen8_set_seqno; 1984 ring->emit_request = gen8_emit_request; 1985 ring->emit_flush = gen8_emit_flush; 1986 ring->irq_get = gen8_logical_ring_get_irq; 1987 ring->irq_put = gen8_logical_ring_put_irq; 1988 ring->emit_bb_start = gen8_emit_bb_start; 1989 1990 return logical_ring_init(dev, ring); 1991 } 1992 1993 static int logical_vebox_ring_init(struct drm_device *dev) 1994 { 1995 struct drm_i915_private *dev_priv = dev->dev_private; 1996 struct intel_engine_cs *ring = &dev_priv->ring[VECS]; 1997 1998 ring->name = "video enhancement ring"; 1999 ring->id = VECS; 2000 ring->mmio_base = VEBOX_RING_BASE; 2001 ring->irq_enable_mask = 2002 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; 2003 ring->irq_keep_mask = 2004 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; 2005 2006 ring->init_hw = gen8_init_common_ring; 2007 ring->get_seqno = gen8_get_seqno; 2008 ring->set_seqno = gen8_set_seqno; 2009 ring->emit_request = gen8_emit_request; 2010 ring->emit_flush = gen8_emit_flush; 2011 ring->irq_get = gen8_logical_ring_get_irq; 2012 ring->irq_put = gen8_logical_ring_put_irq; 2013 ring->emit_bb_start = gen8_emit_bb_start; 2014 2015 return logical_ring_init(dev, ring); 2016 } 2017 2018 /** 2019 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers 2020 * @dev: DRM device. 2021 * 2022 * This function inits the engines for an Execlists submission style (the equivalent in the 2023 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for 2024 * those engines that are present in the hardware. 2025 * 2026 * Return: non-zero if the initialization failed. 2027 */ 2028 int intel_logical_rings_init(struct drm_device *dev) 2029 { 2030 struct drm_i915_private *dev_priv = dev->dev_private; 2031 int ret; 2032 2033 ret = logical_render_ring_init(dev); 2034 if (ret) 2035 return ret; 2036 2037 if (HAS_BSD(dev)) { 2038 ret = logical_bsd_ring_init(dev); 2039 if (ret) 2040 goto cleanup_render_ring; 2041 } 2042 2043 if (HAS_BLT(dev)) { 2044 ret = logical_blt_ring_init(dev); 2045 if (ret) 2046 goto cleanup_bsd_ring; 2047 } 2048 2049 if (HAS_VEBOX(dev)) { 2050 ret = logical_vebox_ring_init(dev); 2051 if (ret) 2052 goto cleanup_blt_ring; 2053 } 2054 2055 if (HAS_BSD2(dev)) { 2056 ret = logical_bsd2_ring_init(dev); 2057 if (ret) 2058 goto cleanup_vebox_ring; 2059 } 2060 2061 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); 2062 if (ret) 2063 goto cleanup_bsd2_ring; 2064 2065 return 0; 2066 2067 cleanup_bsd2_ring: 2068 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); 2069 cleanup_vebox_ring: 2070 intel_logical_ring_cleanup(&dev_priv->ring[VECS]); 2071 cleanup_blt_ring: 2072 intel_logical_ring_cleanup(&dev_priv->ring[BCS]); 2073 cleanup_bsd_ring: 2074 intel_logical_ring_cleanup(&dev_priv->ring[VCS]); 2075 cleanup_render_ring: 2076 intel_logical_ring_cleanup(&dev_priv->ring[RCS]); 2077 2078 return ret; 2079 } 2080 2081 static u32 2082 make_rpcs(struct drm_device *dev) 2083 { 2084 u32 rpcs = 0; 2085 2086 /* 2087 * No explicit RPCS request is needed to ensure full 2088 * slice/subslice/EU enablement prior to Gen9. 2089 */ 2090 if (INTEL_INFO(dev)->gen < 9) 2091 return 0; 2092 2093 /* 2094 * Starting in Gen9, render power gating can leave 2095 * slice/subslice/EU in a partially enabled state. We 2096 * must make an explicit request through RPCS for full 2097 * enablement. 2098 */ 2099 if (INTEL_INFO(dev)->has_slice_pg) { 2100 rpcs |= GEN8_RPCS_S_CNT_ENABLE; 2101 rpcs |= INTEL_INFO(dev)->slice_total << 2102 GEN8_RPCS_S_CNT_SHIFT; 2103 rpcs |= GEN8_RPCS_ENABLE; 2104 } 2105 2106 if (INTEL_INFO(dev)->has_subslice_pg) { 2107 rpcs |= GEN8_RPCS_SS_CNT_ENABLE; 2108 rpcs |= INTEL_INFO(dev)->subslice_per_slice << 2109 GEN8_RPCS_SS_CNT_SHIFT; 2110 rpcs |= GEN8_RPCS_ENABLE; 2111 } 2112 2113 if (INTEL_INFO(dev)->has_eu_pg) { 2114 rpcs |= INTEL_INFO(dev)->eu_per_subslice << 2115 GEN8_RPCS_EU_MIN_SHIFT; 2116 rpcs |= INTEL_INFO(dev)->eu_per_subslice << 2117 GEN8_RPCS_EU_MAX_SHIFT; 2118 rpcs |= GEN8_RPCS_ENABLE; 2119 } 2120 2121 return rpcs; 2122 } 2123 2124 static int 2125 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, 2126 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) 2127 { 2128 struct drm_device *dev = ring->dev; 2129 struct drm_i915_private *dev_priv = dev->dev_private; 2130 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; 2131 struct vm_page *page; 2132 uint32_t *reg_state; 2133 int ret; 2134 2135 if (!ppgtt) 2136 ppgtt = dev_priv->mm.aliasing_ppgtt; 2137 2138 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); 2139 if (ret) { 2140 DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); 2141 return ret; 2142 } 2143 2144 ret = i915_gem_object_get_pages(ctx_obj); 2145 if (ret) { 2146 DRM_DEBUG_DRIVER("Could not get object pages\n"); 2147 return ret; 2148 } 2149 2150 i915_gem_object_pin_pages(ctx_obj); 2151 2152 /* The second page of the context object contains some fields which must 2153 * be set up prior to the first execution. */ 2154 page = i915_gem_object_get_page(ctx_obj, 1); 2155 reg_state = kmap_atomic(page); 2156 2157 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM 2158 * commands followed by (reg, value) pairs. The values we are setting here are 2159 * only for the first context restore: on a subsequent save, the GPU will 2160 * recreate this batchbuffer with new values (including all the missing 2161 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ 2162 if (ring->id == RCS) 2163 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); 2164 else 2165 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); 2166 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; 2167 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); 2168 reg_state[CTX_CONTEXT_CONTROL+1] = 2169 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | 2170 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | 2171 CTX_CTRL_RS_CTX_ENABLE); 2172 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); 2173 reg_state[CTX_RING_HEAD+1] = 0; 2174 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); 2175 reg_state[CTX_RING_TAIL+1] = 0; 2176 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); 2177 /* Ring buffer start address is not known until the buffer is pinned. 2178 * It is written to the context image in execlists_update_context() 2179 */ 2180 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); 2181 reg_state[CTX_RING_BUFFER_CONTROL+1] = 2182 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; 2183 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; 2184 reg_state[CTX_BB_HEAD_U+1] = 0; 2185 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; 2186 reg_state[CTX_BB_HEAD_L+1] = 0; 2187 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; 2188 reg_state[CTX_BB_STATE+1] = (1<<5); 2189 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; 2190 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; 2191 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; 2192 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; 2193 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; 2194 reg_state[CTX_SECOND_BB_STATE+1] = 0; 2195 if (ring->id == RCS) { 2196 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; 2197 reg_state[CTX_BB_PER_CTX_PTR+1] = 0; 2198 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; 2199 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; 2200 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; 2201 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; 2202 if (ring->wa_ctx.obj) { 2203 struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; 2204 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); 2205 2206 reg_state[CTX_RCS_INDIRECT_CTX+1] = 2207 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | 2208 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); 2209 2210 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 2211 CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; 2212 2213 reg_state[CTX_BB_PER_CTX_PTR+1] = 2214 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | 2215 0x01; 2216 } 2217 } 2218 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); 2219 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; 2220 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; 2221 reg_state[CTX_CTX_TIMESTAMP+1] = 0; 2222 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); 2223 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); 2224 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); 2225 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); 2226 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); 2227 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); 2228 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); 2229 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); 2230 2231 /* With dynamic page allocation, PDPs may not be allocated at this point, 2232 * Point the unallocated PDPs to the scratch page 2233 */ 2234 ASSIGN_CTX_PDP(ppgtt, reg_state, 3); 2235 ASSIGN_CTX_PDP(ppgtt, reg_state, 2); 2236 ASSIGN_CTX_PDP(ppgtt, reg_state, 1); 2237 ASSIGN_CTX_PDP(ppgtt, reg_state, 0); 2238 if (ring->id == RCS) { 2239 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); 2240 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; 2241 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); 2242 } 2243 2244 kunmap_atomic(reg_state); 2245 2246 ctx_obj->dirty = 1; 2247 set_page_dirty(page); 2248 i915_gem_object_unpin_pages(ctx_obj); 2249 2250 return 0; 2251 } 2252 2253 /** 2254 * intel_lr_context_free() - free the LRC specific bits of a context 2255 * @ctx: the LR context to free. 2256 * 2257 * The real context freeing is done in i915_gem_context_free: this only 2258 * takes care of the bits that are LRC related: the per-engine backing 2259 * objects and the logical ringbuffer. 2260 */ 2261 void intel_lr_context_free(struct intel_context *ctx) 2262 { 2263 int i; 2264 2265 for (i = 0; i < I915_NUM_RINGS; i++) { 2266 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; 2267 2268 if (ctx_obj) { 2269 struct intel_ringbuffer *ringbuf = 2270 ctx->engine[i].ringbuf; 2271 struct intel_engine_cs *ring = ringbuf->ring; 2272 2273 if (ctx == ring->default_context) { 2274 intel_unpin_ringbuffer_obj(ringbuf); 2275 i915_gem_object_ggtt_unpin(ctx_obj); 2276 } 2277 WARN_ON(ctx->engine[ring->id].pin_count); 2278 intel_destroy_ringbuffer_obj(ringbuf); 2279 kfree(ringbuf); 2280 drm_gem_object_unreference(&ctx_obj->base); 2281 } 2282 } 2283 } 2284 2285 static uint32_t get_lr_context_size(struct intel_engine_cs *ring) 2286 { 2287 int ret = 0; 2288 2289 WARN_ON(INTEL_INFO(ring->dev)->gen < 8); 2290 2291 switch (ring->id) { 2292 case RCS: 2293 if (INTEL_INFO(ring->dev)->gen >= 9) 2294 ret = GEN9_LR_CONTEXT_RENDER_SIZE; 2295 else 2296 ret = GEN8_LR_CONTEXT_RENDER_SIZE; 2297 break; 2298 case VCS: 2299 case BCS: 2300 case VECS: 2301 case VCS2: 2302 ret = GEN8_LR_CONTEXT_OTHER_SIZE; 2303 break; 2304 } 2305 2306 return ret; 2307 } 2308 2309 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, 2310 struct drm_i915_gem_object *default_ctx_obj) 2311 { 2312 struct drm_i915_private *dev_priv = ring->dev->dev_private; 2313 2314 /* The status page is offset 0 from the default context object 2315 * in LRC mode. */ 2316 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); 2317 ring->status_page.page_addr = 2318 kmap(sg_page(default_ctx_obj->pages->sgl)); 2319 ring->status_page.obj = default_ctx_obj; 2320 2321 I915_WRITE(RING_HWS_PGA(ring->mmio_base), 2322 (u32)ring->status_page.gfx_addr); 2323 POSTING_READ(RING_HWS_PGA(ring->mmio_base)); 2324 } 2325 2326 /** 2327 * intel_lr_context_deferred_create() - create the LRC specific bits of a context 2328 * @ctx: LR context to create. 2329 * @ring: engine to be used with the context. 2330 * 2331 * This function can be called more than once, with different engines, if we plan 2332 * to use the context with them. The context backing objects and the ringbuffers 2333 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why 2334 * the creation is a deferred call: it's better to make sure first that we need to use 2335 * a given ring with the context. 2336 * 2337 * Return: non-zero on error. 2338 */ 2339 int intel_lr_context_deferred_create(struct intel_context *ctx, 2340 struct intel_engine_cs *ring) 2341 { 2342 const bool is_global_default_ctx = (ctx == ring->default_context); 2343 struct drm_device *dev = ring->dev; 2344 struct drm_i915_gem_object *ctx_obj; 2345 uint32_t context_size; 2346 struct intel_ringbuffer *ringbuf; 2347 int ret; 2348 2349 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); 2350 WARN_ON(ctx->engine[ring->id].state); 2351 2352 context_size = round_up(get_lr_context_size(ring), 4096); 2353 2354 ctx_obj = i915_gem_alloc_object(dev, context_size); 2355 if (!ctx_obj) { 2356 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); 2357 return -ENOMEM; 2358 } 2359 2360 if (is_global_default_ctx) { 2361 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); 2362 if (ret) { 2363 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", 2364 ret); 2365 drm_gem_object_unreference(&ctx_obj->base); 2366 return ret; 2367 } 2368 } 2369 2370 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); 2371 if (!ringbuf) { 2372 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", 2373 ring->name); 2374 ret = -ENOMEM; 2375 goto error_unpin_ctx; 2376 } 2377 2378 ringbuf->ring = ring; 2379 2380 ringbuf->size = 32 * PAGE_SIZE; 2381 ringbuf->effective_size = ringbuf->size; 2382 ringbuf->head = 0; 2383 ringbuf->tail = 0; 2384 ringbuf->last_retired_head = -1; 2385 intel_ring_update_space(ringbuf); 2386 2387 if (ringbuf->obj == NULL) { 2388 ret = intel_alloc_ringbuffer_obj(dev, ringbuf); 2389 if (ret) { 2390 DRM_DEBUG_DRIVER( 2391 "Failed to allocate ringbuffer obj %s: %d\n", 2392 ring->name, ret); 2393 goto error_free_rbuf; 2394 } 2395 2396 if (is_global_default_ctx) { 2397 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); 2398 if (ret) { 2399 DRM_ERROR( 2400 "Failed to pin and map ringbuffer %s: %d\n", 2401 ring->name, ret); 2402 goto error_destroy_rbuf; 2403 } 2404 } 2405 2406 } 2407 2408 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); 2409 if (ret) { 2410 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); 2411 goto error; 2412 } 2413 2414 ctx->engine[ring->id].ringbuf = ringbuf; 2415 ctx->engine[ring->id].state = ctx_obj; 2416 2417 if (ctx == ring->default_context) 2418 lrc_setup_hardware_status_page(ring, ctx_obj); 2419 else if (ring->id == RCS && !ctx->rcs_initialized) { 2420 if (ring->init_context) { 2421 struct drm_i915_gem_request *req; 2422 2423 ret = i915_gem_request_alloc(ring, ctx, &req); 2424 if (ret) 2425 return ret; 2426 2427 ret = ring->init_context(req); 2428 if (ret) { 2429 DRM_ERROR("ring init context: %d\n", ret); 2430 i915_gem_request_cancel(req); 2431 ctx->engine[ring->id].ringbuf = NULL; 2432 ctx->engine[ring->id].state = NULL; 2433 goto error; 2434 } 2435 2436 i915_add_request_no_flush(req); 2437 } 2438 2439 ctx->rcs_initialized = true; 2440 } 2441 2442 return 0; 2443 2444 error: 2445 if (is_global_default_ctx) 2446 intel_unpin_ringbuffer_obj(ringbuf); 2447 error_destroy_rbuf: 2448 intel_destroy_ringbuffer_obj(ringbuf); 2449 error_free_rbuf: 2450 kfree(ringbuf); 2451 error_unpin_ctx: 2452 if (is_global_default_ctx) 2453 i915_gem_object_ggtt_unpin(ctx_obj); 2454 drm_gem_object_unreference(&ctx_obj->base); 2455 return ret; 2456 } 2457 2458 void intel_lr_context_reset(struct drm_device *dev, 2459 struct intel_context *ctx) 2460 { 2461 struct drm_i915_private *dev_priv = dev->dev_private; 2462 struct intel_engine_cs *ring; 2463 int i; 2464 2465 for_each_ring(ring, dev_priv, i) { 2466 struct drm_i915_gem_object *ctx_obj = 2467 ctx->engine[ring->id].state; 2468 struct intel_ringbuffer *ringbuf = 2469 ctx->engine[ring->id].ringbuf; 2470 uint32_t *reg_state; 2471 struct vm_page *page; 2472 2473 if (!ctx_obj) 2474 continue; 2475 2476 if (i915_gem_object_get_pages(ctx_obj)) { 2477 WARN(1, "Failed get_pages for context obj\n"); 2478 continue; 2479 } 2480 page = i915_gem_object_get_page(ctx_obj, 1); 2481 reg_state = kmap_atomic(page); 2482 2483 reg_state[CTX_RING_HEAD+1] = 0; 2484 reg_state[CTX_RING_TAIL+1] = 0; 2485 2486 kunmap_atomic(reg_state); 2487 2488 ringbuf->head = 0; 2489 ringbuf->tail = 0; 2490 } 2491 } 2492