1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _INTEL_LRC_H_ 25 #define _INTEL_LRC_H_ 26 27 #include "intel_ringbuffer.h" 28 #include "i915_gem_context.h" 29 30 #define GEN8_LR_CONTEXT_ALIGN I915_GTT_MIN_ALIGNMENT 31 32 /* Execlists regs */ 33 #define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230) 34 #define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234) 35 #define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4) 36 #define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244) 37 #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) 38 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) 39 #define CTX_CTRL_RS_CTX_ENABLE (1 << 1) 40 #define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370) 41 #define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8) 42 #define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4) 43 #define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0) 44 45 /* The docs specify that the write pointer wraps around after 5h, "After status 46 * is written out to the last available status QW at offset 5h, this pointer 47 * wraps to 0." 48 * 49 * Therefore, one must infer than even though there are 3 bits available, 6 and 50 * 7 appear to be * reserved. 51 */ 52 #define GEN8_CSB_ENTRIES 6 53 #define GEN8_CSB_PTR_MASK 0x7 54 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8) 55 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0) 56 #define GEN8_CSB_WRITE_PTR(csb_status) \ 57 (((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0) 58 #define GEN8_CSB_READ_PTR(csb_status) \ 59 (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8) 60 61 enum { 62 INTEL_CONTEXT_SCHEDULE_IN = 0, 63 INTEL_CONTEXT_SCHEDULE_OUT, 64 INTEL_CONTEXT_SCHEDULE_PREEMPTED, 65 }; 66 67 /* Logical Rings */ 68 void intel_logical_ring_cleanup(struct intel_engine_cs *engine); 69 int logical_render_ring_init(struct intel_engine_cs *engine); 70 int logical_xcs_ring_init(struct intel_engine_cs *engine); 71 72 /* Logical Ring Contexts */ 73 74 /* 75 * We allocate a header at the start of the context image for our own 76 * use, therefore the actual location of the logical state is offset 77 * from the start of the VMA. The layout is 78 * 79 * | [guc] | [hwsp] [logical state] | 80 * |<- our header ->|<- context image ->| 81 * 82 */ 83 /* The first page is used for sharing data with the GuC */ 84 #define LRC_GUCSHR_PN (0) 85 #define LRC_GUCSHR_SZ (1) 86 /* At the start of the context image is its per-process HWS page */ 87 #define LRC_PPHWSP_PN (LRC_GUCSHR_PN + LRC_GUCSHR_SZ) 88 #define LRC_PPHWSP_SZ (1) 89 /* Finally we have the logical state for the context */ 90 #define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ) 91 92 /* 93 * Currently we include the PPHWSP in __intel_engine_context_size() so 94 * the size of the header is synonymous with the start of the PPHWSP. 95 */ 96 #define LRC_HEADER_PAGES LRC_PPHWSP_PN 97 98 struct drm_i915_private; 99 struct i915_gem_context; 100 101 void intel_lr_context_resume(struct drm_i915_private *dev_priv); 102 103 static inline uint64_t 104 intel_lr_context_descriptor(struct i915_gem_context *ctx, 105 struct intel_engine_cs *engine) 106 { 107 return ctx->engine[engine->id].lrc_desc; 108 } 109 110 111 /* Execlists */ 112 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, 113 int enable_execlists); 114 115 #endif /* _INTEL_LRC_H_ */ 116