xref: /dragonfly/sys/dev/drm/i915/intel_lvds.c (revision 2c3b1d1b)
1 /*
2  * Copyright © 2006-2007 Intel Corporation
3  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *	Eric Anholt <eric@anholt.net>
26  *      Dave Airlie <airlied@linux.ie>
27  *      Jesse Barnes <jesse.barnes@intel.com>
28  */
29 
30 #include "opt_drm.h"
31 
32 #include <linux/dmi.h>
33 #include <linux/i2c.h>
34 #include <linux/slab.h>
35 #include <linux/vga_switcheroo.h>
36 #include <drm/drmP.h>
37 #include <drm/drm_atomic_helper.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_edid.h>
40 #include "intel_drv.h"
41 #include <drm/i915_drm.h>
42 #include "i915_drv.h"
43 #include <linux/acpi.h>
44 
45 /* Private structure for the integrated LVDS support */
46 struct intel_lvds_connector {
47 	struct intel_connector base;
48 
49 	struct notifier_block lid_notifier;
50 };
51 
52 struct intel_lvds_encoder {
53 	struct intel_encoder base;
54 
55 	bool is_dual_link;
56 	i915_reg_t reg;
57 	u32 a3_power;
58 
59 	struct intel_lvds_connector *attached_connector;
60 };
61 
62 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
63 {
64 	return container_of(encoder, struct intel_lvds_encoder, base.base);
65 }
66 
67 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
68 {
69 	return container_of(connector, struct intel_lvds_connector, base.base);
70 }
71 
72 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
73 				    enum i915_pipe *pipe)
74 {
75 	struct drm_device *dev = encoder->base.dev;
76 	struct drm_i915_private *dev_priv = to_i915(dev);
77 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
78 	enum intel_display_power_domain power_domain;
79 	u32 tmp;
80 	bool ret;
81 
82 	power_domain = intel_display_port_power_domain(encoder);
83 	if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
84 		return false;
85 
86 	ret = false;
87 
88 	tmp = I915_READ(lvds_encoder->reg);
89 
90 	if (!(tmp & LVDS_PORT_EN))
91 		goto out;
92 
93 	if (HAS_PCH_CPT(dev))
94 		*pipe = PORT_TO_PIPE_CPT(tmp);
95 	else
96 		*pipe = PORT_TO_PIPE(tmp);
97 
98 	ret = true;
99 
100 out:
101 	intel_display_power_put(dev_priv, power_domain);
102 
103 	return ret;
104 }
105 
106 static void intel_lvds_get_config(struct intel_encoder *encoder,
107 				  struct intel_crtc_state *pipe_config)
108 {
109 	struct drm_device *dev = encoder->base.dev;
110 	struct drm_i915_private *dev_priv = to_i915(dev);
111 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
112 	u32 tmp, flags = 0;
113 
114 	tmp = I915_READ(lvds_encoder->reg);
115 	if (tmp & LVDS_HSYNC_POLARITY)
116 		flags |= DRM_MODE_FLAG_NHSYNC;
117 	else
118 		flags |= DRM_MODE_FLAG_PHSYNC;
119 	if (tmp & LVDS_VSYNC_POLARITY)
120 		flags |= DRM_MODE_FLAG_NVSYNC;
121 	else
122 		flags |= DRM_MODE_FLAG_PVSYNC;
123 
124 	pipe_config->base.adjusted_mode.flags |= flags;
125 
126 	if (INTEL_INFO(dev)->gen < 5)
127 		pipe_config->gmch_pfit.lvds_border_bits =
128 			tmp & LVDS_BORDER_ENABLE;
129 
130 	/* gen2/3 store dither state in pfit control, needs to match */
131 	if (INTEL_INFO(dev)->gen < 4) {
132 		tmp = I915_READ(PFIT_CONTROL);
133 
134 		pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
135 	}
136 
137 	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
138 }
139 
140 static void intel_pre_enable_lvds(struct intel_encoder *encoder)
141 {
142 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
143 	struct drm_device *dev = encoder->base.dev;
144 	struct drm_i915_private *dev_priv = to_i915(dev);
145 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
146 	const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
147 	int pipe = crtc->pipe;
148 	u32 temp;
149 
150 	if (HAS_PCH_SPLIT(dev)) {
151 		assert_fdi_rx_pll_disabled(dev_priv, pipe);
152 		assert_shared_dpll_disabled(dev_priv,
153 					    crtc->config->shared_dpll);
154 	} else {
155 		assert_pll_disabled(dev_priv, pipe);
156 	}
157 
158 	temp = I915_READ(lvds_encoder->reg);
159 	temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
160 
161 	if (HAS_PCH_CPT(dev)) {
162 		temp &= ~PORT_TRANS_SEL_MASK;
163 		temp |= PORT_TRANS_SEL_CPT(pipe);
164 	} else {
165 		if (pipe == 1) {
166 			temp |= LVDS_PIPEB_SELECT;
167 		} else {
168 			temp &= ~LVDS_PIPEB_SELECT;
169 		}
170 	}
171 
172 	/* set the corresponsding LVDS_BORDER bit */
173 	temp &= ~LVDS_BORDER_ENABLE;
174 	temp |= crtc->config->gmch_pfit.lvds_border_bits;
175 	/* Set the B0-B3 data pairs corresponding to whether we're going to
176 	 * set the DPLLs for dual-channel mode or not.
177 	 */
178 	if (lvds_encoder->is_dual_link)
179 		temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
180 	else
181 		temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
182 
183 	/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
184 	 * appropriately here, but we need to look more thoroughly into how
185 	 * panels behave in the two modes. For now, let's just maintain the
186 	 * value we got from the BIOS.
187 	 */
188 	temp &= ~LVDS_A3_POWER_MASK;
189 	temp |= lvds_encoder->a3_power;
190 
191 	/* Set the dithering flag on LVDS as needed, note that there is no
192 	 * special lvds dither control bit on pch-split platforms, dithering is
193 	 * only controlled through the PIPECONF reg. */
194 	if (IS_GEN4(dev_priv)) {
195 		/* Bspec wording suggests that LVDS port dithering only exists
196 		 * for 18bpp panels. */
197 		if (crtc->config->dither && crtc->config->pipe_bpp == 18)
198 			temp |= LVDS_ENABLE_DITHER;
199 		else
200 			temp &= ~LVDS_ENABLE_DITHER;
201 	}
202 	temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
203 	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
204 		temp |= LVDS_HSYNC_POLARITY;
205 	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
206 		temp |= LVDS_VSYNC_POLARITY;
207 
208 	I915_WRITE(lvds_encoder->reg, temp);
209 }
210 
211 /**
212  * Sets the power state for the panel.
213  */
214 static void intel_enable_lvds(struct intel_encoder *encoder)
215 {
216 	struct drm_device *dev = encoder->base.dev;
217 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
218 	struct intel_connector *intel_connector =
219 		&lvds_encoder->attached_connector->base;
220 	struct drm_i915_private *dev_priv = to_i915(dev);
221 	i915_reg_t ctl_reg, stat_reg;
222 
223 	if (HAS_PCH_SPLIT(dev)) {
224 		ctl_reg = PCH_PP_CONTROL;
225 		stat_reg = PCH_PP_STATUS;
226 	} else {
227 		ctl_reg = PP_CONTROL;
228 		stat_reg = PP_STATUS;
229 	}
230 
231 	I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
232 
233 	I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
234 	POSTING_READ(lvds_encoder->reg);
235 	if (intel_wait_for_register(dev_priv, stat_reg, PP_ON, PP_ON, 1000))
236 		DRM_ERROR("timed out waiting for panel to power on\n");
237 
238 	intel_panel_enable_backlight(intel_connector);
239 }
240 
241 static void intel_disable_lvds(struct intel_encoder *encoder)
242 {
243 	struct drm_device *dev = encoder->base.dev;
244 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
245 	struct drm_i915_private *dev_priv = to_i915(dev);
246 	i915_reg_t ctl_reg, stat_reg;
247 
248 	if (HAS_PCH_SPLIT(dev)) {
249 		ctl_reg = PCH_PP_CONTROL;
250 		stat_reg = PCH_PP_STATUS;
251 	} else {
252 		ctl_reg = PP_CONTROL;
253 		stat_reg = PP_STATUS;
254 	}
255 
256 	I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
257 	if (intel_wait_for_register(dev_priv, stat_reg, PP_ON, 0, 1000))
258 		DRM_ERROR("timed out waiting for panel to power off\n");
259 
260 	I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
261 	POSTING_READ(lvds_encoder->reg);
262 }
263 
264 static void gmch_disable_lvds(struct intel_encoder *encoder)
265 {
266 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
267 	struct intel_connector *intel_connector =
268 		&lvds_encoder->attached_connector->base;
269 
270 	intel_panel_disable_backlight(intel_connector);
271 
272 	intel_disable_lvds(encoder);
273 }
274 
275 static void pch_disable_lvds(struct intel_encoder *encoder)
276 {
277 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
278 	struct intel_connector *intel_connector =
279 		&lvds_encoder->attached_connector->base;
280 
281 	intel_panel_disable_backlight(intel_connector);
282 }
283 
284 static void pch_post_disable_lvds(struct intel_encoder *encoder)
285 {
286 	intel_disable_lvds(encoder);
287 }
288 
289 static enum drm_mode_status
290 intel_lvds_mode_valid(struct drm_connector *connector,
291 		      struct drm_display_mode *mode)
292 {
293 	struct intel_connector *intel_connector = to_intel_connector(connector);
294 	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
295 	int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
296 
297 	if (mode->hdisplay > fixed_mode->hdisplay)
298 		return MODE_PANEL;
299 	if (mode->vdisplay > fixed_mode->vdisplay)
300 		return MODE_PANEL;
301 	if (fixed_mode->clock > max_pixclk)
302 		return MODE_CLOCK_HIGH;
303 
304 	return MODE_OK;
305 }
306 
307 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
308 				      struct intel_crtc_state *pipe_config)
309 {
310 	struct drm_device *dev = intel_encoder->base.dev;
311 	struct intel_lvds_encoder *lvds_encoder =
312 		to_lvds_encoder(&intel_encoder->base);
313 	struct intel_connector *intel_connector =
314 		&lvds_encoder->attached_connector->base;
315 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
316 	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
317 	unsigned int lvds_bpp;
318 
319 	/* Should never happen!! */
320 	if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
321 		DRM_ERROR("Can't support LVDS on pipe A\n");
322 		return false;
323 	}
324 
325 	if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
326 		lvds_bpp = 8*3;
327 	else
328 		lvds_bpp = 6*3;
329 
330 	if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
331 		DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
332 			      pipe_config->pipe_bpp, lvds_bpp);
333 		pipe_config->pipe_bpp = lvds_bpp;
334 	}
335 
336 	/*
337 	 * We have timings from the BIOS for the panel, put them in
338 	 * to the adjusted mode.  The CRTC will be set up for this mode,
339 	 * with the panel scaling set up to source from the H/VDisplay
340 	 * of the original mode.
341 	 */
342 	intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
343 			       adjusted_mode);
344 
345 	if (HAS_PCH_SPLIT(dev)) {
346 		pipe_config->has_pch_encoder = true;
347 
348 		intel_pch_panel_fitting(intel_crtc, pipe_config,
349 					intel_connector->panel.fitting_mode);
350 	} else {
351 		intel_gmch_panel_fitting(intel_crtc, pipe_config,
352 					 intel_connector->panel.fitting_mode);
353 
354 	}
355 
356 	/*
357 	 * XXX: It would be nice to support lower refresh rates on the
358 	 * panels to reduce power consumption, and perhaps match the
359 	 * user's requested refresh rate.
360 	 */
361 
362 	return true;
363 }
364 
365 /**
366  * Detect the LVDS connection.
367  *
368  * Since LVDS doesn't have hotlug, we use the lid as a proxy.  Open means
369  * connected and closed means disconnected.  We also send hotplug events as
370  * needed, using lid status notification from the input layer.
371  */
372 static enum drm_connector_status
373 intel_lvds_detect(struct drm_connector *connector, bool force)
374 {
375 	struct drm_device *dev = connector->dev;
376 	enum drm_connector_status status;
377 
378 	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
379 		      connector->base.id, connector->name);
380 
381 	status = intel_panel_detect(dev);
382 	if (status != connector_status_unknown)
383 		return status;
384 
385 	return connector_status_connected;
386 }
387 
388 /**
389  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
390  */
391 static int intel_lvds_get_modes(struct drm_connector *connector)
392 {
393 	struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
394 	struct drm_device *dev = connector->dev;
395 	struct drm_display_mode *mode;
396 
397 	/* use cached edid if we have one */
398 	if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
399 		return drm_add_edid_modes(connector, lvds_connector->base.edid);
400 
401 	mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
402 	if (mode == NULL)
403 		return 0;
404 
405 	drm_mode_probed_add(connector, mode);
406 	return 1;
407 }
408 
409 #if 0 /* unused */
410 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
411 {
412 	DRM_INFO("Skipping forced modeset for %s\n", id->ident);
413 	return 1;
414 }
415 
416 /* The GPU hangs up on these systems if modeset is performed on LID open */
417 static const struct dmi_system_id intel_no_modeset_on_lid[] = {
418 	{
419 		.callback = intel_no_modeset_on_lid_dmi_callback,
420 		.ident = "Toshiba Tecra A11",
421 		.matches = {
422 			DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
423 			DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
424 		},
425 	},
426 
427 	{ }	/* terminating entry */
428 };
429 
430 /*
431  * Lid events. Note the use of 'modeset':
432  *  - we set it to MODESET_ON_LID_OPEN on lid close,
433  *    and set it to MODESET_DONE on open
434  *  - we use it as a "only once" bit (ie we ignore
435  *    duplicate events where it was already properly set)
436  *  - the suspend/resume paths will set it to
437  *    MODESET_SUSPENDED and ignore the lid open event,
438  *    because they restore the mode ("lid open").
439  */
440 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
441 			    void *unused)
442 {
443 	struct intel_lvds_connector *lvds_connector =
444 		container_of(nb, struct intel_lvds_connector, lid_notifier);
445 	struct drm_connector *connector = &lvds_connector->base.base;
446 	struct drm_device *dev = connector->dev;
447 	struct drm_i915_private *dev_priv = to_i915(dev);
448 
449 	if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
450 		return NOTIFY_OK;
451 
452 	mutex_lock(&dev_priv->modeset_restore_lock);
453 	if (dev_priv->modeset_restore == MODESET_SUSPENDED)
454 		goto exit;
455 	/*
456 	 * check and update the status of LVDS connector after receiving
457 	 * the LID nofication event.
458 	 */
459 	connector->status = connector->funcs->detect(connector, false);
460 
461 	/* Don't force modeset on machines where it causes a GPU lockup */
462 	if (dmi_check_system(intel_no_modeset_on_lid))
463 		goto exit;
464 	if (!acpi_lid_open()) {
465 		/* do modeset on next lid open event */
466 		dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
467 		goto exit;
468 	}
469 
470 	if (dev_priv->modeset_restore == MODESET_DONE)
471 		goto exit;
472 
473 	/*
474 	 * Some old platform's BIOS love to wreak havoc while the lid is closed.
475 	 * We try to detect this here and undo any damage. The split for PCH
476 	 * platforms is rather conservative and a bit arbitrary expect that on
477 	 * those platforms VGA disabling requires actual legacy VGA I/O access,
478 	 * and as part of the cleanup in the hw state restore we also redisable
479 	 * the vga plane.
480 	 */
481 	if (!HAS_PCH_SPLIT(dev))
482 		intel_display_resume(dev);
483 
484 	dev_priv->modeset_restore = MODESET_DONE;
485 
486 exit:
487 	mutex_unlock(&dev_priv->modeset_restore_lock);
488 	return NOTIFY_OK;
489 }
490 #endif
491 
492 /**
493  * intel_lvds_destroy - unregister and free LVDS structures
494  * @connector: connector to free
495  *
496  * Unregister the DDC bus for this connector then free the driver private
497  * structure.
498  */
499 static void intel_lvds_destroy(struct drm_connector *connector)
500 {
501 	struct intel_lvds_connector *lvds_connector =
502 		to_lvds_connector(connector);
503 
504 #if 0
505 	if (lvds_connector->lid_notifier.notifier_call)
506 		acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
507 #endif
508 
509 	if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
510 		kfree(lvds_connector->base.edid);
511 
512 	intel_panel_fini(&lvds_connector->base.panel);
513 
514 	drm_connector_cleanup(connector);
515 	kfree(connector);
516 }
517 
518 static int intel_lvds_set_property(struct drm_connector *connector,
519 				   struct drm_property *property,
520 				   uint64_t value)
521 {
522 	struct intel_connector *intel_connector = to_intel_connector(connector);
523 	struct drm_device *dev = connector->dev;
524 
525 	if (property == dev->mode_config.scaling_mode_property) {
526 		struct drm_crtc *crtc;
527 
528 		if (value == DRM_MODE_SCALE_NONE) {
529 			DRM_DEBUG_KMS("no scaling not supported\n");
530 			return -EINVAL;
531 		}
532 
533 		if (intel_connector->panel.fitting_mode == value) {
534 			/* the LVDS scaling property is not changed */
535 			return 0;
536 		}
537 		intel_connector->panel.fitting_mode = value;
538 
539 		crtc = intel_attached_encoder(connector)->base.crtc;
540 		if (crtc && crtc->state->enable) {
541 			/*
542 			 * If the CRTC is enabled, the display will be changed
543 			 * according to the new panel fitting mode.
544 			 */
545 			intel_crtc_restore_mode(crtc);
546 		}
547 	}
548 
549 	return 0;
550 }
551 
552 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
553 	.get_modes = intel_lvds_get_modes,
554 	.mode_valid = intel_lvds_mode_valid,
555 };
556 
557 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
558 	.dpms = drm_atomic_helper_connector_dpms,
559 	.detect = intel_lvds_detect,
560 	.fill_modes = drm_helper_probe_single_connector_modes,
561 	.set_property = intel_lvds_set_property,
562 	.atomic_get_property = intel_connector_atomic_get_property,
563 	.late_register = intel_connector_register,
564 	.early_unregister = intel_connector_unregister,
565 	.destroy = intel_lvds_destroy,
566 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
567 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
568 };
569 
570 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
571 	.destroy = intel_encoder_destroy,
572 };
573 
574 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
575 {
576 	DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
577 	return 1;
578 }
579 
580 /* These systems claim to have LVDS, but really don't */
581 static const struct dmi_system_id intel_no_lvds[] = {
582 	{
583 		.callback = intel_no_lvds_dmi_callback,
584 		.ident = "Apple Mac Mini (Core series)",
585 		.matches = {
586 			DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
587 			DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
588 		},
589 	},
590 	{
591 		.callback = intel_no_lvds_dmi_callback,
592 		.ident = "Apple Mac Mini (Core 2 series)",
593 		.matches = {
594 			DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
595 			DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
596 		},
597 	},
598 	{
599 		.callback = intel_no_lvds_dmi_callback,
600 		.ident = "MSI IM-945GSE-A",
601 		.matches = {
602 			DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
603 			DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
604 		},
605 	},
606 	{
607 		.callback = intel_no_lvds_dmi_callback,
608 		.ident = "Dell Studio Hybrid",
609 		.matches = {
610 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
611 			DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
612 		},
613 	},
614 	{
615 		.callback = intel_no_lvds_dmi_callback,
616 		.ident = "Dell OptiPlex FX170",
617 		.matches = {
618 			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
619 			DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
620 		},
621 	},
622 	{
623 		.callback = intel_no_lvds_dmi_callback,
624 		.ident = "AOpen Mini PC",
625 		.matches = {
626 			DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
627 			DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
628 		},
629 	},
630 	{
631 		.callback = intel_no_lvds_dmi_callback,
632 		.ident = "AOpen Mini PC MP915",
633 		.matches = {
634 			DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
635 			DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
636 		},
637 	},
638 	{
639 		.callback = intel_no_lvds_dmi_callback,
640 		.ident = "AOpen i915GMm-HFS",
641 		.matches = {
642 			DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
643 			DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
644 		},
645 	},
646 	{
647 		.callback = intel_no_lvds_dmi_callback,
648                 .ident = "AOpen i45GMx-I",
649                 .matches = {
650                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
651                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
652                 },
653         },
654 	{
655 		.callback = intel_no_lvds_dmi_callback,
656 		.ident = "Aopen i945GTt-VFA",
657 		.matches = {
658 			DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
659 		},
660 	},
661 	{
662 		.callback = intel_no_lvds_dmi_callback,
663 		.ident = "Clientron U800",
664 		.matches = {
665 			DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
666 			DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
667 		},
668 	},
669 	{
670                 .callback = intel_no_lvds_dmi_callback,
671                 .ident = "Clientron E830",
672                 .matches = {
673                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
674                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
675                 },
676         },
677         {
678 		.callback = intel_no_lvds_dmi_callback,
679 		.ident = "Asus EeeBox PC EB1007",
680 		.matches = {
681 			DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
682 			DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
683 		},
684 	},
685 	{
686 		.callback = intel_no_lvds_dmi_callback,
687 		.ident = "Asus AT5NM10T-I",
688 		.matches = {
689 			DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
690 			DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
691 		},
692 	},
693 	{
694 		.callback = intel_no_lvds_dmi_callback,
695 		.ident = "Hewlett-Packard HP t5740",
696 		.matches = {
697 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
698 			DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
699 		},
700 	},
701 	{
702 		.callback = intel_no_lvds_dmi_callback,
703 		.ident = "Hewlett-Packard t5745",
704 		.matches = {
705 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
706 			DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
707 		},
708 	},
709 	{
710 		.callback = intel_no_lvds_dmi_callback,
711 		.ident = "Hewlett-Packard st5747",
712 		.matches = {
713 			DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
714 			DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
715 		},
716 	},
717 	{
718 		.callback = intel_no_lvds_dmi_callback,
719 		.ident = "MSI Wind Box DC500",
720 		.matches = {
721 			DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
722 			DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
723 		},
724 	},
725 	{
726 		.callback = intel_no_lvds_dmi_callback,
727 		.ident = "Gigabyte GA-D525TUD",
728 		.matches = {
729 			DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
730 			DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
731 		},
732 	},
733 	{
734 		.callback = intel_no_lvds_dmi_callback,
735 		.ident = "Supermicro X7SPA-H",
736 		.matches = {
737 			DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
738 			DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
739 		},
740 	},
741 	{
742 		.callback = intel_no_lvds_dmi_callback,
743 		.ident = "Fujitsu Esprimo Q900",
744 		.matches = {
745 			DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
746 			DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
747 		},
748 	},
749 	{
750 		.callback = intel_no_lvds_dmi_callback,
751 		.ident = "Intel D410PT",
752 		.matches = {
753 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
754 			DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
755 		},
756 	},
757 	{
758 		.callback = intel_no_lvds_dmi_callback,
759 		.ident = "Intel D425KT",
760 		.matches = {
761 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
762 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
763 		},
764 	},
765 	{
766 		.callback = intel_no_lvds_dmi_callback,
767 		.ident = "Intel D510MO",
768 		.matches = {
769 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
770 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
771 		},
772 	},
773 	{
774 		.callback = intel_no_lvds_dmi_callback,
775 		.ident = "Intel D525MW",
776 		.matches = {
777 			DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
778 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
779 		},
780 	},
781 
782 	{ }	/* terminating entry */
783 };
784 
785 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
786 {
787 	DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
788 	return 1;
789 }
790 
791 static const struct dmi_system_id intel_dual_link_lvds[] = {
792 	{
793 		.callback = intel_dual_link_lvds_callback,
794 		.ident = "Apple MacBook Pro 15\" (2010)",
795 		.matches = {
796 			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
797 			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
798 		},
799 	},
800 	{
801 		.callback = intel_dual_link_lvds_callback,
802 		.ident = "Apple MacBook Pro 15\" (2011)",
803 		.matches = {
804 			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
805 			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
806 		},
807 	},
808 	{
809 		.callback = intel_dual_link_lvds_callback,
810 		.ident = "Apple MacBook Pro 15\" (2012)",
811 		.matches = {
812 			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
813 			DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
814 		},
815 	},
816 	{ }	/* terminating entry */
817 };
818 
819 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
820 {
821 	struct intel_encoder *intel_encoder;
822 
823 	for_each_intel_encoder(dev, intel_encoder)
824 		if (intel_encoder->type == INTEL_OUTPUT_LVDS)
825 			return intel_encoder;
826 
827 	return NULL;
828 }
829 
830 bool intel_is_dual_link_lvds(struct drm_device *dev)
831 {
832 	struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
833 
834 	return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
835 }
836 
837 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
838 {
839 	struct drm_device *dev = lvds_encoder->base.base.dev;
840 	unsigned int val;
841 	struct drm_i915_private *dev_priv = to_i915(dev);
842 
843 	/* use the module option value if specified */
844 	if (i915.lvds_channel_mode > 0)
845 		return i915.lvds_channel_mode == 2;
846 
847 	/* single channel LVDS is limited to 112 MHz */
848 	if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
849 	    > 112999)
850 		return true;
851 
852 	if (dmi_check_system(intel_dual_link_lvds))
853 		return true;
854 
855 	/* BIOS should set the proper LVDS register value at boot, but
856 	 * in reality, it doesn't set the value when the lid is closed;
857 	 * we need to check "the value to be set" in VBT when LVDS
858 	 * register is uninitialized.
859 	 */
860 	val = I915_READ(lvds_encoder->reg);
861 	if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
862 		val = dev_priv->vbt.bios_lvds_val;
863 
864 	return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
865 }
866 
867 static bool intel_lvds_supported(struct drm_device *dev)
868 {
869 	/* With the introduction of the PCH we gained a dedicated
870 	 * LVDS presence pin, use it. */
871 	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
872 		return true;
873 
874 	/* Otherwise LVDS was only attached to mobile products,
875 	 * except for the inglorious 830gm */
876 	if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
877 		return true;
878 
879 	return false;
880 }
881 
882 /**
883  * intel_lvds_init - setup LVDS connectors on this device
884  * @dev: drm device
885  *
886  * Create the connector, register the LVDS DDC bus, and try to figure out what
887  * modes we can display on the LVDS panel (if present).
888  */
889 void intel_lvds_init(struct drm_device *dev)
890 {
891 	struct drm_i915_private *dev_priv = to_i915(dev);
892 	struct intel_lvds_encoder *lvds_encoder;
893 	struct intel_encoder *intel_encoder;
894 	struct intel_lvds_connector *lvds_connector;
895 	struct intel_connector *intel_connector;
896 	struct drm_connector *connector;
897 	struct drm_encoder *encoder;
898 	struct drm_display_mode *scan; /* *modes, *bios_mode; */
899 	struct drm_display_mode *fixed_mode = NULL;
900 	struct drm_display_mode *downclock_mode = NULL;
901 	struct edid *edid;
902 	struct drm_crtc *crtc;
903 	i915_reg_t lvds_reg;
904 	u32 lvds;
905 	int pipe;
906 	u8 pin;
907 
908 	/*
909 	 * Unlock registers and just leave them unlocked. Do this before
910 	 * checking quirk lists to avoid bogus WARNINGs.
911 	 */
912 	if (HAS_PCH_SPLIT(dev)) {
913 		I915_WRITE(PCH_PP_CONTROL,
914 			   I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
915 	} else if (INTEL_INFO(dev_priv)->gen < 5) {
916 		I915_WRITE(PP_CONTROL,
917 			   I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
918 	}
919 	if (!intel_lvds_supported(dev))
920 		return;
921 
922 	/* Skip init on machines we know falsely report LVDS */
923 	if (dmi_check_system(intel_no_lvds))
924 		return;
925 
926 	if (HAS_PCH_SPLIT(dev))
927 		lvds_reg = PCH_LVDS;
928 	else
929 		lvds_reg = LVDS;
930 
931 	lvds = I915_READ(lvds_reg);
932 
933 	if (HAS_PCH_SPLIT(dev)) {
934 		if ((lvds & LVDS_DETECTED) == 0)
935 			return;
936 		if (dev_priv->vbt.edp.support) {
937 			DRM_DEBUG_KMS("disable LVDS for eDP support\n");
938 			return;
939 		}
940 	}
941 
942 	pin = GMBUS_PIN_PANEL;
943 	if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
944 		if ((lvds & LVDS_PORT_EN) == 0) {
945 			DRM_DEBUG_KMS("LVDS is not present in VBT\n");
946 			return;
947 		}
948 		DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
949 	}
950 
951 	 /* Set the Panel Power On/Off timings if uninitialized. */
952 	if (INTEL_INFO(dev_priv)->gen < 5 &&
953 	    I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {
954 		/* Set T2 to 40ms and T5 to 200ms */
955 		I915_WRITE(PP_ON_DELAYS, 0x019007d0);
956 
957 		/* Set T3 to 35ms and Tx to 200ms */
958 		I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);
959 
960 		DRM_DEBUG_KMS("Panel power timings uninitialized, setting defaults\n");
961 	}
962 
963 	lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
964 	if (!lvds_encoder)
965 		return;
966 
967 	lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
968 	if (!lvds_connector) {
969 		kfree(lvds_encoder);
970 		return;
971 	}
972 
973 	if (intel_connector_init(&lvds_connector->base) < 0) {
974 		kfree(lvds_connector);
975 		kfree(lvds_encoder);
976 		return;
977 	}
978 
979 	lvds_encoder->attached_connector = lvds_connector;
980 
981 	intel_encoder = &lvds_encoder->base;
982 	encoder = &intel_encoder->base;
983 	intel_connector = &lvds_connector->base;
984 	connector = &intel_connector->base;
985 	drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
986 			   DRM_MODE_CONNECTOR_LVDS);
987 
988 	drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
989 			 DRM_MODE_ENCODER_LVDS, "LVDS");
990 
991 	intel_encoder->enable = intel_enable_lvds;
992 	intel_encoder->pre_enable = intel_pre_enable_lvds;
993 	intel_encoder->compute_config = intel_lvds_compute_config;
994 	if (HAS_PCH_SPLIT(dev_priv)) {
995 		intel_encoder->disable = pch_disable_lvds;
996 		intel_encoder->post_disable = pch_post_disable_lvds;
997 	} else {
998 		intel_encoder->disable = gmch_disable_lvds;
999 	}
1000 	intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1001 	intel_encoder->get_config = intel_lvds_get_config;
1002 	intel_connector->get_hw_state = intel_connector_get_hw_state;
1003 
1004 	intel_connector_attach_encoder(intel_connector, intel_encoder);
1005 	intel_encoder->type = INTEL_OUTPUT_LVDS;
1006 
1007 	intel_encoder->cloneable = 0;
1008 	if (HAS_PCH_SPLIT(dev))
1009 		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1010 	else if (IS_GEN4(dev))
1011 		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1012 	else
1013 		intel_encoder->crtc_mask = (1 << 1);
1014 
1015 	drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1016 	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1017 	connector->interlace_allowed = false;
1018 	connector->doublescan_allowed = false;
1019 
1020 	lvds_encoder->reg = lvds_reg;
1021 
1022 	/* create the scaling mode property */
1023 	drm_mode_create_scaling_mode_property(dev);
1024 	drm_object_attach_property(&connector->base,
1025 				      dev->mode_config.scaling_mode_property,
1026 				      DRM_MODE_SCALE_ASPECT);
1027 	intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
1028 	/*
1029 	 * LVDS discovery:
1030 	 * 1) check for EDID on DDC
1031 	 * 2) check for VBT data
1032 	 * 3) check to see if LVDS is already on
1033 	 *    if none of the above, no panel
1034 	 * 4) make sure lid is open
1035 	 *    if closed, act like it's not there for now
1036 	 */
1037 
1038 	/*
1039 	 * Attempt to get the fixed panel mode from DDC.  Assume that the
1040 	 * preferred mode is the right one.
1041 	 */
1042 	mutex_lock(&dev->mode_config.mutex);
1043 	if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
1044 		edid = drm_get_edid_switcheroo(connector,
1045 				    intel_gmbus_get_adapter(dev_priv, pin));
1046 	else
1047 		edid = drm_get_edid(connector,
1048 				    intel_gmbus_get_adapter(dev_priv, pin));
1049 	if (edid) {
1050 		if (drm_add_edid_modes(connector, edid)) {
1051 			drm_mode_connector_update_edid_property(connector,
1052 								edid);
1053 		} else {
1054 			kfree(edid);
1055 			edid = ERR_PTR(-EINVAL);
1056 		}
1057 	} else {
1058 		edid = ERR_PTR(-ENOENT);
1059 	}
1060 	lvds_connector->base.edid = edid;
1061 
1062 	list_for_each_entry(scan, &connector->probed_modes, head) {
1063 		if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1064 			DRM_DEBUG_KMS("using preferred mode from EDID: ");
1065 			drm_mode_debug_printmodeline(scan);
1066 
1067 			fixed_mode = drm_mode_duplicate(dev, scan);
1068 			if (fixed_mode)
1069 				goto out;
1070 		}
1071 	}
1072 
1073 	/* Failed to get EDID, what about VBT? */
1074 	if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1075 		DRM_DEBUG_KMS("using mode from VBT: ");
1076 		drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1077 
1078 		fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1079 		if (fixed_mode) {
1080 			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1081 			connector->display_info.width_mm = fixed_mode->width_mm;
1082 			connector->display_info.height_mm = fixed_mode->height_mm;
1083 			goto out;
1084 		}
1085 	}
1086 
1087 	/*
1088 	 * If we didn't get EDID, try checking if the panel is already turned
1089 	 * on.  If so, assume that whatever is currently programmed is the
1090 	 * correct mode.
1091 	 */
1092 
1093 	/* Ironlake: FIXME if still fail, not try pipe mode now */
1094 	if (HAS_PCH_SPLIT(dev))
1095 		goto failed;
1096 
1097 	pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
1098 	crtc = intel_get_crtc_for_pipe(dev, pipe);
1099 
1100 	if (crtc && (lvds & LVDS_PORT_EN)) {
1101 		fixed_mode = intel_crtc_mode_get(dev, crtc);
1102 		if (fixed_mode) {
1103 			DRM_DEBUG_KMS("using current (BIOS) mode: ");
1104 			drm_mode_debug_printmodeline(fixed_mode);
1105 			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1106 			goto out;
1107 		}
1108 	}
1109 
1110 	/* If we still don't have a mode after all that, give up. */
1111 	if (!fixed_mode)
1112 		goto failed;
1113 
1114 out:
1115 	mutex_unlock(&dev->mode_config.mutex);
1116 
1117 	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1118 	intel_panel_setup_backlight(connector, INVALID_PIPE);
1119 
1120 	lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1121 	DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1122 		      lvds_encoder->is_dual_link ? "dual" : "single");
1123 
1124 	lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1125 
1126 #if 0
1127 	lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1128 	if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
1129 		DRM_DEBUG_KMS("lid notifier registration failed\n");
1130 		lvds_connector->lid_notifier.notifier_call = NULL;
1131 	}
1132 #endif
1133 
1134 	return;
1135 
1136 failed:
1137 	mutex_unlock(&dev->mode_config.mutex);
1138 
1139 	DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1140 	drm_connector_cleanup(connector);
1141 	drm_encoder_cleanup(encoder);
1142 	kfree(lvds_encoder);
1143 	kfree(lvds_connector);
1144 	return;
1145 }
1146