1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include "opt_drm.h" 31 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drmP.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 #include "intel_drv.h" 41 #include <drm/i915_drm.h> 42 #include "i915_drv.h" 43 #include <linux/acpi.h> 44 45 /* Private structure for the integrated LVDS support */ 46 struct intel_lvds_connector { 47 struct intel_connector base; 48 49 struct notifier_block lid_notifier; 50 }; 51 52 struct intel_lvds_pps { 53 /* 100us units */ 54 int t1_t2; 55 int t3; 56 int t4; 57 int t5; 58 int tx; 59 60 int divider; 61 62 int port; 63 bool powerdown_on_reset; 64 }; 65 66 struct intel_lvds_encoder { 67 struct intel_encoder base; 68 69 bool is_dual_link; 70 i915_reg_t reg; 71 u32 a3_power; 72 73 struct intel_lvds_pps init_pps; 74 u32 init_lvds_val; 75 76 struct intel_lvds_connector *attached_connector; 77 }; 78 79 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 80 { 81 return container_of(encoder, struct intel_lvds_encoder, base.base); 82 } 83 84 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) 85 { 86 return container_of(connector, struct intel_lvds_connector, base.base); 87 } 88 89 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 90 enum i915_pipe *pipe) 91 { 92 struct drm_device *dev = encoder->base.dev; 93 struct drm_i915_private *dev_priv = to_i915(dev); 94 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 95 enum intel_display_power_domain power_domain; 96 u32 tmp; 97 bool ret; 98 99 power_domain = intel_display_port_power_domain(encoder); 100 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 101 return false; 102 103 ret = false; 104 105 tmp = I915_READ(lvds_encoder->reg); 106 107 if (!(tmp & LVDS_PORT_EN)) 108 goto out; 109 110 if (HAS_PCH_CPT(dev_priv)) 111 *pipe = PORT_TO_PIPE_CPT(tmp); 112 else 113 *pipe = PORT_TO_PIPE(tmp); 114 115 ret = true; 116 117 out: 118 intel_display_power_put(dev_priv, power_domain); 119 120 return ret; 121 } 122 123 static void intel_lvds_get_config(struct intel_encoder *encoder, 124 struct intel_crtc_state *pipe_config) 125 { 126 struct drm_device *dev = encoder->base.dev; 127 struct drm_i915_private *dev_priv = to_i915(dev); 128 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 129 u32 tmp, flags = 0; 130 131 tmp = I915_READ(lvds_encoder->reg); 132 if (tmp & LVDS_HSYNC_POLARITY) 133 flags |= DRM_MODE_FLAG_NHSYNC; 134 else 135 flags |= DRM_MODE_FLAG_PHSYNC; 136 if (tmp & LVDS_VSYNC_POLARITY) 137 flags |= DRM_MODE_FLAG_NVSYNC; 138 else 139 flags |= DRM_MODE_FLAG_PVSYNC; 140 141 pipe_config->base.adjusted_mode.flags |= flags; 142 143 if (INTEL_INFO(dev)->gen < 5) 144 pipe_config->gmch_pfit.lvds_border_bits = 145 tmp & LVDS_BORDER_ENABLE; 146 147 /* gen2/3 store dither state in pfit control, needs to match */ 148 if (INTEL_INFO(dev)->gen < 4) { 149 tmp = I915_READ(PFIT_CONTROL); 150 151 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 152 } 153 154 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 155 } 156 157 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 158 struct intel_lvds_pps *pps) 159 { 160 u32 val; 161 162 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; 163 164 val = I915_READ(PP_ON_DELAYS(0)); 165 pps->port = (val & PANEL_PORT_SELECT_MASK) >> 166 PANEL_PORT_SELECT_SHIFT; 167 pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >> 168 PANEL_POWER_UP_DELAY_SHIFT; 169 pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >> 170 PANEL_LIGHT_ON_DELAY_SHIFT; 171 172 val = I915_READ(PP_OFF_DELAYS(0)); 173 pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >> 174 PANEL_POWER_DOWN_DELAY_SHIFT; 175 pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >> 176 PANEL_LIGHT_OFF_DELAY_SHIFT; 177 178 val = I915_READ(PP_DIVISOR(0)); 179 pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >> 180 PP_REFERENCE_DIVIDER_SHIFT; 181 val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >> 182 PANEL_POWER_CYCLE_DELAY_SHIFT; 183 /* 184 * Remove the BSpec specified +1 (100ms) offset that accounts for a 185 * too short power-cycle delay due to the asynchronous programming of 186 * the register. 187 */ 188 if (val) 189 val--; 190 /* Convert from 100ms to 100us units */ 191 pps->t4 = val * 1000; 192 193 if (INTEL_INFO(dev_priv)->gen <= 4 && 194 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 195 DRM_DEBUG_KMS("Panel power timings uninitialized, " 196 "setting defaults\n"); 197 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 198 pps->t1_t2 = 40 * 10; 199 pps->t5 = 200 * 10; 200 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 201 pps->t3 = 35 * 10; 202 pps->tx = 200 * 10; 203 } 204 205 DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 206 "divider %d port %d powerdown_on_reset %d\n", 207 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 208 pps->divider, pps->port, pps->powerdown_on_reset); 209 } 210 211 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 212 struct intel_lvds_pps *pps) 213 { 214 u32 val; 215 216 val = I915_READ(PP_CONTROL(0)); 217 WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 218 if (pps->powerdown_on_reset) 219 val |= PANEL_POWER_RESET; 220 I915_WRITE(PP_CONTROL(0), val); 221 222 I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) | 223 (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) | 224 (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT)); 225 I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) | 226 (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT)); 227 228 val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT; 229 val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) << 230 PANEL_POWER_CYCLE_DELAY_SHIFT; 231 I915_WRITE(PP_DIVISOR(0), val); 232 } 233 234 static void intel_pre_enable_lvds(struct intel_encoder *encoder, 235 struct intel_crtc_state *pipe_config, 236 struct drm_connector_state *conn_state) 237 { 238 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 240 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 241 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 242 int pipe = crtc->pipe; 243 u32 temp; 244 245 if (HAS_PCH_SPLIT(dev_priv)) { 246 assert_fdi_rx_pll_disabled(dev_priv, pipe); 247 assert_shared_dpll_disabled(dev_priv, 248 pipe_config->shared_dpll); 249 } else { 250 assert_pll_disabled(dev_priv, pipe); 251 } 252 253 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); 254 255 temp = lvds_encoder->init_lvds_val; 256 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 257 258 if (HAS_PCH_CPT(dev_priv)) { 259 temp &= ~PORT_TRANS_SEL_MASK; 260 temp |= PORT_TRANS_SEL_CPT(pipe); 261 } else { 262 if (pipe == 1) { 263 temp |= LVDS_PIPEB_SELECT; 264 } else { 265 temp &= ~LVDS_PIPEB_SELECT; 266 } 267 } 268 269 /* set the corresponsding LVDS_BORDER bit */ 270 temp &= ~LVDS_BORDER_ENABLE; 271 temp |= pipe_config->gmch_pfit.lvds_border_bits; 272 /* Set the B0-B3 data pairs corresponding to whether we're going to 273 * set the DPLLs for dual-channel mode or not. 274 */ 275 if (lvds_encoder->is_dual_link) 276 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 277 else 278 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 279 280 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 281 * appropriately here, but we need to look more thoroughly into how 282 * panels behave in the two modes. For now, let's just maintain the 283 * value we got from the BIOS. 284 */ 285 temp &= ~LVDS_A3_POWER_MASK; 286 temp |= lvds_encoder->a3_power; 287 288 /* Set the dithering flag on LVDS as needed, note that there is no 289 * special lvds dither control bit on pch-split platforms, dithering is 290 * only controlled through the PIPECONF reg. */ 291 if (IS_GEN4(dev_priv)) { 292 /* Bspec wording suggests that LVDS port dithering only exists 293 * for 18bpp panels. */ 294 if (pipe_config->dither && pipe_config->pipe_bpp == 18) 295 temp |= LVDS_ENABLE_DITHER; 296 else 297 temp &= ~LVDS_ENABLE_DITHER; 298 } 299 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 300 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 301 temp |= LVDS_HSYNC_POLARITY; 302 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 303 temp |= LVDS_VSYNC_POLARITY; 304 305 I915_WRITE(lvds_encoder->reg, temp); 306 } 307 308 /** 309 * Sets the power state for the panel. 310 */ 311 static void intel_enable_lvds(struct intel_encoder *encoder, 312 struct intel_crtc_state *pipe_config, 313 struct drm_connector_state *conn_state) 314 { 315 struct drm_device *dev = encoder->base.dev; 316 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 317 struct intel_connector *intel_connector = 318 &lvds_encoder->attached_connector->base; 319 struct drm_i915_private *dev_priv = to_i915(dev); 320 321 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); 322 323 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); 324 POSTING_READ(lvds_encoder->reg); 325 if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000)) 326 DRM_ERROR("timed out waiting for panel to power on\n"); 327 328 intel_panel_enable_backlight(intel_connector); 329 } 330 331 static void intel_disable_lvds(struct intel_encoder *encoder, 332 struct intel_crtc_state *old_crtc_state, 333 struct drm_connector_state *old_conn_state) 334 { 335 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 337 338 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON); 339 if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000)) 340 DRM_ERROR("timed out waiting for panel to power off\n"); 341 342 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); 343 POSTING_READ(lvds_encoder->reg); 344 } 345 346 static void gmch_disable_lvds(struct intel_encoder *encoder, 347 struct intel_crtc_state *old_crtc_state, 348 struct drm_connector_state *old_conn_state) 349 350 { 351 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 352 struct intel_connector *intel_connector = 353 &lvds_encoder->attached_connector->base; 354 355 intel_panel_disable_backlight(intel_connector); 356 357 intel_disable_lvds(encoder, old_crtc_state, old_conn_state); 358 } 359 360 static void pch_disable_lvds(struct intel_encoder *encoder, 361 struct intel_crtc_state *old_crtc_state, 362 struct drm_connector_state *old_conn_state) 363 { 364 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 365 struct intel_connector *intel_connector = 366 &lvds_encoder->attached_connector->base; 367 368 intel_panel_disable_backlight(intel_connector); 369 } 370 371 static void pch_post_disable_lvds(struct intel_encoder *encoder, 372 struct intel_crtc_state *old_crtc_state, 373 struct drm_connector_state *old_conn_state) 374 { 375 intel_disable_lvds(encoder, old_crtc_state, old_conn_state); 376 } 377 378 static enum drm_mode_status 379 intel_lvds_mode_valid(struct drm_connector *connector, 380 struct drm_display_mode *mode) 381 { 382 struct intel_connector *intel_connector = to_intel_connector(connector); 383 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 384 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 385 386 if (mode->hdisplay > fixed_mode->hdisplay) 387 return MODE_PANEL; 388 if (mode->vdisplay > fixed_mode->vdisplay) 389 return MODE_PANEL; 390 if (fixed_mode->clock > max_pixclk) 391 return MODE_CLOCK_HIGH; 392 393 return MODE_OK; 394 } 395 396 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, 397 struct intel_crtc_state *pipe_config, 398 struct drm_connector_state *conn_state) 399 { 400 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 401 struct intel_lvds_encoder *lvds_encoder = 402 to_lvds_encoder(&intel_encoder->base); 403 struct intel_connector *intel_connector = 404 &lvds_encoder->attached_connector->base; 405 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 406 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 407 unsigned int lvds_bpp; 408 409 /* Should never happen!! */ 410 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { 411 DRM_ERROR("Can't support LVDS on pipe A\n"); 412 return false; 413 } 414 415 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 416 lvds_bpp = 8*3; 417 else 418 lvds_bpp = 6*3; 419 420 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 421 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", 422 pipe_config->pipe_bpp, lvds_bpp); 423 pipe_config->pipe_bpp = lvds_bpp; 424 } 425 426 /* 427 * We have timings from the BIOS for the panel, put them in 428 * to the adjusted mode. The CRTC will be set up for this mode, 429 * with the panel scaling set up to source from the H/VDisplay 430 * of the original mode. 431 */ 432 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 433 adjusted_mode); 434 435 if (HAS_PCH_SPLIT(dev_priv)) { 436 pipe_config->has_pch_encoder = true; 437 438 intel_pch_panel_fitting(intel_crtc, pipe_config, 439 intel_connector->panel.fitting_mode); 440 } else { 441 intel_gmch_panel_fitting(intel_crtc, pipe_config, 442 intel_connector->panel.fitting_mode); 443 444 } 445 446 /* 447 * XXX: It would be nice to support lower refresh rates on the 448 * panels to reduce power consumption, and perhaps match the 449 * user's requested refresh rate. 450 */ 451 452 return true; 453 } 454 455 /** 456 * Detect the LVDS connection. 457 * 458 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means 459 * connected and closed means disconnected. We also send hotplug events as 460 * needed, using lid status notification from the input layer. 461 */ 462 static enum drm_connector_status 463 intel_lvds_detect(struct drm_connector *connector, bool force) 464 { 465 struct drm_device *dev = connector->dev; 466 enum drm_connector_status status; 467 468 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 469 connector->base.id, connector->name); 470 471 status = intel_panel_detect(dev); 472 if (status != connector_status_unknown) 473 return status; 474 475 return connector_status_connected; 476 } 477 478 /** 479 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 480 */ 481 static int intel_lvds_get_modes(struct drm_connector *connector) 482 { 483 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); 484 struct drm_device *dev = connector->dev; 485 struct drm_display_mode *mode; 486 487 /* use cached edid if we have one */ 488 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 489 return drm_add_edid_modes(connector, lvds_connector->base.edid); 490 491 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); 492 if (mode == NULL) 493 return 0; 494 495 drm_mode_probed_add(connector, mode); 496 return 1; 497 } 498 499 #if 0 /* unused */ 500 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) 501 { 502 DRM_INFO("Skipping forced modeset for %s\n", id->ident); 503 return 1; 504 } 505 506 /* The GPU hangs up on these systems if modeset is performed on LID open */ 507 static const struct dmi_system_id intel_no_modeset_on_lid[] = { 508 { 509 .callback = intel_no_modeset_on_lid_dmi_callback, 510 .ident = "Toshiba Tecra A11", 511 .matches = { 512 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 513 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), 514 }, 515 }, 516 517 { } /* terminating entry */ 518 }; 519 520 /* 521 * Lid events. Note the use of 'modeset': 522 * - we set it to MODESET_ON_LID_OPEN on lid close, 523 * and set it to MODESET_DONE on open 524 * - we use it as a "only once" bit (ie we ignore 525 * duplicate events where it was already properly set) 526 * - the suspend/resume paths will set it to 527 * MODESET_SUSPENDED and ignore the lid open event, 528 * because they restore the mode ("lid open"). 529 */ 530 static int intel_lid_notify(struct notifier_block *nb, unsigned long val, 531 void *unused) 532 { 533 struct intel_lvds_connector *lvds_connector = 534 container_of(nb, struct intel_lvds_connector, lid_notifier); 535 struct drm_connector *connector = &lvds_connector->base.base; 536 struct drm_device *dev = connector->dev; 537 struct drm_i915_private *dev_priv = to_i915(dev); 538 539 if (dev->switch_power_state != DRM_SWITCH_POWER_ON) 540 return NOTIFY_OK; 541 542 mutex_lock(&dev_priv->modeset_restore_lock); 543 if (dev_priv->modeset_restore == MODESET_SUSPENDED) 544 goto exit; 545 /* 546 * check and update the status of LVDS connector after receiving 547 * the LID nofication event. 548 */ 549 connector->status = connector->funcs->detect(connector, false); 550 551 /* Don't force modeset on machines where it causes a GPU lockup */ 552 if (dmi_check_system(intel_no_modeset_on_lid)) 553 goto exit; 554 if (!acpi_lid_open()) { 555 /* do modeset on next lid open event */ 556 dev_priv->modeset_restore = MODESET_ON_LID_OPEN; 557 goto exit; 558 } 559 560 if (dev_priv->modeset_restore == MODESET_DONE) 561 goto exit; 562 563 /* 564 * Some old platform's BIOS love to wreak havoc while the lid is closed. 565 * We try to detect this here and undo any damage. The split for PCH 566 * platforms is rather conservative and a bit arbitrary expect that on 567 * those platforms VGA disabling requires actual legacy VGA I/O access, 568 * and as part of the cleanup in the hw state restore we also redisable 569 * the vga plane. 570 */ 571 if (!HAS_PCH_SPLIT(dev_priv)) 572 intel_display_resume(dev); 573 574 dev_priv->modeset_restore = MODESET_DONE; 575 576 exit: 577 mutex_unlock(&dev_priv->modeset_restore_lock); 578 return NOTIFY_OK; 579 } 580 #endif 581 582 /** 583 * intel_lvds_destroy - unregister and free LVDS structures 584 * @connector: connector to free 585 * 586 * Unregister the DDC bus for this connector then free the driver private 587 * structure. 588 */ 589 static void intel_lvds_destroy(struct drm_connector *connector) 590 { 591 struct intel_lvds_connector *lvds_connector = 592 to_lvds_connector(connector); 593 594 #if 0 595 if (lvds_connector->lid_notifier.notifier_call) 596 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); 597 #endif 598 599 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 600 kfree(lvds_connector->base.edid); 601 602 intel_panel_fini(&lvds_connector->base.panel); 603 604 drm_connector_cleanup(connector); 605 kfree(connector); 606 } 607 608 static int intel_lvds_set_property(struct drm_connector *connector, 609 struct drm_property *property, 610 uint64_t value) 611 { 612 struct intel_connector *intel_connector = to_intel_connector(connector); 613 struct drm_device *dev = connector->dev; 614 615 if (property == dev->mode_config.scaling_mode_property) { 616 struct drm_crtc *crtc; 617 618 if (value == DRM_MODE_SCALE_NONE) { 619 DRM_DEBUG_KMS("no scaling not supported\n"); 620 return -EINVAL; 621 } 622 623 if (intel_connector->panel.fitting_mode == value) { 624 /* the LVDS scaling property is not changed */ 625 return 0; 626 } 627 intel_connector->panel.fitting_mode = value; 628 629 crtc = intel_attached_encoder(connector)->base.crtc; 630 if (crtc && crtc->state->enable) { 631 /* 632 * If the CRTC is enabled, the display will be changed 633 * according to the new panel fitting mode. 634 */ 635 intel_crtc_restore_mode(crtc); 636 } 637 } 638 639 return 0; 640 } 641 642 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 643 .get_modes = intel_lvds_get_modes, 644 .mode_valid = intel_lvds_mode_valid, 645 }; 646 647 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 648 .dpms = drm_atomic_helper_connector_dpms, 649 .detect = intel_lvds_detect, 650 .fill_modes = drm_helper_probe_single_connector_modes, 651 .set_property = intel_lvds_set_property, 652 .atomic_get_property = intel_connector_atomic_get_property, 653 .late_register = intel_connector_register, 654 .early_unregister = intel_connector_unregister, 655 .destroy = intel_lvds_destroy, 656 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 657 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 658 }; 659 660 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 661 .destroy = intel_encoder_destroy, 662 }; 663 664 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 665 { 666 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 667 return 1; 668 } 669 670 /* These systems claim to have LVDS, but really don't */ 671 static const struct dmi_system_id intel_no_lvds[] = { 672 { 673 .callback = intel_no_lvds_dmi_callback, 674 .ident = "Apple Mac Mini (Core series)", 675 .matches = { 676 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 677 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 678 }, 679 }, 680 { 681 .callback = intel_no_lvds_dmi_callback, 682 .ident = "Apple Mac Mini (Core 2 series)", 683 .matches = { 684 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 685 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 686 }, 687 }, 688 { 689 .callback = intel_no_lvds_dmi_callback, 690 .ident = "MSI IM-945GSE-A", 691 .matches = { 692 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 693 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 694 }, 695 }, 696 { 697 .callback = intel_no_lvds_dmi_callback, 698 .ident = "Dell Studio Hybrid", 699 .matches = { 700 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 701 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 702 }, 703 }, 704 { 705 .callback = intel_no_lvds_dmi_callback, 706 .ident = "Dell OptiPlex FX170", 707 .matches = { 708 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 709 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 710 }, 711 }, 712 { 713 .callback = intel_no_lvds_dmi_callback, 714 .ident = "AOpen Mini PC", 715 .matches = { 716 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 717 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 718 }, 719 }, 720 { 721 .callback = intel_no_lvds_dmi_callback, 722 .ident = "AOpen Mini PC MP915", 723 .matches = { 724 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 725 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 726 }, 727 }, 728 { 729 .callback = intel_no_lvds_dmi_callback, 730 .ident = "AOpen i915GMm-HFS", 731 .matches = { 732 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 733 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 734 }, 735 }, 736 { 737 .callback = intel_no_lvds_dmi_callback, 738 .ident = "AOpen i45GMx-I", 739 .matches = { 740 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 741 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 742 }, 743 }, 744 { 745 .callback = intel_no_lvds_dmi_callback, 746 .ident = "Aopen i945GTt-VFA", 747 .matches = { 748 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 749 }, 750 }, 751 { 752 .callback = intel_no_lvds_dmi_callback, 753 .ident = "Clientron U800", 754 .matches = { 755 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 756 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 757 }, 758 }, 759 { 760 .callback = intel_no_lvds_dmi_callback, 761 .ident = "Clientron E830", 762 .matches = { 763 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 764 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 765 }, 766 }, 767 { 768 .callback = intel_no_lvds_dmi_callback, 769 .ident = "Asus EeeBox PC EB1007", 770 .matches = { 771 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 772 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 773 }, 774 }, 775 { 776 .callback = intel_no_lvds_dmi_callback, 777 .ident = "Asus AT5NM10T-I", 778 .matches = { 779 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 780 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 781 }, 782 }, 783 { 784 .callback = intel_no_lvds_dmi_callback, 785 .ident = "Hewlett-Packard HP t5740", 786 .matches = { 787 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 788 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 789 }, 790 }, 791 { 792 .callback = intel_no_lvds_dmi_callback, 793 .ident = "Hewlett-Packard t5745", 794 .matches = { 795 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 796 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 797 }, 798 }, 799 { 800 .callback = intel_no_lvds_dmi_callback, 801 .ident = "Hewlett-Packard st5747", 802 .matches = { 803 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 804 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 805 }, 806 }, 807 { 808 .callback = intel_no_lvds_dmi_callback, 809 .ident = "MSI Wind Box DC500", 810 .matches = { 811 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 812 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 813 }, 814 }, 815 { 816 .callback = intel_no_lvds_dmi_callback, 817 .ident = "Gigabyte GA-D525TUD", 818 .matches = { 819 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 820 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 821 }, 822 }, 823 { 824 .callback = intel_no_lvds_dmi_callback, 825 .ident = "Supermicro X7SPA-H", 826 .matches = { 827 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 828 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 829 }, 830 }, 831 { 832 .callback = intel_no_lvds_dmi_callback, 833 .ident = "Fujitsu Esprimo Q900", 834 .matches = { 835 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 836 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 837 }, 838 }, 839 { 840 .callback = intel_no_lvds_dmi_callback, 841 .ident = "Intel D410PT", 842 .matches = { 843 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 844 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 845 }, 846 }, 847 { 848 .callback = intel_no_lvds_dmi_callback, 849 .ident = "Intel D425KT", 850 .matches = { 851 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 852 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 853 }, 854 }, 855 { 856 .callback = intel_no_lvds_dmi_callback, 857 .ident = "Intel D510MO", 858 .matches = { 859 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 860 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 861 }, 862 }, 863 { 864 .callback = intel_no_lvds_dmi_callback, 865 .ident = "Intel D525MW", 866 .matches = { 867 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 868 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 869 }, 870 }, 871 872 { } /* terminating entry */ 873 }; 874 875 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 876 { 877 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 878 return 1; 879 } 880 881 static const struct dmi_system_id intel_dual_link_lvds[] = { 882 { 883 .callback = intel_dual_link_lvds_callback, 884 .ident = "Apple MacBook Pro 15\" (2010)", 885 .matches = { 886 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 887 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 888 }, 889 }, 890 { 891 .callback = intel_dual_link_lvds_callback, 892 .ident = "Apple MacBook Pro 15\" (2011)", 893 .matches = { 894 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 895 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 896 }, 897 }, 898 { 899 .callback = intel_dual_link_lvds_callback, 900 .ident = "Apple MacBook Pro 15\" (2012)", 901 .matches = { 902 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 903 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 904 }, 905 }, 906 { } /* terminating entry */ 907 }; 908 909 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev) 910 { 911 struct intel_encoder *intel_encoder; 912 913 for_each_intel_encoder(dev, intel_encoder) 914 if (intel_encoder->type == INTEL_OUTPUT_LVDS) 915 return intel_encoder; 916 917 return NULL; 918 } 919 920 bool intel_is_dual_link_lvds(struct drm_device *dev) 921 { 922 struct intel_encoder *encoder = intel_get_lvds_encoder(dev); 923 924 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; 925 } 926 927 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 928 { 929 struct drm_device *dev = lvds_encoder->base.base.dev; 930 unsigned int val; 931 struct drm_i915_private *dev_priv = to_i915(dev); 932 933 /* use the module option value if specified */ 934 if (i915.lvds_channel_mode > 0) 935 return i915.lvds_channel_mode == 2; 936 937 /* single channel LVDS is limited to 112 MHz */ 938 if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock 939 > 112999) 940 return true; 941 942 if (dmi_check_system(intel_dual_link_lvds)) 943 return true; 944 945 /* BIOS should set the proper LVDS register value at boot, but 946 * in reality, it doesn't set the value when the lid is closed; 947 * we need to check "the value to be set" in VBT when LVDS 948 * register is uninitialized. 949 */ 950 val = I915_READ(lvds_encoder->reg); 951 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) 952 val = dev_priv->vbt.bios_lvds_val; 953 954 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 955 } 956 957 static bool intel_lvds_supported(struct drm_i915_private *dev_priv) 958 { 959 /* With the introduction of the PCH we gained a dedicated 960 * LVDS presence pin, use it. */ 961 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) 962 return true; 963 964 /* Otherwise LVDS was only attached to mobile products, 965 * except for the inglorious 830gm */ 966 if (INTEL_GEN(dev_priv) <= 4 && 967 IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) 968 return true; 969 970 return false; 971 } 972 973 /** 974 * intel_lvds_init - setup LVDS connectors on this device 975 * @dev: drm device 976 * 977 * Create the connector, register the LVDS DDC bus, and try to figure out what 978 * modes we can display on the LVDS panel (if present). 979 */ 980 void intel_lvds_init(struct drm_device *dev) 981 { 982 struct drm_i915_private *dev_priv = to_i915(dev); 983 struct intel_lvds_encoder *lvds_encoder; 984 struct intel_encoder *intel_encoder; 985 struct intel_lvds_connector *lvds_connector; 986 struct intel_connector *intel_connector; 987 struct drm_connector *connector; 988 struct drm_encoder *encoder; 989 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 990 struct drm_display_mode *fixed_mode = NULL; 991 struct drm_display_mode *downclock_mode = NULL; 992 struct edid *edid; 993 struct drm_crtc *crtc; 994 i915_reg_t lvds_reg; 995 u32 lvds; 996 int pipe; 997 u8 pin; 998 999 if (!intel_lvds_supported(dev_priv)) 1000 return; 1001 1002 /* Skip init on machines we know falsely report LVDS */ 1003 if (dmi_check_system(intel_no_lvds)) 1004 return; 1005 1006 if (HAS_PCH_SPLIT(dev_priv)) 1007 lvds_reg = PCH_LVDS; 1008 else 1009 lvds_reg = LVDS; 1010 1011 lvds = I915_READ(lvds_reg); 1012 1013 if (HAS_PCH_SPLIT(dev_priv)) { 1014 if ((lvds & LVDS_DETECTED) == 0) 1015 return; 1016 if (dev_priv->vbt.edp.support) { 1017 DRM_DEBUG_KMS("disable LVDS for eDP support\n"); 1018 return; 1019 } 1020 } 1021 1022 pin = GMBUS_PIN_PANEL; 1023 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 1024 if ((lvds & LVDS_PORT_EN) == 0) { 1025 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); 1026 return; 1027 } 1028 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); 1029 } 1030 1031 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 1032 if (!lvds_encoder) 1033 return; 1034 1035 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); 1036 if (!lvds_connector) { 1037 kfree(lvds_encoder); 1038 return; 1039 } 1040 1041 if (intel_connector_init(&lvds_connector->base) < 0) { 1042 kfree(lvds_connector); 1043 kfree(lvds_encoder); 1044 return; 1045 } 1046 1047 lvds_encoder->attached_connector = lvds_connector; 1048 1049 intel_encoder = &lvds_encoder->base; 1050 encoder = &intel_encoder->base; 1051 intel_connector = &lvds_connector->base; 1052 connector = &intel_connector->base; 1053 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 1054 DRM_MODE_CONNECTOR_LVDS); 1055 1056 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 1057 DRM_MODE_ENCODER_LVDS, "LVDS"); 1058 1059 intel_encoder->enable = intel_enable_lvds; 1060 intel_encoder->pre_enable = intel_pre_enable_lvds; 1061 intel_encoder->compute_config = intel_lvds_compute_config; 1062 if (HAS_PCH_SPLIT(dev_priv)) { 1063 intel_encoder->disable = pch_disable_lvds; 1064 intel_encoder->post_disable = pch_post_disable_lvds; 1065 } else { 1066 intel_encoder->disable = gmch_disable_lvds; 1067 } 1068 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 1069 intel_encoder->get_config = intel_lvds_get_config; 1070 intel_connector->get_hw_state = intel_connector_get_hw_state; 1071 1072 intel_connector_attach_encoder(intel_connector, intel_encoder); 1073 1074 intel_encoder->type = INTEL_OUTPUT_LVDS; 1075 intel_encoder->port = PORT_NONE; 1076 intel_encoder->cloneable = 0; 1077 if (HAS_PCH_SPLIT(dev_priv)) 1078 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1079 else if (IS_GEN4(dev_priv)) 1080 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1081 else 1082 intel_encoder->crtc_mask = (1 << 1); 1083 1084 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 1085 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1086 connector->interlace_allowed = false; 1087 connector->doublescan_allowed = false; 1088 1089 lvds_encoder->reg = lvds_reg; 1090 1091 /* create the scaling mode property */ 1092 drm_mode_create_scaling_mode_property(dev); 1093 drm_object_attach_property(&connector->base, 1094 dev->mode_config.scaling_mode_property, 1095 DRM_MODE_SCALE_ASPECT); 1096 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 1097 1098 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); 1099 lvds_encoder->init_lvds_val = lvds; 1100 1101 /* 1102 * LVDS discovery: 1103 * 1) check for EDID on DDC 1104 * 2) check for VBT data 1105 * 3) check to see if LVDS is already on 1106 * if none of the above, no panel 1107 * 4) make sure lid is open 1108 * if closed, act like it's not there for now 1109 */ 1110 1111 /* 1112 * Attempt to get the fixed panel mode from DDC. Assume that the 1113 * preferred mode is the right one. 1114 */ 1115 mutex_lock(&dev->mode_config.mutex); 1116 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 1117 edid = drm_get_edid_switcheroo(connector, 1118 intel_gmbus_get_adapter(dev_priv, pin)); 1119 else 1120 edid = drm_get_edid(connector, 1121 intel_gmbus_get_adapter(dev_priv, pin)); 1122 if (edid) { 1123 if (drm_add_edid_modes(connector, edid)) { 1124 drm_mode_connector_update_edid_property(connector, 1125 edid); 1126 } else { 1127 kfree(edid); 1128 edid = ERR_PTR(-EINVAL); 1129 } 1130 } else { 1131 edid = ERR_PTR(-ENOENT); 1132 } 1133 lvds_connector->base.edid = edid; 1134 1135 list_for_each_entry(scan, &connector->probed_modes, head) { 1136 if (scan->type & DRM_MODE_TYPE_PREFERRED) { 1137 DRM_DEBUG_KMS("using preferred mode from EDID: "); 1138 drm_mode_debug_printmodeline(scan); 1139 1140 fixed_mode = drm_mode_duplicate(dev, scan); 1141 if (fixed_mode) 1142 goto out; 1143 } 1144 } 1145 1146 /* Failed to get EDID, what about VBT? */ 1147 if (dev_priv->vbt.lfp_lvds_vbt_mode) { 1148 DRM_DEBUG_KMS("using mode from VBT: "); 1149 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); 1150 1151 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); 1152 if (fixed_mode) { 1153 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1154 connector->display_info.width_mm = fixed_mode->width_mm; 1155 connector->display_info.height_mm = fixed_mode->height_mm; 1156 goto out; 1157 } 1158 } 1159 1160 /* 1161 * If we didn't get EDID, try checking if the panel is already turned 1162 * on. If so, assume that whatever is currently programmed is the 1163 * correct mode. 1164 */ 1165 1166 /* Ironlake: FIXME if still fail, not try pipe mode now */ 1167 if (HAS_PCH_SPLIT(dev_priv)) 1168 goto failed; 1169 1170 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; 1171 crtc = intel_get_crtc_for_pipe(dev, pipe); 1172 1173 if (crtc && (lvds & LVDS_PORT_EN)) { 1174 fixed_mode = intel_crtc_mode_get(dev, crtc); 1175 if (fixed_mode) { 1176 DRM_DEBUG_KMS("using current (BIOS) mode: "); 1177 drm_mode_debug_printmodeline(fixed_mode); 1178 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1179 goto out; 1180 } 1181 } 1182 1183 /* If we still don't have a mode after all that, give up. */ 1184 if (!fixed_mode) 1185 goto failed; 1186 1187 out: 1188 mutex_unlock(&dev->mode_config.mutex); 1189 1190 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 1191 intel_panel_setup_backlight(connector, INVALID_PIPE); 1192 1193 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1194 DRM_DEBUG_KMS("detected %s-link lvds configuration\n", 1195 lvds_encoder->is_dual_link ? "dual" : "single"); 1196 1197 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1198 1199 #if 0 1200 lvds_connector->lid_notifier.notifier_call = intel_lid_notify; 1201 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { 1202 DRM_DEBUG_KMS("lid notifier registration failed\n"); 1203 lvds_connector->lid_notifier.notifier_call = NULL; 1204 } 1205 #endif 1206 1207 return; 1208 1209 failed: 1210 mutex_unlock(&dev->mode_config.mutex); 1211 1212 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1213 drm_connector_cleanup(connector); 1214 drm_encoder_cleanup(encoder); 1215 kfree(lvds_encoder); 1216 kfree(lvds_connector); 1217 return; 1218 } 1219