1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include "opt_drm.h" 31 32 #include <linux/dmi.h> 33 #include <linux/i2c.h> 34 #include <linux/slab.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drmP.h> 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_edid.h> 40 #include "intel_drv.h" 41 #include <drm/i915_drm.h> 42 #include "i915_drv.h" 43 #include <linux/acpi.h> 44 45 /* Private structure for the integrated LVDS support */ 46 struct intel_lvds_connector { 47 struct intel_connector base; 48 49 struct notifier_block lid_notifier; 50 }; 51 52 struct intel_lvds_pps { 53 /* 100us units */ 54 int t1_t2; 55 int t3; 56 int t4; 57 int t5; 58 int tx; 59 60 int divider; 61 62 int port; 63 bool powerdown_on_reset; 64 }; 65 66 struct intel_lvds_encoder { 67 struct intel_encoder base; 68 69 bool is_dual_link; 70 i915_reg_t reg; 71 u32 a3_power; 72 73 struct intel_lvds_pps init_pps; 74 u32 init_lvds_val; 75 76 struct intel_lvds_connector *attached_connector; 77 }; 78 79 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 80 { 81 return container_of(encoder, struct intel_lvds_encoder, base.base); 82 } 83 84 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) 85 { 86 return container_of(connector, struct intel_lvds_connector, base.base); 87 } 88 89 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 90 enum i915_pipe *pipe) 91 { 92 struct drm_device *dev = encoder->base.dev; 93 struct drm_i915_private *dev_priv = to_i915(dev); 94 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 95 enum intel_display_power_domain power_domain; 96 u32 tmp; 97 bool ret; 98 99 power_domain = intel_display_port_power_domain(encoder); 100 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 101 return false; 102 103 ret = false; 104 105 tmp = I915_READ(lvds_encoder->reg); 106 107 if (!(tmp & LVDS_PORT_EN)) 108 goto out; 109 110 if (HAS_PCH_CPT(dev_priv)) 111 *pipe = PORT_TO_PIPE_CPT(tmp); 112 else 113 *pipe = PORT_TO_PIPE(tmp); 114 115 ret = true; 116 117 out: 118 intel_display_power_put(dev_priv, power_domain); 119 120 return ret; 121 } 122 123 static void intel_lvds_get_config(struct intel_encoder *encoder, 124 struct intel_crtc_state *pipe_config) 125 { 126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 127 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 128 u32 tmp, flags = 0; 129 130 tmp = I915_READ(lvds_encoder->reg); 131 if (tmp & LVDS_HSYNC_POLARITY) 132 flags |= DRM_MODE_FLAG_NHSYNC; 133 else 134 flags |= DRM_MODE_FLAG_PHSYNC; 135 if (tmp & LVDS_VSYNC_POLARITY) 136 flags |= DRM_MODE_FLAG_NVSYNC; 137 else 138 flags |= DRM_MODE_FLAG_PVSYNC; 139 140 pipe_config->base.adjusted_mode.flags |= flags; 141 142 if (INTEL_GEN(dev_priv) < 5) 143 pipe_config->gmch_pfit.lvds_border_bits = 144 tmp & LVDS_BORDER_ENABLE; 145 146 /* gen2/3 store dither state in pfit control, needs to match */ 147 if (INTEL_GEN(dev_priv) < 4) { 148 tmp = I915_READ(PFIT_CONTROL); 149 150 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 151 } 152 153 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 154 } 155 156 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, 157 struct intel_lvds_pps *pps) 158 { 159 u32 val; 160 161 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; 162 163 val = I915_READ(PP_ON_DELAYS(0)); 164 pps->port = (val & PANEL_PORT_SELECT_MASK) >> 165 PANEL_PORT_SELECT_SHIFT; 166 pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >> 167 PANEL_POWER_UP_DELAY_SHIFT; 168 pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >> 169 PANEL_LIGHT_ON_DELAY_SHIFT; 170 171 val = I915_READ(PP_OFF_DELAYS(0)); 172 pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >> 173 PANEL_POWER_DOWN_DELAY_SHIFT; 174 pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >> 175 PANEL_LIGHT_OFF_DELAY_SHIFT; 176 177 val = I915_READ(PP_DIVISOR(0)); 178 pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >> 179 PP_REFERENCE_DIVIDER_SHIFT; 180 val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >> 181 PANEL_POWER_CYCLE_DELAY_SHIFT; 182 /* 183 * Remove the BSpec specified +1 (100ms) offset that accounts for a 184 * too short power-cycle delay due to the asynchronous programming of 185 * the register. 186 */ 187 if (val) 188 val--; 189 /* Convert from 100ms to 100us units */ 190 pps->t4 = val * 1000; 191 192 if (INTEL_INFO(dev_priv)->gen <= 4 && 193 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { 194 DRM_DEBUG_KMS("Panel power timings uninitialized, " 195 "setting defaults\n"); 196 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ 197 pps->t1_t2 = 40 * 10; 198 pps->t5 = 200 * 10; 199 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ 200 pps->t3 = 35 * 10; 201 pps->tx = 200 * 10; 202 } 203 204 DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " 205 "divider %d port %d powerdown_on_reset %d\n", 206 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, 207 pps->divider, pps->port, pps->powerdown_on_reset); 208 } 209 210 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, 211 struct intel_lvds_pps *pps) 212 { 213 u32 val; 214 215 val = I915_READ(PP_CONTROL(0)); 216 WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); 217 if (pps->powerdown_on_reset) 218 val |= PANEL_POWER_RESET; 219 I915_WRITE(PP_CONTROL(0), val); 220 221 I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) | 222 (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) | 223 (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT)); 224 I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) | 225 (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT)); 226 227 val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT; 228 val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) << 229 PANEL_POWER_CYCLE_DELAY_SHIFT; 230 I915_WRITE(PP_DIVISOR(0), val); 231 } 232 233 static void intel_pre_enable_lvds(struct intel_encoder *encoder, 234 struct intel_crtc_state *pipe_config, 235 struct drm_connector_state *conn_state) 236 { 237 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 238 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 239 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 240 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 241 int pipe = crtc->pipe; 242 u32 temp; 243 244 if (HAS_PCH_SPLIT(dev_priv)) { 245 assert_fdi_rx_pll_disabled(dev_priv, pipe); 246 assert_shared_dpll_disabled(dev_priv, 247 pipe_config->shared_dpll); 248 } else { 249 assert_pll_disabled(dev_priv, pipe); 250 } 251 252 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); 253 254 temp = lvds_encoder->init_lvds_val; 255 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 256 257 if (HAS_PCH_CPT(dev_priv)) { 258 temp &= ~PORT_TRANS_SEL_MASK; 259 temp |= PORT_TRANS_SEL_CPT(pipe); 260 } else { 261 if (pipe == 1) { 262 temp |= LVDS_PIPEB_SELECT; 263 } else { 264 temp &= ~LVDS_PIPEB_SELECT; 265 } 266 } 267 268 /* set the corresponsding LVDS_BORDER bit */ 269 temp &= ~LVDS_BORDER_ENABLE; 270 temp |= pipe_config->gmch_pfit.lvds_border_bits; 271 /* Set the B0-B3 data pairs corresponding to whether we're going to 272 * set the DPLLs for dual-channel mode or not. 273 */ 274 if (lvds_encoder->is_dual_link) 275 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 276 else 277 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 278 279 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 280 * appropriately here, but we need to look more thoroughly into how 281 * panels behave in the two modes. For now, let's just maintain the 282 * value we got from the BIOS. 283 */ 284 temp &= ~LVDS_A3_POWER_MASK; 285 temp |= lvds_encoder->a3_power; 286 287 /* Set the dithering flag on LVDS as needed, note that there is no 288 * special lvds dither control bit on pch-split platforms, dithering is 289 * only controlled through the PIPECONF reg. */ 290 if (IS_GEN4(dev_priv)) { 291 /* Bspec wording suggests that LVDS port dithering only exists 292 * for 18bpp panels. */ 293 if (pipe_config->dither && pipe_config->pipe_bpp == 18) 294 temp |= LVDS_ENABLE_DITHER; 295 else 296 temp &= ~LVDS_ENABLE_DITHER; 297 } 298 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 299 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 300 temp |= LVDS_HSYNC_POLARITY; 301 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 302 temp |= LVDS_VSYNC_POLARITY; 303 304 I915_WRITE(lvds_encoder->reg, temp); 305 } 306 307 /** 308 * Sets the power state for the panel. 309 */ 310 static void intel_enable_lvds(struct intel_encoder *encoder, 311 struct intel_crtc_state *pipe_config, 312 struct drm_connector_state *conn_state) 313 { 314 struct drm_device *dev = encoder->base.dev; 315 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 316 struct intel_connector *intel_connector = 317 &lvds_encoder->attached_connector->base; 318 struct drm_i915_private *dev_priv = to_i915(dev); 319 320 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); 321 322 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); 323 POSTING_READ(lvds_encoder->reg); 324 if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000)) 325 DRM_ERROR("timed out waiting for panel to power on\n"); 326 327 intel_panel_enable_backlight(intel_connector); 328 } 329 330 static void intel_disable_lvds(struct intel_encoder *encoder, 331 struct intel_crtc_state *old_crtc_state, 332 struct drm_connector_state *old_conn_state) 333 { 334 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 335 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 336 337 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON); 338 if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000)) 339 DRM_ERROR("timed out waiting for panel to power off\n"); 340 341 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); 342 POSTING_READ(lvds_encoder->reg); 343 } 344 345 static void gmch_disable_lvds(struct intel_encoder *encoder, 346 struct intel_crtc_state *old_crtc_state, 347 struct drm_connector_state *old_conn_state) 348 349 { 350 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 351 struct intel_connector *intel_connector = 352 &lvds_encoder->attached_connector->base; 353 354 intel_panel_disable_backlight(intel_connector); 355 356 intel_disable_lvds(encoder, old_crtc_state, old_conn_state); 357 } 358 359 static void pch_disable_lvds(struct intel_encoder *encoder, 360 struct intel_crtc_state *old_crtc_state, 361 struct drm_connector_state *old_conn_state) 362 { 363 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 364 struct intel_connector *intel_connector = 365 &lvds_encoder->attached_connector->base; 366 367 intel_panel_disable_backlight(intel_connector); 368 } 369 370 static void pch_post_disable_lvds(struct intel_encoder *encoder, 371 struct intel_crtc_state *old_crtc_state, 372 struct drm_connector_state *old_conn_state) 373 { 374 intel_disable_lvds(encoder, old_crtc_state, old_conn_state); 375 } 376 377 static enum drm_mode_status 378 intel_lvds_mode_valid(struct drm_connector *connector, 379 struct drm_display_mode *mode) 380 { 381 struct intel_connector *intel_connector = to_intel_connector(connector); 382 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 383 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 384 385 if (mode->hdisplay > fixed_mode->hdisplay) 386 return MODE_PANEL; 387 if (mode->vdisplay > fixed_mode->vdisplay) 388 return MODE_PANEL; 389 if (fixed_mode->clock > max_pixclk) 390 return MODE_CLOCK_HIGH; 391 392 return MODE_OK; 393 } 394 395 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, 396 struct intel_crtc_state *pipe_config, 397 struct drm_connector_state *conn_state) 398 { 399 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 400 struct intel_lvds_encoder *lvds_encoder = 401 to_lvds_encoder(&intel_encoder->base); 402 struct intel_connector *intel_connector = 403 &lvds_encoder->attached_connector->base; 404 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 405 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 406 unsigned int lvds_bpp; 407 408 /* Should never happen!! */ 409 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { 410 DRM_ERROR("Can't support LVDS on pipe A\n"); 411 return false; 412 } 413 414 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 415 lvds_bpp = 8*3; 416 else 417 lvds_bpp = 6*3; 418 419 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 420 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", 421 pipe_config->pipe_bpp, lvds_bpp); 422 pipe_config->pipe_bpp = lvds_bpp; 423 } 424 425 /* 426 * We have timings from the BIOS for the panel, put them in 427 * to the adjusted mode. The CRTC will be set up for this mode, 428 * with the panel scaling set up to source from the H/VDisplay 429 * of the original mode. 430 */ 431 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 432 adjusted_mode); 433 434 if (HAS_PCH_SPLIT(dev_priv)) { 435 pipe_config->has_pch_encoder = true; 436 437 intel_pch_panel_fitting(intel_crtc, pipe_config, 438 intel_connector->panel.fitting_mode); 439 } else { 440 intel_gmch_panel_fitting(intel_crtc, pipe_config, 441 intel_connector->panel.fitting_mode); 442 443 } 444 445 /* 446 * XXX: It would be nice to support lower refresh rates on the 447 * panels to reduce power consumption, and perhaps match the 448 * user's requested refresh rate. 449 */ 450 451 return true; 452 } 453 454 /** 455 * Detect the LVDS connection. 456 * 457 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means 458 * connected and closed means disconnected. We also send hotplug events as 459 * needed, using lid status notification from the input layer. 460 */ 461 static enum drm_connector_status 462 intel_lvds_detect(struct drm_connector *connector, bool force) 463 { 464 struct drm_device *dev = connector->dev; 465 enum drm_connector_status status; 466 467 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 468 connector->base.id, connector->name); 469 470 status = intel_panel_detect(dev); 471 if (status != connector_status_unknown) 472 return status; 473 474 return connector_status_connected; 475 } 476 477 /** 478 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 479 */ 480 static int intel_lvds_get_modes(struct drm_connector *connector) 481 { 482 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); 483 struct drm_device *dev = connector->dev; 484 struct drm_display_mode *mode; 485 486 /* use cached edid if we have one */ 487 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 488 return drm_add_edid_modes(connector, lvds_connector->base.edid); 489 490 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); 491 if (mode == NULL) 492 return 0; 493 494 drm_mode_probed_add(connector, mode); 495 return 1; 496 } 497 498 #if 0 /* unused */ 499 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) 500 { 501 DRM_INFO("Skipping forced modeset for %s\n", id->ident); 502 return 1; 503 } 504 505 /* The GPU hangs up on these systems if modeset is performed on LID open */ 506 static const struct dmi_system_id intel_no_modeset_on_lid[] = { 507 { 508 .callback = intel_no_modeset_on_lid_dmi_callback, 509 .ident = "Toshiba Tecra A11", 510 .matches = { 511 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 512 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), 513 }, 514 }, 515 516 { } /* terminating entry */ 517 }; 518 519 /* 520 * Lid events. Note the use of 'modeset': 521 * - we set it to MODESET_ON_LID_OPEN on lid close, 522 * and set it to MODESET_DONE on open 523 * - we use it as a "only once" bit (ie we ignore 524 * duplicate events where it was already properly set) 525 * - the suspend/resume paths will set it to 526 * MODESET_SUSPENDED and ignore the lid open event, 527 * because they restore the mode ("lid open"). 528 */ 529 static int intel_lid_notify(struct notifier_block *nb, unsigned long val, 530 void *unused) 531 { 532 struct intel_lvds_connector *lvds_connector = 533 container_of(nb, struct intel_lvds_connector, lid_notifier); 534 struct drm_connector *connector = &lvds_connector->base.base; 535 struct drm_device *dev = connector->dev; 536 struct drm_i915_private *dev_priv = to_i915(dev); 537 538 if (dev->switch_power_state != DRM_SWITCH_POWER_ON) 539 return NOTIFY_OK; 540 541 mutex_lock(&dev_priv->modeset_restore_lock); 542 if (dev_priv->modeset_restore == MODESET_SUSPENDED) 543 goto exit; 544 /* 545 * check and update the status of LVDS connector after receiving 546 * the LID nofication event. 547 */ 548 connector->status = connector->funcs->detect(connector, false); 549 550 /* Don't force modeset on machines where it causes a GPU lockup */ 551 if (dmi_check_system(intel_no_modeset_on_lid)) 552 goto exit; 553 if (!acpi_lid_open()) { 554 /* do modeset on next lid open event */ 555 dev_priv->modeset_restore = MODESET_ON_LID_OPEN; 556 goto exit; 557 } 558 559 if (dev_priv->modeset_restore == MODESET_DONE) 560 goto exit; 561 562 /* 563 * Some old platform's BIOS love to wreak havoc while the lid is closed. 564 * We try to detect this here and undo any damage. The split for PCH 565 * platforms is rather conservative and a bit arbitrary expect that on 566 * those platforms VGA disabling requires actual legacy VGA I/O access, 567 * and as part of the cleanup in the hw state restore we also redisable 568 * the vga plane. 569 */ 570 if (!HAS_PCH_SPLIT(dev_priv)) 571 intel_display_resume(dev); 572 573 dev_priv->modeset_restore = MODESET_DONE; 574 575 exit: 576 mutex_unlock(&dev_priv->modeset_restore_lock); 577 return NOTIFY_OK; 578 } 579 #endif 580 581 /** 582 * intel_lvds_destroy - unregister and free LVDS structures 583 * @connector: connector to free 584 * 585 * Unregister the DDC bus for this connector then free the driver private 586 * structure. 587 */ 588 static void intel_lvds_destroy(struct drm_connector *connector) 589 { 590 struct intel_lvds_connector *lvds_connector = 591 to_lvds_connector(connector); 592 593 #if 0 594 if (lvds_connector->lid_notifier.notifier_call) 595 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); 596 #endif 597 598 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 599 kfree(lvds_connector->base.edid); 600 601 intel_panel_fini(&lvds_connector->base.panel); 602 603 drm_connector_cleanup(connector); 604 kfree(connector); 605 } 606 607 static int intel_lvds_set_property(struct drm_connector *connector, 608 struct drm_property *property, 609 uint64_t value) 610 { 611 struct intel_connector *intel_connector = to_intel_connector(connector); 612 struct drm_device *dev = connector->dev; 613 614 if (property == dev->mode_config.scaling_mode_property) { 615 struct drm_crtc *crtc; 616 617 if (value == DRM_MODE_SCALE_NONE) { 618 DRM_DEBUG_KMS("no scaling not supported\n"); 619 return -EINVAL; 620 } 621 622 if (intel_connector->panel.fitting_mode == value) { 623 /* the LVDS scaling property is not changed */ 624 return 0; 625 } 626 intel_connector->panel.fitting_mode = value; 627 628 crtc = intel_attached_encoder(connector)->base.crtc; 629 if (crtc && crtc->state->enable) { 630 /* 631 * If the CRTC is enabled, the display will be changed 632 * according to the new panel fitting mode. 633 */ 634 intel_crtc_restore_mode(crtc); 635 } 636 } 637 638 return 0; 639 } 640 641 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 642 .get_modes = intel_lvds_get_modes, 643 .mode_valid = intel_lvds_mode_valid, 644 }; 645 646 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 647 .dpms = drm_atomic_helper_connector_dpms, 648 .detect = intel_lvds_detect, 649 .fill_modes = drm_helper_probe_single_connector_modes, 650 .set_property = intel_lvds_set_property, 651 .atomic_get_property = intel_connector_atomic_get_property, 652 .late_register = intel_connector_register, 653 .early_unregister = intel_connector_unregister, 654 .destroy = intel_lvds_destroy, 655 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 656 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 657 }; 658 659 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 660 .destroy = intel_encoder_destroy, 661 }; 662 663 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 664 { 665 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 666 return 1; 667 } 668 669 /* These systems claim to have LVDS, but really don't */ 670 static const struct dmi_system_id intel_no_lvds[] = { 671 { 672 .callback = intel_no_lvds_dmi_callback, 673 .ident = "Apple Mac Mini (Core series)", 674 .matches = { 675 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 676 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 677 }, 678 }, 679 { 680 .callback = intel_no_lvds_dmi_callback, 681 .ident = "Apple Mac Mini (Core 2 series)", 682 .matches = { 683 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 684 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 685 }, 686 }, 687 { 688 .callback = intel_no_lvds_dmi_callback, 689 .ident = "MSI IM-945GSE-A", 690 .matches = { 691 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 692 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 693 }, 694 }, 695 { 696 .callback = intel_no_lvds_dmi_callback, 697 .ident = "Dell Studio Hybrid", 698 .matches = { 699 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 700 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 701 }, 702 }, 703 { 704 .callback = intel_no_lvds_dmi_callback, 705 .ident = "Dell OptiPlex FX170", 706 .matches = { 707 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 708 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 709 }, 710 }, 711 { 712 .callback = intel_no_lvds_dmi_callback, 713 .ident = "AOpen Mini PC", 714 .matches = { 715 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 716 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 717 }, 718 }, 719 { 720 .callback = intel_no_lvds_dmi_callback, 721 .ident = "AOpen Mini PC MP915", 722 .matches = { 723 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 724 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 725 }, 726 }, 727 { 728 .callback = intel_no_lvds_dmi_callback, 729 .ident = "AOpen i915GMm-HFS", 730 .matches = { 731 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 732 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 733 }, 734 }, 735 { 736 .callback = intel_no_lvds_dmi_callback, 737 .ident = "AOpen i45GMx-I", 738 .matches = { 739 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 740 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 741 }, 742 }, 743 { 744 .callback = intel_no_lvds_dmi_callback, 745 .ident = "Aopen i945GTt-VFA", 746 .matches = { 747 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 748 }, 749 }, 750 { 751 .callback = intel_no_lvds_dmi_callback, 752 .ident = "Clientron U800", 753 .matches = { 754 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 755 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 756 }, 757 }, 758 { 759 .callback = intel_no_lvds_dmi_callback, 760 .ident = "Clientron E830", 761 .matches = { 762 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 763 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 764 }, 765 }, 766 { 767 .callback = intel_no_lvds_dmi_callback, 768 .ident = "Asus EeeBox PC EB1007", 769 .matches = { 770 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 771 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 772 }, 773 }, 774 { 775 .callback = intel_no_lvds_dmi_callback, 776 .ident = "Asus AT5NM10T-I", 777 .matches = { 778 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 779 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 780 }, 781 }, 782 { 783 .callback = intel_no_lvds_dmi_callback, 784 .ident = "Hewlett-Packard HP t5740", 785 .matches = { 786 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 787 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 788 }, 789 }, 790 { 791 .callback = intel_no_lvds_dmi_callback, 792 .ident = "Hewlett-Packard t5745", 793 .matches = { 794 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 795 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 796 }, 797 }, 798 { 799 .callback = intel_no_lvds_dmi_callback, 800 .ident = "Hewlett-Packard st5747", 801 .matches = { 802 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 803 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 804 }, 805 }, 806 { 807 .callback = intel_no_lvds_dmi_callback, 808 .ident = "MSI Wind Box DC500", 809 .matches = { 810 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 811 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 812 }, 813 }, 814 { 815 .callback = intel_no_lvds_dmi_callback, 816 .ident = "Gigabyte GA-D525TUD", 817 .matches = { 818 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 819 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 820 }, 821 }, 822 { 823 .callback = intel_no_lvds_dmi_callback, 824 .ident = "Supermicro X7SPA-H", 825 .matches = { 826 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 827 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 828 }, 829 }, 830 { 831 .callback = intel_no_lvds_dmi_callback, 832 .ident = "Fujitsu Esprimo Q900", 833 .matches = { 834 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 835 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 836 }, 837 }, 838 { 839 .callback = intel_no_lvds_dmi_callback, 840 .ident = "Intel D410PT", 841 .matches = { 842 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 843 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 844 }, 845 }, 846 { 847 .callback = intel_no_lvds_dmi_callback, 848 .ident = "Intel D425KT", 849 .matches = { 850 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 851 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 852 }, 853 }, 854 { 855 .callback = intel_no_lvds_dmi_callback, 856 .ident = "Intel D510MO", 857 .matches = { 858 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 859 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 860 }, 861 }, 862 { 863 .callback = intel_no_lvds_dmi_callback, 864 .ident = "Intel D525MW", 865 .matches = { 866 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 867 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 868 }, 869 }, 870 871 { } /* terminating entry */ 872 }; 873 874 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 875 { 876 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 877 return 1; 878 } 879 880 static const struct dmi_system_id intel_dual_link_lvds[] = { 881 { 882 .callback = intel_dual_link_lvds_callback, 883 .ident = "Apple MacBook Pro 15\" (2010)", 884 .matches = { 885 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 886 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 887 }, 888 }, 889 { 890 .callback = intel_dual_link_lvds_callback, 891 .ident = "Apple MacBook Pro 15\" (2011)", 892 .matches = { 893 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 894 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 895 }, 896 }, 897 { 898 .callback = intel_dual_link_lvds_callback, 899 .ident = "Apple MacBook Pro 15\" (2012)", 900 .matches = { 901 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 902 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 903 }, 904 }, 905 { } /* terminating entry */ 906 }; 907 908 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev) 909 { 910 struct intel_encoder *intel_encoder; 911 912 for_each_intel_encoder(dev, intel_encoder) 913 if (intel_encoder->type == INTEL_OUTPUT_LVDS) 914 return intel_encoder; 915 916 return NULL; 917 } 918 919 bool intel_is_dual_link_lvds(struct drm_device *dev) 920 { 921 struct intel_encoder *encoder = intel_get_lvds_encoder(dev); 922 923 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; 924 } 925 926 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 927 { 928 struct drm_device *dev = lvds_encoder->base.base.dev; 929 unsigned int val; 930 struct drm_i915_private *dev_priv = to_i915(dev); 931 932 /* use the module option value if specified */ 933 if (i915.lvds_channel_mode > 0) 934 return i915.lvds_channel_mode == 2; 935 936 /* single channel LVDS is limited to 112 MHz */ 937 if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock 938 > 112999) 939 return true; 940 941 if (dmi_check_system(intel_dual_link_lvds)) 942 return true; 943 944 /* BIOS should set the proper LVDS register value at boot, but 945 * in reality, it doesn't set the value when the lid is closed; 946 * we need to check "the value to be set" in VBT when LVDS 947 * register is uninitialized. 948 */ 949 val = I915_READ(lvds_encoder->reg); 950 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) 951 val = dev_priv->vbt.bios_lvds_val; 952 953 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 954 } 955 956 static bool intel_lvds_supported(struct drm_i915_private *dev_priv) 957 { 958 /* With the introduction of the PCH we gained a dedicated 959 * LVDS presence pin, use it. */ 960 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) 961 return true; 962 963 /* Otherwise LVDS was only attached to mobile products, 964 * except for the inglorious 830gm */ 965 if (INTEL_GEN(dev_priv) <= 4 && 966 IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) 967 return true; 968 969 return false; 970 } 971 972 /** 973 * intel_lvds_init - setup LVDS connectors on this device 974 * @dev: drm device 975 * 976 * Create the connector, register the LVDS DDC bus, and try to figure out what 977 * modes we can display on the LVDS panel (if present). 978 */ 979 void intel_lvds_init(struct drm_device *dev) 980 { 981 struct drm_i915_private *dev_priv = to_i915(dev); 982 struct intel_lvds_encoder *lvds_encoder; 983 struct intel_encoder *intel_encoder; 984 struct intel_lvds_connector *lvds_connector; 985 struct intel_connector *intel_connector; 986 struct drm_connector *connector; 987 struct drm_encoder *encoder; 988 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 989 struct drm_display_mode *fixed_mode = NULL; 990 struct drm_display_mode *downclock_mode = NULL; 991 struct edid *edid; 992 struct intel_crtc *crtc; 993 i915_reg_t lvds_reg; 994 u32 lvds; 995 int pipe; 996 u8 pin; 997 998 if (!intel_lvds_supported(dev_priv)) 999 return; 1000 1001 /* Skip init on machines we know falsely report LVDS */ 1002 if (dmi_check_system(intel_no_lvds)) 1003 return; 1004 1005 if (HAS_PCH_SPLIT(dev_priv)) 1006 lvds_reg = PCH_LVDS; 1007 else 1008 lvds_reg = LVDS; 1009 1010 lvds = I915_READ(lvds_reg); 1011 1012 if (HAS_PCH_SPLIT(dev_priv)) { 1013 if ((lvds & LVDS_DETECTED) == 0) 1014 return; 1015 if (dev_priv->vbt.edp.support) { 1016 DRM_DEBUG_KMS("disable LVDS for eDP support\n"); 1017 return; 1018 } 1019 } 1020 1021 pin = GMBUS_PIN_PANEL; 1022 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 1023 if ((lvds & LVDS_PORT_EN) == 0) { 1024 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); 1025 return; 1026 } 1027 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); 1028 } 1029 1030 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 1031 if (!lvds_encoder) 1032 return; 1033 1034 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); 1035 if (!lvds_connector) { 1036 kfree(lvds_encoder); 1037 return; 1038 } 1039 1040 if (intel_connector_init(&lvds_connector->base) < 0) { 1041 kfree(lvds_connector); 1042 kfree(lvds_encoder); 1043 return; 1044 } 1045 1046 lvds_encoder->attached_connector = lvds_connector; 1047 1048 intel_encoder = &lvds_encoder->base; 1049 encoder = &intel_encoder->base; 1050 intel_connector = &lvds_connector->base; 1051 connector = &intel_connector->base; 1052 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 1053 DRM_MODE_CONNECTOR_LVDS); 1054 1055 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 1056 DRM_MODE_ENCODER_LVDS, "LVDS"); 1057 1058 intel_encoder->enable = intel_enable_lvds; 1059 intel_encoder->pre_enable = intel_pre_enable_lvds; 1060 intel_encoder->compute_config = intel_lvds_compute_config; 1061 if (HAS_PCH_SPLIT(dev_priv)) { 1062 intel_encoder->disable = pch_disable_lvds; 1063 intel_encoder->post_disable = pch_post_disable_lvds; 1064 } else { 1065 intel_encoder->disable = gmch_disable_lvds; 1066 } 1067 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 1068 intel_encoder->get_config = intel_lvds_get_config; 1069 intel_connector->get_hw_state = intel_connector_get_hw_state; 1070 1071 intel_connector_attach_encoder(intel_connector, intel_encoder); 1072 1073 intel_encoder->type = INTEL_OUTPUT_LVDS; 1074 intel_encoder->port = PORT_NONE; 1075 intel_encoder->cloneable = 0; 1076 if (HAS_PCH_SPLIT(dev_priv)) 1077 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1078 else if (IS_GEN4(dev_priv)) 1079 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1080 else 1081 intel_encoder->crtc_mask = (1 << 1); 1082 1083 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 1084 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1085 connector->interlace_allowed = false; 1086 connector->doublescan_allowed = false; 1087 1088 lvds_encoder->reg = lvds_reg; 1089 1090 /* create the scaling mode property */ 1091 drm_mode_create_scaling_mode_property(dev); 1092 drm_object_attach_property(&connector->base, 1093 dev->mode_config.scaling_mode_property, 1094 DRM_MODE_SCALE_ASPECT); 1095 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 1096 1097 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); 1098 lvds_encoder->init_lvds_val = lvds; 1099 1100 /* 1101 * LVDS discovery: 1102 * 1) check for EDID on DDC 1103 * 2) check for VBT data 1104 * 3) check to see if LVDS is already on 1105 * if none of the above, no panel 1106 * 4) make sure lid is open 1107 * if closed, act like it's not there for now 1108 */ 1109 1110 /* 1111 * Attempt to get the fixed panel mode from DDC. Assume that the 1112 * preferred mode is the right one. 1113 */ 1114 mutex_lock(&dev->mode_config.mutex); 1115 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 1116 edid = drm_get_edid_switcheroo(connector, 1117 intel_gmbus_get_adapter(dev_priv, pin)); 1118 else 1119 edid = drm_get_edid(connector, 1120 intel_gmbus_get_adapter(dev_priv, pin)); 1121 if (edid) { 1122 if (drm_add_edid_modes(connector, edid)) { 1123 drm_mode_connector_update_edid_property(connector, 1124 edid); 1125 } else { 1126 kfree(edid); 1127 edid = ERR_PTR(-EINVAL); 1128 } 1129 } else { 1130 edid = ERR_PTR(-ENOENT); 1131 } 1132 lvds_connector->base.edid = edid; 1133 1134 list_for_each_entry(scan, &connector->probed_modes, head) { 1135 if (scan->type & DRM_MODE_TYPE_PREFERRED) { 1136 DRM_DEBUG_KMS("using preferred mode from EDID: "); 1137 drm_mode_debug_printmodeline(scan); 1138 1139 fixed_mode = drm_mode_duplicate(dev, scan); 1140 if (fixed_mode) 1141 goto out; 1142 } 1143 } 1144 1145 /* Failed to get EDID, what about VBT? */ 1146 if (dev_priv->vbt.lfp_lvds_vbt_mode) { 1147 DRM_DEBUG_KMS("using mode from VBT: "); 1148 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); 1149 1150 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); 1151 if (fixed_mode) { 1152 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1153 connector->display_info.width_mm = fixed_mode->width_mm; 1154 connector->display_info.height_mm = fixed_mode->height_mm; 1155 goto out; 1156 } 1157 } 1158 1159 /* 1160 * If we didn't get EDID, try checking if the panel is already turned 1161 * on. If so, assume that whatever is currently programmed is the 1162 * correct mode. 1163 */ 1164 1165 /* Ironlake: FIXME if still fail, not try pipe mode now */ 1166 if (HAS_PCH_SPLIT(dev_priv)) 1167 goto failed; 1168 1169 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; 1170 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1171 1172 if (crtc && (lvds & LVDS_PORT_EN)) { 1173 fixed_mode = intel_crtc_mode_get(dev, &crtc->base); 1174 if (fixed_mode) { 1175 DRM_DEBUG_KMS("using current (BIOS) mode: "); 1176 drm_mode_debug_printmodeline(fixed_mode); 1177 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1178 goto out; 1179 } 1180 } 1181 1182 /* If we still don't have a mode after all that, give up. */ 1183 if (!fixed_mode) 1184 goto failed; 1185 1186 out: 1187 mutex_unlock(&dev->mode_config.mutex); 1188 1189 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 1190 intel_panel_setup_backlight(connector, INVALID_PIPE); 1191 1192 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1193 DRM_DEBUG_KMS("detected %s-link lvds configuration\n", 1194 lvds_encoder->is_dual_link ? "dual" : "single"); 1195 1196 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1197 1198 #if 0 1199 lvds_connector->lid_notifier.notifier_call = intel_lid_notify; 1200 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { 1201 DRM_DEBUG_KMS("lid notifier registration failed\n"); 1202 lvds_connector->lid_notifier.notifier_call = NULL; 1203 } 1204 #endif 1205 1206 return; 1207 1208 failed: 1209 mutex_unlock(&dev->mode_config.mutex); 1210 1211 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1212 drm_connector_cleanup(connector); 1213 drm_encoder_cleanup(encoder); 1214 kfree(lvds_encoder); 1215 kfree(lvds_connector); 1216 return; 1217 } 1218