1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 30 #include <linux/i2c.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 38 /* Private structure for the integrated LVDS support */ 39 struct intel_lvds_connector { 40 struct intel_connector base; 41 42 #if 0 43 struct notifier_block lid_notifier; 44 #endif 45 }; 46 47 struct intel_lvds_encoder { 48 struct intel_encoder base; 49 50 u32 pfit_control; 51 u32 pfit_pgm_ratios; 52 bool is_dual_link; 53 u32 reg; 54 55 struct intel_lvds_connector *attached_connector; 56 }; 57 58 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 59 { 60 return container_of(encoder, struct intel_lvds_encoder, base.base); 61 } 62 63 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) 64 { 65 return container_of(connector, struct intel_lvds_connector, base.base); 66 } 67 68 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 69 enum i915_pipe *pipe) 70 { 71 struct drm_device *dev = encoder->base.dev; 72 struct drm_i915_private *dev_priv = dev->dev_private; 73 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 74 u32 tmp; 75 76 tmp = I915_READ(lvds_encoder->reg); 77 78 if (!(tmp & LVDS_PORT_EN)) 79 return false; 80 81 if (HAS_PCH_CPT(dev)) 82 *pipe = PORT_TO_PIPE_CPT(tmp); 83 else 84 *pipe = PORT_TO_PIPE(tmp); 85 86 return true; 87 } 88 89 /* The LVDS pin pair needs to be on before the DPLLs are enabled. 90 * This is an exception to the general rule that mode_set doesn't turn 91 * things on. 92 */ 93 static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder) 94 { 95 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 96 struct drm_device *dev = encoder->base.dev; 97 struct drm_i915_private *dev_priv = dev->dev_private; 98 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 99 struct drm_display_mode *fixed_mode = 100 lvds_encoder->attached_connector->base.panel.fixed_mode; 101 int pipe = intel_crtc->pipe; 102 u32 temp; 103 104 temp = I915_READ(lvds_encoder->reg); 105 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 106 107 if (HAS_PCH_CPT(dev)) { 108 temp &= ~PORT_TRANS_SEL_MASK; 109 temp |= PORT_TRANS_SEL_CPT(pipe); 110 } else { 111 if (pipe == 1) { 112 temp |= LVDS_PIPEB_SELECT; 113 } else { 114 temp &= ~LVDS_PIPEB_SELECT; 115 } 116 } 117 118 /* set the corresponsding LVDS_BORDER bit */ 119 temp |= dev_priv->lvds_border_bits; 120 /* Set the B0-B3 data pairs corresponding to whether we're going to 121 * set the DPLLs for dual-channel mode or not. 122 */ 123 if (lvds_encoder->is_dual_link) 124 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 125 else 126 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 127 128 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 129 * appropriately here, but we need to look more thoroughly into how 130 * panels behave in the two modes. 131 */ 132 133 /* Set the dithering flag on LVDS as needed, note that there is no 134 * special lvds dither control bit on pch-split platforms, dithering is 135 * only controlled through the PIPECONF reg. */ 136 if (INTEL_INFO(dev)->gen == 4) { 137 if (dev_priv->lvds_dither) 138 temp |= LVDS_ENABLE_DITHER; 139 else 140 temp &= ~LVDS_ENABLE_DITHER; 141 } 142 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 143 if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC) 144 temp |= LVDS_HSYNC_POLARITY; 145 if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC) 146 temp |= LVDS_VSYNC_POLARITY; 147 148 I915_WRITE(lvds_encoder->reg, temp); 149 } 150 151 static void intel_pre_enable_lvds(struct intel_encoder *encoder) 152 { 153 struct drm_device *dev = encoder->base.dev; 154 struct intel_lvds_encoder *enc = to_lvds_encoder(&encoder->base); 155 struct drm_i915_private *dev_priv = dev->dev_private; 156 157 if (HAS_PCH_SPLIT(dev) || !enc->pfit_control) 158 return; 159 160 /* 161 * Enable automatic panel scaling so that non-native modes 162 * fill the screen. The panel fitter should only be 163 * adjusted whilst the pipe is disabled, according to 164 * register description and PRM. 165 */ 166 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", 167 enc->pfit_control, 168 enc->pfit_pgm_ratios); 169 170 I915_WRITE(PFIT_PGM_RATIOS, enc->pfit_pgm_ratios); 171 I915_WRITE(PFIT_CONTROL, enc->pfit_control); 172 } 173 174 /** 175 * Sets the power state for the panel. 176 */ 177 static void intel_enable_lvds(struct intel_encoder *encoder) 178 { 179 struct drm_device *dev = encoder->base.dev; 180 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 181 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 182 struct drm_i915_private *dev_priv = dev->dev_private; 183 u32 ctl_reg, stat_reg; 184 185 if (HAS_PCH_SPLIT(dev)) { 186 ctl_reg = PCH_PP_CONTROL; 187 stat_reg = PCH_PP_STATUS; 188 } else { 189 ctl_reg = PP_CONTROL; 190 stat_reg = PP_STATUS; 191 } 192 193 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); 194 195 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); 196 POSTING_READ(lvds_encoder->reg); 197 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) 198 DRM_ERROR("timed out waiting for panel to power on\n"); 199 200 intel_panel_enable_backlight(dev, intel_crtc->pipe); 201 } 202 203 static void intel_disable_lvds(struct intel_encoder *encoder) 204 { 205 struct drm_device *dev = encoder->base.dev; 206 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 207 struct drm_i915_private *dev_priv = dev->dev_private; 208 u32 ctl_reg, stat_reg; 209 210 if (HAS_PCH_SPLIT(dev)) { 211 ctl_reg = PCH_PP_CONTROL; 212 stat_reg = PCH_PP_STATUS; 213 } else { 214 ctl_reg = PP_CONTROL; 215 stat_reg = PP_STATUS; 216 } 217 218 intel_panel_disable_backlight(dev); 219 220 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); 221 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) 222 DRM_ERROR("timed out waiting for panel to power off\n"); 223 224 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); 225 POSTING_READ(lvds_encoder->reg); 226 } 227 228 static int intel_lvds_mode_valid(struct drm_connector *connector, 229 struct drm_display_mode *mode) 230 { 231 struct intel_connector *intel_connector = to_intel_connector(connector); 232 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 233 234 if (mode->hdisplay > fixed_mode->hdisplay) 235 return MODE_PANEL; 236 if (mode->vdisplay > fixed_mode->vdisplay) 237 return MODE_PANEL; 238 239 return MODE_OK; 240 } 241 242 static void 243 centre_horizontally(struct drm_display_mode *mode, 244 int width) 245 { 246 u32 border, sync_pos, blank_width, sync_width; 247 248 /* keep the hsync and hblank widths constant */ 249 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; 250 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; 251 sync_pos = (blank_width - sync_width + 1) / 2; 252 253 border = (mode->hdisplay - width + 1) / 2; 254 border += border & 1; /* make the border even */ 255 256 mode->crtc_hdisplay = width; 257 mode->crtc_hblank_start = width + border; 258 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; 259 260 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; 261 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; 262 } 263 264 static void 265 centre_vertically(struct drm_display_mode *mode, 266 int height) 267 { 268 u32 border, sync_pos, blank_width, sync_width; 269 270 /* keep the vsync and vblank widths constant */ 271 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; 272 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; 273 sync_pos = (blank_width - sync_width + 1) / 2; 274 275 border = (mode->vdisplay - height + 1) / 2; 276 277 mode->crtc_vdisplay = height; 278 mode->crtc_vblank_start = height + border; 279 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; 280 281 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; 282 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; 283 } 284 285 static inline u32 panel_fitter_scaling(u32 source, u32 target) 286 { 287 /* 288 * Floating point operation is not supported. So the FACTOR 289 * is defined, which can avoid the floating point computation 290 * when calculating the panel ratio. 291 */ 292 #define ACCURACY 12 293 #define FACTOR (1 << ACCURACY) 294 u32 ratio = source * FACTOR / target; 295 return (FACTOR * ratio + FACTOR/2) / FACTOR; 296 } 297 298 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, 299 struct intel_crtc_config *pipe_config) 300 { 301 struct drm_device *dev = intel_encoder->base.dev; 302 struct drm_i915_private *dev_priv = dev->dev_private; 303 struct intel_lvds_encoder *lvds_encoder = 304 to_lvds_encoder(&intel_encoder->base); 305 struct intel_connector *intel_connector = 306 &lvds_encoder->attached_connector->base; 307 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 308 struct drm_display_mode *mode = &pipe_config->requested_mode; 309 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; 310 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; 311 unsigned int lvds_bpp; 312 int pipe; 313 314 /* Should never happen!! */ 315 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { 316 DRM_ERROR("Can't support LVDS on pipe A\n"); 317 return false; 318 } 319 320 if (intel_encoder_check_is_cloned(&lvds_encoder->base)) 321 return false; 322 323 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) == 324 LVDS_A3_POWER_UP) 325 lvds_bpp = 8*3; 326 else 327 lvds_bpp = 6*3; 328 329 if (lvds_bpp != pipe_config->pipe_bpp) { 330 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", 331 pipe_config->pipe_bpp, lvds_bpp); 332 pipe_config->pipe_bpp = lvds_bpp; 333 } 334 /* 335 * We have timings from the BIOS for the panel, put them in 336 * to the adjusted mode. The CRTC will be set up for this mode, 337 * with the panel scaling set up to source from the H/VDisplay 338 * of the original mode. 339 */ 340 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 341 adjusted_mode); 342 343 if (HAS_PCH_SPLIT(dev)) { 344 pipe_config->has_pch_encoder = true; 345 346 intel_pch_panel_fitting(dev, 347 intel_connector->panel.fitting_mode, 348 mode, adjusted_mode); 349 return true; 350 } 351 352 /* Native modes don't need fitting */ 353 if (adjusted_mode->hdisplay == mode->hdisplay && 354 adjusted_mode->vdisplay == mode->vdisplay) 355 goto out; 356 357 /* 965+ wants fuzzy fitting */ 358 if (INTEL_INFO(dev)->gen >= 4) 359 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | 360 PFIT_FILTER_FUZZY); 361 362 /* 363 * Enable automatic panel scaling for non-native modes so that they fill 364 * the screen. Should be enabled before the pipe is enabled, according 365 * to register description and PRM. 366 * Change the value here to see the borders for debugging 367 */ 368 for_each_pipe(pipe) 369 I915_WRITE(BCLRPAT(pipe), 0); 370 371 drm_mode_set_crtcinfo(adjusted_mode, 0); 372 pipe_config->timings_set = true; 373 374 switch (intel_connector->panel.fitting_mode) { 375 case DRM_MODE_SCALE_CENTER: 376 /* 377 * For centered modes, we have to calculate border widths & 378 * heights and modify the values programmed into the CRTC. 379 */ 380 centre_horizontally(adjusted_mode, mode->hdisplay); 381 centre_vertically(adjusted_mode, mode->vdisplay); 382 border = LVDS_BORDER_ENABLE; 383 break; 384 385 case DRM_MODE_SCALE_ASPECT: 386 /* Scale but preserve the aspect ratio */ 387 if (INTEL_INFO(dev)->gen >= 4) { 388 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; 389 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; 390 391 /* 965+ is easy, it does everything in hw */ 392 if (scaled_width > scaled_height) 393 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; 394 else if (scaled_width < scaled_height) 395 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; 396 else if (adjusted_mode->hdisplay != mode->hdisplay) 397 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; 398 } else { 399 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; 400 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; 401 /* 402 * For earlier chips we have to calculate the scaling 403 * ratio by hand and program it into the 404 * PFIT_PGM_RATIO register 405 */ 406 if (scaled_width > scaled_height) { /* pillar */ 407 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); 408 409 border = LVDS_BORDER_ENABLE; 410 if (mode->vdisplay != adjusted_mode->vdisplay) { 411 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); 412 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | 413 bits << PFIT_VERT_SCALE_SHIFT); 414 pfit_control |= (PFIT_ENABLE | 415 VERT_INTERP_BILINEAR | 416 HORIZ_INTERP_BILINEAR); 417 } 418 } else if (scaled_width < scaled_height) { /* letter */ 419 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); 420 421 border = LVDS_BORDER_ENABLE; 422 if (mode->hdisplay != adjusted_mode->hdisplay) { 423 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); 424 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | 425 bits << PFIT_VERT_SCALE_SHIFT); 426 pfit_control |= (PFIT_ENABLE | 427 VERT_INTERP_BILINEAR | 428 HORIZ_INTERP_BILINEAR); 429 } 430 } else 431 /* Aspects match, Let hw scale both directions */ 432 pfit_control |= (PFIT_ENABLE | 433 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | 434 VERT_INTERP_BILINEAR | 435 HORIZ_INTERP_BILINEAR); 436 } 437 break; 438 439 case DRM_MODE_SCALE_FULLSCREEN: 440 /* 441 * Full scaling, even if it changes the aspect ratio. 442 * Fortunately this is all done for us in hw. 443 */ 444 if (mode->vdisplay != adjusted_mode->vdisplay || 445 mode->hdisplay != adjusted_mode->hdisplay) { 446 pfit_control |= PFIT_ENABLE; 447 if (INTEL_INFO(dev)->gen >= 4) 448 pfit_control |= PFIT_SCALING_AUTO; 449 else 450 pfit_control |= (VERT_AUTO_SCALE | 451 VERT_INTERP_BILINEAR | 452 HORIZ_AUTO_SCALE | 453 HORIZ_INTERP_BILINEAR); 454 } 455 break; 456 457 default: 458 break; 459 } 460 461 out: 462 /* If not enabling scaling, be consistent and always use 0. */ 463 if ((pfit_control & PFIT_ENABLE) == 0) { 464 pfit_control = 0; 465 pfit_pgm_ratios = 0; 466 } 467 468 /* Make sure pre-965 set dither correctly */ 469 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) 470 pfit_control |= PANEL_8TO6_DITHER_ENABLE; 471 472 if (pfit_control != lvds_encoder->pfit_control || 473 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) { 474 lvds_encoder->pfit_control = pfit_control; 475 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios; 476 } 477 dev_priv->lvds_border_bits = border; 478 479 /* 480 * XXX: It would be nice to support lower refresh rates on the 481 * panels to reduce power consumption, and perhaps match the 482 * user's requested refresh rate. 483 */ 484 485 return true; 486 } 487 488 static void intel_lvds_mode_set(struct drm_encoder *encoder, 489 struct drm_display_mode *mode, 490 struct drm_display_mode *adjusted_mode) 491 { 492 /* 493 * The LVDS pin pair will already have been turned on in the 494 * intel_crtc_mode_set since it has a large impact on the DPLL 495 * settings. 496 */ 497 } 498 499 /** 500 * Detect the LVDS connection. 501 * 502 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means 503 * connected and closed means disconnected. We also send hotplug events as 504 * needed, using lid status notification from the input layer. 505 */ 506 static enum drm_connector_status 507 intel_lvds_detect(struct drm_connector *connector, bool force) 508 { 509 struct drm_device *dev = connector->dev; 510 enum drm_connector_status status; 511 512 status = intel_panel_detect(dev); 513 if (status != connector_status_unknown) 514 return status; 515 516 return connector_status_connected; 517 } 518 519 /** 520 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 521 */ 522 static int intel_lvds_get_modes(struct drm_connector *connector) 523 { 524 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); 525 struct drm_device *dev = connector->dev; 526 struct drm_display_mode *mode; 527 528 /* use cached edid if we have one */ 529 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 530 return drm_add_edid_modes(connector, lvds_connector->base.edid); 531 532 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); 533 if (mode == NULL) 534 return 0; 535 536 drm_mode_probed_add(connector, mode); 537 return 1; 538 } 539 540 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) 541 { 542 DRM_INFO("Skipping forced modeset for %s\n", id->ident); 543 return 1; 544 } 545 546 /* The GPU hangs up on these systems if modeset is performed on LID open */ 547 static const struct dmi_system_id intel_no_modeset_on_lid[] = { 548 { 549 .callback = intel_no_modeset_on_lid_dmi_callback, 550 .ident = "Toshiba Tecra A11", 551 .matches = { 552 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 553 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), 554 }, 555 }, 556 557 { } /* terminating entry */ 558 }; 559 560 #if 0 561 /* 562 * Lid events. Note the use of 'modeset': 563 * - we set it to MODESET_ON_LID_OPEN on lid close, 564 * and set it to MODESET_DONE on open 565 * - we use it as a "only once" bit (ie we ignore 566 * duplicate events where it was already properly set) 567 * - the suspend/resume paths will set it to 568 * MODESET_SUSPENDED and ignore the lid open event, 569 * because they restore the mode ("lid open"). 570 */ 571 static int intel_lid_notify(struct notifier_block *nb, unsigned long val, 572 void *unused) 573 { 574 struct intel_lvds_connector *lvds_connector = 575 container_of(nb, struct intel_lvds_connector, lid_notifier); 576 struct drm_connector *connector = &lvds_connector->base.base; 577 struct drm_device *dev = connector->dev; 578 struct drm_i915_private *dev_priv = dev->dev_private; 579 580 if (dev->switch_power_state != DRM_SWITCH_POWER_ON) 581 return NOTIFY_OK; 582 583 mutex_lock(&dev_priv->modeset_restore_lock); 584 if (dev_priv->modeset_restore == MODESET_SUSPENDED) 585 goto exit; 586 /* 587 * check and update the status of LVDS connector after receiving 588 * the LID nofication event. 589 */ 590 connector->status = connector->funcs->detect(connector, false); 591 592 /* Don't force modeset on machines where it causes a GPU lockup */ 593 if (dmi_check_system(intel_no_modeset_on_lid)) 594 goto exit; 595 if (!acpi_lid_open()) { 596 /* do modeset on next lid open event */ 597 dev_priv->modeset_restore = MODESET_ON_LID_OPEN; 598 goto exit; 599 } 600 601 if (dev_priv->modeset_restore == MODESET_DONE) 602 goto exit; 603 604 drm_modeset_lock_all(dev); 605 intel_modeset_setup_hw_state(dev, true); 606 drm_modeset_unlock_all(dev); 607 608 dev_priv->modeset_restore = MODESET_DONE; 609 610 exit: 611 mutex_unlock(&dev_priv->modeset_restore_lock); 612 return NOTIFY_OK; 613 } 614 #endif 615 616 /** 617 * intel_lvds_destroy - unregister and free LVDS structures 618 * @connector: connector to free 619 * 620 * Unregister the DDC bus for this connector then free the driver private 621 * structure. 622 */ 623 static void intel_lvds_destroy(struct drm_connector *connector) 624 { 625 struct intel_lvds_connector *lvds_connector = 626 to_lvds_connector(connector); 627 628 #if 0 629 if (lvds_connector->lid_notifier.notifier_call) 630 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); 631 #endif 632 633 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 634 kfree(lvds_connector->base.edid); 635 636 intel_panel_fini(&lvds_connector->base.panel); 637 638 #if 0 639 drm_sysfs_connector_remove(connector); 640 #endif 641 drm_connector_cleanup(connector); 642 kfree(connector); 643 } 644 645 static int intel_lvds_set_property(struct drm_connector *connector, 646 struct drm_property *property, 647 uint64_t value) 648 { 649 struct intel_connector *intel_connector = to_intel_connector(connector); 650 struct drm_device *dev = connector->dev; 651 652 if (property == dev->mode_config.scaling_mode_property) { 653 struct drm_crtc *crtc; 654 655 if (value == DRM_MODE_SCALE_NONE) { 656 DRM_DEBUG_KMS("no scaling not supported\n"); 657 return -EINVAL; 658 } 659 660 if (intel_connector->panel.fitting_mode == value) { 661 /* the LVDS scaling property is not changed */ 662 return 0; 663 } 664 intel_connector->panel.fitting_mode = value; 665 666 crtc = intel_attached_encoder(connector)->base.crtc; 667 if (crtc && crtc->enabled) { 668 /* 669 * If the CRTC is enabled, the display will be changed 670 * according to the new panel fitting mode. 671 */ 672 intel_crtc_restore_mode(crtc); 673 } 674 } 675 676 return 0; 677 } 678 679 static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { 680 .mode_set = intel_lvds_mode_set, 681 }; 682 683 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 684 .get_modes = intel_lvds_get_modes, 685 .mode_valid = intel_lvds_mode_valid, 686 .best_encoder = intel_best_encoder, 687 }; 688 689 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 690 .dpms = intel_connector_dpms, 691 .detect = intel_lvds_detect, 692 .fill_modes = drm_helper_probe_single_connector_modes, 693 .set_property = intel_lvds_set_property, 694 .destroy = intel_lvds_destroy, 695 }; 696 697 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 698 .destroy = intel_encoder_destroy, 699 }; 700 701 static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 702 { 703 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 704 return 1; 705 } 706 707 /* These systems claim to have LVDS, but really don't */ 708 static const struct dmi_system_id intel_no_lvds[] = { 709 { 710 .callback = intel_no_lvds_dmi_callback, 711 .ident = "Apple Mac Mini (Core series)", 712 .matches = { 713 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 714 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 715 }, 716 }, 717 { 718 .callback = intel_no_lvds_dmi_callback, 719 .ident = "Apple Mac Mini (Core 2 series)", 720 .matches = { 721 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 722 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 723 }, 724 }, 725 { 726 .callback = intel_no_lvds_dmi_callback, 727 .ident = "MSI IM-945GSE-A", 728 .matches = { 729 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 730 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 731 }, 732 }, 733 { 734 .callback = intel_no_lvds_dmi_callback, 735 .ident = "Dell Studio Hybrid", 736 .matches = { 737 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 738 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 739 }, 740 }, 741 { 742 .callback = intel_no_lvds_dmi_callback, 743 .ident = "Dell OptiPlex FX170", 744 .matches = { 745 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 746 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 747 }, 748 }, 749 { 750 .callback = intel_no_lvds_dmi_callback, 751 .ident = "AOpen Mini PC", 752 .matches = { 753 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 754 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 755 }, 756 }, 757 { 758 .callback = intel_no_lvds_dmi_callback, 759 .ident = "AOpen Mini PC MP915", 760 .matches = { 761 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 762 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 763 }, 764 }, 765 { 766 .callback = intel_no_lvds_dmi_callback, 767 .ident = "AOpen i915GMm-HFS", 768 .matches = { 769 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 770 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 771 }, 772 }, 773 { 774 .callback = intel_no_lvds_dmi_callback, 775 .ident = "AOpen i45GMx-I", 776 .matches = { 777 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 778 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 779 }, 780 }, 781 { 782 .callback = intel_no_lvds_dmi_callback, 783 .ident = "Aopen i945GTt-VFA", 784 .matches = { 785 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 786 }, 787 }, 788 { 789 .callback = intel_no_lvds_dmi_callback, 790 .ident = "Clientron U800", 791 .matches = { 792 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 793 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 794 }, 795 }, 796 { 797 .callback = intel_no_lvds_dmi_callback, 798 .ident = "Clientron E830", 799 .matches = { 800 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 801 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 802 }, 803 }, 804 { 805 .callback = intel_no_lvds_dmi_callback, 806 .ident = "Asus EeeBox PC EB1007", 807 .matches = { 808 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 809 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 810 }, 811 }, 812 { 813 .callback = intel_no_lvds_dmi_callback, 814 .ident = "Asus AT5NM10T-I", 815 .matches = { 816 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 817 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 818 }, 819 }, 820 { 821 .callback = intel_no_lvds_dmi_callback, 822 .ident = "Hewlett-Packard HP t5740", 823 .matches = { 824 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 825 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 826 }, 827 }, 828 { 829 .callback = intel_no_lvds_dmi_callback, 830 .ident = "Hewlett-Packard t5745", 831 .matches = { 832 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 833 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 834 }, 835 }, 836 { 837 .callback = intel_no_lvds_dmi_callback, 838 .ident = "Hewlett-Packard st5747", 839 .matches = { 840 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 841 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 842 }, 843 }, 844 { 845 .callback = intel_no_lvds_dmi_callback, 846 .ident = "MSI Wind Box DC500", 847 .matches = { 848 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 849 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 850 }, 851 }, 852 { 853 .callback = intel_no_lvds_dmi_callback, 854 .ident = "Gigabyte GA-D525TUD", 855 .matches = { 856 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 857 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 858 }, 859 }, 860 { 861 .callback = intel_no_lvds_dmi_callback, 862 .ident = "Supermicro X7SPA-H", 863 .matches = { 864 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 865 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 866 }, 867 }, 868 { 869 .callback = intel_no_lvds_dmi_callback, 870 .ident = "Fujitsu Esprimo Q900", 871 .matches = { 872 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 873 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 874 }, 875 }, 876 877 { } /* terminating entry */ 878 }; 879 880 /** 881 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID 882 * @dev: drm device 883 * @connector: LVDS connector 884 * 885 * Find the reduced downclock for LVDS in EDID. 886 */ 887 static void intel_find_lvds_downclock(struct drm_device *dev, 888 struct drm_display_mode *fixed_mode, 889 struct drm_connector *connector) 890 { 891 struct drm_i915_private *dev_priv = dev->dev_private; 892 struct drm_display_mode *scan; 893 int temp_downclock; 894 895 temp_downclock = fixed_mode->clock; 896 list_for_each_entry(scan, &connector->probed_modes, head) { 897 /* 898 * If one mode has the same resolution with the fixed_panel 899 * mode while they have the different refresh rate, it means 900 * that the reduced downclock is found for the LVDS. In such 901 * case we can set the different FPx0/1 to dynamically select 902 * between low and high frequency. 903 */ 904 if (scan->hdisplay == fixed_mode->hdisplay && 905 scan->hsync_start == fixed_mode->hsync_start && 906 scan->hsync_end == fixed_mode->hsync_end && 907 scan->htotal == fixed_mode->htotal && 908 scan->vdisplay == fixed_mode->vdisplay && 909 scan->vsync_start == fixed_mode->vsync_start && 910 scan->vsync_end == fixed_mode->vsync_end && 911 scan->vtotal == fixed_mode->vtotal) { 912 if (scan->clock < temp_downclock) { 913 /* 914 * The downclock is already found. But we 915 * expect to find the lower downclock. 916 */ 917 temp_downclock = scan->clock; 918 } 919 } 920 } 921 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { 922 /* We found the downclock for LVDS. */ 923 dev_priv->lvds_downclock_avail = 1; 924 dev_priv->lvds_downclock = temp_downclock; 925 DRM_DEBUG_KMS("LVDS downclock is found in EDID. " 926 "Normal clock %dKhz, downclock %dKhz\n", 927 fixed_mode->clock, temp_downclock); 928 } 929 } 930 931 /* 932 * Enumerate the child dev array parsed from VBT to check whether 933 * the LVDS is present. 934 * If it is present, return 1. 935 * If it is not present, return false. 936 * If no child dev is parsed from VBT, it assumes that the LVDS is present. 937 */ 938 static bool lvds_is_present_in_vbt(struct drm_device *dev, 939 u8 *i2c_pin) 940 { 941 struct drm_i915_private *dev_priv = dev->dev_private; 942 int i; 943 944 if (!dev_priv->child_dev_num) 945 return true; 946 947 for (i = 0; i < dev_priv->child_dev_num; i++) { 948 struct child_device_config *child = dev_priv->child_dev + i; 949 950 /* If the device type is not LFP, continue. 951 * We have to check both the new identifiers as well as the 952 * old for compatibility with some BIOSes. 953 */ 954 if (child->device_type != DEVICE_TYPE_INT_LFP && 955 child->device_type != DEVICE_TYPE_LFP) 956 continue; 957 958 if (intel_gmbus_is_port_valid(child->i2c_pin)) 959 *i2c_pin = child->i2c_pin; 960 961 /* However, we cannot trust the BIOS writers to populate 962 * the VBT correctly. Since LVDS requires additional 963 * information from AIM blocks, a non-zero addin offset is 964 * a good indicator that the LVDS is actually present. 965 */ 966 if (child->addin_offset) 967 return true; 968 969 /* But even then some BIOS writers perform some black magic 970 * and instantiate the device without reference to any 971 * additional data. Trust that if the VBT was written into 972 * the OpRegion then they have validated the LVDS's existence. 973 */ 974 if (dev_priv->opregion.vbt) 975 return true; 976 } 977 978 return false; 979 } 980 981 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 982 { 983 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 984 return 1; 985 } 986 987 static const struct dmi_system_id intel_dual_link_lvds[] = { 988 { 989 .callback = intel_dual_link_lvds_callback, 990 .ident = "Apple MacBook Pro (Core i5/i7 Series)", 991 .matches = { 992 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 993 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 994 }, 995 }, 996 { } /* terminating entry */ 997 }; 998 999 bool intel_is_dual_link_lvds(struct drm_device *dev) 1000 { 1001 struct intel_encoder *encoder; 1002 struct intel_lvds_encoder *lvds_encoder; 1003 1004 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 1005 base.head) { 1006 if (encoder->type == INTEL_OUTPUT_LVDS) { 1007 lvds_encoder = to_lvds_encoder(&encoder->base); 1008 1009 return lvds_encoder->is_dual_link; 1010 } 1011 } 1012 1013 return false; 1014 } 1015 1016 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 1017 { 1018 struct drm_device *dev = lvds_encoder->base.base.dev; 1019 unsigned int val; 1020 struct drm_i915_private *dev_priv = dev->dev_private; 1021 1022 /* use the module option value if specified */ 1023 if (i915_lvds_channel_mode > 0) 1024 return i915_lvds_channel_mode == 2; 1025 1026 if (dmi_check_system(intel_dual_link_lvds)) 1027 return true; 1028 1029 /* BIOS should set the proper LVDS register value at boot, but 1030 * in reality, it doesn't set the value when the lid is closed; 1031 * we need to check "the value to be set" in VBT when LVDS 1032 * register is uninitialized. 1033 */ 1034 val = I915_READ(lvds_encoder->reg); 1035 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) 1036 val = dev_priv->bios_lvds_val; 1037 1038 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 1039 } 1040 1041 static bool intel_lvds_supported(struct drm_device *dev) 1042 { 1043 /* With the introduction of the PCH we gained a dedicated 1044 * LVDS presence pin, use it. */ 1045 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 1046 return true; 1047 1048 /* Otherwise LVDS was only attached to mobile products, 1049 * except for the inglorious 830gm */ 1050 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) 1051 return true; 1052 1053 return false; 1054 } 1055 1056 /** 1057 * intel_lvds_init - setup LVDS connectors on this device 1058 * @dev: drm device 1059 * 1060 * Create the connector, register the LVDS DDC bus, and try to figure out what 1061 * modes we can display on the LVDS panel (if present). 1062 */ 1063 bool intel_lvds_init(struct drm_device *dev) 1064 { 1065 struct drm_i915_private *dev_priv = dev->dev_private; 1066 struct intel_lvds_encoder *lvds_encoder; 1067 struct intel_encoder *intel_encoder; 1068 struct intel_lvds_connector *lvds_connector; 1069 struct intel_connector *intel_connector; 1070 struct drm_connector *connector; 1071 struct drm_encoder *encoder; 1072 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 1073 struct drm_display_mode *fixed_mode = NULL; 1074 struct edid *edid; 1075 struct drm_crtc *crtc; 1076 u32 lvds; 1077 int pipe; 1078 u8 pin; 1079 1080 if (!intel_lvds_supported(dev)) 1081 return false; 1082 1083 /* Skip init on machines we know falsely report LVDS */ 1084 if (dmi_check_system(intel_no_lvds)) 1085 return false; 1086 1087 pin = GMBUS_PORT_PANEL; 1088 if (!lvds_is_present_in_vbt(dev, &pin)) { 1089 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); 1090 return false; 1091 } 1092 1093 if (HAS_PCH_SPLIT(dev)) { 1094 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) 1095 return false; 1096 if (dev_priv->edp.support) { 1097 DRM_DEBUG_KMS("disable LVDS for eDP support\n"); 1098 return false; 1099 } 1100 } 1101 1102 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL); 1103 if (!lvds_encoder) 1104 return false; 1105 1106 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL); 1107 if (!lvds_connector) { 1108 kfree(lvds_encoder); 1109 return false; 1110 } 1111 1112 lvds_encoder->attached_connector = lvds_connector; 1113 1114 if (!HAS_PCH_SPLIT(dev)) { 1115 lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL); 1116 } 1117 1118 intel_encoder = &lvds_encoder->base; 1119 encoder = &intel_encoder->base; 1120 intel_connector = &lvds_connector->base; 1121 connector = &intel_connector->base; 1122 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 1123 DRM_MODE_CONNECTOR_LVDS); 1124 1125 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 1126 DRM_MODE_ENCODER_LVDS); 1127 1128 intel_encoder->enable = intel_enable_lvds; 1129 intel_encoder->pre_enable = intel_pre_enable_lvds; 1130 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds; 1131 intel_encoder->compute_config = intel_lvds_compute_config; 1132 intel_encoder->disable = intel_disable_lvds; 1133 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 1134 intel_connector->get_hw_state = intel_connector_get_hw_state; 1135 1136 intel_connector_attach_encoder(intel_connector, intel_encoder); 1137 intel_encoder->type = INTEL_OUTPUT_LVDS; 1138 1139 intel_encoder->cloneable = false; 1140 if (HAS_PCH_SPLIT(dev)) 1141 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1142 else if (IS_GEN4(dev)) 1143 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1144 else 1145 intel_encoder->crtc_mask = (1 << 1); 1146 1147 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); 1148 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 1149 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1150 connector->interlace_allowed = false; 1151 connector->doublescan_allowed = false; 1152 1153 if (HAS_PCH_SPLIT(dev)) { 1154 lvds_encoder->reg = PCH_LVDS; 1155 } else { 1156 lvds_encoder->reg = LVDS; 1157 } 1158 1159 /* create the scaling mode property */ 1160 drm_mode_create_scaling_mode_property(dev); 1161 drm_object_attach_property(&connector->base, 1162 dev->mode_config.scaling_mode_property, 1163 DRM_MODE_SCALE_ASPECT); 1164 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 1165 /* 1166 * LVDS discovery: 1167 * 1) check for EDID on DDC 1168 * 2) check for VBT data 1169 * 3) check to see if LVDS is already on 1170 * if none of the above, no panel 1171 * 4) make sure lid is open 1172 * if closed, act like it's not there for now 1173 */ 1174 1175 /* 1176 * Attempt to get the fixed panel mode from DDC. Assume that the 1177 * preferred mode is the right one. 1178 */ 1179 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); 1180 if (edid) { 1181 if (drm_add_edid_modes(connector, edid)) { 1182 drm_mode_connector_update_edid_property(connector, 1183 edid); 1184 } else { 1185 kfree(edid); 1186 edid = ERR_PTR(-EINVAL); 1187 } 1188 } else { 1189 edid = ERR_PTR(-ENOENT); 1190 } 1191 lvds_connector->base.edid = edid; 1192 1193 if (IS_ERR_OR_NULL(edid)) { 1194 /* Didn't get an EDID, so 1195 * Set wide sync ranges so we get all modes 1196 * handed to valid_mode for checking 1197 */ 1198 connector->display_info.min_vfreq = 0; 1199 connector->display_info.max_vfreq = 200; 1200 connector->display_info.min_hfreq = 0; 1201 connector->display_info.max_hfreq = 200; 1202 } 1203 1204 list_for_each_entry(scan, &connector->probed_modes, head) { 1205 if (scan->type & DRM_MODE_TYPE_PREFERRED) { 1206 DRM_DEBUG_KMS("using preferred mode from EDID: "); 1207 drm_mode_debug_printmodeline(scan); 1208 1209 fixed_mode = drm_mode_duplicate(dev, scan); 1210 if (fixed_mode) { 1211 intel_find_lvds_downclock(dev, fixed_mode, 1212 connector); 1213 goto out; 1214 } 1215 } 1216 } 1217 1218 /* Failed to get EDID, what about VBT? */ 1219 if (dev_priv->lfp_lvds_vbt_mode) { 1220 DRM_DEBUG_KMS("using mode from VBT: "); 1221 drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode); 1222 1223 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 1224 if (fixed_mode) { 1225 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1226 goto out; 1227 } 1228 } 1229 1230 /* 1231 * If we didn't get EDID, try checking if the panel is already turned 1232 * on. If so, assume that whatever is currently programmed is the 1233 * correct mode. 1234 */ 1235 1236 /* Ironlake: FIXME if still fail, not try pipe mode now */ 1237 if (HAS_PCH_SPLIT(dev)) 1238 goto failed; 1239 1240 lvds = I915_READ(LVDS); 1241 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; 1242 crtc = intel_get_crtc_for_pipe(dev, pipe); 1243 1244 if (crtc && (lvds & LVDS_PORT_EN)) { 1245 fixed_mode = intel_crtc_mode_get(dev, crtc); 1246 if (fixed_mode) { 1247 DRM_DEBUG_KMS("using current (BIOS) mode: "); 1248 drm_mode_debug_printmodeline(fixed_mode); 1249 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1250 goto out; 1251 } 1252 } 1253 1254 /* If we still don't have a mode after all that, give up. */ 1255 if (!fixed_mode) 1256 goto failed; 1257 1258 out: 1259 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1260 DRM_DEBUG_KMS("detected %s-link lvds configuration\n", 1261 lvds_encoder->is_dual_link ? "dual" : "single"); 1262 1263 /* 1264 * Unlock registers and just 1265 * leave them unlocked 1266 */ 1267 if (HAS_PCH_SPLIT(dev)) { 1268 I915_WRITE(PCH_PP_CONTROL, 1269 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); 1270 } else { 1271 I915_WRITE(PP_CONTROL, 1272 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); 1273 } 1274 #if 0 1275 lvds_connector->lid_notifier.notifier_call = intel_lid_notify; 1276 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { 1277 DRM_DEBUG_KMS("lid notifier registration failed\n"); 1278 lvds_connector->lid_notifier.notifier_call = NULL; 1279 } 1280 drm_sysfs_connector_add(connector); 1281 #endif 1282 1283 intel_panel_init(&intel_connector->panel, fixed_mode); 1284 intel_panel_setup_backlight(connector); 1285 1286 return true; 1287 1288 failed: 1289 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1290 drm_connector_cleanup(connector); 1291 drm_encoder_cleanup(encoder); 1292 if (fixed_mode) 1293 drm_mode_destroy(dev, fixed_mode); 1294 kfree(lvds_encoder); 1295 kfree(lvds_connector); 1296 return false; 1297 } 1298