1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 #include "opt_drm.h" 30 31 #include <linux/dmi.h> 32 #include <linux/i2c.h> 33 #include <linux/vga_switcheroo.h> 34 #include <drm/drmP.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 #include "intel_drv.h" 39 #include <drm/i915_drm.h> 40 #include "i915_drv.h" 41 42 /* Private structure for the integrated LVDS support */ 43 struct intel_lvds_connector { 44 struct intel_connector base; 45 46 struct notifier_block lid_notifier; 47 }; 48 49 struct intel_lvds_encoder { 50 struct intel_encoder base; 51 52 bool is_dual_link; 53 i915_reg_t reg; 54 u32 a3_power; 55 56 struct intel_lvds_connector *attached_connector; 57 }; 58 59 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 60 { 61 return container_of(encoder, struct intel_lvds_encoder, base.base); 62 } 63 64 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) 65 { 66 return container_of(connector, struct intel_lvds_connector, base.base); 67 } 68 69 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 70 enum i915_pipe *pipe) 71 { 72 struct drm_device *dev = encoder->base.dev; 73 struct drm_i915_private *dev_priv = dev->dev_private; 74 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 75 enum intel_display_power_domain power_domain; 76 u32 tmp; 77 bool ret; 78 79 power_domain = intel_display_port_power_domain(encoder); 80 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 81 return false; 82 83 ret = false; 84 85 tmp = I915_READ(lvds_encoder->reg); 86 87 if (!(tmp & LVDS_PORT_EN)) 88 goto out; 89 90 if (HAS_PCH_CPT(dev)) 91 *pipe = PORT_TO_PIPE_CPT(tmp); 92 else 93 *pipe = PORT_TO_PIPE(tmp); 94 95 ret = true; 96 97 out: 98 intel_display_power_put(dev_priv, power_domain); 99 100 return ret; 101 } 102 103 static void intel_lvds_get_config(struct intel_encoder *encoder, 104 struct intel_crtc_state *pipe_config) 105 { 106 struct drm_device *dev = encoder->base.dev; 107 struct drm_i915_private *dev_priv = dev->dev_private; 108 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 109 u32 tmp, flags = 0; 110 111 tmp = I915_READ(lvds_encoder->reg); 112 if (tmp & LVDS_HSYNC_POLARITY) 113 flags |= DRM_MODE_FLAG_NHSYNC; 114 else 115 flags |= DRM_MODE_FLAG_PHSYNC; 116 if (tmp & LVDS_VSYNC_POLARITY) 117 flags |= DRM_MODE_FLAG_NVSYNC; 118 else 119 flags |= DRM_MODE_FLAG_PVSYNC; 120 121 pipe_config->base.adjusted_mode.flags |= flags; 122 123 if (INTEL_INFO(dev)->gen < 5) 124 pipe_config->gmch_pfit.lvds_border_bits = 125 tmp & LVDS_BORDER_ENABLE; 126 127 /* gen2/3 store dither state in pfit control, needs to match */ 128 if (INTEL_INFO(dev)->gen < 4) { 129 tmp = I915_READ(PFIT_CONTROL); 130 131 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 132 } 133 134 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 135 } 136 137 static void intel_pre_enable_lvds(struct intel_encoder *encoder) 138 { 139 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 140 struct drm_device *dev = encoder->base.dev; 141 struct drm_i915_private *dev_priv = dev->dev_private; 142 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 143 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 144 int pipe = crtc->pipe; 145 u32 temp; 146 147 if (HAS_PCH_SPLIT(dev)) { 148 assert_fdi_rx_pll_disabled(dev_priv, pipe); 149 assert_shared_dpll_disabled(dev_priv, 150 crtc->config->shared_dpll); 151 } else { 152 assert_pll_disabled(dev_priv, pipe); 153 } 154 155 temp = I915_READ(lvds_encoder->reg); 156 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 157 158 if (HAS_PCH_CPT(dev)) { 159 temp &= ~PORT_TRANS_SEL_MASK; 160 temp |= PORT_TRANS_SEL_CPT(pipe); 161 } else { 162 if (pipe == 1) { 163 temp |= LVDS_PIPEB_SELECT; 164 } else { 165 temp &= ~LVDS_PIPEB_SELECT; 166 } 167 } 168 169 /* set the corresponsding LVDS_BORDER bit */ 170 temp &= ~LVDS_BORDER_ENABLE; 171 temp |= crtc->config->gmch_pfit.lvds_border_bits; 172 /* Set the B0-B3 data pairs corresponding to whether we're going to 173 * set the DPLLs for dual-channel mode or not. 174 */ 175 if (lvds_encoder->is_dual_link) 176 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 177 else 178 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 179 180 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 181 * appropriately here, but we need to look more thoroughly into how 182 * panels behave in the two modes. For now, let's just maintain the 183 * value we got from the BIOS. 184 */ 185 temp &= ~LVDS_A3_POWER_MASK; 186 temp |= lvds_encoder->a3_power; 187 188 /* Set the dithering flag on LVDS as needed, note that there is no 189 * special lvds dither control bit on pch-split platforms, dithering is 190 * only controlled through the PIPECONF reg. */ 191 if (INTEL_INFO(dev)->gen == 4) { 192 /* Bspec wording suggests that LVDS port dithering only exists 193 * for 18bpp panels. */ 194 if (crtc->config->dither && crtc->config->pipe_bpp == 18) 195 temp |= LVDS_ENABLE_DITHER; 196 else 197 temp &= ~LVDS_ENABLE_DITHER; 198 } 199 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 200 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 201 temp |= LVDS_HSYNC_POLARITY; 202 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 203 temp |= LVDS_VSYNC_POLARITY; 204 205 I915_WRITE(lvds_encoder->reg, temp); 206 } 207 208 /** 209 * Sets the power state for the panel. 210 */ 211 static void intel_enable_lvds(struct intel_encoder *encoder) 212 { 213 struct drm_device *dev = encoder->base.dev; 214 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 215 struct intel_connector *intel_connector = 216 &lvds_encoder->attached_connector->base; 217 struct drm_i915_private *dev_priv = dev->dev_private; 218 i915_reg_t ctl_reg, stat_reg; 219 220 if (HAS_PCH_SPLIT(dev)) { 221 ctl_reg = PCH_PP_CONTROL; 222 stat_reg = PCH_PP_STATUS; 223 } else { 224 ctl_reg = PP_CONTROL; 225 stat_reg = PP_STATUS; 226 } 227 228 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); 229 230 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); 231 POSTING_READ(lvds_encoder->reg); 232 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) 233 DRM_ERROR("timed out waiting for panel to power on\n"); 234 235 intel_panel_enable_backlight(intel_connector); 236 } 237 238 static void intel_disable_lvds(struct intel_encoder *encoder) 239 { 240 struct drm_device *dev = encoder->base.dev; 241 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 242 struct drm_i915_private *dev_priv = dev->dev_private; 243 i915_reg_t ctl_reg, stat_reg; 244 245 if (HAS_PCH_SPLIT(dev)) { 246 ctl_reg = PCH_PP_CONTROL; 247 stat_reg = PCH_PP_STATUS; 248 } else { 249 ctl_reg = PP_CONTROL; 250 stat_reg = PP_STATUS; 251 } 252 253 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); 254 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) 255 DRM_ERROR("timed out waiting for panel to power off\n"); 256 257 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); 258 POSTING_READ(lvds_encoder->reg); 259 } 260 261 static void gmch_disable_lvds(struct intel_encoder *encoder) 262 { 263 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 264 struct intel_connector *intel_connector = 265 &lvds_encoder->attached_connector->base; 266 267 intel_panel_disable_backlight(intel_connector); 268 269 intel_disable_lvds(encoder); 270 } 271 272 static void pch_disable_lvds(struct intel_encoder *encoder) 273 { 274 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 275 struct intel_connector *intel_connector = 276 &lvds_encoder->attached_connector->base; 277 278 intel_panel_disable_backlight(intel_connector); 279 } 280 281 static void pch_post_disable_lvds(struct intel_encoder *encoder) 282 { 283 intel_disable_lvds(encoder); 284 } 285 286 static enum drm_mode_status 287 intel_lvds_mode_valid(struct drm_connector *connector, 288 struct drm_display_mode *mode) 289 { 290 struct intel_connector *intel_connector = to_intel_connector(connector); 291 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 292 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 293 294 if (mode->hdisplay > fixed_mode->hdisplay) 295 return MODE_PANEL; 296 if (mode->vdisplay > fixed_mode->vdisplay) 297 return MODE_PANEL; 298 if (fixed_mode->clock > max_pixclk) 299 return MODE_CLOCK_HIGH; 300 301 return MODE_OK; 302 } 303 304 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, 305 struct intel_crtc_state *pipe_config) 306 { 307 struct drm_device *dev = intel_encoder->base.dev; 308 struct intel_lvds_encoder *lvds_encoder = 309 to_lvds_encoder(&intel_encoder->base); 310 struct intel_connector *intel_connector = 311 &lvds_encoder->attached_connector->base; 312 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 313 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 314 unsigned int lvds_bpp; 315 316 /* Should never happen!! */ 317 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { 318 DRM_ERROR("Can't support LVDS on pipe A\n"); 319 return false; 320 } 321 322 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 323 lvds_bpp = 8*3; 324 else 325 lvds_bpp = 6*3; 326 327 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 328 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", 329 pipe_config->pipe_bpp, lvds_bpp); 330 pipe_config->pipe_bpp = lvds_bpp; 331 } 332 333 /* 334 * We have timings from the BIOS for the panel, put them in 335 * to the adjusted mode. The CRTC will be set up for this mode, 336 * with the panel scaling set up to source from the H/VDisplay 337 * of the original mode. 338 */ 339 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 340 adjusted_mode); 341 342 if (HAS_PCH_SPLIT(dev)) { 343 pipe_config->has_pch_encoder = true; 344 345 intel_pch_panel_fitting(intel_crtc, pipe_config, 346 intel_connector->panel.fitting_mode); 347 } else { 348 intel_gmch_panel_fitting(intel_crtc, pipe_config, 349 intel_connector->panel.fitting_mode); 350 351 } 352 353 /* 354 * XXX: It would be nice to support lower refresh rates on the 355 * panels to reduce power consumption, and perhaps match the 356 * user's requested refresh rate. 357 */ 358 359 return true; 360 } 361 362 /** 363 * Detect the LVDS connection. 364 * 365 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means 366 * connected and closed means disconnected. We also send hotplug events as 367 * needed, using lid status notification from the input layer. 368 */ 369 static enum drm_connector_status 370 intel_lvds_detect(struct drm_connector *connector, bool force) 371 { 372 struct drm_device *dev = connector->dev; 373 enum drm_connector_status status; 374 375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 376 connector->base.id, connector->name); 377 378 status = intel_panel_detect(dev); 379 if (status != connector_status_unknown) 380 return status; 381 382 return connector_status_connected; 383 } 384 385 /** 386 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 387 */ 388 static int intel_lvds_get_modes(struct drm_connector *connector) 389 { 390 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); 391 struct drm_device *dev = connector->dev; 392 struct drm_display_mode *mode; 393 394 /* use cached edid if we have one */ 395 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 396 return drm_add_edid_modes(connector, lvds_connector->base.edid); 397 398 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); 399 if (mode == NULL) 400 return 0; 401 402 drm_mode_probed_add(connector, mode); 403 return 1; 404 } 405 406 #if 0 /* unused */ 407 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) 408 { 409 DRM_INFO("Skipping forced modeset for %s\n", id->ident); 410 return 1; 411 } 412 413 /* The GPU hangs up on these systems if modeset is performed on LID open */ 414 static const struct dmi_system_id intel_no_modeset_on_lid[] = { 415 { 416 .callback = intel_no_modeset_on_lid_dmi_callback, 417 .ident = "Toshiba Tecra A11", 418 .matches = { 419 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 420 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), 421 }, 422 }, 423 424 { } /* terminating entry */ 425 }; 426 #endif 427 428 #if 0 429 /* 430 * Lid events. Note the use of 'modeset': 431 * - we set it to MODESET_ON_LID_OPEN on lid close, 432 * and set it to MODESET_DONE on open 433 * - we use it as a "only once" bit (ie we ignore 434 * duplicate events where it was already properly set) 435 * - the suspend/resume paths will set it to 436 * MODESET_SUSPENDED and ignore the lid open event, 437 * because they restore the mode ("lid open"). 438 */ 439 static int intel_lid_notify(struct notifier_block *nb, unsigned long val, 440 void *unused) 441 { 442 struct intel_lvds_connector *lvds_connector = 443 container_of(nb, struct intel_lvds_connector, lid_notifier); 444 struct drm_connector *connector = &lvds_connector->base.base; 445 struct drm_device *dev = connector->dev; 446 struct drm_i915_private *dev_priv = dev->dev_private; 447 448 if (dev->switch_power_state != DRM_SWITCH_POWER_ON) 449 return NOTIFY_OK; 450 451 mutex_lock(&dev_priv->modeset_restore_lock); 452 if (dev_priv->modeset_restore == MODESET_SUSPENDED) 453 goto exit; 454 /* 455 * check and update the status of LVDS connector after receiving 456 * the LID nofication event. 457 */ 458 connector->status = connector->funcs->detect(connector, false); 459 460 /* Don't force modeset on machines where it causes a GPU lockup */ 461 if (dmi_check_system(intel_no_modeset_on_lid)) 462 goto exit; 463 if (!acpi_lid_open()) { 464 /* do modeset on next lid open event */ 465 dev_priv->modeset_restore = MODESET_ON_LID_OPEN; 466 goto exit; 467 } 468 469 if (dev_priv->modeset_restore == MODESET_DONE) 470 goto exit; 471 472 /* 473 * Some old platform's BIOS love to wreak havoc while the lid is closed. 474 * We try to detect this here and undo any damage. The split for PCH 475 * platforms is rather conservative and a bit arbitrary expect that on 476 * those platforms VGA disabling requires actual legacy VGA I/O access, 477 * and as part of the cleanup in the hw state restore we also redisable 478 * the vga plane. 479 */ 480 if (!HAS_PCH_SPLIT(dev)) 481 intel_display_resume(dev); 482 483 dev_priv->modeset_restore = MODESET_DONE; 484 485 exit: 486 mutex_unlock(&dev_priv->modeset_restore_lock); 487 return NOTIFY_OK; 488 } 489 #endif 490 491 /** 492 * intel_lvds_destroy - unregister and free LVDS structures 493 * @connector: connector to free 494 * 495 * Unregister the DDC bus for this connector then free the driver private 496 * structure. 497 */ 498 static void intel_lvds_destroy(struct drm_connector *connector) 499 { 500 struct intel_lvds_connector *lvds_connector = 501 to_lvds_connector(connector); 502 503 #if 0 504 if (lvds_connector->lid_notifier.notifier_call) 505 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); 506 #endif 507 508 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 509 kfree(lvds_connector->base.edid); 510 511 intel_panel_fini(&lvds_connector->base.panel); 512 513 drm_connector_cleanup(connector); 514 kfree(connector); 515 } 516 517 static int intel_lvds_set_property(struct drm_connector *connector, 518 struct drm_property *property, 519 uint64_t value) 520 { 521 struct intel_connector *intel_connector = to_intel_connector(connector); 522 struct drm_device *dev = connector->dev; 523 524 if (property == dev->mode_config.scaling_mode_property) { 525 struct drm_crtc *crtc; 526 527 if (value == DRM_MODE_SCALE_NONE) { 528 DRM_DEBUG_KMS("no scaling not supported\n"); 529 return -EINVAL; 530 } 531 532 if (intel_connector->panel.fitting_mode == value) { 533 /* the LVDS scaling property is not changed */ 534 return 0; 535 } 536 intel_connector->panel.fitting_mode = value; 537 538 crtc = intel_attached_encoder(connector)->base.crtc; 539 if (crtc && crtc->state->enable) { 540 /* 541 * If the CRTC is enabled, the display will be changed 542 * according to the new panel fitting mode. 543 */ 544 intel_crtc_restore_mode(crtc); 545 } 546 } 547 548 return 0; 549 } 550 551 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 552 .get_modes = intel_lvds_get_modes, 553 .mode_valid = intel_lvds_mode_valid, 554 .best_encoder = intel_best_encoder, 555 }; 556 557 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 558 .dpms = drm_atomic_helper_connector_dpms, 559 .detect = intel_lvds_detect, 560 .fill_modes = drm_helper_probe_single_connector_modes, 561 .set_property = intel_lvds_set_property, 562 .atomic_get_property = intel_connector_atomic_get_property, 563 .destroy = intel_lvds_destroy, 564 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 565 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 566 }; 567 568 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 569 .destroy = intel_encoder_destroy, 570 }; 571 572 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 573 { 574 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 575 return 1; 576 } 577 578 /* These systems claim to have LVDS, but really don't */ 579 static const struct dmi_system_id intel_no_lvds[] = { 580 { 581 .callback = intel_no_lvds_dmi_callback, 582 .ident = "Apple Mac Mini (Core series)", 583 .matches = { 584 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 585 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 586 }, 587 }, 588 { 589 .callback = intel_no_lvds_dmi_callback, 590 .ident = "Apple Mac Mini (Core 2 series)", 591 .matches = { 592 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 593 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 594 }, 595 }, 596 { 597 .callback = intel_no_lvds_dmi_callback, 598 .ident = "MSI IM-945GSE-A", 599 .matches = { 600 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 601 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 602 }, 603 }, 604 { 605 .callback = intel_no_lvds_dmi_callback, 606 .ident = "Dell Studio Hybrid", 607 .matches = { 608 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 609 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 610 }, 611 }, 612 { 613 .callback = intel_no_lvds_dmi_callback, 614 .ident = "Dell OptiPlex FX170", 615 .matches = { 616 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 617 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 618 }, 619 }, 620 { 621 .callback = intel_no_lvds_dmi_callback, 622 .ident = "AOpen Mini PC", 623 .matches = { 624 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 625 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 626 }, 627 }, 628 { 629 .callback = intel_no_lvds_dmi_callback, 630 .ident = "AOpen Mini PC MP915", 631 .matches = { 632 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 633 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 634 }, 635 }, 636 { 637 .callback = intel_no_lvds_dmi_callback, 638 .ident = "AOpen i915GMm-HFS", 639 .matches = { 640 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 641 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 642 }, 643 }, 644 { 645 .callback = intel_no_lvds_dmi_callback, 646 .ident = "AOpen i45GMx-I", 647 .matches = { 648 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 649 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 650 }, 651 }, 652 { 653 .callback = intel_no_lvds_dmi_callback, 654 .ident = "Aopen i945GTt-VFA", 655 .matches = { 656 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 657 }, 658 }, 659 { 660 .callback = intel_no_lvds_dmi_callback, 661 .ident = "Clientron U800", 662 .matches = { 663 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 664 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 665 }, 666 }, 667 { 668 .callback = intel_no_lvds_dmi_callback, 669 .ident = "Clientron E830", 670 .matches = { 671 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 672 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 673 }, 674 }, 675 { 676 .callback = intel_no_lvds_dmi_callback, 677 .ident = "Asus EeeBox PC EB1007", 678 .matches = { 679 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 680 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 681 }, 682 }, 683 { 684 .callback = intel_no_lvds_dmi_callback, 685 .ident = "Asus AT5NM10T-I", 686 .matches = { 687 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 688 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 689 }, 690 }, 691 { 692 .callback = intel_no_lvds_dmi_callback, 693 .ident = "Hewlett-Packard HP t5740", 694 .matches = { 695 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 696 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 697 }, 698 }, 699 { 700 .callback = intel_no_lvds_dmi_callback, 701 .ident = "Hewlett-Packard t5745", 702 .matches = { 703 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 704 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 705 }, 706 }, 707 { 708 .callback = intel_no_lvds_dmi_callback, 709 .ident = "Hewlett-Packard st5747", 710 .matches = { 711 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 712 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 713 }, 714 }, 715 { 716 .callback = intel_no_lvds_dmi_callback, 717 .ident = "MSI Wind Box DC500", 718 .matches = { 719 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 720 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 721 }, 722 }, 723 { 724 .callback = intel_no_lvds_dmi_callback, 725 .ident = "Gigabyte GA-D525TUD", 726 .matches = { 727 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 728 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 729 }, 730 }, 731 { 732 .callback = intel_no_lvds_dmi_callback, 733 .ident = "Supermicro X7SPA-H", 734 .matches = { 735 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 736 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 737 }, 738 }, 739 { 740 .callback = intel_no_lvds_dmi_callback, 741 .ident = "Fujitsu Esprimo Q900", 742 .matches = { 743 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 744 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 745 }, 746 }, 747 { 748 .callback = intel_no_lvds_dmi_callback, 749 .ident = "Intel D410PT", 750 .matches = { 751 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 752 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 753 }, 754 }, 755 { 756 .callback = intel_no_lvds_dmi_callback, 757 .ident = "Intel D425KT", 758 .matches = { 759 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 760 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 761 }, 762 }, 763 { 764 .callback = intel_no_lvds_dmi_callback, 765 .ident = "Intel D510MO", 766 .matches = { 767 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 768 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 769 }, 770 }, 771 { 772 .callback = intel_no_lvds_dmi_callback, 773 .ident = "Intel D525MW", 774 .matches = { 775 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 776 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 777 }, 778 }, 779 780 { } /* terminating entry */ 781 }; 782 783 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 784 { 785 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 786 return 1; 787 } 788 789 static const struct dmi_system_id intel_dual_link_lvds[] = { 790 { 791 .callback = intel_dual_link_lvds_callback, 792 .ident = "Apple MacBook Pro 15\" (2010)", 793 .matches = { 794 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 795 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 796 }, 797 }, 798 { 799 .callback = intel_dual_link_lvds_callback, 800 .ident = "Apple MacBook Pro 15\" (2011)", 801 .matches = { 802 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 803 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 804 }, 805 }, 806 { 807 .callback = intel_dual_link_lvds_callback, 808 .ident = "Apple MacBook Pro 15\" (2012)", 809 .matches = { 810 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 811 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 812 }, 813 }, 814 { } /* terminating entry */ 815 }; 816 817 bool intel_is_dual_link_lvds(struct drm_device *dev) 818 { 819 struct intel_encoder *encoder; 820 struct intel_lvds_encoder *lvds_encoder; 821 822 for_each_intel_encoder(dev, encoder) { 823 if (encoder->type == INTEL_OUTPUT_LVDS) { 824 lvds_encoder = to_lvds_encoder(&encoder->base); 825 826 return lvds_encoder->is_dual_link; 827 } 828 } 829 830 return false; 831 } 832 833 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 834 { 835 struct drm_device *dev = lvds_encoder->base.base.dev; 836 unsigned int val; 837 struct drm_i915_private *dev_priv = dev->dev_private; 838 839 /* use the module option value if specified */ 840 if (i915.lvds_channel_mode > 0) 841 return i915.lvds_channel_mode == 2; 842 843 /* single channel LVDS is limited to 112 MHz */ 844 if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock 845 > 112999) 846 return true; 847 848 if (dmi_check_system(intel_dual_link_lvds)) 849 return true; 850 851 /* BIOS should set the proper LVDS register value at boot, but 852 * in reality, it doesn't set the value when the lid is closed; 853 * we need to check "the value to be set" in VBT when LVDS 854 * register is uninitialized. 855 */ 856 val = I915_READ(lvds_encoder->reg); 857 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) 858 val = dev_priv->vbt.bios_lvds_val; 859 860 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 861 } 862 863 static bool intel_lvds_supported(struct drm_device *dev) 864 { 865 /* With the introduction of the PCH we gained a dedicated 866 * LVDS presence pin, use it. */ 867 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 868 return true; 869 870 /* Otherwise LVDS was only attached to mobile products, 871 * except for the inglorious 830gm */ 872 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) 873 return true; 874 875 return false; 876 } 877 878 /** 879 * intel_lvds_init - setup LVDS connectors on this device 880 * @dev: drm device 881 * 882 * Create the connector, register the LVDS DDC bus, and try to figure out what 883 * modes we can display on the LVDS panel (if present). 884 */ 885 void intel_lvds_init(struct drm_device *dev) 886 { 887 struct drm_i915_private *dev_priv = dev->dev_private; 888 struct intel_lvds_encoder *lvds_encoder; 889 struct intel_encoder *intel_encoder; 890 struct intel_lvds_connector *lvds_connector; 891 struct intel_connector *intel_connector; 892 struct drm_connector *connector; 893 struct drm_encoder *encoder; 894 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 895 struct drm_display_mode *fixed_mode = NULL; 896 struct drm_display_mode *downclock_mode = NULL; 897 struct edid *edid; 898 struct drm_crtc *crtc; 899 i915_reg_t lvds_reg; 900 u32 lvds; 901 int pipe; 902 u8 pin; 903 904 /* 905 * Unlock registers and just leave them unlocked. Do this before 906 * checking quirk lists to avoid bogus WARNINGs. 907 */ 908 if (HAS_PCH_SPLIT(dev)) { 909 I915_WRITE(PCH_PP_CONTROL, 910 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); 911 } else if (INTEL_INFO(dev_priv)->gen < 5) { 912 I915_WRITE(PP_CONTROL, 913 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); 914 } 915 if (!intel_lvds_supported(dev)) 916 return; 917 918 /* Skip init on machines we know falsely report LVDS */ 919 if (dmi_check_system(intel_no_lvds)) 920 return; 921 922 if (HAS_PCH_SPLIT(dev)) 923 lvds_reg = PCH_LVDS; 924 else 925 lvds_reg = LVDS; 926 927 lvds = I915_READ(lvds_reg); 928 929 if (HAS_PCH_SPLIT(dev)) { 930 if ((lvds & LVDS_DETECTED) == 0) 931 return; 932 if (dev_priv->vbt.edp.support) { 933 DRM_DEBUG_KMS("disable LVDS for eDP support\n"); 934 return; 935 } 936 } 937 938 pin = GMBUS_PIN_PANEL; 939 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 940 if ((lvds & LVDS_PORT_EN) == 0) { 941 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); 942 return; 943 } 944 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); 945 } 946 947 /* Set the Panel Power On/Off timings if uninitialized. */ 948 if (INTEL_INFO(dev_priv)->gen < 5 && 949 I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) { 950 /* Set T2 to 40ms and T5 to 200ms */ 951 I915_WRITE(PP_ON_DELAYS, 0x019007d0); 952 953 /* Set T3 to 35ms and Tx to 200ms */ 954 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0); 955 956 DRM_DEBUG_KMS("Panel power timings uninitialized, setting defaults\n"); 957 } 958 959 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 960 if (!lvds_encoder) 961 return; 962 963 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); 964 if (!lvds_connector) { 965 kfree(lvds_encoder); 966 return; 967 } 968 969 if (intel_connector_init(&lvds_connector->base) < 0) { 970 kfree(lvds_connector); 971 kfree(lvds_encoder); 972 return; 973 } 974 975 lvds_encoder->attached_connector = lvds_connector; 976 977 intel_encoder = &lvds_encoder->base; 978 encoder = &intel_encoder->base; 979 intel_connector = &lvds_connector->base; 980 connector = &intel_connector->base; 981 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 982 DRM_MODE_CONNECTOR_LVDS); 983 984 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 985 DRM_MODE_ENCODER_LVDS, NULL); 986 987 intel_encoder->enable = intel_enable_lvds; 988 intel_encoder->pre_enable = intel_pre_enable_lvds; 989 intel_encoder->compute_config = intel_lvds_compute_config; 990 if (HAS_PCH_SPLIT(dev_priv)) { 991 intel_encoder->disable = pch_disable_lvds; 992 intel_encoder->post_disable = pch_post_disable_lvds; 993 } else { 994 intel_encoder->disable = gmch_disable_lvds; 995 } 996 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 997 intel_encoder->get_config = intel_lvds_get_config; 998 intel_connector->get_hw_state = intel_connector_get_hw_state; 999 intel_connector->unregister = intel_connector_unregister; 1000 1001 intel_connector_attach_encoder(intel_connector, intel_encoder); 1002 intel_encoder->type = INTEL_OUTPUT_LVDS; 1003 1004 intel_encoder->cloneable = 0; 1005 if (HAS_PCH_SPLIT(dev)) 1006 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1007 else if (IS_GEN4(dev)) 1008 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1009 else 1010 intel_encoder->crtc_mask = (1 << 1); 1011 1012 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 1013 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1014 connector->interlace_allowed = false; 1015 connector->doublescan_allowed = false; 1016 1017 lvds_encoder->reg = lvds_reg; 1018 1019 /* create the scaling mode property */ 1020 drm_mode_create_scaling_mode_property(dev); 1021 drm_object_attach_property(&connector->base, 1022 dev->mode_config.scaling_mode_property, 1023 DRM_MODE_SCALE_ASPECT); 1024 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 1025 /* 1026 * LVDS discovery: 1027 * 1) check for EDID on DDC 1028 * 2) check for VBT data 1029 * 3) check to see if LVDS is already on 1030 * if none of the above, no panel 1031 * 4) make sure lid is open 1032 * if closed, act like it's not there for now 1033 */ 1034 1035 /* 1036 * Attempt to get the fixed panel mode from DDC. Assume that the 1037 * preferred mode is the right one. 1038 */ 1039 mutex_lock(&dev->mode_config.mutex); 1040 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 1041 edid = drm_get_edid_switcheroo(connector, 1042 intel_gmbus_get_adapter(dev_priv, pin)); 1043 else 1044 edid = drm_get_edid(connector, 1045 intel_gmbus_get_adapter(dev_priv, pin)); 1046 if (edid) { 1047 if (drm_add_edid_modes(connector, edid)) { 1048 drm_mode_connector_update_edid_property(connector, 1049 edid); 1050 } else { 1051 kfree(edid); 1052 edid = ERR_PTR(-EINVAL); 1053 } 1054 } else { 1055 edid = ERR_PTR(-ENOENT); 1056 } 1057 lvds_connector->base.edid = edid; 1058 1059 if (IS_ERR_OR_NULL(edid)) { 1060 /* Didn't get an EDID, so 1061 * Set wide sync ranges so we get all modes 1062 * handed to valid_mode for checking 1063 */ 1064 connector->display_info.min_vfreq = 0; 1065 connector->display_info.max_vfreq = 200; 1066 connector->display_info.min_hfreq = 0; 1067 connector->display_info.max_hfreq = 200; 1068 } 1069 1070 list_for_each_entry(scan, &connector->probed_modes, head) { 1071 if (scan->type & DRM_MODE_TYPE_PREFERRED) { 1072 DRM_DEBUG_KMS("using preferred mode from EDID: "); 1073 drm_mode_debug_printmodeline(scan); 1074 1075 fixed_mode = drm_mode_duplicate(dev, scan); 1076 if (fixed_mode) 1077 goto out; 1078 } 1079 } 1080 1081 /* Failed to get EDID, what about VBT? */ 1082 if (dev_priv->vbt.lfp_lvds_vbt_mode) { 1083 DRM_DEBUG_KMS("using mode from VBT: "); 1084 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); 1085 1086 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); 1087 if (fixed_mode) { 1088 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1089 connector->display_info.width_mm = fixed_mode->width_mm; 1090 connector->display_info.height_mm = fixed_mode->height_mm; 1091 goto out; 1092 } 1093 } 1094 1095 /* 1096 * If we didn't get EDID, try checking if the panel is already turned 1097 * on. If so, assume that whatever is currently programmed is the 1098 * correct mode. 1099 */ 1100 1101 /* Ironlake: FIXME if still fail, not try pipe mode now */ 1102 if (HAS_PCH_SPLIT(dev)) 1103 goto failed; 1104 1105 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; 1106 crtc = intel_get_crtc_for_pipe(dev, pipe); 1107 1108 if (crtc && (lvds & LVDS_PORT_EN)) { 1109 fixed_mode = intel_crtc_mode_get(dev, crtc); 1110 if (fixed_mode) { 1111 DRM_DEBUG_KMS("using current (BIOS) mode: "); 1112 drm_mode_debug_printmodeline(fixed_mode); 1113 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1114 goto out; 1115 } 1116 } 1117 1118 /* If we still don't have a mode after all that, give up. */ 1119 if (!fixed_mode) 1120 goto failed; 1121 1122 out: 1123 mutex_unlock(&dev->mode_config.mutex); 1124 1125 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 1126 1127 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1128 DRM_DEBUG_KMS("detected %s-link lvds configuration\n", 1129 lvds_encoder->is_dual_link ? "dual" : "single"); 1130 1131 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1132 1133 #if 0 1134 lvds_connector->lid_notifier.notifier_call = intel_lid_notify; 1135 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { 1136 DRM_DEBUG_KMS("lid notifier registration failed\n"); 1137 lvds_connector->lid_notifier.notifier_call = NULL; 1138 } 1139 drm_connector_register(connector); 1140 #endif 1141 1142 intel_panel_setup_backlight(connector, INVALID_PIPE); 1143 1144 return; 1145 1146 failed: 1147 mutex_unlock(&dev->mode_config.mutex); 1148 1149 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1150 drm_connector_cleanup(connector); 1151 drm_encoder_cleanup(encoder); 1152 kfree(lvds_encoder); 1153 kfree(lvds_connector); 1154 return; 1155 } 1156