1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Dave Airlie <airlied@linux.ie> 27 * Jesse Barnes <jesse.barnes@intel.com> 28 */ 29 #include "opt_drm.h" 30 31 #include <linux/dmi.h> 32 #include <linux/i2c.h> 33 #include <linux/vga_switcheroo.h> 34 #include <drm/drmP.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 #include "intel_drv.h" 39 #include <drm/i915_drm.h> 40 #include "i915_drv.h" 41 42 /* Private structure for the integrated LVDS support */ 43 struct intel_lvds_connector { 44 struct intel_connector base; 45 46 struct notifier_block lid_notifier; 47 }; 48 49 struct intel_lvds_encoder { 50 struct intel_encoder base; 51 52 bool is_dual_link; 53 i915_reg_t reg; 54 u32 a3_power; 55 56 struct intel_lvds_connector *attached_connector; 57 }; 58 59 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) 60 { 61 return container_of(encoder, struct intel_lvds_encoder, base.base); 62 } 63 64 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) 65 { 66 return container_of(connector, struct intel_lvds_connector, base.base); 67 } 68 69 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, 70 enum i915_pipe *pipe) 71 { 72 struct drm_device *dev = encoder->base.dev; 73 struct drm_i915_private *dev_priv = dev->dev_private; 74 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 75 enum intel_display_power_domain power_domain; 76 u32 tmp; 77 bool ret; 78 79 power_domain = intel_display_port_power_domain(encoder); 80 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 81 return false; 82 83 ret = false; 84 85 tmp = I915_READ(lvds_encoder->reg); 86 87 if (!(tmp & LVDS_PORT_EN)) 88 goto out; 89 90 if (HAS_PCH_CPT(dev)) 91 *pipe = PORT_TO_PIPE_CPT(tmp); 92 else 93 *pipe = PORT_TO_PIPE(tmp); 94 95 ret = true; 96 97 out: 98 intel_display_power_put(dev_priv, power_domain); 99 100 return ret; 101 } 102 103 static void intel_lvds_get_config(struct intel_encoder *encoder, 104 struct intel_crtc_state *pipe_config) 105 { 106 struct drm_device *dev = encoder->base.dev; 107 struct drm_i915_private *dev_priv = dev->dev_private; 108 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 109 u32 tmp, flags = 0; 110 111 tmp = I915_READ(lvds_encoder->reg); 112 if (tmp & LVDS_HSYNC_POLARITY) 113 flags |= DRM_MODE_FLAG_NHSYNC; 114 else 115 flags |= DRM_MODE_FLAG_PHSYNC; 116 if (tmp & LVDS_VSYNC_POLARITY) 117 flags |= DRM_MODE_FLAG_NVSYNC; 118 else 119 flags |= DRM_MODE_FLAG_PVSYNC; 120 121 pipe_config->base.adjusted_mode.flags |= flags; 122 123 if (INTEL_INFO(dev)->gen < 5) 124 pipe_config->gmch_pfit.lvds_border_bits = 125 tmp & LVDS_BORDER_ENABLE; 126 127 /* gen2/3 store dither state in pfit control, needs to match */ 128 if (INTEL_INFO(dev)->gen < 4) { 129 tmp = I915_READ(PFIT_CONTROL); 130 131 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; 132 } 133 134 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; 135 } 136 137 static void intel_pre_enable_lvds(struct intel_encoder *encoder) 138 { 139 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 140 struct drm_device *dev = encoder->base.dev; 141 struct drm_i915_private *dev_priv = dev->dev_private; 142 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 143 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 144 int pipe = crtc->pipe; 145 u32 temp; 146 147 if (HAS_PCH_SPLIT(dev)) { 148 assert_fdi_rx_pll_disabled(dev_priv, pipe); 149 assert_shared_dpll_disabled(dev_priv, 150 crtc->config->shared_dpll); 151 } else { 152 assert_pll_disabled(dev_priv, pipe); 153 } 154 155 temp = I915_READ(lvds_encoder->reg); 156 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; 157 158 if (HAS_PCH_CPT(dev)) { 159 temp &= ~PORT_TRANS_SEL_MASK; 160 temp |= PORT_TRANS_SEL_CPT(pipe); 161 } else { 162 if (pipe == 1) { 163 temp |= LVDS_PIPEB_SELECT; 164 } else { 165 temp &= ~LVDS_PIPEB_SELECT; 166 } 167 } 168 169 /* set the corresponsding LVDS_BORDER bit */ 170 temp &= ~LVDS_BORDER_ENABLE; 171 temp |= crtc->config->gmch_pfit.lvds_border_bits; 172 /* Set the B0-B3 data pairs corresponding to whether we're going to 173 * set the DPLLs for dual-channel mode or not. 174 */ 175 if (lvds_encoder->is_dual_link) 176 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; 177 else 178 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); 179 180 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) 181 * appropriately here, but we need to look more thoroughly into how 182 * panels behave in the two modes. For now, let's just maintain the 183 * value we got from the BIOS. 184 */ 185 temp &= ~LVDS_A3_POWER_MASK; 186 temp |= lvds_encoder->a3_power; 187 188 /* Set the dithering flag on LVDS as needed, note that there is no 189 * special lvds dither control bit on pch-split platforms, dithering is 190 * only controlled through the PIPECONF reg. */ 191 if (IS_GEN4(dev_priv)) { 192 /* Bspec wording suggests that LVDS port dithering only exists 193 * for 18bpp panels. */ 194 if (crtc->config->dither && crtc->config->pipe_bpp == 18) 195 temp |= LVDS_ENABLE_DITHER; 196 else 197 temp &= ~LVDS_ENABLE_DITHER; 198 } 199 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); 200 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 201 temp |= LVDS_HSYNC_POLARITY; 202 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 203 temp |= LVDS_VSYNC_POLARITY; 204 205 I915_WRITE(lvds_encoder->reg, temp); 206 } 207 208 /** 209 * Sets the power state for the panel. 210 */ 211 static void intel_enable_lvds(struct intel_encoder *encoder) 212 { 213 struct drm_device *dev = encoder->base.dev; 214 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 215 struct intel_connector *intel_connector = 216 &lvds_encoder->attached_connector->base; 217 struct drm_i915_private *dev_priv = dev->dev_private; 218 i915_reg_t ctl_reg, stat_reg; 219 220 if (HAS_PCH_SPLIT(dev)) { 221 ctl_reg = PCH_PP_CONTROL; 222 stat_reg = PCH_PP_STATUS; 223 } else { 224 ctl_reg = PP_CONTROL; 225 stat_reg = PP_STATUS; 226 } 227 228 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); 229 230 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); 231 POSTING_READ(lvds_encoder->reg); 232 if (intel_wait_for_register(dev_priv, stat_reg, PP_ON, PP_ON, 1000)) 233 DRM_ERROR("timed out waiting for panel to power on\n"); 234 235 intel_panel_enable_backlight(intel_connector); 236 } 237 238 static void intel_disable_lvds(struct intel_encoder *encoder) 239 { 240 struct drm_device *dev = encoder->base.dev; 241 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 242 struct drm_i915_private *dev_priv = dev->dev_private; 243 i915_reg_t ctl_reg, stat_reg; 244 245 if (HAS_PCH_SPLIT(dev)) { 246 ctl_reg = PCH_PP_CONTROL; 247 stat_reg = PCH_PP_STATUS; 248 } else { 249 ctl_reg = PP_CONTROL; 250 stat_reg = PP_STATUS; 251 } 252 253 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); 254 if (intel_wait_for_register(dev_priv, stat_reg, PP_ON, 0, 1000)) 255 DRM_ERROR("timed out waiting for panel to power off\n"); 256 257 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); 258 POSTING_READ(lvds_encoder->reg); 259 } 260 261 static void gmch_disable_lvds(struct intel_encoder *encoder) 262 { 263 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 264 struct intel_connector *intel_connector = 265 &lvds_encoder->attached_connector->base; 266 267 intel_panel_disable_backlight(intel_connector); 268 269 intel_disable_lvds(encoder); 270 } 271 272 static void pch_disable_lvds(struct intel_encoder *encoder) 273 { 274 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); 275 struct intel_connector *intel_connector = 276 &lvds_encoder->attached_connector->base; 277 278 intel_panel_disable_backlight(intel_connector); 279 } 280 281 static void pch_post_disable_lvds(struct intel_encoder *encoder) 282 { 283 intel_disable_lvds(encoder); 284 } 285 286 static enum drm_mode_status 287 intel_lvds_mode_valid(struct drm_connector *connector, 288 struct drm_display_mode *mode) 289 { 290 struct intel_connector *intel_connector = to_intel_connector(connector); 291 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 292 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; 293 294 if (mode->hdisplay > fixed_mode->hdisplay) 295 return MODE_PANEL; 296 if (mode->vdisplay > fixed_mode->vdisplay) 297 return MODE_PANEL; 298 if (fixed_mode->clock > max_pixclk) 299 return MODE_CLOCK_HIGH; 300 301 return MODE_OK; 302 } 303 304 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, 305 struct intel_crtc_state *pipe_config) 306 { 307 struct drm_device *dev = intel_encoder->base.dev; 308 struct intel_lvds_encoder *lvds_encoder = 309 to_lvds_encoder(&intel_encoder->base); 310 struct intel_connector *intel_connector = 311 &lvds_encoder->attached_connector->base; 312 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 313 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 314 unsigned int lvds_bpp; 315 316 /* Should never happen!! */ 317 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { 318 DRM_ERROR("Can't support LVDS on pipe A\n"); 319 return false; 320 } 321 322 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) 323 lvds_bpp = 8*3; 324 else 325 lvds_bpp = 6*3; 326 327 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { 328 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", 329 pipe_config->pipe_bpp, lvds_bpp); 330 pipe_config->pipe_bpp = lvds_bpp; 331 } 332 333 /* 334 * We have timings from the BIOS for the panel, put them in 335 * to the adjusted mode. The CRTC will be set up for this mode, 336 * with the panel scaling set up to source from the H/VDisplay 337 * of the original mode. 338 */ 339 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 340 adjusted_mode); 341 342 if (HAS_PCH_SPLIT(dev)) { 343 pipe_config->has_pch_encoder = true; 344 345 intel_pch_panel_fitting(intel_crtc, pipe_config, 346 intel_connector->panel.fitting_mode); 347 } else { 348 intel_gmch_panel_fitting(intel_crtc, pipe_config, 349 intel_connector->panel.fitting_mode); 350 351 } 352 353 /* 354 * XXX: It would be nice to support lower refresh rates on the 355 * panels to reduce power consumption, and perhaps match the 356 * user's requested refresh rate. 357 */ 358 359 return true; 360 } 361 362 /** 363 * Detect the LVDS connection. 364 * 365 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means 366 * connected and closed means disconnected. We also send hotplug events as 367 * needed, using lid status notification from the input layer. 368 */ 369 static enum drm_connector_status 370 intel_lvds_detect(struct drm_connector *connector, bool force) 371 { 372 struct drm_device *dev = connector->dev; 373 enum drm_connector_status status; 374 375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 376 connector->base.id, connector->name); 377 378 status = intel_panel_detect(dev); 379 if (status != connector_status_unknown) 380 return status; 381 382 return connector_status_connected; 383 } 384 385 /** 386 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. 387 */ 388 static int intel_lvds_get_modes(struct drm_connector *connector) 389 { 390 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); 391 struct drm_device *dev = connector->dev; 392 struct drm_display_mode *mode; 393 394 /* use cached edid if we have one */ 395 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 396 return drm_add_edid_modes(connector, lvds_connector->base.edid); 397 398 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); 399 if (mode == NULL) 400 return 0; 401 402 drm_mode_probed_add(connector, mode); 403 return 1; 404 } 405 406 #if 0 /* unused */ 407 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) 408 { 409 DRM_INFO("Skipping forced modeset for %s\n", id->ident); 410 return 1; 411 } 412 413 /* The GPU hangs up on these systems if modeset is performed on LID open */ 414 static const struct dmi_system_id intel_no_modeset_on_lid[] = { 415 { 416 .callback = intel_no_modeset_on_lid_dmi_callback, 417 .ident = "Toshiba Tecra A11", 418 .matches = { 419 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), 420 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), 421 }, 422 }, 423 424 { } /* terminating entry */ 425 }; 426 #endif 427 428 #if 0 429 /* 430 * Lid events. Note the use of 'modeset': 431 * - we set it to MODESET_ON_LID_OPEN on lid close, 432 * and set it to MODESET_DONE on open 433 * - we use it as a "only once" bit (ie we ignore 434 * duplicate events where it was already properly set) 435 * - the suspend/resume paths will set it to 436 * MODESET_SUSPENDED and ignore the lid open event, 437 * because they restore the mode ("lid open"). 438 */ 439 static int intel_lid_notify(struct notifier_block *nb, unsigned long val, 440 void *unused) 441 { 442 struct intel_lvds_connector *lvds_connector = 443 container_of(nb, struct intel_lvds_connector, lid_notifier); 444 struct drm_connector *connector = &lvds_connector->base.base; 445 struct drm_device *dev = connector->dev; 446 struct drm_i915_private *dev_priv = dev->dev_private; 447 448 if (dev->switch_power_state != DRM_SWITCH_POWER_ON) 449 return NOTIFY_OK; 450 451 mutex_lock(&dev_priv->modeset_restore_lock); 452 if (dev_priv->modeset_restore == MODESET_SUSPENDED) 453 goto exit; 454 /* 455 * check and update the status of LVDS connector after receiving 456 * the LID nofication event. 457 */ 458 connector->status = connector->funcs->detect(connector, false); 459 460 /* Don't force modeset on machines where it causes a GPU lockup */ 461 if (dmi_check_system(intel_no_modeset_on_lid)) 462 goto exit; 463 if (!acpi_lid_open()) { 464 /* do modeset on next lid open event */ 465 dev_priv->modeset_restore = MODESET_ON_LID_OPEN; 466 goto exit; 467 } 468 469 if (dev_priv->modeset_restore == MODESET_DONE) 470 goto exit; 471 472 /* 473 * Some old platform's BIOS love to wreak havoc while the lid is closed. 474 * We try to detect this here and undo any damage. The split for PCH 475 * platforms is rather conservative and a bit arbitrary expect that on 476 * those platforms VGA disabling requires actual legacy VGA I/O access, 477 * and as part of the cleanup in the hw state restore we also redisable 478 * the vga plane. 479 */ 480 if (!HAS_PCH_SPLIT(dev)) 481 intel_display_resume(dev); 482 483 dev_priv->modeset_restore = MODESET_DONE; 484 485 exit: 486 mutex_unlock(&dev_priv->modeset_restore_lock); 487 return NOTIFY_OK; 488 } 489 #endif 490 491 /** 492 * intel_lvds_destroy - unregister and free LVDS structures 493 * @connector: connector to free 494 * 495 * Unregister the DDC bus for this connector then free the driver private 496 * structure. 497 */ 498 static void intel_lvds_destroy(struct drm_connector *connector) 499 { 500 struct intel_lvds_connector *lvds_connector = 501 to_lvds_connector(connector); 502 503 #if 0 504 if (lvds_connector->lid_notifier.notifier_call) 505 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); 506 #endif 507 508 if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) 509 kfree(lvds_connector->base.edid); 510 511 intel_panel_fini(&lvds_connector->base.panel); 512 513 drm_connector_cleanup(connector); 514 kfree(connector); 515 } 516 517 static int intel_lvds_set_property(struct drm_connector *connector, 518 struct drm_property *property, 519 uint64_t value) 520 { 521 struct intel_connector *intel_connector = to_intel_connector(connector); 522 struct drm_device *dev = connector->dev; 523 524 if (property == dev->mode_config.scaling_mode_property) { 525 struct drm_crtc *crtc; 526 527 if (value == DRM_MODE_SCALE_NONE) { 528 DRM_DEBUG_KMS("no scaling not supported\n"); 529 return -EINVAL; 530 } 531 532 if (intel_connector->panel.fitting_mode == value) { 533 /* the LVDS scaling property is not changed */ 534 return 0; 535 } 536 intel_connector->panel.fitting_mode = value; 537 538 crtc = intel_attached_encoder(connector)->base.crtc; 539 if (crtc && crtc->state->enable) { 540 /* 541 * If the CRTC is enabled, the display will be changed 542 * according to the new panel fitting mode. 543 */ 544 intel_crtc_restore_mode(crtc); 545 } 546 } 547 548 return 0; 549 } 550 551 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { 552 .get_modes = intel_lvds_get_modes, 553 .mode_valid = intel_lvds_mode_valid, 554 }; 555 556 static const struct drm_connector_funcs intel_lvds_connector_funcs = { 557 .dpms = drm_atomic_helper_connector_dpms, 558 .detect = intel_lvds_detect, 559 .fill_modes = drm_helper_probe_single_connector_modes, 560 .set_property = intel_lvds_set_property, 561 .atomic_get_property = intel_connector_atomic_get_property, 562 .late_register = intel_connector_register, 563 .early_unregister = intel_connector_unregister, 564 .destroy = intel_lvds_destroy, 565 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 566 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 567 }; 568 569 static const struct drm_encoder_funcs intel_lvds_enc_funcs = { 570 .destroy = intel_encoder_destroy, 571 }; 572 573 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) 574 { 575 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); 576 return 1; 577 } 578 579 /* These systems claim to have LVDS, but really don't */ 580 static const struct dmi_system_id intel_no_lvds[] = { 581 { 582 .callback = intel_no_lvds_dmi_callback, 583 .ident = "Apple Mac Mini (Core series)", 584 .matches = { 585 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 586 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), 587 }, 588 }, 589 { 590 .callback = intel_no_lvds_dmi_callback, 591 .ident = "Apple Mac Mini (Core 2 series)", 592 .matches = { 593 DMI_MATCH(DMI_SYS_VENDOR, "Apple"), 594 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), 595 }, 596 }, 597 { 598 .callback = intel_no_lvds_dmi_callback, 599 .ident = "MSI IM-945GSE-A", 600 .matches = { 601 DMI_MATCH(DMI_SYS_VENDOR, "MSI"), 602 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), 603 }, 604 }, 605 { 606 .callback = intel_no_lvds_dmi_callback, 607 .ident = "Dell Studio Hybrid", 608 .matches = { 609 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 610 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), 611 }, 612 }, 613 { 614 .callback = intel_no_lvds_dmi_callback, 615 .ident = "Dell OptiPlex FX170", 616 .matches = { 617 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 618 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), 619 }, 620 }, 621 { 622 .callback = intel_no_lvds_dmi_callback, 623 .ident = "AOpen Mini PC", 624 .matches = { 625 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), 626 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), 627 }, 628 }, 629 { 630 .callback = intel_no_lvds_dmi_callback, 631 .ident = "AOpen Mini PC MP915", 632 .matches = { 633 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 634 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), 635 }, 636 }, 637 { 638 .callback = intel_no_lvds_dmi_callback, 639 .ident = "AOpen i915GMm-HFS", 640 .matches = { 641 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 642 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), 643 }, 644 }, 645 { 646 .callback = intel_no_lvds_dmi_callback, 647 .ident = "AOpen i45GMx-I", 648 .matches = { 649 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), 650 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), 651 }, 652 }, 653 { 654 .callback = intel_no_lvds_dmi_callback, 655 .ident = "Aopen i945GTt-VFA", 656 .matches = { 657 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), 658 }, 659 }, 660 { 661 .callback = intel_no_lvds_dmi_callback, 662 .ident = "Clientron U800", 663 .matches = { 664 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 665 DMI_MATCH(DMI_PRODUCT_NAME, "U800"), 666 }, 667 }, 668 { 669 .callback = intel_no_lvds_dmi_callback, 670 .ident = "Clientron E830", 671 .matches = { 672 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), 673 DMI_MATCH(DMI_PRODUCT_NAME, "E830"), 674 }, 675 }, 676 { 677 .callback = intel_no_lvds_dmi_callback, 678 .ident = "Asus EeeBox PC EB1007", 679 .matches = { 680 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), 681 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), 682 }, 683 }, 684 { 685 .callback = intel_no_lvds_dmi_callback, 686 .ident = "Asus AT5NM10T-I", 687 .matches = { 688 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 689 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), 690 }, 691 }, 692 { 693 .callback = intel_no_lvds_dmi_callback, 694 .ident = "Hewlett-Packard HP t5740", 695 .matches = { 696 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 697 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), 698 }, 699 }, 700 { 701 .callback = intel_no_lvds_dmi_callback, 702 .ident = "Hewlett-Packard t5745", 703 .matches = { 704 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 705 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), 706 }, 707 }, 708 { 709 .callback = intel_no_lvds_dmi_callback, 710 .ident = "Hewlett-Packard st5747", 711 .matches = { 712 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), 713 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), 714 }, 715 }, 716 { 717 .callback = intel_no_lvds_dmi_callback, 718 .ident = "MSI Wind Box DC500", 719 .matches = { 720 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), 721 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), 722 }, 723 }, 724 { 725 .callback = intel_no_lvds_dmi_callback, 726 .ident = "Gigabyte GA-D525TUD", 727 .matches = { 728 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), 729 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), 730 }, 731 }, 732 { 733 .callback = intel_no_lvds_dmi_callback, 734 .ident = "Supermicro X7SPA-H", 735 .matches = { 736 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), 737 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), 738 }, 739 }, 740 { 741 .callback = intel_no_lvds_dmi_callback, 742 .ident = "Fujitsu Esprimo Q900", 743 .matches = { 744 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), 745 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), 746 }, 747 }, 748 { 749 .callback = intel_no_lvds_dmi_callback, 750 .ident = "Intel D410PT", 751 .matches = { 752 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 753 DMI_MATCH(DMI_BOARD_NAME, "D410PT"), 754 }, 755 }, 756 { 757 .callback = intel_no_lvds_dmi_callback, 758 .ident = "Intel D425KT", 759 .matches = { 760 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 761 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), 762 }, 763 }, 764 { 765 .callback = intel_no_lvds_dmi_callback, 766 .ident = "Intel D510MO", 767 .matches = { 768 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 769 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), 770 }, 771 }, 772 { 773 .callback = intel_no_lvds_dmi_callback, 774 .ident = "Intel D525MW", 775 .matches = { 776 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), 777 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), 778 }, 779 }, 780 781 { } /* terminating entry */ 782 }; 783 784 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) 785 { 786 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); 787 return 1; 788 } 789 790 static const struct dmi_system_id intel_dual_link_lvds[] = { 791 { 792 .callback = intel_dual_link_lvds_callback, 793 .ident = "Apple MacBook Pro 15\" (2010)", 794 .matches = { 795 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 796 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), 797 }, 798 }, 799 { 800 .callback = intel_dual_link_lvds_callback, 801 .ident = "Apple MacBook Pro 15\" (2011)", 802 .matches = { 803 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 804 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), 805 }, 806 }, 807 { 808 .callback = intel_dual_link_lvds_callback, 809 .ident = "Apple MacBook Pro 15\" (2012)", 810 .matches = { 811 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), 812 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), 813 }, 814 }, 815 { } /* terminating entry */ 816 }; 817 818 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev) 819 { 820 struct intel_encoder *intel_encoder; 821 822 for_each_intel_encoder(dev, intel_encoder) 823 if (intel_encoder->type == INTEL_OUTPUT_LVDS) 824 return intel_encoder; 825 826 return NULL; 827 } 828 829 bool intel_is_dual_link_lvds(struct drm_device *dev) 830 { 831 struct intel_encoder *encoder = intel_get_lvds_encoder(dev); 832 833 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; 834 } 835 836 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) 837 { 838 struct drm_device *dev = lvds_encoder->base.base.dev; 839 unsigned int val; 840 struct drm_i915_private *dev_priv = dev->dev_private; 841 842 /* use the module option value if specified */ 843 if (i915.lvds_channel_mode > 0) 844 return i915.lvds_channel_mode == 2; 845 846 /* single channel LVDS is limited to 112 MHz */ 847 if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock 848 > 112999) 849 return true; 850 851 if (dmi_check_system(intel_dual_link_lvds)) 852 return true; 853 854 /* BIOS should set the proper LVDS register value at boot, but 855 * in reality, it doesn't set the value when the lid is closed; 856 * we need to check "the value to be set" in VBT when LVDS 857 * register is uninitialized. 858 */ 859 val = I915_READ(lvds_encoder->reg); 860 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) 861 val = dev_priv->vbt.bios_lvds_val; 862 863 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; 864 } 865 866 static bool intel_lvds_supported(struct drm_device *dev) 867 { 868 /* With the introduction of the PCH we gained a dedicated 869 * LVDS presence pin, use it. */ 870 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 871 return true; 872 873 /* Otherwise LVDS was only attached to mobile products, 874 * except for the inglorious 830gm */ 875 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) 876 return true; 877 878 return false; 879 } 880 881 /** 882 * intel_lvds_init - setup LVDS connectors on this device 883 * @dev: drm device 884 * 885 * Create the connector, register the LVDS DDC bus, and try to figure out what 886 * modes we can display on the LVDS panel (if present). 887 */ 888 void intel_lvds_init(struct drm_device *dev) 889 { 890 struct drm_i915_private *dev_priv = dev->dev_private; 891 struct intel_lvds_encoder *lvds_encoder; 892 struct intel_encoder *intel_encoder; 893 struct intel_lvds_connector *lvds_connector; 894 struct intel_connector *intel_connector; 895 struct drm_connector *connector; 896 struct drm_encoder *encoder; 897 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 898 struct drm_display_mode *fixed_mode = NULL; 899 struct drm_display_mode *downclock_mode = NULL; 900 struct edid *edid; 901 struct drm_crtc *crtc; 902 i915_reg_t lvds_reg; 903 u32 lvds; 904 int pipe; 905 u8 pin; 906 907 /* 908 * Unlock registers and just leave them unlocked. Do this before 909 * checking quirk lists to avoid bogus WARNINGs. 910 */ 911 if (HAS_PCH_SPLIT(dev)) { 912 I915_WRITE(PCH_PP_CONTROL, 913 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); 914 } else if (INTEL_INFO(dev_priv)->gen < 5) { 915 I915_WRITE(PP_CONTROL, 916 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); 917 } 918 if (!intel_lvds_supported(dev)) 919 return; 920 921 /* Skip init on machines we know falsely report LVDS */ 922 if (dmi_check_system(intel_no_lvds)) 923 return; 924 925 if (HAS_PCH_SPLIT(dev)) 926 lvds_reg = PCH_LVDS; 927 else 928 lvds_reg = LVDS; 929 930 lvds = I915_READ(lvds_reg); 931 932 if (HAS_PCH_SPLIT(dev)) { 933 if ((lvds & LVDS_DETECTED) == 0) 934 return; 935 if (dev_priv->vbt.edp.support) { 936 DRM_DEBUG_KMS("disable LVDS for eDP support\n"); 937 return; 938 } 939 } 940 941 pin = GMBUS_PIN_PANEL; 942 if (!intel_bios_is_lvds_present(dev_priv, &pin)) { 943 if ((lvds & LVDS_PORT_EN) == 0) { 944 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); 945 return; 946 } 947 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); 948 } 949 950 /* Set the Panel Power On/Off timings if uninitialized. */ 951 if (INTEL_INFO(dev_priv)->gen < 5 && 952 I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) { 953 /* Set T2 to 40ms and T5 to 200ms */ 954 I915_WRITE(PP_ON_DELAYS, 0x019007d0); 955 956 /* Set T3 to 35ms and Tx to 200ms */ 957 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0); 958 959 DRM_DEBUG_KMS("Panel power timings uninitialized, setting defaults\n"); 960 } 961 962 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); 963 if (!lvds_encoder) 964 return; 965 966 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); 967 if (!lvds_connector) { 968 kfree(lvds_encoder); 969 return; 970 } 971 972 if (intel_connector_init(&lvds_connector->base) < 0) { 973 kfree(lvds_connector); 974 kfree(lvds_encoder); 975 return; 976 } 977 978 lvds_encoder->attached_connector = lvds_connector; 979 980 intel_encoder = &lvds_encoder->base; 981 encoder = &intel_encoder->base; 982 intel_connector = &lvds_connector->base; 983 connector = &intel_connector->base; 984 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, 985 DRM_MODE_CONNECTOR_LVDS); 986 987 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, 988 DRM_MODE_ENCODER_LVDS, "LVDS"); 989 990 intel_encoder->enable = intel_enable_lvds; 991 intel_encoder->pre_enable = intel_pre_enable_lvds; 992 intel_encoder->compute_config = intel_lvds_compute_config; 993 if (HAS_PCH_SPLIT(dev_priv)) { 994 intel_encoder->disable = pch_disable_lvds; 995 intel_encoder->post_disable = pch_post_disable_lvds; 996 } else { 997 intel_encoder->disable = gmch_disable_lvds; 998 } 999 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 1000 intel_encoder->get_config = intel_lvds_get_config; 1001 intel_connector->get_hw_state = intel_connector_get_hw_state; 1002 1003 intel_connector_attach_encoder(intel_connector, intel_encoder); 1004 intel_encoder->type = INTEL_OUTPUT_LVDS; 1005 1006 intel_encoder->cloneable = 0; 1007 if (HAS_PCH_SPLIT(dev)) 1008 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 1009 else if (IS_GEN4(dev)) 1010 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 1011 else 1012 intel_encoder->crtc_mask = (1 << 1); 1013 1014 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); 1015 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1016 connector->interlace_allowed = false; 1017 connector->doublescan_allowed = false; 1018 1019 lvds_encoder->reg = lvds_reg; 1020 1021 /* create the scaling mode property */ 1022 drm_mode_create_scaling_mode_property(dev); 1023 drm_object_attach_property(&connector->base, 1024 dev->mode_config.scaling_mode_property, 1025 DRM_MODE_SCALE_ASPECT); 1026 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 1027 /* 1028 * LVDS discovery: 1029 * 1) check for EDID on DDC 1030 * 2) check for VBT data 1031 * 3) check to see if LVDS is already on 1032 * if none of the above, no panel 1033 * 4) make sure lid is open 1034 * if closed, act like it's not there for now 1035 */ 1036 1037 /* 1038 * Attempt to get the fixed panel mode from DDC. Assume that the 1039 * preferred mode is the right one. 1040 */ 1041 mutex_lock(&dev->mode_config.mutex); 1042 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) 1043 edid = drm_get_edid_switcheroo(connector, 1044 intel_gmbus_get_adapter(dev_priv, pin)); 1045 else 1046 edid = drm_get_edid(connector, 1047 intel_gmbus_get_adapter(dev_priv, pin)); 1048 if (edid) { 1049 if (drm_add_edid_modes(connector, edid)) { 1050 drm_mode_connector_update_edid_property(connector, 1051 edid); 1052 } else { 1053 kfree(edid); 1054 edid = ERR_PTR(-EINVAL); 1055 } 1056 } else { 1057 edid = ERR_PTR(-ENOENT); 1058 } 1059 lvds_connector->base.edid = edid; 1060 1061 list_for_each_entry(scan, &connector->probed_modes, head) { 1062 if (scan->type & DRM_MODE_TYPE_PREFERRED) { 1063 DRM_DEBUG_KMS("using preferred mode from EDID: "); 1064 drm_mode_debug_printmodeline(scan); 1065 1066 fixed_mode = drm_mode_duplicate(dev, scan); 1067 if (fixed_mode) 1068 goto out; 1069 } 1070 } 1071 1072 /* Failed to get EDID, what about VBT? */ 1073 if (dev_priv->vbt.lfp_lvds_vbt_mode) { 1074 DRM_DEBUG_KMS("using mode from VBT: "); 1075 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); 1076 1077 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); 1078 if (fixed_mode) { 1079 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1080 connector->display_info.width_mm = fixed_mode->width_mm; 1081 connector->display_info.height_mm = fixed_mode->height_mm; 1082 goto out; 1083 } 1084 } 1085 1086 /* 1087 * If we didn't get EDID, try checking if the panel is already turned 1088 * on. If so, assume that whatever is currently programmed is the 1089 * correct mode. 1090 */ 1091 1092 /* Ironlake: FIXME if still fail, not try pipe mode now */ 1093 if (HAS_PCH_SPLIT(dev)) 1094 goto failed; 1095 1096 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; 1097 crtc = intel_get_crtc_for_pipe(dev, pipe); 1098 1099 if (crtc && (lvds & LVDS_PORT_EN)) { 1100 fixed_mode = intel_crtc_mode_get(dev, crtc); 1101 if (fixed_mode) { 1102 DRM_DEBUG_KMS("using current (BIOS) mode: "); 1103 drm_mode_debug_printmodeline(fixed_mode); 1104 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 1105 goto out; 1106 } 1107 } 1108 1109 /* If we still don't have a mode after all that, give up. */ 1110 if (!fixed_mode) 1111 goto failed; 1112 1113 out: 1114 mutex_unlock(&dev->mode_config.mutex); 1115 1116 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 1117 intel_panel_setup_backlight(connector, INVALID_PIPE); 1118 1119 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); 1120 DRM_DEBUG_KMS("detected %s-link lvds configuration\n", 1121 lvds_encoder->is_dual_link ? "dual" : "single"); 1122 1123 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; 1124 1125 #if 0 1126 lvds_connector->lid_notifier.notifier_call = intel_lid_notify; 1127 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { 1128 DRM_DEBUG_KMS("lid notifier registration failed\n"); 1129 lvds_connector->lid_notifier.notifier_call = NULL; 1130 } 1131 drm_connector_register(connector); 1132 #endif 1133 1134 return; 1135 1136 failed: 1137 mutex_unlock(&dev->mode_config.mutex); 1138 1139 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1140 drm_connector_cleanup(connector); 1141 drm_encoder_cleanup(encoder); 1142 kfree(lvds_encoder); 1143 kfree(lvds_connector); 1144 return; 1145 } 1146