1 /* 2 * Copyright (c) 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23 #include "intel_mocs.h" 24 #include "intel_lrc.h" 25 #include "intel_ringbuffer.h" 26 27 /* structures required */ 28 struct drm_i915_mocs_entry { 29 u32 control_value; 30 u16 l3cc_value; 31 }; 32 33 struct drm_i915_mocs_table { 34 u32 size; 35 const struct drm_i915_mocs_entry *table; 36 }; 37 38 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ 39 #define LE_CACHEABILITY(value) ((value) << 0) 40 #define LE_TGT_CACHE(value) ((value) << 2) 41 #define LE_LRUM(value) ((value) << 4) 42 #define LE_AOM(value) ((value) << 6) 43 #define LE_RSC(value) ((value) << 7) 44 #define LE_SCC(value) ((value) << 8) 45 #define LE_PFM(value) ((value) << 11) 46 #define LE_SCF(value) ((value) << 14) 47 48 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ 49 #define L3_ESC(value) ((value) << 0) 50 #define L3_SCC(value) ((value) << 1) 51 #define L3_CACHEABILITY(value) ((value) << 4) 52 53 /* Helper defines */ 54 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */ 55 56 /* (e)LLC caching options */ 57 #define LE_PAGETABLE 0 58 #define LE_UC 1 59 #define LE_WT 2 60 #define LE_WB 3 61 62 /* L3 caching options */ 63 #define L3_DIRECT 0 64 #define L3_UC 1 65 #define L3_RESERVED 2 66 #define L3_WB 3 67 68 /* Target cache */ 69 #define LE_TC_PAGETABLE 0 70 #define LE_TC_LLC 1 71 #define LE_TC_LLC_ELLC 2 72 #define LE_TC_LLC_ELLC_ALT 3 73 74 /* 75 * MOCS tables 76 * 77 * These are the MOCS tables that are programmed across all the rings. 78 * The control value is programmed to all the rings that support the 79 * MOCS registers. While the l3cc_values are only programmed to the 80 * LNCFCMOCS0 - LNCFCMOCS32 registers. 81 * 82 * These tables are intended to be kept reasonably consistent across 83 * platforms. However some of the fields are not applicable to all of 84 * them. 85 * 86 * Entries not part of the following tables are undefined as far as 87 * userspace is concerned and shouldn't be relied upon. For the time 88 * being they will be implicitly initialized to the strictest caching 89 * configuration (uncached) to guarantee forwards compatibility with 90 * userspace programs written against more recent kernels providing 91 * additional MOCS entries. 92 * 93 * NOTE: These tables MUST start with being uncached and the length 94 * MUST be less than 63 as the last two registers are reserved 95 * by the hardware. These tables are part of the kernel ABI and 96 * may only be updated incrementally by adding entries at the 97 * end. 98 */ 99 static const struct drm_i915_mocs_entry skylake_mocs_table[] = { 100 [I915_MOCS_UNCACHED] = { 101 /* 0x00000009 */ 102 .control_value = LE_CACHEABILITY(LE_UC) | 103 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 104 LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 105 LE_PFM(0) | LE_SCF(0), 106 107 /* 0x0010 */ 108 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), 109 }, 110 [I915_MOCS_PTE] = { 111 /* 0x00000038 */ 112 .control_value = LE_CACHEABILITY(LE_PAGETABLE) | 113 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 114 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 115 LE_PFM(0) | LE_SCF(0), 116 /* 0x0030 */ 117 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), 118 }, 119 [I915_MOCS_CACHED] = { 120 /* 0x0000003b */ 121 .control_value = LE_CACHEABILITY(LE_WB) | 122 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 123 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 124 LE_PFM(0) | LE_SCF(0), 125 /* 0x0030 */ 126 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), 127 }, 128 }; 129 130 /* NOTE: the LE_TGT_CACHE is not used on Broxton */ 131 static const struct drm_i915_mocs_entry broxton_mocs_table[] = { 132 [I915_MOCS_UNCACHED] = { 133 /* 0x00000009 */ 134 .control_value = LE_CACHEABILITY(LE_UC) | 135 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 136 LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 137 LE_PFM(0) | LE_SCF(0), 138 139 /* 0x0010 */ 140 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), 141 }, 142 [I915_MOCS_PTE] = { 143 /* 0x00000038 */ 144 .control_value = LE_CACHEABILITY(LE_PAGETABLE) | 145 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 146 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 147 LE_PFM(0) | LE_SCF(0), 148 149 /* 0x0030 */ 150 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), 151 }, 152 [I915_MOCS_CACHED] = { 153 /* 0x00000039 */ 154 .control_value = LE_CACHEABILITY(LE_UC) | 155 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 156 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 157 LE_PFM(0) | LE_SCF(0), 158 159 /* 0x0030 */ 160 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), 161 }, 162 }; 163 164 /** 165 * get_mocs_settings() 166 * @dev_priv: i915 device. 167 * @table: Output table that will be made to point at appropriate 168 * MOCS values for the device. 169 * 170 * This function will return the values of the MOCS table that needs to 171 * be programmed for the platform. It will return the values that need 172 * to be programmed and if they need to be programmed. 173 * 174 * Return: true if there are applicable MOCS settings for the device. 175 */ 176 static bool get_mocs_settings(struct drm_i915_private *dev_priv, 177 struct drm_i915_mocs_table *table) 178 { 179 bool result = false; 180 181 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 182 table->size = ARRAY_SIZE(skylake_mocs_table); 183 table->table = skylake_mocs_table; 184 result = true; 185 } else if (IS_BROXTON(dev_priv)) { 186 table->size = ARRAY_SIZE(broxton_mocs_table); 187 table->table = broxton_mocs_table; 188 result = true; 189 } else { 190 WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9, 191 "Platform that should have a MOCS table does not.\n"); 192 } 193 194 /* WaDisableSkipCaching:skl,bxt,kbl */ 195 if (IS_GEN9(dev_priv)) { 196 int i; 197 198 for (i = 0; i < table->size; i++) 199 if (WARN_ON(table->table[i].l3cc_value & 200 (L3_ESC(1) | L3_SCC(0x7)))) 201 return false; 202 } 203 204 return result; 205 } 206 207 static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index) 208 { 209 switch (engine_id) { 210 case RCS: 211 return GEN9_GFX_MOCS(index); 212 case VCS: 213 return GEN9_MFX0_MOCS(index); 214 case BCS: 215 return GEN9_BLT_MOCS(index); 216 case VECS: 217 return GEN9_VEBOX_MOCS(index); 218 case VCS2: 219 return GEN9_MFX1_MOCS(index); 220 default: 221 MISSING_CASE(engine_id); 222 return INVALID_MMIO_REG; 223 } 224 } 225 226 /** 227 * intel_mocs_init_engine() - emit the mocs control table 228 * @engine: The engine for whom to emit the registers. 229 * 230 * This function simply emits a MI_LOAD_REGISTER_IMM command for the 231 * given table starting at the given address. 232 * 233 * Return: 0 on success, otherwise the error status. 234 */ 235 int intel_mocs_init_engine(struct intel_engine_cs *engine) 236 { 237 struct drm_i915_private *dev_priv = engine->i915; 238 struct drm_i915_mocs_table table; 239 unsigned int index; 240 241 if (!get_mocs_settings(dev_priv, &table)) 242 return 0; 243 244 if (WARN_ON(table.size > GEN9_NUM_MOCS_ENTRIES)) 245 return -ENODEV; 246 247 for (index = 0; index < table.size; index++) 248 I915_WRITE(mocs_register(engine->id, index), 249 table.table[index].control_value); 250 251 /* 252 * Ok, now set the unused entries to uncached. These entries 253 * are officially undefined and no contract for the contents 254 * and settings is given for these entries. 255 * 256 * Entry 0 in the table is uncached - so we are just writing 257 * that value to all the used entries. 258 */ 259 for (; index < GEN9_NUM_MOCS_ENTRIES; index++) 260 I915_WRITE(mocs_register(engine->id, index), 261 table.table[0].control_value); 262 263 return 0; 264 } 265 266 /** 267 * emit_mocs_control_table() - emit the mocs control table 268 * @req: Request to set up the MOCS table for. 269 * @table: The values to program into the control regs. 270 * 271 * This function simply emits a MI_LOAD_REGISTER_IMM command for the 272 * given table starting at the given address. 273 * 274 * Return: 0 on success, otherwise the error status. 275 */ 276 static int emit_mocs_control_table(struct drm_i915_gem_request *req, 277 const struct drm_i915_mocs_table *table) 278 { 279 struct intel_ring *ring = req->ring; 280 enum intel_engine_id engine = req->engine->id; 281 unsigned int index; 282 int ret; 283 284 if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES)) 285 return -ENODEV; 286 287 ret = intel_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES); 288 if (ret) 289 return ret; 290 291 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES)); 292 293 for (index = 0; index < table->size; index++) { 294 intel_ring_emit_reg(ring, mocs_register(engine, index)); 295 intel_ring_emit(ring, table->table[index].control_value); 296 } 297 298 /* 299 * Ok, now set the unused entries to uncached. These entries 300 * are officially undefined and no contract for the contents 301 * and settings is given for these entries. 302 * 303 * Entry 0 in the table is uncached - so we are just writing 304 * that value to all the used entries. 305 */ 306 for (; index < GEN9_NUM_MOCS_ENTRIES; index++) { 307 intel_ring_emit_reg(ring, mocs_register(engine, index)); 308 intel_ring_emit(ring, table->table[0].control_value); 309 } 310 311 intel_ring_emit(ring, MI_NOOP); 312 intel_ring_advance(ring); 313 314 return 0; 315 } 316 317 static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table, 318 u16 low, 319 u16 high) 320 { 321 return table->table[low].l3cc_value | 322 table->table[high].l3cc_value << 16; 323 } 324 325 /** 326 * emit_mocs_l3cc_table() - emit the mocs control table 327 * @req: Request to set up the MOCS table for. 328 * @table: The values to program into the control regs. 329 * 330 * This function simply emits a MI_LOAD_REGISTER_IMM command for the 331 * given table starting at the given address. This register set is 332 * programmed in pairs. 333 * 334 * Return: 0 on success, otherwise the error status. 335 */ 336 static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req, 337 const struct drm_i915_mocs_table *table) 338 { 339 struct intel_ring *ring = req->ring; 340 unsigned int i; 341 int ret; 342 343 if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES)) 344 return -ENODEV; 345 346 ret = intel_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES); 347 if (ret) 348 return ret; 349 350 intel_ring_emit(ring, 351 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2)); 352 353 for (i = 0; i < table->size/2; i++) { 354 intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i)); 355 intel_ring_emit(ring, l3cc_combine(table, 2*i, 2*i+1)); 356 } 357 358 if (table->size & 0x01) { 359 /* Odd table size - 1 left over */ 360 intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i)); 361 intel_ring_emit(ring, l3cc_combine(table, 2*i, 0)); 362 i++; 363 } 364 365 /* 366 * Now set the rest of the table to uncached - use entry 0 as 367 * this will be uncached. Leave the last pair uninitialised as 368 * they are reserved by the hardware. 369 */ 370 for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) { 371 intel_ring_emit_reg(ring, GEN9_LNCFCMOCS(i)); 372 intel_ring_emit(ring, l3cc_combine(table, 0, 0)); 373 } 374 375 intel_ring_emit(ring, MI_NOOP); 376 intel_ring_advance(ring); 377 378 return 0; 379 } 380 381 /** 382 * intel_mocs_init_l3cc_table() - program the mocs control table 383 * @dev: The the device to be programmed. 384 * 385 * This function simply programs the mocs registers for the given table 386 * starting at the given address. This register set is programmed in pairs. 387 * 388 * These registers may get programmed more than once, it is simpler to 389 * re-program 32 registers than maintain the state of when they were programmed. 390 * We are always reprogramming with the same values and this only on context 391 * start. 392 * 393 * Return: Nothing. 394 */ 395 void intel_mocs_init_l3cc_table(struct drm_device *dev) 396 { 397 struct drm_i915_private *dev_priv = to_i915(dev); 398 struct drm_i915_mocs_table table; 399 unsigned int i; 400 401 if (!get_mocs_settings(dev_priv, &table)) 402 return; 403 404 for (i = 0; i < table.size/2; i++) 405 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 2*i+1)); 406 407 /* Odd table size - 1 left over */ 408 if (table.size & 0x01) { 409 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 0)); 410 i++; 411 } 412 413 /* 414 * Now set the rest of the table to uncached - use entry 0 as 415 * this will be uncached. Leave the last pair as initialised as 416 * they are reserved by the hardware. 417 */ 418 for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++) 419 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0)); 420 } 421 422 /** 423 * intel_rcs_context_init_mocs() - program the MOCS register. 424 * @req: Request to set up the MOCS tables for. 425 * 426 * This function will emit a batch buffer with the values required for 427 * programming the MOCS register values for all the currently supported 428 * rings. 429 * 430 * These registers are partially stored in the RCS context, so they are 431 * emitted at the same time so that when a context is created these registers 432 * are set up. These registers have to be emitted into the start of the 433 * context as setting the ELSP will re-init some of these registers back 434 * to the hw values. 435 * 436 * Return: 0 on success, otherwise the error status. 437 */ 438 int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req) 439 { 440 struct drm_i915_mocs_table t; 441 int ret; 442 443 if (get_mocs_settings(req->i915, &t)) { 444 /* Program the RCS control registers */ 445 ret = emit_mocs_control_table(req, &t); 446 if (ret) 447 return ret; 448 449 /* Now program the l3cc registers */ 450 ret = emit_mocs_l3cc_table(req, &t); 451 if (ret) 452 return ret; 453 } 454 455 return 0; 456 } 457