1 /* 2 * Copyright (c) 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: * 10 * The above copyright notice and this permission notice (including the next 11 * paragraph) shall be included in all copies or substantial portions of the 12 * Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23 #include "intel_mocs.h" 24 #include "intel_lrc.h" 25 #include "intel_ringbuffer.h" 26 27 /* structures required */ 28 struct drm_i915_mocs_entry { 29 u32 control_value; 30 u16 l3cc_value; 31 }; 32 33 struct drm_i915_mocs_table { 34 u32 size; 35 const struct drm_i915_mocs_entry *table; 36 }; 37 38 /* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */ 39 #define LE_CACHEABILITY(value) ((value) << 0) 40 #define LE_TGT_CACHE(value) ((value) << 2) 41 #define LE_LRUM(value) ((value) << 4) 42 #define LE_AOM(value) ((value) << 6) 43 #define LE_RSC(value) ((value) << 7) 44 #define LE_SCC(value) ((value) << 8) 45 #define LE_PFM(value) ((value) << 11) 46 #define LE_SCF(value) ((value) << 14) 47 48 /* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */ 49 #define L3_ESC(value) ((value) << 0) 50 #define L3_SCC(value) ((value) << 1) 51 #define L3_CACHEABILITY(value) ((value) << 4) 52 53 /* Helper defines */ 54 #define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */ 55 56 /* (e)LLC caching options */ 57 #define LE_PAGETABLE 0 58 #define LE_UC 1 59 #define LE_WT 2 60 #define LE_WB 3 61 62 /* L3 caching options */ 63 #define L3_DIRECT 0 64 #define L3_UC 1 65 #define L3_RESERVED 2 66 #define L3_WB 3 67 68 /* Target cache */ 69 #define LE_TC_PAGETABLE 0 70 #define LE_TC_LLC 1 71 #define LE_TC_LLC_ELLC 2 72 #define LE_TC_LLC_ELLC_ALT 3 73 74 /* 75 * MOCS tables 76 * 77 * These are the MOCS tables that are programmed across all the rings. 78 * The control value is programmed to all the rings that support the 79 * MOCS registers. While the l3cc_values are only programmed to the 80 * LNCFCMOCS0 - LNCFCMOCS32 registers. 81 * 82 * These tables are intended to be kept reasonably consistent across 83 * platforms. However some of the fields are not applicable to all of 84 * them. 85 * 86 * Entries not part of the following tables are undefined as far as 87 * userspace is concerned and shouldn't be relied upon. For the time 88 * being they will be implicitly initialized to the strictest caching 89 * configuration (uncached) to guarantee forwards compatibility with 90 * userspace programs written against more recent kernels providing 91 * additional MOCS entries. 92 * 93 * NOTE: These tables MUST start with being uncached and the length 94 * MUST be less than 63 as the last two registers are reserved 95 * by the hardware. These tables are part of the kernel ABI and 96 * may only be updated incrementally by adding entries at the 97 * end. 98 */ 99 static const struct drm_i915_mocs_entry skylake_mocs_table[] = { 100 { /* 0x00000009 */ 101 .control_value = LE_CACHEABILITY(LE_UC) | 102 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 103 LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 104 LE_PFM(0) | LE_SCF(0), 105 106 /* 0x0010 */ 107 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), 108 }, 109 { 110 /* 0x00000038 */ 111 .control_value = LE_CACHEABILITY(LE_PAGETABLE) | 112 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 113 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 114 LE_PFM(0) | LE_SCF(0), 115 /* 0x0030 */ 116 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), 117 }, 118 { 119 /* 0x0000003b */ 120 .control_value = LE_CACHEABILITY(LE_WB) | 121 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 122 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 123 LE_PFM(0) | LE_SCF(0), 124 /* 0x0030 */ 125 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), 126 }, 127 }; 128 129 /* NOTE: the LE_TGT_CACHE is not used on Broxton */ 130 static const struct drm_i915_mocs_entry broxton_mocs_table[] = { 131 { 132 /* 0x00000009 */ 133 .control_value = LE_CACHEABILITY(LE_UC) | 134 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 135 LE_LRUM(0) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 136 LE_PFM(0) | LE_SCF(0), 137 138 /* 0x0010 */ 139 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_UC), 140 }, 141 { 142 /* 0x00000038 */ 143 .control_value = LE_CACHEABILITY(LE_PAGETABLE) | 144 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 145 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 146 LE_PFM(0) | LE_SCF(0), 147 148 /* 0x0030 */ 149 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), 150 }, 151 { 152 /* 0x00000039 */ 153 .control_value = LE_CACHEABILITY(LE_UC) | 154 LE_TGT_CACHE(LE_TC_LLC_ELLC) | 155 LE_LRUM(3) | LE_AOM(0) | LE_RSC(0) | LE_SCC(0) | 156 LE_PFM(0) | LE_SCF(0), 157 158 /* 0x0030 */ 159 .l3cc_value = L3_ESC(0) | L3_SCC(0) | L3_CACHEABILITY(L3_WB), 160 }, 161 }; 162 163 /** 164 * get_mocs_settings() 165 * @dev_priv: i915 device. 166 * @table: Output table that will be made to point at appropriate 167 * MOCS values for the device. 168 * 169 * This function will return the values of the MOCS table that needs to 170 * be programmed for the platform. It will return the values that need 171 * to be programmed and if they need to be programmed. 172 * 173 * Return: true if there are applicable MOCS settings for the device. 174 */ 175 static bool get_mocs_settings(struct drm_i915_private *dev_priv, 176 struct drm_i915_mocs_table *table) 177 { 178 bool result = false; 179 180 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 181 table->size = ARRAY_SIZE(skylake_mocs_table); 182 table->table = skylake_mocs_table; 183 result = true; 184 } else if (IS_BROXTON(dev_priv)) { 185 table->size = ARRAY_SIZE(broxton_mocs_table); 186 table->table = broxton_mocs_table; 187 result = true; 188 } else { 189 WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9, 190 "Platform that should have a MOCS table does not.\n"); 191 } 192 193 /* WaDisableSkipCaching:skl,bxt,kbl */ 194 if (IS_GEN9(dev_priv)) { 195 int i; 196 197 for (i = 0; i < table->size; i++) 198 if (WARN_ON(table->table[i].l3cc_value & 199 (L3_ESC(1) | L3_SCC(0x7)))) 200 return false; 201 } 202 203 return result; 204 } 205 206 static i915_reg_t mocs_register(enum intel_engine_id ring, int index) 207 { 208 switch (ring) { 209 case RCS: 210 return GEN9_GFX_MOCS(index); 211 case VCS: 212 return GEN9_MFX0_MOCS(index); 213 case BCS: 214 return GEN9_BLT_MOCS(index); 215 case VECS: 216 return GEN9_VEBOX_MOCS(index); 217 case VCS2: 218 return GEN9_MFX1_MOCS(index); 219 default: 220 MISSING_CASE(ring); 221 return INVALID_MMIO_REG; 222 } 223 } 224 225 /** 226 * intel_mocs_init_engine() - emit the mocs control table 227 * @engine: The engine for whom to emit the registers. 228 * 229 * This function simply emits a MI_LOAD_REGISTER_IMM command for the 230 * given table starting at the given address. 231 * 232 * Return: 0 on success, otherwise the error status. 233 */ 234 int intel_mocs_init_engine(struct intel_engine_cs *engine) 235 { 236 struct drm_i915_private *dev_priv = engine->i915; 237 struct drm_i915_mocs_table table; 238 unsigned int index; 239 240 if (!get_mocs_settings(dev_priv, &table)) 241 return 0; 242 243 if (WARN_ON(table.size > GEN9_NUM_MOCS_ENTRIES)) 244 return -ENODEV; 245 246 for (index = 0; index < table.size; index++) 247 I915_WRITE(mocs_register(engine->id, index), 248 table.table[index].control_value); 249 250 /* 251 * Ok, now set the unused entries to uncached. These entries 252 * are officially undefined and no contract for the contents 253 * and settings is given for these entries. 254 * 255 * Entry 0 in the table is uncached - so we are just writing 256 * that value to all the used entries. 257 */ 258 for (; index < GEN9_NUM_MOCS_ENTRIES; index++) 259 I915_WRITE(mocs_register(engine->id, index), 260 table.table[0].control_value); 261 262 return 0; 263 } 264 265 /** 266 * emit_mocs_control_table() - emit the mocs control table 267 * @req: Request to set up the MOCS table for. 268 * @table: The values to program into the control regs. 269 * 270 * This function simply emits a MI_LOAD_REGISTER_IMM command for the 271 * given table starting at the given address. 272 * 273 * Return: 0 on success, otherwise the error status. 274 */ 275 static int emit_mocs_control_table(struct drm_i915_gem_request *req, 276 const struct drm_i915_mocs_table *table) 277 { 278 struct intel_ringbuffer *ringbuf = req->ringbuf; 279 enum intel_engine_id engine = req->engine->id; 280 unsigned int index; 281 int ret; 282 283 if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES)) 284 return -ENODEV; 285 286 ret = intel_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES); 287 if (ret) 288 return ret; 289 290 intel_logical_ring_emit(ringbuf, 291 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES)); 292 293 for (index = 0; index < table->size; index++) { 294 intel_logical_ring_emit_reg(ringbuf, 295 mocs_register(engine, index)); 296 intel_logical_ring_emit(ringbuf, 297 table->table[index].control_value); 298 } 299 300 /* 301 * Ok, now set the unused entries to uncached. These entries 302 * are officially undefined and no contract for the contents 303 * and settings is given for these entries. 304 * 305 * Entry 0 in the table is uncached - so we are just writing 306 * that value to all the used entries. 307 */ 308 for (; index < GEN9_NUM_MOCS_ENTRIES; index++) { 309 intel_logical_ring_emit_reg(ringbuf, 310 mocs_register(engine, index)); 311 intel_logical_ring_emit(ringbuf, 312 table->table[0].control_value); 313 } 314 315 intel_logical_ring_emit(ringbuf, MI_NOOP); 316 intel_logical_ring_advance(ringbuf); 317 318 return 0; 319 } 320 321 static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table, 322 u16 low, 323 u16 high) 324 { 325 return table->table[low].l3cc_value | 326 table->table[high].l3cc_value << 16; 327 } 328 329 /** 330 * emit_mocs_l3cc_table() - emit the mocs control table 331 * @req: Request to set up the MOCS table for. 332 * @table: The values to program into the control regs. 333 * 334 * This function simply emits a MI_LOAD_REGISTER_IMM command for the 335 * given table starting at the given address. This register set is 336 * programmed in pairs. 337 * 338 * Return: 0 on success, otherwise the error status. 339 */ 340 static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req, 341 const struct drm_i915_mocs_table *table) 342 { 343 struct intel_ringbuffer *ringbuf = req->ringbuf; 344 unsigned int i; 345 int ret; 346 347 if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES)) 348 return -ENODEV; 349 350 ret = intel_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES); 351 if (ret) 352 return ret; 353 354 intel_logical_ring_emit(ringbuf, 355 MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2)); 356 357 for (i = 0; i < table->size/2; i++) { 358 intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i)); 359 intel_logical_ring_emit(ringbuf, 360 l3cc_combine(table, 2*i, 2*i+1)); 361 } 362 363 if (table->size & 0x01) { 364 /* Odd table size - 1 left over */ 365 intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i)); 366 intel_logical_ring_emit(ringbuf, l3cc_combine(table, 2*i, 0)); 367 i++; 368 } 369 370 /* 371 * Now set the rest of the table to uncached - use entry 0 as 372 * this will be uncached. Leave the last pair uninitialised as 373 * they are reserved by the hardware. 374 */ 375 for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) { 376 intel_logical_ring_emit_reg(ringbuf, GEN9_LNCFCMOCS(i)); 377 intel_logical_ring_emit(ringbuf, l3cc_combine(table, 0, 0)); 378 } 379 380 intel_logical_ring_emit(ringbuf, MI_NOOP); 381 intel_logical_ring_advance(ringbuf); 382 383 return 0; 384 } 385 386 /** 387 * intel_mocs_init_l3cc_table() - program the mocs control table 388 * @dev: The the device to be programmed. 389 * 390 * This function simply programs the mocs registers for the given table 391 * starting at the given address. This register set is programmed in pairs. 392 * 393 * These registers may get programmed more than once, it is simpler to 394 * re-program 32 registers than maintain the state of when they were programmed. 395 * We are always reprogramming with the same values and this only on context 396 * start. 397 * 398 * Return: Nothing. 399 */ 400 void intel_mocs_init_l3cc_table(struct drm_device *dev) 401 { 402 struct drm_i915_private *dev_priv = to_i915(dev); 403 struct drm_i915_mocs_table table; 404 unsigned int i; 405 406 if (!get_mocs_settings(dev_priv, &table)) 407 return; 408 409 for (i = 0; i < table.size/2; i++) 410 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 2*i+1)); 411 412 /* Odd table size - 1 left over */ 413 if (table.size & 0x01) { 414 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 2*i, 0)); 415 i++; 416 } 417 418 /* 419 * Now set the rest of the table to uncached - use entry 0 as 420 * this will be uncached. Leave the last pair as initialised as 421 * they are reserved by the hardware. 422 */ 423 for (; i < (GEN9_NUM_MOCS_ENTRIES / 2); i++) 424 I915_WRITE(GEN9_LNCFCMOCS(i), l3cc_combine(&table, 0, 0)); 425 } 426 427 /** 428 * intel_rcs_context_init_mocs() - program the MOCS register. 429 * @req: Request to set up the MOCS tables for. 430 * 431 * This function will emit a batch buffer with the values required for 432 * programming the MOCS register values for all the currently supported 433 * rings. 434 * 435 * These registers are partially stored in the RCS context, so they are 436 * emitted at the same time so that when a context is created these registers 437 * are set up. These registers have to be emitted into the start of the 438 * context as setting the ELSP will re-init some of these registers back 439 * to the hw values. 440 * 441 * Return: 0 on success, otherwise the error status. 442 */ 443 int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req) 444 { 445 struct drm_i915_mocs_table t; 446 int ret; 447 448 if (get_mocs_settings(req->i915, &t)) { 449 /* Program the RCS control registers */ 450 ret = emit_mocs_control_table(req, &t); 451 if (ret) 452 return ret; 453 454 /* Now program the l3cc registers */ 455 ret = emit_mocs_l3cc_table(req, &t); 456 if (ret) 457 return ret; 458 } 459 460 return 0; 461 } 462