1 /* 2 * Copyright © 2009 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Daniel Vetter <daniel@ffwll.ch> 25 * 26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 27 */ 28 #include <drm/drmP.h> 29 #include <drm/i915_drm.h> 30 #include "i915_drv.h" 31 #include "i915_reg.h" 32 #include "intel_drv.h" 33 #include "intel_frontbuffer.h" 34 35 /* Limits for overlay size. According to intel doc, the real limits are: 36 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 37 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 38 * the mininum of both. */ 39 #define IMAGE_MAX_WIDTH 2048 40 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 41 /* on 830 and 845 these large limits result in the card hanging */ 42 #define IMAGE_MAX_WIDTH_LEGACY 1024 43 #define IMAGE_MAX_HEIGHT_LEGACY 1088 44 45 /* overlay register definitions */ 46 /* OCMD register */ 47 #define OCMD_TILED_SURFACE (0x1<<19) 48 #define OCMD_MIRROR_MASK (0x3<<17) 49 #define OCMD_MIRROR_MODE (0x3<<17) 50 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 51 #define OCMD_MIRROR_VERTICAL (0x2<<17) 52 #define OCMD_MIRROR_BOTH (0x3<<17) 53 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 54 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 55 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 56 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 58 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 59 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 60 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 61 #define OCMD_YUV_422_PACKED (0x8<<10) 62 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 63 #define OCMD_YUV_420_PLANAR (0xc<<10) 64 #define OCMD_YUV_422_PLANAR (0xd<<10) 65 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 66 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 67 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 68 #define OCMD_BUF_TYPE_MASK (0x1<<5) 69 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 70 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 71 #define OCMD_TEST_MODE (0x1<<4) 72 #define OCMD_BUFFER_SELECT (0x3<<2) 73 #define OCMD_BUFFER0 (0x0<<2) 74 #define OCMD_BUFFER1 (0x1<<2) 75 #define OCMD_FIELD_SELECT (0x1<<2) 76 #define OCMD_FIELD0 (0x0<<1) 77 #define OCMD_FIELD1 (0x1<<1) 78 #define OCMD_ENABLE (0x1<<0) 79 80 /* OCONFIG register */ 81 #define OCONF_PIPE_MASK (0x1<<18) 82 #define OCONF_PIPE_A (0x0<<18) 83 #define OCONF_PIPE_B (0x1<<18) 84 #define OCONF_GAMMA2_ENABLE (0x1<<16) 85 #define OCONF_CSC_MODE_BT601 (0x0<<5) 86 #define OCONF_CSC_MODE_BT709 (0x1<<5) 87 #define OCONF_CSC_BYPASS (0x1<<4) 88 #define OCONF_CC_OUT_8BIT (0x1<<3) 89 #define OCONF_TEST_MODE (0x1<<2) 90 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 91 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 92 93 /* DCLRKM (dst-key) register */ 94 #define DST_KEY_ENABLE (0x1<<31) 95 #define CLK_RGB24_MASK 0x0 96 #define CLK_RGB16_MASK 0x070307 97 #define CLK_RGB15_MASK 0x070707 98 #define CLK_RGB8I_MASK 0xffffff 99 100 #define RGB16_TO_COLORKEY(c) \ 101 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 102 #define RGB15_TO_COLORKEY(c) \ 103 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 104 105 /* overlay flip addr flag */ 106 #define OFC_UPDATE 0x1 107 108 /* polyphase filter coefficients */ 109 #define N_HORIZ_Y_TAPS 5 110 #define N_VERT_Y_TAPS 3 111 #define N_HORIZ_UV_TAPS 3 112 #define N_VERT_UV_TAPS 3 113 #define N_PHASES 17 114 #define MAX_TAPS 5 115 116 /* memory bufferd overlay registers */ 117 struct overlay_registers { 118 u32 OBUF_0Y; 119 u32 OBUF_1Y; 120 u32 OBUF_0U; 121 u32 OBUF_0V; 122 u32 OBUF_1U; 123 u32 OBUF_1V; 124 u32 OSTRIDE; 125 u32 YRGB_VPH; 126 u32 UV_VPH; 127 u32 HORZ_PH; 128 u32 INIT_PHS; 129 u32 DWINPOS; 130 u32 DWINSZ; 131 u32 SWIDTH; 132 u32 SWIDTHSW; 133 u32 SHEIGHT; 134 u32 YRGBSCALE; 135 u32 UVSCALE; 136 u32 OCLRC0; 137 u32 OCLRC1; 138 u32 DCLRKV; 139 u32 DCLRKM; 140 u32 SCLRKVH; 141 u32 SCLRKVL; 142 u32 SCLRKEN; 143 u32 OCONFIG; 144 u32 OCMD; 145 u32 RESERVED1; /* 0x6C */ 146 u32 OSTART_0Y; 147 u32 OSTART_1Y; 148 u32 OSTART_0U; 149 u32 OSTART_0V; 150 u32 OSTART_1U; 151 u32 OSTART_1V; 152 u32 OTILEOFF_0Y; 153 u32 OTILEOFF_1Y; 154 u32 OTILEOFF_0U; 155 u32 OTILEOFF_0V; 156 u32 OTILEOFF_1U; 157 u32 OTILEOFF_1V; 158 u32 FASTHSCALE; /* 0xA0 */ 159 u32 UVSCALEV; /* 0xA4 */ 160 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 161 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 162 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 163 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 164 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 165 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 166 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 167 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 168 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 169 }; 170 171 struct intel_overlay { 172 struct drm_i915_private *i915; 173 struct intel_crtc *crtc; 174 struct i915_vma *vma; 175 struct i915_vma *old_vma; 176 bool active; 177 bool pfit_active; 178 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 179 u32 color_key:24; 180 u32 color_key_enabled:1; 181 u32 brightness, contrast, saturation; 182 u32 old_xscale, old_yscale; 183 /* register access */ 184 u32 flip_addr; 185 struct drm_i915_gem_object *reg_bo; 186 /* flip handling */ 187 struct i915_gem_active last_flip; 188 }; 189 190 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 191 bool enable) 192 { 193 struct pci_dev *pdev = dev_priv->drm.pdev; 194 u8 val; 195 196 /* WA_OVERLAY_CLKGATE:alm */ 197 if (enable) 198 I915_WRITE(DSPCLK_GATE_D, 0); 199 else 200 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 201 202 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 203 pci_bus_read_config_byte(pdev->bus, 204 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 205 if (enable) 206 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 207 else 208 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 209 #if 0 210 pci_bus_write_config_byte(pdev->bus, 211 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 212 #endif 213 } 214 215 static struct overlay_registers __iomem * 216 intel_overlay_map_regs(struct intel_overlay *overlay) 217 { 218 struct drm_i915_private *dev_priv = overlay->i915; 219 struct overlay_registers __iomem *regs; 220 221 if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) 222 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr; 223 else 224 regs = io_mapping_map_wc(&dev_priv->ggtt.mappable, 225 overlay->flip_addr, 226 PAGE_SIZE); 227 228 return regs; 229 } 230 231 static void intel_overlay_unmap_regs(struct intel_overlay *overlay, 232 struct overlay_registers __iomem *regs) 233 { 234 if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915)) 235 io_mapping_unmap(regs); 236 } 237 238 static void intel_overlay_submit_request(struct intel_overlay *overlay, 239 struct drm_i915_gem_request *req, 240 i915_gem_retire_fn retire) 241 { 242 GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip, 243 &overlay->i915->drm.struct_mutex)); 244 i915_gem_active_set_retire_fn(&overlay->last_flip, retire, 245 &overlay->i915->drm.struct_mutex); 246 i915_gem_active_set(&overlay->last_flip, req); 247 i915_add_request(req); 248 } 249 250 static int intel_overlay_do_wait_request(struct intel_overlay *overlay, 251 struct drm_i915_gem_request *req, 252 i915_gem_retire_fn retire) 253 { 254 intel_overlay_submit_request(overlay, req, retire); 255 return i915_gem_active_retire(&overlay->last_flip, 256 &overlay->i915->drm.struct_mutex); 257 } 258 259 static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay) 260 { 261 struct drm_i915_private *dev_priv = overlay->i915; 262 struct intel_engine_cs *engine = dev_priv->engine[RCS]; 263 264 return i915_gem_request_alloc(engine, dev_priv->kernel_context); 265 } 266 267 /* overlay needs to be disable in OCMD reg */ 268 static int intel_overlay_on(struct intel_overlay *overlay) 269 { 270 struct drm_i915_private *dev_priv = overlay->i915; 271 struct drm_i915_gem_request *req; 272 u32 *cs; 273 274 WARN_ON(overlay->active); 275 276 req = alloc_request(overlay); 277 if (IS_ERR(req)) 278 return PTR_ERR(req); 279 280 cs = intel_ring_begin(req, 4); 281 if (IS_ERR(cs)) { 282 i915_add_request(req); 283 return PTR_ERR(cs); 284 } 285 286 overlay->active = true; 287 288 if (IS_I830(dev_priv)) 289 i830_overlay_clock_gating(dev_priv, false); 290 291 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 292 *cs++ = overlay->flip_addr | OFC_UPDATE; 293 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 294 *cs++ = MI_NOOP; 295 intel_ring_advance(req, cs); 296 297 return intel_overlay_do_wait_request(overlay, req, NULL); 298 } 299 300 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 301 struct i915_vma *vma) 302 { 303 enum i915_pipe pipe = overlay->crtc->pipe; 304 305 WARN_ON(overlay->old_vma); 306 307 i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL, 308 vma ? vma->obj : NULL, 309 INTEL_FRONTBUFFER_OVERLAY(pipe)); 310 311 intel_frontbuffer_flip_prepare(overlay->i915, 312 INTEL_FRONTBUFFER_OVERLAY(pipe)); 313 314 overlay->old_vma = overlay->vma; 315 if (vma) 316 overlay->vma = i915_vma_get(vma); 317 else 318 overlay->vma = NULL; 319 } 320 321 /* overlay needs to be enabled in OCMD reg */ 322 static int intel_overlay_continue(struct intel_overlay *overlay, 323 struct i915_vma *vma, 324 bool load_polyphase_filter) 325 { 326 struct drm_i915_private *dev_priv = overlay->i915; 327 struct drm_i915_gem_request *req; 328 u32 flip_addr = overlay->flip_addr; 329 u32 tmp, *cs; 330 331 WARN_ON(!overlay->active); 332 333 if (load_polyphase_filter) 334 flip_addr |= OFC_UPDATE; 335 336 /* check for underruns */ 337 tmp = I915_READ(DOVSTA); 338 if (tmp & (1 << 17)) 339 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); 340 341 req = alloc_request(overlay); 342 if (IS_ERR(req)) 343 return PTR_ERR(req); 344 345 cs = intel_ring_begin(req, 2); 346 if (IS_ERR(cs)) { 347 i915_add_request(req); 348 return PTR_ERR(cs); 349 } 350 351 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 352 *cs++ = flip_addr; 353 intel_ring_advance(req, cs); 354 355 intel_overlay_flip_prepare(overlay, vma); 356 357 intel_overlay_submit_request(overlay, req, NULL); 358 359 return 0; 360 } 361 362 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 363 { 364 struct i915_vma *vma; 365 366 vma = fetch_and_zero(&overlay->old_vma); 367 if (WARN_ON(!vma)) 368 return; 369 370 intel_frontbuffer_flip_complete(overlay->i915, 371 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 372 373 i915_gem_object_unpin_from_display_plane(vma); 374 i915_vma_put(vma); 375 } 376 377 static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active, 378 struct drm_i915_gem_request *req) 379 { 380 struct intel_overlay *overlay = 381 container_of(active, typeof(*overlay), last_flip); 382 383 intel_overlay_release_old_vma(overlay); 384 } 385 386 static void intel_overlay_off_tail(struct i915_gem_active *active, 387 struct drm_i915_gem_request *req) 388 { 389 struct intel_overlay *overlay = 390 container_of(active, typeof(*overlay), last_flip); 391 struct drm_i915_private *dev_priv = overlay->i915; 392 393 intel_overlay_release_old_vma(overlay); 394 395 overlay->crtc->overlay = NULL; 396 overlay->crtc = NULL; 397 overlay->active = false; 398 399 if (IS_I830(dev_priv)) 400 i830_overlay_clock_gating(dev_priv, true); 401 } 402 403 /* overlay needs to be disabled in OCMD reg */ 404 static int intel_overlay_off(struct intel_overlay *overlay) 405 { 406 struct drm_i915_gem_request *req; 407 u32 *cs, flip_addr = overlay->flip_addr; 408 409 WARN_ON(!overlay->active); 410 411 /* According to intel docs the overlay hw may hang (when switching 412 * off) without loading the filter coeffs. It is however unclear whether 413 * this applies to the disabling of the overlay or to the switching off 414 * of the hw. Do it in both cases */ 415 flip_addr |= OFC_UPDATE; 416 417 req = alloc_request(overlay); 418 if (IS_ERR(req)) 419 return PTR_ERR(req); 420 421 cs = intel_ring_begin(req, 6); 422 if (IS_ERR(cs)) { 423 i915_add_request(req); 424 return PTR_ERR(cs); 425 } 426 427 /* wait for overlay to go idle */ 428 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 429 *cs++ = flip_addr; 430 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 431 432 /* turn overlay off */ 433 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 434 *cs++ = flip_addr; 435 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 436 437 intel_ring_advance(req, cs); 438 439 intel_overlay_flip_prepare(overlay, NULL); 440 441 return intel_overlay_do_wait_request(overlay, req, 442 intel_overlay_off_tail); 443 } 444 445 /* recover from an interruption due to a signal 446 * We have to be careful not to repeat work forever an make forward progess. */ 447 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 448 { 449 return i915_gem_active_retire(&overlay->last_flip, 450 &overlay->i915->drm.struct_mutex); 451 } 452 453 /* Wait for pending overlay flip and release old frame. 454 * Needs to be called before the overlay register are changed 455 * via intel_overlay_(un)map_regs 456 */ 457 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 458 { 459 struct drm_i915_private *dev_priv = overlay->i915; 460 u32 *cs; 461 int ret; 462 463 lockdep_assert_held(&dev_priv->drm.struct_mutex); 464 465 /* Only wait if there is actually an old frame to release to 466 * guarantee forward progress. 467 */ 468 if (!overlay->old_vma) 469 return 0; 470 471 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) { 472 /* synchronous slowpath */ 473 struct drm_i915_gem_request *req; 474 475 req = alloc_request(overlay); 476 if (IS_ERR(req)) 477 return PTR_ERR(req); 478 479 cs = intel_ring_begin(req, 2); 480 if (IS_ERR(cs)) { 481 i915_add_request(req); 482 return PTR_ERR(cs); 483 } 484 485 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 486 *cs++ = MI_NOOP; 487 intel_ring_advance(req, cs); 488 489 ret = intel_overlay_do_wait_request(overlay, req, 490 intel_overlay_release_old_vid_tail); 491 if (ret) 492 return ret; 493 } else 494 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL); 495 496 return 0; 497 } 498 499 void intel_overlay_reset(struct drm_i915_private *dev_priv) 500 { 501 struct intel_overlay *overlay = dev_priv->overlay; 502 503 if (!overlay) 504 return; 505 506 intel_overlay_release_old_vid(overlay); 507 508 overlay->old_xscale = 0; 509 overlay->old_yscale = 0; 510 overlay->crtc = NULL; 511 overlay->active = false; 512 } 513 514 struct put_image_params { 515 int format; 516 short dst_x; 517 short dst_y; 518 short dst_w; 519 short dst_h; 520 short src_w; 521 short src_scan_h; 522 short src_scan_w; 523 short src_h; 524 short stride_Y; 525 short stride_UV; 526 int offset_Y; 527 int offset_U; 528 int offset_V; 529 }; 530 531 static int packed_depth_bytes(u32 format) 532 { 533 switch (format & I915_OVERLAY_DEPTH_MASK) { 534 case I915_OVERLAY_YUV422: 535 return 4; 536 case I915_OVERLAY_YUV411: 537 /* return 6; not implemented */ 538 default: 539 return -EINVAL; 540 } 541 } 542 543 static int packed_width_bytes(u32 format, short width) 544 { 545 switch (format & I915_OVERLAY_DEPTH_MASK) { 546 case I915_OVERLAY_YUV422: 547 return width << 1; 548 default: 549 return -EINVAL; 550 } 551 } 552 553 static int uv_hsubsampling(u32 format) 554 { 555 switch (format & I915_OVERLAY_DEPTH_MASK) { 556 case I915_OVERLAY_YUV422: 557 case I915_OVERLAY_YUV420: 558 return 2; 559 case I915_OVERLAY_YUV411: 560 case I915_OVERLAY_YUV410: 561 return 4; 562 default: 563 return -EINVAL; 564 } 565 } 566 567 static int uv_vsubsampling(u32 format) 568 { 569 switch (format & I915_OVERLAY_DEPTH_MASK) { 570 case I915_OVERLAY_YUV420: 571 case I915_OVERLAY_YUV410: 572 return 2; 573 case I915_OVERLAY_YUV422: 574 case I915_OVERLAY_YUV411: 575 return 1; 576 default: 577 return -EINVAL; 578 } 579 } 580 581 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 582 { 583 u32 sw; 584 585 if (IS_GEN2(dev_priv)) 586 sw = ALIGN((offset & 31) + width, 32); 587 else 588 sw = ALIGN((offset & 63) + width, 64); 589 590 if (sw == 0) 591 return 0; 592 593 return (sw - 32) >> 3; 594 } 595 596 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 597 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 598 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 599 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 600 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 601 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 602 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 603 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 604 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 605 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 606 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 607 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 608 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 609 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 610 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 611 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 612 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 613 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 614 }; 615 616 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 617 [ 0] = { 0x3000, 0x1800, 0x1800, }, 618 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 619 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 620 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 621 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 622 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 623 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 624 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 625 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 626 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 627 [10] = { 0xb100, 0x1eb8, 0x3620, }, 628 [11] = { 0xb100, 0x1f18, 0x34a0, }, 629 [12] = { 0xb100, 0x1f68, 0x3360, }, 630 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 631 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 632 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 633 [16] = { 0x3000, 0x0800, 0x3000, }, 634 }; 635 636 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 637 { 638 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 639 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 640 sizeof(uv_static_hcoeffs)); 641 } 642 643 static bool update_scaling_factors(struct intel_overlay *overlay, 644 struct overlay_registers __iomem *regs, 645 struct put_image_params *params) 646 { 647 /* fixed point with a 12 bit shift */ 648 u32 xscale, yscale, xscale_UV, yscale_UV; 649 #define FP_SHIFT 12 650 #define FRACT_MASK 0xfff 651 bool scale_changed = false; 652 int uv_hscale = uv_hsubsampling(params->format); 653 int uv_vscale = uv_vsubsampling(params->format); 654 655 if (params->dst_w > 1) 656 xscale = ((params->src_scan_w - 1) << FP_SHIFT) 657 /(params->dst_w); 658 else 659 xscale = 1 << FP_SHIFT; 660 661 if (params->dst_h > 1) 662 yscale = ((params->src_scan_h - 1) << FP_SHIFT) 663 /(params->dst_h); 664 else 665 yscale = 1 << FP_SHIFT; 666 667 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 668 xscale_UV = xscale/uv_hscale; 669 yscale_UV = yscale/uv_vscale; 670 /* make the Y scale to UV scale ratio an exact multiply */ 671 xscale = xscale_UV * uv_hscale; 672 yscale = yscale_UV * uv_vscale; 673 /*} else { 674 xscale_UV = 0; 675 yscale_UV = 0; 676 }*/ 677 678 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 679 scale_changed = true; 680 overlay->old_xscale = xscale; 681 overlay->old_yscale = yscale; 682 683 iowrite32(((yscale & FRACT_MASK) << 20) | 684 ((xscale >> FP_SHIFT) << 16) | 685 ((xscale & FRACT_MASK) << 3), 686 ®s->YRGBSCALE); 687 688 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 689 ((xscale_UV >> FP_SHIFT) << 16) | 690 ((xscale_UV & FRACT_MASK) << 3), 691 ®s->UVSCALE); 692 693 iowrite32((((yscale >> FP_SHIFT) << 16) | 694 ((yscale_UV >> FP_SHIFT) << 0)), 695 ®s->UVSCALEV); 696 697 if (scale_changed) 698 update_polyphase_filter(regs); 699 700 return scale_changed; 701 } 702 703 static void update_colorkey(struct intel_overlay *overlay, 704 struct overlay_registers __iomem *regs) 705 { 706 const struct intel_plane_state *state = 707 to_intel_plane_state(overlay->crtc->base.primary->state); 708 u32 key = overlay->color_key; 709 u32 format = 0; 710 u32 flags = 0; 711 712 if (overlay->color_key_enabled) 713 flags |= DST_KEY_ENABLE; 714 715 if (state->base.visible) 716 format = state->base.fb->format->format; 717 718 switch (format) { 719 case DRM_FORMAT_C8: 720 key = 0; 721 flags |= CLK_RGB8I_MASK; 722 break; 723 case DRM_FORMAT_XRGB1555: 724 key = RGB15_TO_COLORKEY(key); 725 flags |= CLK_RGB15_MASK; 726 break; 727 case DRM_FORMAT_RGB565: 728 key = RGB16_TO_COLORKEY(key); 729 flags |= CLK_RGB16_MASK; 730 break; 731 default: 732 flags |= CLK_RGB24_MASK; 733 break; 734 } 735 736 iowrite32(key, ®s->DCLRKV); 737 iowrite32(flags, ®s->DCLRKM); 738 } 739 740 static u32 overlay_cmd_reg(struct put_image_params *params) 741 { 742 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 743 744 if (params->format & I915_OVERLAY_YUV_PLANAR) { 745 switch (params->format & I915_OVERLAY_DEPTH_MASK) { 746 case I915_OVERLAY_YUV422: 747 cmd |= OCMD_YUV_422_PLANAR; 748 break; 749 case I915_OVERLAY_YUV420: 750 cmd |= OCMD_YUV_420_PLANAR; 751 break; 752 case I915_OVERLAY_YUV411: 753 case I915_OVERLAY_YUV410: 754 cmd |= OCMD_YUV_410_PLANAR; 755 break; 756 } 757 } else { /* YUV packed */ 758 switch (params->format & I915_OVERLAY_DEPTH_MASK) { 759 case I915_OVERLAY_YUV422: 760 cmd |= OCMD_YUV_422_PACKED; 761 break; 762 case I915_OVERLAY_YUV411: 763 cmd |= OCMD_YUV_411_PACKED; 764 break; 765 } 766 767 switch (params->format & I915_OVERLAY_SWAP_MASK) { 768 case I915_OVERLAY_NO_SWAP: 769 break; 770 case I915_OVERLAY_UV_SWAP: 771 cmd |= OCMD_UV_SWAP; 772 break; 773 case I915_OVERLAY_Y_SWAP: 774 cmd |= OCMD_Y_SWAP; 775 break; 776 case I915_OVERLAY_Y_AND_UV_SWAP: 777 cmd |= OCMD_Y_AND_UV_SWAP; 778 break; 779 } 780 } 781 782 return cmd; 783 } 784 785 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 786 struct drm_i915_gem_object *new_bo, 787 struct put_image_params *params) 788 { 789 int ret, tmp_width; 790 struct overlay_registers __iomem *regs; 791 bool scale_changed = false; 792 struct drm_i915_private *dev_priv = overlay->i915; 793 u32 swidth, swidthsw, sheight, ostride; 794 enum i915_pipe pipe = overlay->crtc->pipe; 795 struct i915_vma *vma; 796 797 lockdep_assert_held(&dev_priv->drm.struct_mutex); 798 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 799 800 ret = intel_overlay_release_old_vid(overlay); 801 if (ret != 0) 802 return ret; 803 804 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 805 806 vma = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL); 807 if (IS_ERR(vma)) { 808 ret = PTR_ERR(vma); 809 goto out_pin_section; 810 } 811 812 ret = i915_vma_put_fence(vma); 813 if (ret) 814 goto out_unpin; 815 816 if (!overlay->active) { 817 u32 oconfig; 818 regs = intel_overlay_map_regs(overlay); 819 if (!regs) { 820 ret = -ENOMEM; 821 goto out_unpin; 822 } 823 oconfig = OCONF_CC_OUT_8BIT; 824 if (IS_GEN4(dev_priv)) 825 oconfig |= OCONF_CSC_MODE_BT709; 826 oconfig |= pipe == 0 ? 827 OCONF_PIPE_A : OCONF_PIPE_B; 828 iowrite32(oconfig, ®s->OCONFIG); 829 intel_overlay_unmap_regs(overlay, regs); 830 831 ret = intel_overlay_on(overlay); 832 if (ret != 0) 833 goto out_unpin; 834 } 835 836 regs = intel_overlay_map_regs(overlay); 837 if (!regs) { 838 ret = -ENOMEM; 839 goto out_unpin; 840 } 841 842 iowrite32((params->dst_y << 16) | params->dst_x, ®s->DWINPOS); 843 iowrite32((params->dst_h << 16) | params->dst_w, ®s->DWINSZ); 844 845 if (params->format & I915_OVERLAY_YUV_PACKED) 846 tmp_width = packed_width_bytes(params->format, params->src_w); 847 else 848 tmp_width = params->src_w; 849 850 swidth = params->src_w; 851 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 852 sheight = params->src_h; 853 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 854 ostride = params->stride_Y; 855 856 if (params->format & I915_OVERLAY_YUV_PLANAR) { 857 int uv_hscale = uv_hsubsampling(params->format); 858 int uv_vscale = uv_vsubsampling(params->format); 859 u32 tmp_U, tmp_V; 860 swidth |= (params->src_w/uv_hscale) << 16; 861 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 862 params->src_w/uv_hscale); 863 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 864 params->src_w/uv_hscale); 865 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16; 866 sheight |= (params->src_h/uv_vscale) << 16; 867 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 868 ®s->OBUF_0U); 869 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 870 ®s->OBUF_0V); 871 ostride |= params->stride_UV << 16; 872 } 873 874 iowrite32(swidth, ®s->SWIDTH); 875 iowrite32(swidthsw, ®s->SWIDTHSW); 876 iowrite32(sheight, ®s->SHEIGHT); 877 iowrite32(ostride, ®s->OSTRIDE); 878 879 scale_changed = update_scaling_factors(overlay, regs, params); 880 881 update_colorkey(overlay, regs); 882 883 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 884 885 intel_overlay_unmap_regs(overlay, regs); 886 887 ret = intel_overlay_continue(overlay, vma, scale_changed); 888 if (ret) 889 goto out_unpin; 890 891 return 0; 892 893 out_unpin: 894 i915_gem_object_unpin_from_display_plane(vma); 895 out_pin_section: 896 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 897 898 return ret; 899 } 900 901 int intel_overlay_switch_off(struct intel_overlay *overlay) 902 { 903 struct drm_i915_private *dev_priv = overlay->i915; 904 struct overlay_registers __iomem *regs; 905 int ret; 906 907 lockdep_assert_held(&dev_priv->drm.struct_mutex); 908 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 909 910 ret = intel_overlay_recover_from_interrupt(overlay); 911 if (ret != 0) 912 return ret; 913 914 if (!overlay->active) 915 return 0; 916 917 ret = intel_overlay_release_old_vid(overlay); 918 if (ret != 0) 919 return ret; 920 921 regs = intel_overlay_map_regs(overlay); 922 iowrite32(0, ®s->OCMD); 923 intel_overlay_unmap_regs(overlay, regs); 924 925 return intel_overlay_off(overlay); 926 } 927 928 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 929 struct intel_crtc *crtc) 930 { 931 if (!crtc->active) 932 return -EINVAL; 933 934 /* can't use the overlay with double wide pipe */ 935 if (crtc->config->double_wide) 936 return -EINVAL; 937 938 return 0; 939 } 940 941 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 942 { 943 struct drm_i915_private *dev_priv = overlay->i915; 944 u32 pfit_control = I915_READ(PFIT_CONTROL); 945 u32 ratio; 946 947 /* XXX: This is not the same logic as in the xorg driver, but more in 948 * line with the intel documentation for the i965 949 */ 950 if (INTEL_GEN(dev_priv) >= 4) { 951 /* on i965 use the PGM reg to read out the autoscaler values */ 952 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 953 } else { 954 if (pfit_control & VERT_AUTO_SCALE) 955 ratio = I915_READ(PFIT_AUTO_RATIOS); 956 else 957 ratio = I915_READ(PFIT_PGM_RATIOS); 958 ratio >>= PFIT_VERT_SCALE_SHIFT; 959 } 960 961 overlay->pfit_vscale_ratio = ratio; 962 } 963 964 static int check_overlay_dst(struct intel_overlay *overlay, 965 struct drm_intel_overlay_put_image *rec) 966 { 967 const struct intel_crtc_state *pipe_config = 968 overlay->crtc->config; 969 970 if (rec->dst_x < pipe_config->pipe_src_w && 971 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 972 rec->dst_y < pipe_config->pipe_src_h && 973 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 974 return 0; 975 else 976 return -EINVAL; 977 } 978 979 static int check_overlay_scaling(struct put_image_params *rec) 980 { 981 u32 tmp; 982 983 /* downscaling limit is 8.0 */ 984 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16; 985 if (tmp > 7) 986 return -EINVAL; 987 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16; 988 if (tmp > 7) 989 return -EINVAL; 990 991 return 0; 992 } 993 994 static int check_overlay_src(struct drm_i915_private *dev_priv, 995 struct drm_intel_overlay_put_image *rec, 996 struct drm_i915_gem_object *new_bo) 997 { 998 int uv_hscale = uv_hsubsampling(rec->flags); 999 int uv_vscale = uv_vsubsampling(rec->flags); 1000 u32 stride_mask; 1001 int depth; 1002 u32 tmp; 1003 1004 /* check src dimensions */ 1005 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 1006 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 1007 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 1008 return -EINVAL; 1009 } else { 1010 if (rec->src_height > IMAGE_MAX_HEIGHT || 1011 rec->src_width > IMAGE_MAX_WIDTH) 1012 return -EINVAL; 1013 } 1014 1015 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 1016 if (rec->src_height < N_VERT_Y_TAPS*4 || 1017 rec->src_width < N_HORIZ_Y_TAPS*4) 1018 return -EINVAL; 1019 1020 /* check alignment constraints */ 1021 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1022 case I915_OVERLAY_RGB: 1023 /* not implemented */ 1024 return -EINVAL; 1025 1026 case I915_OVERLAY_YUV_PACKED: 1027 if (uv_vscale != 1) 1028 return -EINVAL; 1029 1030 depth = packed_depth_bytes(rec->flags); 1031 if (depth < 0) 1032 return depth; 1033 1034 /* ignore UV planes */ 1035 rec->stride_UV = 0; 1036 rec->offset_U = 0; 1037 rec->offset_V = 0; 1038 /* check pixel alignment */ 1039 if (rec->offset_Y % depth) 1040 return -EINVAL; 1041 break; 1042 1043 case I915_OVERLAY_YUV_PLANAR: 1044 if (uv_vscale < 0 || uv_hscale < 0) 1045 return -EINVAL; 1046 /* no offset restrictions for planar formats */ 1047 break; 1048 1049 default: 1050 return -EINVAL; 1051 } 1052 1053 if (rec->src_width % uv_hscale) 1054 return -EINVAL; 1055 1056 /* stride checking */ 1057 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1058 stride_mask = 255; 1059 else 1060 stride_mask = 63; 1061 1062 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1063 return -EINVAL; 1064 if (IS_GEN4(dev_priv) && rec->stride_Y < 512) 1065 return -EINVAL; 1066 1067 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1068 4096 : 8192; 1069 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1070 return -EINVAL; 1071 1072 /* check buffer dimensions */ 1073 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1074 case I915_OVERLAY_RGB: 1075 case I915_OVERLAY_YUV_PACKED: 1076 /* always 4 Y values per depth pixels */ 1077 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1078 return -EINVAL; 1079 1080 tmp = rec->stride_Y*rec->src_height; 1081 if (rec->offset_Y + tmp > new_bo->base.size) 1082 return -EINVAL; 1083 break; 1084 1085 case I915_OVERLAY_YUV_PLANAR: 1086 if (rec->src_width > rec->stride_Y) 1087 return -EINVAL; 1088 if (rec->src_width/uv_hscale > rec->stride_UV) 1089 return -EINVAL; 1090 1091 tmp = rec->stride_Y * rec->src_height; 1092 if (rec->offset_Y + tmp > new_bo->base.size) 1093 return -EINVAL; 1094 1095 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1096 if (rec->offset_U + tmp > new_bo->base.size || 1097 rec->offset_V + tmp > new_bo->base.size) 1098 return -EINVAL; 1099 break; 1100 } 1101 1102 return 0; 1103 } 1104 1105 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1106 struct drm_file *file_priv) 1107 { 1108 struct drm_intel_overlay_put_image *put_image_rec = data; 1109 struct drm_i915_private *dev_priv = to_i915(dev); 1110 struct intel_overlay *overlay; 1111 struct drm_crtc *drmmode_crtc; 1112 struct intel_crtc *crtc; 1113 struct drm_i915_gem_object *new_bo; 1114 struct put_image_params *params; 1115 int ret; 1116 1117 overlay = dev_priv->overlay; 1118 if (!overlay) { 1119 DRM_DEBUG("userspace bug: no overlay\n"); 1120 return -ENODEV; 1121 } 1122 1123 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) { 1124 drm_modeset_lock_all(dev); 1125 mutex_lock(&dev->struct_mutex); 1126 1127 ret = intel_overlay_switch_off(overlay); 1128 1129 mutex_unlock(&dev->struct_mutex); 1130 drm_modeset_unlock_all(dev); 1131 1132 return ret; 1133 } 1134 1135 params = kmalloc(sizeof(*params), M_DRM, GFP_KERNEL); 1136 if (!params) 1137 return -ENOMEM; 1138 1139 drmmode_crtc = drm_crtc_find(dev, file_priv, put_image_rec->crtc_id); 1140 if (!drmmode_crtc) { 1141 ret = -ENOENT; 1142 goto out_free; 1143 } 1144 crtc = to_intel_crtc(drmmode_crtc); 1145 1146 new_bo = i915_gem_object_lookup(file_priv, put_image_rec->bo_handle); 1147 if (!new_bo) { 1148 ret = -ENOENT; 1149 goto out_free; 1150 } 1151 1152 drm_modeset_lock_all(dev); 1153 mutex_lock(&dev->struct_mutex); 1154 1155 if (i915_gem_object_is_tiled(new_bo)) { 1156 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); 1157 ret = -EINVAL; 1158 goto out_unlock; 1159 } 1160 1161 ret = intel_overlay_recover_from_interrupt(overlay); 1162 if (ret != 0) 1163 goto out_unlock; 1164 1165 if (overlay->crtc != crtc) { 1166 ret = intel_overlay_switch_off(overlay); 1167 if (ret != 0) 1168 goto out_unlock; 1169 1170 ret = check_overlay_possible_on_crtc(overlay, crtc); 1171 if (ret != 0) 1172 goto out_unlock; 1173 1174 overlay->crtc = crtc; 1175 crtc->overlay = overlay; 1176 1177 /* line too wide, i.e. one-line-mode */ 1178 if (crtc->config->pipe_src_w > 1024 && 1179 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1180 overlay->pfit_active = true; 1181 update_pfit_vscale_ratio(overlay); 1182 } else 1183 overlay->pfit_active = false; 1184 } 1185 1186 ret = check_overlay_dst(overlay, put_image_rec); 1187 if (ret != 0) 1188 goto out_unlock; 1189 1190 if (overlay->pfit_active) { 1191 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) / 1192 overlay->pfit_vscale_ratio); 1193 /* shifting right rounds downwards, so add 1 */ 1194 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) / 1195 overlay->pfit_vscale_ratio) + 1; 1196 } else { 1197 params->dst_y = put_image_rec->dst_y; 1198 params->dst_h = put_image_rec->dst_height; 1199 } 1200 params->dst_x = put_image_rec->dst_x; 1201 params->dst_w = put_image_rec->dst_width; 1202 1203 params->src_w = put_image_rec->src_width; 1204 params->src_h = put_image_rec->src_height; 1205 params->src_scan_w = put_image_rec->src_scan_width; 1206 params->src_scan_h = put_image_rec->src_scan_height; 1207 if (params->src_scan_h > params->src_h || 1208 params->src_scan_w > params->src_w) { 1209 ret = -EINVAL; 1210 goto out_unlock; 1211 } 1212 1213 ret = check_overlay_src(dev_priv, put_image_rec, new_bo); 1214 if (ret != 0) 1215 goto out_unlock; 1216 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK; 1217 params->stride_Y = put_image_rec->stride_Y; 1218 params->stride_UV = put_image_rec->stride_UV; 1219 params->offset_Y = put_image_rec->offset_Y; 1220 params->offset_U = put_image_rec->offset_U; 1221 params->offset_V = put_image_rec->offset_V; 1222 1223 /* Check scaling after src size to prevent a divide-by-zero. */ 1224 ret = check_overlay_scaling(params); 1225 if (ret != 0) 1226 goto out_unlock; 1227 1228 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1229 if (ret != 0) 1230 goto out_unlock; 1231 1232 mutex_unlock(&dev->struct_mutex); 1233 drm_modeset_unlock_all(dev); 1234 i915_gem_object_put(new_bo); 1235 1236 kfree(params); 1237 1238 return 0; 1239 1240 out_unlock: 1241 mutex_unlock(&dev->struct_mutex); 1242 drm_modeset_unlock_all(dev); 1243 i915_gem_object_put(new_bo); 1244 out_free: 1245 kfree(params); 1246 1247 return ret; 1248 } 1249 1250 static void update_reg_attrs(struct intel_overlay *overlay, 1251 struct overlay_registers __iomem *regs) 1252 { 1253 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1254 ®s->OCLRC0); 1255 iowrite32(overlay->saturation, ®s->OCLRC1); 1256 } 1257 1258 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1259 { 1260 int i; 1261 1262 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1263 return false; 1264 1265 for (i = 0; i < 3; i++) { 1266 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1267 return false; 1268 } 1269 1270 return true; 1271 } 1272 1273 static bool check_gamma5_errata(u32 gamma5) 1274 { 1275 int i; 1276 1277 for (i = 0; i < 3; i++) { 1278 if (((gamma5 >> i*8) & 0xff) == 0x80) 1279 return false; 1280 } 1281 1282 return true; 1283 } 1284 1285 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1286 { 1287 if (!check_gamma_bounds(0, attrs->gamma0) || 1288 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1289 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1290 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1291 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1292 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1293 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1294 return -EINVAL; 1295 1296 if (!check_gamma5_errata(attrs->gamma5)) 1297 return -EINVAL; 1298 1299 return 0; 1300 } 1301 1302 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1303 struct drm_file *file_priv) 1304 { 1305 struct drm_intel_overlay_attrs *attrs = data; 1306 struct drm_i915_private *dev_priv = to_i915(dev); 1307 struct intel_overlay *overlay; 1308 struct overlay_registers __iomem *regs; 1309 int ret; 1310 1311 overlay = dev_priv->overlay; 1312 if (!overlay) { 1313 DRM_DEBUG("userspace bug: no overlay\n"); 1314 return -ENODEV; 1315 } 1316 1317 drm_modeset_lock_all(dev); 1318 mutex_lock(&dev->struct_mutex); 1319 1320 ret = -EINVAL; 1321 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1322 attrs->color_key = overlay->color_key; 1323 attrs->brightness = overlay->brightness; 1324 attrs->contrast = overlay->contrast; 1325 attrs->saturation = overlay->saturation; 1326 1327 if (!IS_GEN2(dev_priv)) { 1328 attrs->gamma0 = I915_READ(OGAMC0); 1329 attrs->gamma1 = I915_READ(OGAMC1); 1330 attrs->gamma2 = I915_READ(OGAMC2); 1331 attrs->gamma3 = I915_READ(OGAMC3); 1332 attrs->gamma4 = I915_READ(OGAMC4); 1333 attrs->gamma5 = I915_READ(OGAMC5); 1334 } 1335 } else { 1336 if (attrs->brightness < -128 || attrs->brightness > 127) 1337 goto out_unlock; 1338 if (attrs->contrast > 255) 1339 goto out_unlock; 1340 if (attrs->saturation > 1023) 1341 goto out_unlock; 1342 1343 overlay->color_key = attrs->color_key; 1344 overlay->brightness = attrs->brightness; 1345 overlay->contrast = attrs->contrast; 1346 overlay->saturation = attrs->saturation; 1347 1348 regs = intel_overlay_map_regs(overlay); 1349 if (!regs) { 1350 ret = -ENOMEM; 1351 goto out_unlock; 1352 } 1353 1354 update_reg_attrs(overlay, regs); 1355 1356 intel_overlay_unmap_regs(overlay, regs); 1357 1358 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1359 if (IS_GEN2(dev_priv)) 1360 goto out_unlock; 1361 1362 if (overlay->active) { 1363 ret = -EBUSY; 1364 goto out_unlock; 1365 } 1366 1367 ret = check_gamma(attrs); 1368 if (ret) 1369 goto out_unlock; 1370 1371 I915_WRITE(OGAMC0, attrs->gamma0); 1372 I915_WRITE(OGAMC1, attrs->gamma1); 1373 I915_WRITE(OGAMC2, attrs->gamma2); 1374 I915_WRITE(OGAMC3, attrs->gamma3); 1375 I915_WRITE(OGAMC4, attrs->gamma4); 1376 I915_WRITE(OGAMC5, attrs->gamma5); 1377 } 1378 } 1379 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1380 1381 ret = 0; 1382 out_unlock: 1383 mutex_unlock(&dev->struct_mutex); 1384 drm_modeset_unlock_all(dev); 1385 1386 return ret; 1387 } 1388 1389 void intel_setup_overlay(struct drm_i915_private *dev_priv) 1390 { 1391 struct intel_overlay *overlay; 1392 struct drm_i915_gem_object *reg_bo; 1393 struct overlay_registers __iomem *regs; 1394 struct i915_vma *vma = NULL; 1395 int ret; 1396 1397 if (!HAS_OVERLAY(dev_priv)) 1398 return; 1399 1400 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1401 if (!overlay) 1402 return; 1403 1404 mutex_lock(&dev_priv->drm.struct_mutex); 1405 if (WARN_ON(dev_priv->overlay)) 1406 goto out_free; 1407 1408 overlay->i915 = dev_priv; 1409 1410 reg_bo = NULL; 1411 if (!OVERLAY_NEEDS_PHYSICAL(dev_priv)) 1412 reg_bo = i915_gem_object_create_stolen(dev_priv, PAGE_SIZE); 1413 if (reg_bo == NULL) 1414 reg_bo = i915_gem_object_create(dev_priv, PAGE_SIZE); 1415 if (IS_ERR(reg_bo)) 1416 goto out_free; 1417 overlay->reg_bo = reg_bo; 1418 1419 if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) { 1420 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE); 1421 if (ret) { 1422 DRM_ERROR("failed to attach phys overlay regs\n"); 1423 goto out_free_bo; 1424 } 1425 overlay->flip_addr = reg_bo->phys_handle->busaddr; 1426 } else { 1427 vma = i915_gem_object_ggtt_pin(reg_bo, NULL, 1428 0, PAGE_SIZE, PIN_MAPPABLE); 1429 if (IS_ERR(vma)) { 1430 DRM_ERROR("failed to pin overlay register bo\n"); 1431 ret = PTR_ERR(vma); 1432 goto out_free_bo; 1433 } 1434 overlay->flip_addr = i915_ggtt_offset(vma); 1435 1436 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true); 1437 if (ret) { 1438 DRM_ERROR("failed to move overlay register bo into the GTT\n"); 1439 goto out_unpin_bo; 1440 } 1441 } 1442 1443 /* init all values */ 1444 overlay->color_key = 0x0101fe; 1445 overlay->color_key_enabled = true; 1446 overlay->brightness = -19; 1447 overlay->contrast = 75; 1448 overlay->saturation = 146; 1449 1450 init_request_active(&overlay->last_flip, NULL); 1451 1452 regs = intel_overlay_map_regs(overlay); 1453 if (!regs) 1454 goto out_unpin_bo; 1455 1456 memset_io(regs, 0, sizeof(struct overlay_registers)); 1457 update_polyphase_filter(regs); 1458 update_reg_attrs(overlay, regs); 1459 1460 intel_overlay_unmap_regs(overlay, regs); 1461 1462 dev_priv->overlay = overlay; 1463 mutex_unlock(&dev_priv->drm.struct_mutex); 1464 DRM_INFO("initialized overlay support\n"); 1465 return; 1466 1467 out_unpin_bo: 1468 if (vma) 1469 i915_vma_unpin(vma); 1470 out_free_bo: 1471 i915_gem_object_put(reg_bo); 1472 out_free: 1473 mutex_unlock(&dev_priv->drm.struct_mutex); 1474 kfree(overlay); 1475 return; 1476 } 1477 1478 void intel_cleanup_overlay(struct drm_i915_private *dev_priv) 1479 { 1480 if (!dev_priv->overlay) 1481 return; 1482 1483 /* The bo's should be free'd by the generic code already. 1484 * Furthermore modesetting teardown happens beforehand so the 1485 * hardware should be off already */ 1486 WARN_ON(dev_priv->overlay->active); 1487 1488 i915_gem_object_put(dev_priv->overlay->reg_bo); 1489 kfree(dev_priv->overlay); 1490 } 1491 1492 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1493 1494 struct intel_overlay_error_state { 1495 struct overlay_registers regs; 1496 unsigned long base; 1497 u32 dovsta; 1498 u32 isr; 1499 }; 1500 1501 static struct overlay_registers __iomem * 1502 intel_overlay_map_regs_atomic(struct intel_overlay *overlay) 1503 { 1504 struct drm_i915_private *dev_priv = overlay->i915; 1505 struct overlay_registers __iomem *regs; 1506 1507 if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) 1508 /* Cast to make sparse happy, but it's wc memory anyway, so 1509 * equivalent to the wc io mapping on X86. */ 1510 regs = (struct overlay_registers __iomem *) 1511 overlay->reg_bo->phys_handle->vaddr; 1512 else 1513 regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.mappable, 1514 overlay->flip_addr); 1515 1516 return regs; 1517 } 1518 1519 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay, 1520 struct overlay_registers __iomem *regs) 1521 { 1522 if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915)) 1523 io_mapping_unmap_atomic(regs); 1524 } 1525 1526 struct intel_overlay_error_state * 1527 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1528 { 1529 struct intel_overlay *overlay = dev_priv->overlay; 1530 struct intel_overlay_error_state *error; 1531 struct overlay_registers __iomem *regs; 1532 1533 if (!overlay || !overlay->active) 1534 return NULL; 1535 1536 error = kmalloc(sizeof(*error), M_DRM, GFP_ATOMIC); 1537 if (error == NULL) 1538 return NULL; 1539 1540 error->dovsta = I915_READ(DOVSTA); 1541 error->isr = I915_READ(ISR); 1542 error->base = overlay->flip_addr; 1543 1544 regs = intel_overlay_map_regs_atomic(overlay); 1545 if (!regs) 1546 goto err; 1547 1548 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers)); 1549 intel_overlay_unmap_regs_atomic(overlay, regs); 1550 1551 return error; 1552 1553 err: 1554 kfree(error); 1555 return NULL; 1556 } 1557 1558 void 1559 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1560 struct intel_overlay_error_state *error) 1561 { 1562 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1563 error->dovsta, error->isr); 1564 i915_error_printf(m, " Register file at 0x%08lx:\n", 1565 error->base); 1566 1567 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1568 P(OBUF_0Y); 1569 P(OBUF_1Y); 1570 P(OBUF_0U); 1571 P(OBUF_0V); 1572 P(OBUF_1U); 1573 P(OBUF_1V); 1574 P(OSTRIDE); 1575 P(YRGB_VPH); 1576 P(UV_VPH); 1577 P(HORZ_PH); 1578 P(INIT_PHS); 1579 P(DWINPOS); 1580 P(DWINSZ); 1581 P(SWIDTH); 1582 P(SWIDTHSW); 1583 P(SHEIGHT); 1584 P(YRGBSCALE); 1585 P(UVSCALE); 1586 P(OCLRC0); 1587 P(OCLRC1); 1588 P(DCLRKV); 1589 P(DCLRKM); 1590 P(SCLRKVH); 1591 P(SCLRKVL); 1592 P(SCLRKEN); 1593 P(OCONFIG); 1594 P(OCMD); 1595 P(OSTART_0Y); 1596 P(OSTART_1Y); 1597 P(OSTART_0U); 1598 P(OSTART_0V); 1599 P(OSTART_1U); 1600 P(OSTART_1V); 1601 P(OTILEOFF_0Y); 1602 P(OTILEOFF_1Y); 1603 P(OTILEOFF_0U); 1604 P(OTILEOFF_0V); 1605 P(OTILEOFF_1U); 1606 P(OTILEOFF_1V); 1607 P(FASTHSCALE); 1608 P(UVSCALEV); 1609 #undef P 1610 } 1611 1612 #endif 1613