1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <linux/module.h> 31 #include <machine/clock.h> 32 33 #define FORCEWAKE_ACK_TIMEOUT_MS 2 34 35 /* FBC, or Frame Buffer Compression, is a technique employed to compress the 36 * framebuffer contents in-memory, aiming at reducing the required bandwidth 37 * during in-memory transfers and, therefore, reduce the power packet. 38 * 39 * The benefits of FBC are mostly visible with solid backgrounds and 40 * variation-less patterns. 41 * 42 * FBC-related functionality can be enabled by the means of the 43 * i915.i915_enable_fbc parameter 44 */ 45 46 static bool intel_crtc_active(struct drm_crtc *crtc) 47 { 48 /* Be paranoid as we can arrive here with only partial 49 * state retrieved from the hardware during setup. 50 */ 51 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock; 52 } 53 54 static void i8xx_disable_fbc(struct drm_device *dev) 55 { 56 struct drm_i915_private *dev_priv = dev->dev_private; 57 u32 fbc_ctl; 58 59 /* Disable compression */ 60 fbc_ctl = I915_READ(FBC_CONTROL); 61 if ((fbc_ctl & FBC_CTL_EN) == 0) 62 return; 63 64 fbc_ctl &= ~FBC_CTL_EN; 65 I915_WRITE(FBC_CONTROL, fbc_ctl); 66 67 /* Wait for compressing bit to clear */ 68 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { 69 DRM_DEBUG_KMS("FBC idle timed out\n"); 70 return; 71 } 72 73 DRM_DEBUG_KMS("disabled FBC\n"); 74 } 75 76 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 77 { 78 struct drm_device *dev = crtc->dev; 79 struct drm_i915_private *dev_priv = dev->dev_private; 80 struct drm_framebuffer *fb = crtc->fb; 81 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 82 struct drm_i915_gem_object *obj = intel_fb->obj; 83 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 84 int cfb_pitch; 85 int plane, i; 86 u32 fbc_ctl, fbc_ctl2; 87 88 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; 89 if (fb->pitches[0] < cfb_pitch) 90 cfb_pitch = fb->pitches[0]; 91 92 /* FBC_CTL wants 64B units */ 93 cfb_pitch = (cfb_pitch / 64) - 1; 94 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; 95 96 /* Clear old tags */ 97 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 98 I915_WRITE(FBC_TAG + (i * 4), 0); 99 100 /* Set it up... */ 101 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; 102 fbc_ctl2 |= plane; 103 I915_WRITE(FBC_CONTROL2, fbc_ctl2); 104 I915_WRITE(FBC_FENCE_OFF, crtc->y); 105 106 /* enable it... */ 107 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; 108 if (IS_I945GM(dev)) 109 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 110 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 111 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; 112 fbc_ctl |= obj->fence_reg; 113 I915_WRITE(FBC_CONTROL, fbc_ctl); 114 115 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", 116 cfb_pitch, crtc->y, intel_crtc->plane); 117 } 118 119 static bool i8xx_fbc_enabled(struct drm_device *dev) 120 { 121 struct drm_i915_private *dev_priv = dev->dev_private; 122 123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; 124 } 125 126 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 127 { 128 struct drm_device *dev = crtc->dev; 129 struct drm_i915_private *dev_priv = dev->dev_private; 130 struct drm_framebuffer *fb = crtc->fb; 131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 132 struct drm_i915_gem_object *obj = intel_fb->obj; 133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 134 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; 135 unsigned long stall_watermark = 200; 136 u32 dpfc_ctl; 137 138 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; 139 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; 140 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); 141 142 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 143 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | 144 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); 145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y); 146 147 /* enable it... */ 148 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); 149 150 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 151 } 152 153 static void g4x_disable_fbc(struct drm_device *dev) 154 { 155 struct drm_i915_private *dev_priv = dev->dev_private; 156 u32 dpfc_ctl; 157 158 /* Disable compression */ 159 dpfc_ctl = I915_READ(DPFC_CONTROL); 160 if (dpfc_ctl & DPFC_CTL_EN) { 161 dpfc_ctl &= ~DPFC_CTL_EN; 162 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 163 164 DRM_DEBUG_KMS("disabled FBC\n"); 165 } 166 } 167 168 static bool g4x_fbc_enabled(struct drm_device *dev) 169 { 170 struct drm_i915_private *dev_priv = dev->dev_private; 171 172 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; 173 } 174 175 static void sandybridge_blit_fbc_update(struct drm_device *dev) 176 { 177 struct drm_i915_private *dev_priv = dev->dev_private; 178 u32 blt_ecoskpd; 179 180 /* Make sure blitter notifies FBC of writes */ 181 gen6_gt_force_wake_get(dev_priv); 182 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); 183 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << 184 GEN6_BLITTER_LOCK_SHIFT; 185 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; 187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 188 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << 189 GEN6_BLITTER_LOCK_SHIFT); 190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 191 POSTING_READ(GEN6_BLITTER_ECOSKPD); 192 gen6_gt_force_wake_put(dev_priv); 193 } 194 195 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 196 { 197 struct drm_device *dev = crtc->dev; 198 struct drm_i915_private *dev_priv = dev->dev_private; 199 struct drm_framebuffer *fb = crtc->fb; 200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 201 struct drm_i915_gem_object *obj = intel_fb->obj; 202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 203 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; 204 unsigned long stall_watermark = 200; 205 u32 dpfc_ctl; 206 207 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 208 dpfc_ctl &= DPFC_RESERVED; 209 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); 210 /* Set persistent mode for front-buffer rendering, ala X. */ 211 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; 212 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); 213 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); 214 215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | 217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); 218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); 219 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); 220 /* enable it... */ 221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 222 223 if (IS_GEN6(dev)) { 224 I915_WRITE(SNB_DPFC_CTL_SA, 225 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 226 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); 227 sandybridge_blit_fbc_update(dev); 228 } 229 230 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 231 } 232 233 static void ironlake_disable_fbc(struct drm_device *dev) 234 { 235 struct drm_i915_private *dev_priv = dev->dev_private; 236 u32 dpfc_ctl; 237 238 /* Disable compression */ 239 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 240 if (dpfc_ctl & DPFC_CTL_EN) { 241 dpfc_ctl &= ~DPFC_CTL_EN; 242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 243 244 DRM_DEBUG_KMS("disabled FBC\n"); 245 } 246 } 247 248 static bool ironlake_fbc_enabled(struct drm_device *dev) 249 { 250 struct drm_i915_private *dev_priv = dev->dev_private; 251 252 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; 253 } 254 255 bool intel_fbc_enabled(struct drm_device *dev) 256 { 257 struct drm_i915_private *dev_priv = dev->dev_private; 258 259 if (!dev_priv->display.fbc_enabled) 260 return false; 261 262 return dev_priv->display.fbc_enabled(dev); 263 } 264 265 static void intel_fbc_work_fn(struct work_struct *__work) 266 { 267 struct intel_fbc_work *work = 268 container_of(to_delayed_work(__work), 269 struct intel_fbc_work, work); 270 struct drm_device *dev = work->crtc->dev; 271 struct drm_i915_private *dev_priv = dev->dev_private; 272 273 mutex_lock(&dev->struct_mutex); 274 if (work == dev_priv->fbc_work) { 275 /* Double check that we haven't switched fb without cancelling 276 * the prior work. 277 */ 278 if (work->crtc->fb == work->fb) { 279 dev_priv->display.enable_fbc(work->crtc, 280 work->interval); 281 282 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; 283 dev_priv->cfb_fb = work->crtc->fb->base.id; 284 dev_priv->cfb_y = work->crtc->y; 285 } 286 287 dev_priv->fbc_work = NULL; 288 } 289 mutex_unlock(&dev->struct_mutex); 290 291 kfree(work); 292 } 293 294 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) 295 { 296 if (dev_priv->fbc_work == NULL) 297 return; 298 299 DRM_DEBUG_KMS("cancelling pending FBC enable\n"); 300 301 /* Synchronisation is provided by struct_mutex and checking of 302 * dev_priv->fbc_work, so we can perform the cancellation 303 * entirely asynchronously. 304 */ 305 if (cancel_delayed_work(&dev_priv->fbc_work->work)) 306 /* tasklet was killed before being run, clean up */ 307 kfree(dev_priv->fbc_work); 308 309 /* Mark the work as no longer wanted so that if it does 310 * wake-up (because the work was already running and waiting 311 * for our mutex), it will discover that is no longer 312 * necessary to run. 313 */ 314 dev_priv->fbc_work = NULL; 315 } 316 317 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 318 { 319 struct intel_fbc_work *work; 320 struct drm_device *dev = crtc->dev; 321 struct drm_i915_private *dev_priv = dev->dev_private; 322 323 if (!dev_priv->display.enable_fbc) 324 return; 325 326 intel_cancel_fbc_work(dev_priv); 327 328 work = kzalloc(sizeof *work, GFP_KERNEL); 329 if (work == NULL) { 330 dev_priv->display.enable_fbc(crtc, interval); 331 return; 332 } 333 334 work->crtc = crtc; 335 work->fb = crtc->fb; 336 work->interval = interval; 337 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); 338 339 dev_priv->fbc_work = work; 340 341 DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); 342 343 /* Delay the actual enabling to let pageflipping cease and the 344 * display to settle before starting the compression. Note that 345 * this delay also serves a second purpose: it allows for a 346 * vblank to pass after disabling the FBC before we attempt 347 * to modify the control registers. 348 * 349 * A more complicated solution would involve tracking vblanks 350 * following the termination of the page-flipping sequence 351 * and indeed performing the enable as a co-routine and not 352 * waiting synchronously upon the vblank. 353 */ 354 schedule_delayed_work(&work->work, msecs_to_jiffies(50)); 355 } 356 357 void intel_disable_fbc(struct drm_device *dev) 358 { 359 struct drm_i915_private *dev_priv = dev->dev_private; 360 361 intel_cancel_fbc_work(dev_priv); 362 363 if (!dev_priv->display.disable_fbc) 364 return; 365 366 dev_priv->display.disable_fbc(dev); 367 dev_priv->cfb_plane = -1; 368 } 369 370 /** 371 * intel_update_fbc - enable/disable FBC as needed 372 * @dev: the drm_device 373 * 374 * Set up the framebuffer compression hardware at mode set time. We 375 * enable it if possible: 376 * - plane A only (on pre-965) 377 * - no pixel mulitply/line duplication 378 * - no alpha buffer discard 379 * - no dual wide 380 * - framebuffer <= 2048 in width, 1536 in height 381 * 382 * We can't assume that any compression will take place (worst case), 383 * so the compressed buffer has to be the same size as the uncompressed 384 * one. It also must reside (along with the line length buffer) in 385 * stolen memory. 386 * 387 * We need to enable/disable FBC on a global basis. 388 */ 389 void intel_update_fbc(struct drm_device *dev) 390 { 391 struct drm_i915_private *dev_priv = dev->dev_private; 392 struct drm_crtc *crtc = NULL, *tmp_crtc; 393 struct intel_crtc *intel_crtc; 394 struct drm_framebuffer *fb; 395 struct intel_framebuffer *intel_fb; 396 struct drm_i915_gem_object *obj; 397 int enable_fbc; 398 399 if (!i915_powersave) 400 return; 401 402 if (!I915_HAS_FBC(dev)) 403 return; 404 405 /* 406 * If FBC is already on, we just have to verify that we can 407 * keep it that way... 408 * Need to disable if: 409 * - more than one pipe is active 410 * - changing FBC params (stride, fence, mode) 411 * - new fb is too large to fit in compressed buffer 412 * - going to an unsupported config (interlace, pixel multiply, etc.) 413 */ 414 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { 415 if (intel_crtc_active(tmp_crtc) && 416 !to_intel_crtc(tmp_crtc)->primary_disabled) { 417 if (crtc) { 418 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); 419 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; 420 goto out_disable; 421 } 422 crtc = tmp_crtc; 423 } 424 } 425 426 if (!crtc || crtc->fb == NULL) { 427 DRM_DEBUG_KMS("no output, disabling\n"); 428 dev_priv->no_fbc_reason = FBC_NO_OUTPUT; 429 goto out_disable; 430 } 431 432 intel_crtc = to_intel_crtc(crtc); 433 fb = crtc->fb; 434 intel_fb = to_intel_framebuffer(fb); 435 obj = intel_fb->obj; 436 437 enable_fbc = i915_enable_fbc; 438 if (enable_fbc < 0) { 439 DRM_DEBUG_KMS("fbc set to per-chip default\n"); 440 enable_fbc = 1; 441 if (INTEL_INFO(dev)->gen <= 6) 442 enable_fbc = 0; 443 } 444 if (!enable_fbc) { 445 DRM_DEBUG_KMS("fbc disabled per module param\n"); 446 dev_priv->no_fbc_reason = FBC_MODULE_PARAM; 447 goto out_disable; 448 } 449 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || 450 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { 451 DRM_DEBUG_KMS("mode incompatible with compression, " 452 "disabling\n"); 453 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; 454 goto out_disable; 455 } 456 if ((crtc->mode.hdisplay > 2048) || 457 (crtc->mode.vdisplay > 1536)) { 458 DRM_DEBUG_KMS("mode too large for compression, disabling\n"); 459 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; 460 goto out_disable; 461 } 462 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { 463 DRM_DEBUG_KMS("plane not 0, disabling compression\n"); 464 dev_priv->no_fbc_reason = FBC_BAD_PLANE; 465 goto out_disable; 466 } 467 468 /* The use of a CPU fence is mandatory in order to detect writes 469 * by the CPU to the scanout and trigger updates to the FBC. 470 */ 471 if (obj->tiling_mode != I915_TILING_X || 472 obj->fence_reg == I915_FENCE_REG_NONE) { 473 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); 474 dev_priv->no_fbc_reason = FBC_NOT_TILED; 475 goto out_disable; 476 } 477 478 #ifdef DDB 479 /* If the kernel debugger is active, always disable compression */ 480 if (db_active) 481 goto out_disable; 482 #endif 483 484 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) { 485 DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb->obj->base.size); 486 DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); 487 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); 488 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; 489 goto out_disable; 490 } 491 492 /* If the scanout has not changed, don't modify the FBC settings. 493 * Note that we make the fundamental assumption that the fb->obj 494 * cannot be unpinned (and have its GTT offset and fence revoked) 495 * without first being decoupled from the scanout and FBC disabled. 496 */ 497 if (dev_priv->cfb_plane == intel_crtc->plane && 498 dev_priv->cfb_fb == fb->base.id && 499 dev_priv->cfb_y == crtc->y) 500 return; 501 502 if (intel_fbc_enabled(dev)) { 503 /* We update FBC along two paths, after changing fb/crtc 504 * configuration (modeswitching) and after page-flipping 505 * finishes. For the latter, we know that not only did 506 * we disable the FBC at the start of the page-flip 507 * sequence, but also more than one vblank has passed. 508 * 509 * For the former case of modeswitching, it is possible 510 * to switch between two FBC valid configurations 511 * instantaneously so we do need to disable the FBC 512 * before we can modify its control registers. We also 513 * have to wait for the next vblank for that to take 514 * effect. However, since we delay enabling FBC we can 515 * assume that a vblank has passed since disabling and 516 * that we can safely alter the registers in the deferred 517 * callback. 518 * 519 * In the scenario that we go from a valid to invalid 520 * and then back to valid FBC configuration we have 521 * no strict enforcement that a vblank occurred since 522 * disabling the FBC. However, along all current pipe 523 * disabling paths we do need to wait for a vblank at 524 * some point. And we wait before enabling FBC anyway. 525 */ 526 DRM_DEBUG_KMS("disabling active FBC for update\n"); 527 intel_disable_fbc(dev); 528 } 529 530 intel_enable_fbc(crtc, 500); 531 return; 532 533 out_disable: 534 /* Multiple disables should be harmless */ 535 if (intel_fbc_enabled(dev)) { 536 DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); 537 intel_disable_fbc(dev); 538 } 539 i915_gem_stolen_cleanup_compression(dev); 540 } 541 542 static void i915_pineview_get_mem_freq(struct drm_device *dev) 543 { 544 drm_i915_private_t *dev_priv = dev->dev_private; 545 u32 tmp; 546 547 tmp = I915_READ(CLKCFG); 548 549 switch (tmp & CLKCFG_FSB_MASK) { 550 case CLKCFG_FSB_533: 551 dev_priv->fsb_freq = 533; /* 133*4 */ 552 break; 553 case CLKCFG_FSB_800: 554 dev_priv->fsb_freq = 800; /* 200*4 */ 555 break; 556 case CLKCFG_FSB_667: 557 dev_priv->fsb_freq = 667; /* 167*4 */ 558 break; 559 case CLKCFG_FSB_400: 560 dev_priv->fsb_freq = 400; /* 100*4 */ 561 break; 562 } 563 564 switch (tmp & CLKCFG_MEM_MASK) { 565 case CLKCFG_MEM_533: 566 dev_priv->mem_freq = 533; 567 break; 568 case CLKCFG_MEM_667: 569 dev_priv->mem_freq = 667; 570 break; 571 case CLKCFG_MEM_800: 572 dev_priv->mem_freq = 800; 573 break; 574 } 575 576 /* detect pineview DDR3 setting */ 577 tmp = I915_READ(CSHRDDR3CTL); 578 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 579 } 580 581 static void i915_ironlake_get_mem_freq(struct drm_device *dev) 582 { 583 drm_i915_private_t *dev_priv = dev->dev_private; 584 u16 ddrpll, csipll; 585 586 ddrpll = I915_READ16(DDRMPLL1); 587 csipll = I915_READ16(CSIPLL0); 588 589 switch (ddrpll & 0xff) { 590 case 0xc: 591 dev_priv->mem_freq = 800; 592 break; 593 case 0x10: 594 dev_priv->mem_freq = 1066; 595 break; 596 case 0x14: 597 dev_priv->mem_freq = 1333; 598 break; 599 case 0x18: 600 dev_priv->mem_freq = 1600; 601 break; 602 default: 603 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 604 ddrpll & 0xff); 605 dev_priv->mem_freq = 0; 606 break; 607 } 608 609 dev_priv->ips.r_t = dev_priv->mem_freq; 610 611 switch (csipll & 0x3ff) { 612 case 0x00c: 613 dev_priv->fsb_freq = 3200; 614 break; 615 case 0x00e: 616 dev_priv->fsb_freq = 3733; 617 break; 618 case 0x010: 619 dev_priv->fsb_freq = 4266; 620 break; 621 case 0x012: 622 dev_priv->fsb_freq = 4800; 623 break; 624 case 0x014: 625 dev_priv->fsb_freq = 5333; 626 break; 627 case 0x016: 628 dev_priv->fsb_freq = 5866; 629 break; 630 case 0x018: 631 dev_priv->fsb_freq = 6400; 632 break; 633 default: 634 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 635 csipll & 0x3ff); 636 dev_priv->fsb_freq = 0; 637 break; 638 } 639 640 if (dev_priv->fsb_freq == 3200) { 641 dev_priv->ips.c_m = 0; 642 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 643 dev_priv->ips.c_m = 1; 644 } else { 645 dev_priv->ips.c_m = 2; 646 } 647 } 648 649 static const struct cxsr_latency cxsr_latency_table[] = { 650 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 651 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 652 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 653 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 654 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 655 656 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 657 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 658 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 659 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 660 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 661 662 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 663 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 664 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 665 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 666 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 667 668 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 669 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 670 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 671 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 672 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 673 674 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 675 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 676 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 677 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 678 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 679 680 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 681 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 682 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 683 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 684 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 685 }; 686 687 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 688 int is_ddr3, 689 int fsb, 690 int mem) 691 { 692 const struct cxsr_latency *latency; 693 int i; 694 695 if (fsb == 0 || mem == 0) 696 return NULL; 697 698 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 699 latency = &cxsr_latency_table[i]; 700 if (is_desktop == latency->is_desktop && 701 is_ddr3 == latency->is_ddr3 && 702 fsb == latency->fsb_freq && mem == latency->mem_freq) 703 return latency; 704 } 705 706 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 707 708 return NULL; 709 } 710 711 static void pineview_disable_cxsr(struct drm_device *dev) 712 { 713 struct drm_i915_private *dev_priv = dev->dev_private; 714 715 /* deactivate cxsr */ 716 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); 717 } 718 719 /* 720 * Latency for FIFO fetches is dependent on several factors: 721 * - memory configuration (speed, channels) 722 * - chipset 723 * - current MCH state 724 * It can be fairly high in some situations, so here we assume a fairly 725 * pessimal value. It's a tradeoff between extra memory fetches (if we 726 * set this value too high, the FIFO will fetch frequently to stay full) 727 * and power consumption (set it too low to save power and we might see 728 * FIFO underruns and display "flicker"). 729 * 730 * A value of 5us seems to be a good balance; safe for very low end 731 * platforms but not overly aggressive on lower latency configs. 732 */ 733 static const int latency_ns = 5000; 734 735 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 736 { 737 struct drm_i915_private *dev_priv = dev->dev_private; 738 uint32_t dsparb = I915_READ(DSPARB); 739 int size; 740 741 size = dsparb & 0x7f; 742 if (plane) 743 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 744 745 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 746 plane ? "B" : "A", size); 747 748 return size; 749 } 750 751 static int i85x_get_fifo_size(struct drm_device *dev, int plane) 752 { 753 struct drm_i915_private *dev_priv = dev->dev_private; 754 uint32_t dsparb = I915_READ(DSPARB); 755 int size; 756 757 size = dsparb & 0x1ff; 758 if (plane) 759 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 760 size >>= 1; /* Convert to cachelines */ 761 762 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 763 plane ? "B" : "A", size); 764 765 return size; 766 } 767 768 static int i845_get_fifo_size(struct drm_device *dev, int plane) 769 { 770 struct drm_i915_private *dev_priv = dev->dev_private; 771 uint32_t dsparb = I915_READ(DSPARB); 772 int size; 773 774 size = dsparb & 0x7f; 775 size >>= 2; /* Convert to cachelines */ 776 777 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 778 plane ? "B" : "A", 779 size); 780 781 return size; 782 } 783 784 static int i830_get_fifo_size(struct drm_device *dev, int plane) 785 { 786 struct drm_i915_private *dev_priv = dev->dev_private; 787 uint32_t dsparb = I915_READ(DSPARB); 788 int size; 789 790 size = dsparb & 0x7f; 791 size >>= 1; /* Convert to cachelines */ 792 793 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 794 plane ? "B" : "A", size); 795 796 return size; 797 } 798 799 /* Pineview has different values for various configs */ 800 static const struct intel_watermark_params pineview_display_wm = { 801 PINEVIEW_DISPLAY_FIFO, 802 PINEVIEW_MAX_WM, 803 PINEVIEW_DFT_WM, 804 PINEVIEW_GUARD_WM, 805 PINEVIEW_FIFO_LINE_SIZE 806 }; 807 static const struct intel_watermark_params pineview_display_hplloff_wm = { 808 PINEVIEW_DISPLAY_FIFO, 809 PINEVIEW_MAX_WM, 810 PINEVIEW_DFT_HPLLOFF_WM, 811 PINEVIEW_GUARD_WM, 812 PINEVIEW_FIFO_LINE_SIZE 813 }; 814 static const struct intel_watermark_params pineview_cursor_wm = { 815 PINEVIEW_CURSOR_FIFO, 816 PINEVIEW_CURSOR_MAX_WM, 817 PINEVIEW_CURSOR_DFT_WM, 818 PINEVIEW_CURSOR_GUARD_WM, 819 PINEVIEW_FIFO_LINE_SIZE, 820 }; 821 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 822 PINEVIEW_CURSOR_FIFO, 823 PINEVIEW_CURSOR_MAX_WM, 824 PINEVIEW_CURSOR_DFT_WM, 825 PINEVIEW_CURSOR_GUARD_WM, 826 PINEVIEW_FIFO_LINE_SIZE 827 }; 828 static const struct intel_watermark_params g4x_wm_info = { 829 G4X_FIFO_SIZE, 830 G4X_MAX_WM, 831 G4X_MAX_WM, 832 2, 833 G4X_FIFO_LINE_SIZE, 834 }; 835 static const struct intel_watermark_params g4x_cursor_wm_info = { 836 I965_CURSOR_FIFO, 837 I965_CURSOR_MAX_WM, 838 I965_CURSOR_DFT_WM, 839 2, 840 G4X_FIFO_LINE_SIZE, 841 }; 842 static const struct intel_watermark_params valleyview_wm_info = { 843 VALLEYVIEW_FIFO_SIZE, 844 VALLEYVIEW_MAX_WM, 845 VALLEYVIEW_MAX_WM, 846 2, 847 G4X_FIFO_LINE_SIZE, 848 }; 849 static const struct intel_watermark_params valleyview_cursor_wm_info = { 850 I965_CURSOR_FIFO, 851 VALLEYVIEW_CURSOR_MAX_WM, 852 I965_CURSOR_DFT_WM, 853 2, 854 G4X_FIFO_LINE_SIZE, 855 }; 856 static const struct intel_watermark_params i965_cursor_wm_info = { 857 I965_CURSOR_FIFO, 858 I965_CURSOR_MAX_WM, 859 I965_CURSOR_DFT_WM, 860 2, 861 I915_FIFO_LINE_SIZE, 862 }; 863 static const struct intel_watermark_params i945_wm_info = { 864 I945_FIFO_SIZE, 865 I915_MAX_WM, 866 1, 867 2, 868 I915_FIFO_LINE_SIZE 869 }; 870 static const struct intel_watermark_params i915_wm_info = { 871 I915_FIFO_SIZE, 872 I915_MAX_WM, 873 1, 874 2, 875 I915_FIFO_LINE_SIZE 876 }; 877 static const struct intel_watermark_params i855_wm_info = { 878 I855GM_FIFO_SIZE, 879 I915_MAX_WM, 880 1, 881 2, 882 I830_FIFO_LINE_SIZE 883 }; 884 static const struct intel_watermark_params i830_wm_info = { 885 I830_FIFO_SIZE, 886 I915_MAX_WM, 887 1, 888 2, 889 I830_FIFO_LINE_SIZE 890 }; 891 892 static const struct intel_watermark_params ironlake_display_wm_info = { 893 ILK_DISPLAY_FIFO, 894 ILK_DISPLAY_MAXWM, 895 ILK_DISPLAY_DFTWM, 896 2, 897 ILK_FIFO_LINE_SIZE 898 }; 899 static const struct intel_watermark_params ironlake_cursor_wm_info = { 900 ILK_CURSOR_FIFO, 901 ILK_CURSOR_MAXWM, 902 ILK_CURSOR_DFTWM, 903 2, 904 ILK_FIFO_LINE_SIZE 905 }; 906 static const struct intel_watermark_params ironlake_display_srwm_info = { 907 ILK_DISPLAY_SR_FIFO, 908 ILK_DISPLAY_MAX_SRWM, 909 ILK_DISPLAY_DFT_SRWM, 910 2, 911 ILK_FIFO_LINE_SIZE 912 }; 913 static const struct intel_watermark_params ironlake_cursor_srwm_info = { 914 ILK_CURSOR_SR_FIFO, 915 ILK_CURSOR_MAX_SRWM, 916 ILK_CURSOR_DFT_SRWM, 917 2, 918 ILK_FIFO_LINE_SIZE 919 }; 920 921 static const struct intel_watermark_params sandybridge_display_wm_info = { 922 SNB_DISPLAY_FIFO, 923 SNB_DISPLAY_MAXWM, 924 SNB_DISPLAY_DFTWM, 925 2, 926 SNB_FIFO_LINE_SIZE 927 }; 928 static const struct intel_watermark_params sandybridge_cursor_wm_info = { 929 SNB_CURSOR_FIFO, 930 SNB_CURSOR_MAXWM, 931 SNB_CURSOR_DFTWM, 932 2, 933 SNB_FIFO_LINE_SIZE 934 }; 935 static const struct intel_watermark_params sandybridge_display_srwm_info = { 936 SNB_DISPLAY_SR_FIFO, 937 SNB_DISPLAY_MAX_SRWM, 938 SNB_DISPLAY_DFT_SRWM, 939 2, 940 SNB_FIFO_LINE_SIZE 941 }; 942 static const struct intel_watermark_params sandybridge_cursor_srwm_info = { 943 SNB_CURSOR_SR_FIFO, 944 SNB_CURSOR_MAX_SRWM, 945 SNB_CURSOR_DFT_SRWM, 946 2, 947 SNB_FIFO_LINE_SIZE 948 }; 949 950 951 /** 952 * intel_calculate_wm - calculate watermark level 953 * @clock_in_khz: pixel clock 954 * @wm: chip FIFO params 955 * @pixel_size: display pixel size 956 * @latency_ns: memory latency for the platform 957 * 958 * Calculate the watermark level (the level at which the display plane will 959 * start fetching from memory again). Each chip has a different display 960 * FIFO size and allocation, so the caller needs to figure that out and pass 961 * in the correct intel_watermark_params structure. 962 * 963 * As the pixel clock runs, the FIFO will be drained at a rate that depends 964 * on the pixel size. When it reaches the watermark level, it'll start 965 * fetching FIFO line sized based chunks from memory until the FIFO fills 966 * past the watermark point. If the FIFO drains completely, a FIFO underrun 967 * will occur, and a display engine hang could result. 968 */ 969 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 970 const struct intel_watermark_params *wm, 971 int fifo_size, 972 int pixel_size, 973 unsigned long latency_ns) 974 { 975 long entries_required, wm_size; 976 977 /* 978 * Note: we need to make sure we don't overflow for various clock & 979 * latency values. 980 * clocks go from a few thousand to several hundred thousand. 981 * latency is usually a few thousand 982 */ 983 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 984 1000; 985 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 986 987 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 988 989 wm_size = fifo_size - (entries_required + wm->guard_size); 990 991 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 992 993 /* Don't promote wm_size to unsigned... */ 994 if (wm_size > (long)wm->max_wm) 995 wm_size = wm->max_wm; 996 if (wm_size <= 0) 997 wm_size = wm->default_wm; 998 return wm_size; 999 } 1000 1001 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 1002 { 1003 struct drm_crtc *crtc, *enabled = NULL; 1004 1005 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1006 if (intel_crtc_active(crtc)) { 1007 if (enabled) 1008 return NULL; 1009 enabled = crtc; 1010 } 1011 } 1012 1013 return enabled; 1014 } 1015 1016 static void pineview_update_wm(struct drm_device *dev) 1017 { 1018 struct drm_i915_private *dev_priv = dev->dev_private; 1019 struct drm_crtc *crtc; 1020 const struct cxsr_latency *latency; 1021 u32 reg; 1022 unsigned long wm; 1023 1024 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 1025 dev_priv->fsb_freq, dev_priv->mem_freq); 1026 if (!latency) { 1027 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 1028 pineview_disable_cxsr(dev); 1029 return; 1030 } 1031 1032 crtc = single_enabled_crtc(dev); 1033 if (crtc) { 1034 int clock = crtc->mode.clock; 1035 int pixel_size = crtc->fb->bits_per_pixel / 8; 1036 1037 /* Display SR */ 1038 wm = intel_calculate_wm(clock, &pineview_display_wm, 1039 pineview_display_wm.fifo_size, 1040 pixel_size, latency->display_sr); 1041 reg = I915_READ(DSPFW1); 1042 reg &= ~DSPFW_SR_MASK; 1043 reg |= wm << DSPFW_SR_SHIFT; 1044 I915_WRITE(DSPFW1, reg); 1045 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 1046 1047 /* cursor SR */ 1048 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 1049 pineview_display_wm.fifo_size, 1050 pixel_size, latency->cursor_sr); 1051 reg = I915_READ(DSPFW3); 1052 reg &= ~DSPFW_CURSOR_SR_MASK; 1053 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; 1054 I915_WRITE(DSPFW3, reg); 1055 1056 /* Display HPLL off SR */ 1057 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 1058 pineview_display_hplloff_wm.fifo_size, 1059 pixel_size, latency->display_hpll_disable); 1060 reg = I915_READ(DSPFW3); 1061 reg &= ~DSPFW_HPLL_SR_MASK; 1062 reg |= wm & DSPFW_HPLL_SR_MASK; 1063 I915_WRITE(DSPFW3, reg); 1064 1065 /* cursor HPLL off SR */ 1066 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 1067 pineview_display_hplloff_wm.fifo_size, 1068 pixel_size, latency->cursor_hpll_disable); 1069 reg = I915_READ(DSPFW3); 1070 reg &= ~DSPFW_HPLL_CURSOR_MASK; 1071 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; 1072 I915_WRITE(DSPFW3, reg); 1073 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 1074 1075 /* activate cxsr */ 1076 I915_WRITE(DSPFW3, 1077 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); 1078 DRM_DEBUG_KMS("Self-refresh is enabled\n"); 1079 } else { 1080 pineview_disable_cxsr(dev); 1081 DRM_DEBUG_KMS("Self-refresh is disabled\n"); 1082 } 1083 } 1084 1085 static bool g4x_compute_wm0(struct drm_device *dev, 1086 int plane, 1087 const struct intel_watermark_params *display, 1088 int display_latency_ns, 1089 const struct intel_watermark_params *cursor, 1090 int cursor_latency_ns, 1091 int *plane_wm, 1092 int *cursor_wm) 1093 { 1094 struct drm_crtc *crtc; 1095 int htotal, hdisplay, clock, pixel_size; 1096 int line_time_us, line_count; 1097 int entries, tlb_miss; 1098 1099 crtc = intel_get_crtc_for_plane(dev, plane); 1100 if (!intel_crtc_active(crtc)) { 1101 *cursor_wm = cursor->guard_size; 1102 *plane_wm = display->guard_size; 1103 return false; 1104 } 1105 1106 htotal = crtc->mode.htotal; 1107 hdisplay = crtc->mode.hdisplay; 1108 clock = crtc->mode.clock; 1109 pixel_size = crtc->fb->bits_per_pixel / 8; 1110 1111 /* Use the small buffer method to calculate plane watermark */ 1112 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 1113 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 1114 if (tlb_miss > 0) 1115 entries += tlb_miss; 1116 entries = DIV_ROUND_UP(entries, display->cacheline_size); 1117 *plane_wm = entries + display->guard_size; 1118 if (*plane_wm > (int)display->max_wm) 1119 *plane_wm = display->max_wm; 1120 1121 /* Use the large buffer method to calculate cursor watermark */ 1122 line_time_us = ((htotal * 1000) / clock); 1123 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 1124 entries = line_count * 64 * pixel_size; 1125 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 1126 if (tlb_miss > 0) 1127 entries += tlb_miss; 1128 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1129 *cursor_wm = entries + cursor->guard_size; 1130 if (*cursor_wm > (int)cursor->max_wm) 1131 *cursor_wm = (int)cursor->max_wm; 1132 1133 return true; 1134 } 1135 1136 /* 1137 * Check the wm result. 1138 * 1139 * If any calculated watermark values is larger than the maximum value that 1140 * can be programmed into the associated watermark register, that watermark 1141 * must be disabled. 1142 */ 1143 static bool g4x_check_srwm(struct drm_device *dev, 1144 int display_wm, int cursor_wm, 1145 const struct intel_watermark_params *display, 1146 const struct intel_watermark_params *cursor) 1147 { 1148 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 1149 display_wm, cursor_wm); 1150 1151 if (display_wm > display->max_wm) { 1152 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 1153 display_wm, display->max_wm); 1154 return false; 1155 } 1156 1157 if (cursor_wm > cursor->max_wm) { 1158 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 1159 cursor_wm, cursor->max_wm); 1160 return false; 1161 } 1162 1163 if (!(display_wm || cursor_wm)) { 1164 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 1165 return false; 1166 } 1167 1168 return true; 1169 } 1170 1171 static bool g4x_compute_srwm(struct drm_device *dev, 1172 int plane, 1173 int latency_ns, 1174 const struct intel_watermark_params *display, 1175 const struct intel_watermark_params *cursor, 1176 int *display_wm, int *cursor_wm) 1177 { 1178 struct drm_crtc *crtc; 1179 int hdisplay, htotal, pixel_size, clock; 1180 unsigned long line_time_us; 1181 int line_count, line_size; 1182 int small, large; 1183 int entries; 1184 1185 if (!latency_ns) { 1186 *display_wm = *cursor_wm = 0; 1187 return false; 1188 } 1189 1190 crtc = intel_get_crtc_for_plane(dev, plane); 1191 hdisplay = crtc->mode.hdisplay; 1192 htotal = crtc->mode.htotal; 1193 clock = crtc->mode.clock; 1194 pixel_size = crtc->fb->bits_per_pixel / 8; 1195 1196 line_time_us = (htotal * 1000) / clock; 1197 line_count = (latency_ns / line_time_us + 1000) / 1000; 1198 line_size = hdisplay * pixel_size; 1199 1200 /* Use the minimum of the small and large buffer method for primary */ 1201 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1202 large = line_count * line_size; 1203 1204 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 1205 *display_wm = entries + display->guard_size; 1206 1207 /* calculate the self-refresh watermark for display cursor */ 1208 entries = line_count * pixel_size * 64; 1209 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1210 *cursor_wm = entries + cursor->guard_size; 1211 1212 return g4x_check_srwm(dev, 1213 *display_wm, *cursor_wm, 1214 display, cursor); 1215 } 1216 1217 static bool vlv_compute_drain_latency(struct drm_device *dev, 1218 int plane, 1219 int *plane_prec_mult, 1220 int *plane_dl, 1221 int *cursor_prec_mult, 1222 int *cursor_dl) 1223 { 1224 struct drm_crtc *crtc; 1225 int clock, pixel_size; 1226 int entries; 1227 1228 crtc = intel_get_crtc_for_plane(dev, plane); 1229 if (!intel_crtc_active(crtc)) 1230 return false; 1231 1232 clock = crtc->mode.clock; /* VESA DOT Clock */ 1233 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ 1234 1235 entries = (clock / 1000) * pixel_size; 1236 *plane_prec_mult = (entries > 256) ? 1237 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; 1238 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * 1239 pixel_size); 1240 1241 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ 1242 *cursor_prec_mult = (entries > 256) ? 1243 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; 1244 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); 1245 1246 return true; 1247 } 1248 1249 /* 1250 * Update drain latency registers of memory arbiter 1251 * 1252 * Valleyview SoC has a new memory arbiter and needs drain latency registers 1253 * to be programmed. Each plane has a drain latency multiplier and a drain 1254 * latency value. 1255 */ 1256 1257 static void vlv_update_drain_latency(struct drm_device *dev) 1258 { 1259 struct drm_i915_private *dev_priv = dev->dev_private; 1260 int planea_prec, planea_dl, planeb_prec, planeb_dl; 1261 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; 1262 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is 1263 either 16 or 32 */ 1264 1265 /* For plane A, Cursor A */ 1266 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, 1267 &cursor_prec_mult, &cursora_dl)) { 1268 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1269 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; 1270 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1271 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; 1272 1273 I915_WRITE(VLV_DDL1, cursora_prec | 1274 (cursora_dl << DDL_CURSORA_SHIFT) | 1275 planea_prec | planea_dl); 1276 } 1277 1278 /* For plane B, Cursor B */ 1279 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, 1280 &cursor_prec_mult, &cursorb_dl)) { 1281 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1282 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; 1283 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1284 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; 1285 1286 I915_WRITE(VLV_DDL2, cursorb_prec | 1287 (cursorb_dl << DDL_CURSORB_SHIFT) | 1288 planeb_prec | planeb_dl); 1289 } 1290 } 1291 1292 #define single_plane_enabled(mask) is_power_of_2(mask) 1293 1294 static void valleyview_update_wm(struct drm_device *dev) 1295 { 1296 static const int sr_latency_ns = 12000; 1297 struct drm_i915_private *dev_priv = dev->dev_private; 1298 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1299 int plane_sr, cursor_sr; 1300 int ignore_plane_sr, ignore_cursor_sr; 1301 unsigned int enabled = 0; 1302 1303 vlv_update_drain_latency(dev); 1304 1305 if (g4x_compute_wm0(dev, PIPE_A, 1306 &valleyview_wm_info, latency_ns, 1307 &valleyview_cursor_wm_info, latency_ns, 1308 &planea_wm, &cursora_wm)) 1309 enabled |= 1 << PIPE_A; 1310 1311 if (g4x_compute_wm0(dev, PIPE_B, 1312 &valleyview_wm_info, latency_ns, 1313 &valleyview_cursor_wm_info, latency_ns, 1314 &planeb_wm, &cursorb_wm)) 1315 enabled |= 1 << PIPE_B; 1316 1317 if (single_plane_enabled(enabled) && 1318 g4x_compute_srwm(dev, ffs(enabled) - 1, 1319 sr_latency_ns, 1320 &valleyview_wm_info, 1321 &valleyview_cursor_wm_info, 1322 &plane_sr, &ignore_cursor_sr) && 1323 g4x_compute_srwm(dev, ffs(enabled) - 1, 1324 2*sr_latency_ns, 1325 &valleyview_wm_info, 1326 &valleyview_cursor_wm_info, 1327 &ignore_plane_sr, &cursor_sr)) { 1328 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); 1329 } else { 1330 I915_WRITE(FW_BLC_SELF_VLV, 1331 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); 1332 plane_sr = cursor_sr = 0; 1333 } 1334 1335 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1336 planea_wm, cursora_wm, 1337 planeb_wm, cursorb_wm, 1338 plane_sr, cursor_sr); 1339 1340 I915_WRITE(DSPFW1, 1341 (plane_sr << DSPFW_SR_SHIFT) | 1342 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1343 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1344 planea_wm); 1345 I915_WRITE(DSPFW2, 1346 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1347 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1348 I915_WRITE(DSPFW3, 1349 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | 1350 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1351 } 1352 1353 static void g4x_update_wm(struct drm_device *dev) 1354 { 1355 static const int sr_latency_ns = 12000; 1356 struct drm_i915_private *dev_priv = dev->dev_private; 1357 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1358 int plane_sr, cursor_sr; 1359 unsigned int enabled = 0; 1360 1361 if (g4x_compute_wm0(dev, PIPE_A, 1362 &g4x_wm_info, latency_ns, 1363 &g4x_cursor_wm_info, latency_ns, 1364 &planea_wm, &cursora_wm)) 1365 enabled |= 1 << PIPE_A; 1366 1367 if (g4x_compute_wm0(dev, PIPE_B, 1368 &g4x_wm_info, latency_ns, 1369 &g4x_cursor_wm_info, latency_ns, 1370 &planeb_wm, &cursorb_wm)) 1371 enabled |= 1 << PIPE_B; 1372 1373 if (single_plane_enabled(enabled) && 1374 g4x_compute_srwm(dev, ffs(enabled) - 1, 1375 sr_latency_ns, 1376 &g4x_wm_info, 1377 &g4x_cursor_wm_info, 1378 &plane_sr, &cursor_sr)) { 1379 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1380 } else { 1381 I915_WRITE(FW_BLC_SELF, 1382 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); 1383 plane_sr = cursor_sr = 0; 1384 } 1385 1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1387 planea_wm, cursora_wm, 1388 planeb_wm, cursorb_wm, 1389 plane_sr, cursor_sr); 1390 1391 I915_WRITE(DSPFW1, 1392 (plane_sr << DSPFW_SR_SHIFT) | 1393 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1394 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1395 planea_wm); 1396 I915_WRITE(DSPFW2, 1397 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1398 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1399 /* HPLL off in SR has some issues on G4x... disable it */ 1400 I915_WRITE(DSPFW3, 1401 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1402 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1403 } 1404 1405 static void i965_update_wm(struct drm_device *dev) 1406 { 1407 struct drm_i915_private *dev_priv = dev->dev_private; 1408 struct drm_crtc *crtc; 1409 int srwm = 1; 1410 int cursor_sr = 16; 1411 1412 /* Calc sr entries for one plane configs */ 1413 crtc = single_enabled_crtc(dev); 1414 if (crtc) { 1415 /* self-refresh has much higher latency */ 1416 static const int sr_latency_ns = 12000; 1417 int clock = crtc->mode.clock; 1418 int htotal = crtc->mode.htotal; 1419 int hdisplay = crtc->mode.hdisplay; 1420 int pixel_size = crtc->fb->bits_per_pixel / 8; 1421 unsigned long line_time_us; 1422 int entries; 1423 1424 line_time_us = ((htotal * 1000) / clock); 1425 1426 /* Use ns/us then divide to preserve precision */ 1427 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1428 pixel_size * hdisplay; 1429 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1430 srwm = I965_FIFO_SIZE - entries; 1431 if (srwm < 0) 1432 srwm = 1; 1433 srwm &= 0x1ff; 1434 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1435 entries, srwm); 1436 1437 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1438 pixel_size * 64; 1439 entries = DIV_ROUND_UP(entries, 1440 i965_cursor_wm_info.cacheline_size); 1441 cursor_sr = i965_cursor_wm_info.fifo_size - 1442 (entries + i965_cursor_wm_info.guard_size); 1443 1444 if (cursor_sr > i965_cursor_wm_info.max_wm) 1445 cursor_sr = i965_cursor_wm_info.max_wm; 1446 1447 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1448 "cursor %d\n", srwm, cursor_sr); 1449 1450 if (IS_CRESTLINE(dev)) 1451 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1452 } else { 1453 /* Turn off self refresh if both pipes are enabled */ 1454 if (IS_CRESTLINE(dev)) 1455 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) 1456 & ~FW_BLC_SELF_EN); 1457 } 1458 1459 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1460 srwm); 1461 1462 /* 965 has limitations... */ 1463 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | 1464 (8 << 16) | (8 << 8) | (8 << 0)); 1465 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 1466 /* update cursor SR watermark */ 1467 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1468 } 1469 1470 static void i9xx_update_wm(struct drm_device *dev) 1471 { 1472 struct drm_i915_private *dev_priv = dev->dev_private; 1473 const struct intel_watermark_params *wm_info; 1474 uint32_t fwater_lo; 1475 uint32_t fwater_hi; 1476 int cwm, srwm = 1; 1477 int fifo_size; 1478 int planea_wm, planeb_wm; 1479 struct drm_crtc *crtc, *enabled = NULL; 1480 1481 if (IS_I945GM(dev)) 1482 wm_info = &i945_wm_info; 1483 else if (!IS_GEN2(dev)) 1484 wm_info = &i915_wm_info; 1485 else 1486 wm_info = &i855_wm_info; 1487 1488 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1489 crtc = intel_get_crtc_for_plane(dev, 0); 1490 if (intel_crtc_active(crtc)) { 1491 int cpp = crtc->fb->bits_per_pixel / 8; 1492 if (IS_GEN2(dev)) 1493 cpp = 4; 1494 1495 planea_wm = intel_calculate_wm(crtc->mode.clock, 1496 wm_info, fifo_size, cpp, 1497 latency_ns); 1498 enabled = crtc; 1499 } else 1500 planea_wm = fifo_size - wm_info->guard_size; 1501 1502 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1503 crtc = intel_get_crtc_for_plane(dev, 1); 1504 if (intel_crtc_active(crtc)) { 1505 int cpp = crtc->fb->bits_per_pixel / 8; 1506 if (IS_GEN2(dev)) 1507 cpp = 4; 1508 1509 planeb_wm = intel_calculate_wm(crtc->mode.clock, 1510 wm_info, fifo_size, cpp, 1511 latency_ns); 1512 if (enabled == NULL) 1513 enabled = crtc; 1514 else 1515 enabled = NULL; 1516 } else 1517 planeb_wm = fifo_size - wm_info->guard_size; 1518 1519 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1520 1521 /* 1522 * Overlay gets an aggressive default since video jitter is bad. 1523 */ 1524 cwm = 2; 1525 1526 /* Play safe and disable self-refresh before adjusting watermarks. */ 1527 if (IS_I945G(dev) || IS_I945GM(dev)) 1528 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); 1529 else if (IS_I915GM(dev)) 1530 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); 1531 1532 /* Calc sr entries for one plane configs */ 1533 if (HAS_FW_BLC(dev) && enabled) { 1534 /* self-refresh has much higher latency */ 1535 static const int sr_latency_ns = 6000; 1536 int clock = enabled->mode.clock; 1537 int htotal = enabled->mode.htotal; 1538 int hdisplay = enabled->mode.hdisplay; 1539 int pixel_size = enabled->fb->bits_per_pixel / 8; 1540 unsigned long line_time_us; 1541 int entries; 1542 1543 line_time_us = (htotal * 1000) / clock; 1544 1545 /* Use ns/us then divide to preserve precision */ 1546 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1547 pixel_size * hdisplay; 1548 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1549 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1550 srwm = wm_info->fifo_size - entries; 1551 if (srwm < 0) 1552 srwm = 1; 1553 1554 if (IS_I945G(dev) || IS_I945GM(dev)) 1555 I915_WRITE(FW_BLC_SELF, 1556 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1557 else if (IS_I915GM(dev)) 1558 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1559 } 1560 1561 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1562 planea_wm, planeb_wm, cwm, srwm); 1563 1564 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1565 fwater_hi = (cwm & 0x1f); 1566 1567 /* Set request length to 8 cachelines per fetch */ 1568 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1569 fwater_hi = fwater_hi | (1 << 8); 1570 1571 I915_WRITE(FW_BLC, fwater_lo); 1572 I915_WRITE(FW_BLC2, fwater_hi); 1573 1574 if (HAS_FW_BLC(dev)) { 1575 if (enabled) { 1576 if (IS_I945G(dev) || IS_I945GM(dev)) 1577 I915_WRITE(FW_BLC_SELF, 1578 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); 1579 else if (IS_I915GM(dev)) 1580 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); 1581 DRM_DEBUG_KMS("memory self refresh enabled\n"); 1582 } else 1583 DRM_DEBUG_KMS("memory self refresh disabled\n"); 1584 } 1585 } 1586 1587 static void i830_update_wm(struct drm_device *dev) 1588 { 1589 struct drm_i915_private *dev_priv = dev->dev_private; 1590 struct drm_crtc *crtc; 1591 uint32_t fwater_lo; 1592 int planea_wm; 1593 1594 crtc = single_enabled_crtc(dev); 1595 if (crtc == NULL) 1596 return; 1597 1598 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, 1599 dev_priv->display.get_fifo_size(dev, 0), 1600 4, latency_ns); 1601 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1602 fwater_lo |= (3<<8) | planea_wm; 1603 1604 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1605 1606 I915_WRITE(FW_BLC, fwater_lo); 1607 } 1608 1609 #define ILK_LP0_PLANE_LATENCY 700 1610 #define ILK_LP0_CURSOR_LATENCY 1300 1611 1612 /* 1613 * Check the wm result. 1614 * 1615 * If any calculated watermark values is larger than the maximum value that 1616 * can be programmed into the associated watermark register, that watermark 1617 * must be disabled. 1618 */ 1619 static bool ironlake_check_srwm(struct drm_device *dev, int level, 1620 int fbc_wm, int display_wm, int cursor_wm, 1621 const struct intel_watermark_params *display, 1622 const struct intel_watermark_params *cursor) 1623 { 1624 struct drm_i915_private *dev_priv = dev->dev_private; 1625 1626 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," 1627 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); 1628 1629 if (fbc_wm > SNB_FBC_MAX_SRWM) { 1630 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", 1631 fbc_wm, SNB_FBC_MAX_SRWM, level); 1632 1633 /* fbc has it's own way to disable FBC WM */ 1634 I915_WRITE(DISP_ARB_CTL, 1635 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); 1636 return false; 1637 } 1638 1639 if (display_wm > display->max_wm) { 1640 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", 1641 display_wm, SNB_DISPLAY_MAX_SRWM, level); 1642 return false; 1643 } 1644 1645 if (cursor_wm > cursor->max_wm) { 1646 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", 1647 cursor_wm, SNB_CURSOR_MAX_SRWM, level); 1648 return false; 1649 } 1650 1651 if (!(fbc_wm || display_wm || cursor_wm)) { 1652 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); 1653 return false; 1654 } 1655 1656 return true; 1657 } 1658 1659 /* 1660 * Compute watermark values of WM[1-3], 1661 */ 1662 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, 1663 int latency_ns, 1664 const struct intel_watermark_params *display, 1665 const struct intel_watermark_params *cursor, 1666 int *fbc_wm, int *display_wm, int *cursor_wm) 1667 { 1668 struct drm_crtc *crtc; 1669 unsigned long line_time_us; 1670 int hdisplay, htotal, pixel_size, clock; 1671 int line_count, line_size; 1672 int small, large; 1673 int entries; 1674 1675 if (!latency_ns) { 1676 *fbc_wm = *display_wm = *cursor_wm = 0; 1677 return false; 1678 } 1679 1680 crtc = intel_get_crtc_for_plane(dev, plane); 1681 hdisplay = crtc->mode.hdisplay; 1682 htotal = crtc->mode.htotal; 1683 clock = crtc->mode.clock; 1684 pixel_size = crtc->fb->bits_per_pixel / 8; 1685 1686 line_time_us = (htotal * 1000) / clock; 1687 line_count = (latency_ns / line_time_us + 1000) / 1000; 1688 line_size = hdisplay * pixel_size; 1689 1690 /* Use the minimum of the small and large buffer method for primary */ 1691 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1692 large = line_count * line_size; 1693 1694 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 1695 *display_wm = entries + display->guard_size; 1696 1697 /* 1698 * Spec says: 1699 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 1700 */ 1701 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; 1702 1703 /* calculate the self-refresh watermark for display cursor */ 1704 entries = line_count * pixel_size * 64; 1705 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1706 *cursor_wm = entries + cursor->guard_size; 1707 1708 return ironlake_check_srwm(dev, level, 1709 *fbc_wm, *display_wm, *cursor_wm, 1710 display, cursor); 1711 } 1712 1713 static void ironlake_update_wm(struct drm_device *dev) 1714 { 1715 struct drm_i915_private *dev_priv = dev->dev_private; 1716 int fbc_wm, plane_wm, cursor_wm; 1717 unsigned int enabled; 1718 1719 enabled = 0; 1720 if (g4x_compute_wm0(dev, PIPE_A, 1721 &ironlake_display_wm_info, 1722 ILK_LP0_PLANE_LATENCY, 1723 &ironlake_cursor_wm_info, 1724 ILK_LP0_CURSOR_LATENCY, 1725 &plane_wm, &cursor_wm)) { 1726 I915_WRITE(WM0_PIPEA_ILK, 1727 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); 1728 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1729 " plane %d, " "cursor: %d\n", 1730 plane_wm, cursor_wm); 1731 enabled |= 1 << PIPE_A; 1732 } 1733 1734 if (g4x_compute_wm0(dev, PIPE_B, 1735 &ironlake_display_wm_info, 1736 ILK_LP0_PLANE_LATENCY, 1737 &ironlake_cursor_wm_info, 1738 ILK_LP0_CURSOR_LATENCY, 1739 &plane_wm, &cursor_wm)) { 1740 I915_WRITE(WM0_PIPEB_ILK, 1741 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); 1742 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1743 " plane %d, cursor: %d\n", 1744 plane_wm, cursor_wm); 1745 enabled |= 1 << PIPE_B; 1746 } 1747 1748 /* 1749 * Calculate and update the self-refresh watermark only when one 1750 * display plane is used. 1751 */ 1752 I915_WRITE(WM3_LP_ILK, 0); 1753 I915_WRITE(WM2_LP_ILK, 0); 1754 I915_WRITE(WM1_LP_ILK, 0); 1755 1756 if (!single_plane_enabled(enabled)) 1757 return; 1758 enabled = ffs(enabled) - 1; 1759 1760 /* WM1 */ 1761 if (!ironlake_compute_srwm(dev, 1, enabled, 1762 ILK_READ_WM1_LATENCY() * 500, 1763 &ironlake_display_srwm_info, 1764 &ironlake_cursor_srwm_info, 1765 &fbc_wm, &plane_wm, &cursor_wm)) 1766 return; 1767 1768 I915_WRITE(WM1_LP_ILK, 1769 WM1_LP_SR_EN | 1770 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1771 (fbc_wm << WM1_LP_FBC_SHIFT) | 1772 (plane_wm << WM1_LP_SR_SHIFT) | 1773 cursor_wm); 1774 1775 /* WM2 */ 1776 if (!ironlake_compute_srwm(dev, 2, enabled, 1777 ILK_READ_WM2_LATENCY() * 500, 1778 &ironlake_display_srwm_info, 1779 &ironlake_cursor_srwm_info, 1780 &fbc_wm, &plane_wm, &cursor_wm)) 1781 return; 1782 1783 I915_WRITE(WM2_LP_ILK, 1784 WM2_LP_EN | 1785 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1786 (fbc_wm << WM1_LP_FBC_SHIFT) | 1787 (plane_wm << WM1_LP_SR_SHIFT) | 1788 cursor_wm); 1789 1790 /* 1791 * WM3 is unsupported on ILK, probably because we don't have latency 1792 * data for that power state 1793 */ 1794 } 1795 1796 static void sandybridge_update_wm(struct drm_device *dev) 1797 { 1798 struct drm_i915_private *dev_priv = dev->dev_private; 1799 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 1800 u32 val; 1801 int fbc_wm, plane_wm, cursor_wm; 1802 unsigned int enabled; 1803 1804 enabled = 0; 1805 if (g4x_compute_wm0(dev, PIPE_A, 1806 &sandybridge_display_wm_info, latency, 1807 &sandybridge_cursor_wm_info, latency, 1808 &plane_wm, &cursor_wm)) { 1809 val = I915_READ(WM0_PIPEA_ILK); 1810 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1811 I915_WRITE(WM0_PIPEA_ILK, val | 1812 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1813 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1814 " plane %d, " "cursor: %d\n", 1815 plane_wm, cursor_wm); 1816 enabled |= 1 << PIPE_A; 1817 } 1818 1819 if (g4x_compute_wm0(dev, PIPE_B, 1820 &sandybridge_display_wm_info, latency, 1821 &sandybridge_cursor_wm_info, latency, 1822 &plane_wm, &cursor_wm)) { 1823 val = I915_READ(WM0_PIPEB_ILK); 1824 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1825 I915_WRITE(WM0_PIPEB_ILK, val | 1826 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1827 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1828 " plane %d, cursor: %d\n", 1829 plane_wm, cursor_wm); 1830 enabled |= 1 << PIPE_B; 1831 } 1832 1833 /* 1834 * Calculate and update the self-refresh watermark only when one 1835 * display plane is used. 1836 * 1837 * SNB support 3 levels of watermark. 1838 * 1839 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, 1840 * and disabled in the descending order 1841 * 1842 */ 1843 I915_WRITE(WM3_LP_ILK, 0); 1844 I915_WRITE(WM2_LP_ILK, 0); 1845 I915_WRITE(WM1_LP_ILK, 0); 1846 1847 if (!single_plane_enabled(enabled) || 1848 dev_priv->sprite_scaling_enabled) 1849 return; 1850 enabled = ffs(enabled) - 1; 1851 1852 /* WM1 */ 1853 if (!ironlake_compute_srwm(dev, 1, enabled, 1854 SNB_READ_WM1_LATENCY() * 500, 1855 &sandybridge_display_srwm_info, 1856 &sandybridge_cursor_srwm_info, 1857 &fbc_wm, &plane_wm, &cursor_wm)) 1858 return; 1859 1860 I915_WRITE(WM1_LP_ILK, 1861 WM1_LP_SR_EN | 1862 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1863 (fbc_wm << WM1_LP_FBC_SHIFT) | 1864 (plane_wm << WM1_LP_SR_SHIFT) | 1865 cursor_wm); 1866 1867 /* WM2 */ 1868 if (!ironlake_compute_srwm(dev, 2, enabled, 1869 SNB_READ_WM2_LATENCY() * 500, 1870 &sandybridge_display_srwm_info, 1871 &sandybridge_cursor_srwm_info, 1872 &fbc_wm, &plane_wm, &cursor_wm)) 1873 return; 1874 1875 I915_WRITE(WM2_LP_ILK, 1876 WM2_LP_EN | 1877 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1878 (fbc_wm << WM1_LP_FBC_SHIFT) | 1879 (plane_wm << WM1_LP_SR_SHIFT) | 1880 cursor_wm); 1881 1882 /* WM3 */ 1883 if (!ironlake_compute_srwm(dev, 3, enabled, 1884 SNB_READ_WM3_LATENCY() * 500, 1885 &sandybridge_display_srwm_info, 1886 &sandybridge_cursor_srwm_info, 1887 &fbc_wm, &plane_wm, &cursor_wm)) 1888 return; 1889 1890 I915_WRITE(WM3_LP_ILK, 1891 WM3_LP_EN | 1892 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1893 (fbc_wm << WM1_LP_FBC_SHIFT) | 1894 (plane_wm << WM1_LP_SR_SHIFT) | 1895 cursor_wm); 1896 } 1897 1898 static void ivybridge_update_wm(struct drm_device *dev) 1899 { 1900 struct drm_i915_private *dev_priv = dev->dev_private; 1901 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 1902 u32 val; 1903 int fbc_wm, plane_wm, cursor_wm; 1904 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm; 1905 unsigned int enabled; 1906 1907 enabled = 0; 1908 if (g4x_compute_wm0(dev, PIPE_A, 1909 &sandybridge_display_wm_info, latency, 1910 &sandybridge_cursor_wm_info, latency, 1911 &plane_wm, &cursor_wm)) { 1912 val = I915_READ(WM0_PIPEA_ILK); 1913 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1914 I915_WRITE(WM0_PIPEA_ILK, val | 1915 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1916 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1917 " plane %d, " "cursor: %d\n", 1918 plane_wm, cursor_wm); 1919 enabled |= 1 << PIPE_A; 1920 } 1921 1922 if (g4x_compute_wm0(dev, PIPE_B, 1923 &sandybridge_display_wm_info, latency, 1924 &sandybridge_cursor_wm_info, latency, 1925 &plane_wm, &cursor_wm)) { 1926 val = I915_READ(WM0_PIPEB_ILK); 1927 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1928 I915_WRITE(WM0_PIPEB_ILK, val | 1929 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1930 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1931 " plane %d, cursor: %d\n", 1932 plane_wm, cursor_wm); 1933 enabled |= 1 << PIPE_B; 1934 } 1935 1936 if (g4x_compute_wm0(dev, PIPE_C, 1937 &sandybridge_display_wm_info, latency, 1938 &sandybridge_cursor_wm_info, latency, 1939 &plane_wm, &cursor_wm)) { 1940 val = I915_READ(WM0_PIPEC_IVB); 1941 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1942 I915_WRITE(WM0_PIPEC_IVB, val | 1943 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1944 DRM_DEBUG_KMS("FIFO watermarks For pipe C -" 1945 " plane %d, cursor: %d\n", 1946 plane_wm, cursor_wm); 1947 enabled |= 1 << PIPE_C; 1948 } 1949 1950 /* 1951 * Calculate and update the self-refresh watermark only when one 1952 * display plane is used. 1953 * 1954 * SNB support 3 levels of watermark. 1955 * 1956 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, 1957 * and disabled in the descending order 1958 * 1959 */ 1960 I915_WRITE(WM3_LP_ILK, 0); 1961 I915_WRITE(WM2_LP_ILK, 0); 1962 I915_WRITE(WM1_LP_ILK, 0); 1963 1964 if (!single_plane_enabled(enabled) || 1965 dev_priv->sprite_scaling_enabled) 1966 return; 1967 enabled = ffs(enabled) - 1; 1968 1969 /* WM1 */ 1970 if (!ironlake_compute_srwm(dev, 1, enabled, 1971 SNB_READ_WM1_LATENCY() * 500, 1972 &sandybridge_display_srwm_info, 1973 &sandybridge_cursor_srwm_info, 1974 &fbc_wm, &plane_wm, &cursor_wm)) 1975 return; 1976 1977 I915_WRITE(WM1_LP_ILK, 1978 WM1_LP_SR_EN | 1979 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1980 (fbc_wm << WM1_LP_FBC_SHIFT) | 1981 (plane_wm << WM1_LP_SR_SHIFT) | 1982 cursor_wm); 1983 1984 /* WM2 */ 1985 if (!ironlake_compute_srwm(dev, 2, enabled, 1986 SNB_READ_WM2_LATENCY() * 500, 1987 &sandybridge_display_srwm_info, 1988 &sandybridge_cursor_srwm_info, 1989 &fbc_wm, &plane_wm, &cursor_wm)) 1990 return; 1991 1992 I915_WRITE(WM2_LP_ILK, 1993 WM2_LP_EN | 1994 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1995 (fbc_wm << WM1_LP_FBC_SHIFT) | 1996 (plane_wm << WM1_LP_SR_SHIFT) | 1997 cursor_wm); 1998 1999 /* WM3, note we have to correct the cursor latency */ 2000 if (!ironlake_compute_srwm(dev, 3, enabled, 2001 SNB_READ_WM3_LATENCY() * 500, 2002 &sandybridge_display_srwm_info, 2003 &sandybridge_cursor_srwm_info, 2004 &fbc_wm, &plane_wm, &ignore_cursor_wm) || 2005 !ironlake_compute_srwm(dev, 3, enabled, 2006 2 * SNB_READ_WM3_LATENCY() * 500, 2007 &sandybridge_display_srwm_info, 2008 &sandybridge_cursor_srwm_info, 2009 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm)) 2010 return; 2011 2012 I915_WRITE(WM3_LP_ILK, 2013 WM3_LP_EN | 2014 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | 2015 (fbc_wm << WM1_LP_FBC_SHIFT) | 2016 (plane_wm << WM1_LP_SR_SHIFT) | 2017 cursor_wm); 2018 } 2019 2020 static void 2021 haswell_update_linetime_wm(struct drm_device *dev, int pipe, 2022 struct drm_display_mode *mode) 2023 { 2024 struct drm_i915_private *dev_priv = dev->dev_private; 2025 u32 temp; 2026 2027 temp = I915_READ(PIPE_WM_LINETIME(pipe)); 2028 temp &= ~PIPE_WM_LINETIME_MASK; 2029 2030 /* The WM are computed with base on how long it takes to fill a single 2031 * row at the given clock rate, multiplied by 8. 2032 * */ 2033 temp |= PIPE_WM_LINETIME_TIME( 2034 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8); 2035 2036 /* IPS watermarks are only used by pipe A, and are ignored by 2037 * pipes B and C. They are calculated similarly to the common 2038 * linetime values, except that we are using CD clock frequency 2039 * in MHz instead of pixel rate for the division. 2040 * 2041 * This is a placeholder for the IPS watermark calculation code. 2042 */ 2043 2044 I915_WRITE(PIPE_WM_LINETIME(pipe), temp); 2045 } 2046 2047 static bool 2048 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, 2049 uint32_t sprite_width, int pixel_size, 2050 const struct intel_watermark_params *display, 2051 int display_latency_ns, int *sprite_wm) 2052 { 2053 struct drm_crtc *crtc; 2054 int clock; 2055 int entries, tlb_miss; 2056 2057 crtc = intel_get_crtc_for_plane(dev, plane); 2058 if (!intel_crtc_active(crtc)) { 2059 *sprite_wm = display->guard_size; 2060 return false; 2061 } 2062 2063 clock = crtc->mode.clock; 2064 2065 /* Use the small buffer method to calculate the sprite watermark */ 2066 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 2067 tlb_miss = display->fifo_size*display->cacheline_size - 2068 sprite_width * 8; 2069 if (tlb_miss > 0) 2070 entries += tlb_miss; 2071 entries = DIV_ROUND_UP(entries, display->cacheline_size); 2072 *sprite_wm = entries + display->guard_size; 2073 if (*sprite_wm > (int)display->max_wm) 2074 *sprite_wm = display->max_wm; 2075 2076 return true; 2077 } 2078 2079 static bool 2080 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, 2081 uint32_t sprite_width, int pixel_size, 2082 const struct intel_watermark_params *display, 2083 int latency_ns, int *sprite_wm) 2084 { 2085 struct drm_crtc *crtc; 2086 unsigned long line_time_us; 2087 int clock; 2088 int line_count, line_size; 2089 int small, large; 2090 int entries; 2091 2092 if (!latency_ns) { 2093 *sprite_wm = 0; 2094 return false; 2095 } 2096 2097 crtc = intel_get_crtc_for_plane(dev, plane); 2098 clock = crtc->mode.clock; 2099 if (!clock) { 2100 *sprite_wm = 0; 2101 return false; 2102 } 2103 2104 line_time_us = (sprite_width * 1000) / clock; 2105 if (!line_time_us) { 2106 *sprite_wm = 0; 2107 return false; 2108 } 2109 2110 line_count = (latency_ns / line_time_us + 1000) / 1000; 2111 line_size = sprite_width * pixel_size; 2112 2113 /* Use the minimum of the small and large buffer method for primary */ 2114 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 2115 large = line_count * line_size; 2116 2117 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 2118 *sprite_wm = entries + display->guard_size; 2119 2120 return *sprite_wm > 0x3ff ? false : true; 2121 } 2122 2123 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, 2124 uint32_t sprite_width, int pixel_size) 2125 { 2126 struct drm_i915_private *dev_priv = dev->dev_private; 2127 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 2128 u32 val; 2129 int sprite_wm, reg; 2130 int ret; 2131 2132 switch (pipe) { 2133 case 0: 2134 reg = WM0_PIPEA_ILK; 2135 break; 2136 case 1: 2137 reg = WM0_PIPEB_ILK; 2138 break; 2139 case 2: 2140 reg = WM0_PIPEC_IVB; 2141 break; 2142 default: 2143 return; /* bad pipe */ 2144 } 2145 2146 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, 2147 &sandybridge_display_wm_info, 2148 latency, &sprite_wm); 2149 if (!ret) { 2150 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", 2151 pipe); 2152 return; 2153 } 2154 2155 val = I915_READ(reg); 2156 val &= ~WM0_PIPE_SPRITE_MASK; 2157 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); 2158 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); 2159 2160 2161 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2162 pixel_size, 2163 &sandybridge_display_srwm_info, 2164 SNB_READ_WM1_LATENCY() * 500, 2165 &sprite_wm); 2166 if (!ret) { 2167 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", 2168 pipe); 2169 return; 2170 } 2171 I915_WRITE(WM1S_LP_ILK, sprite_wm); 2172 2173 /* Only IVB has two more LP watermarks for sprite */ 2174 if (!IS_IVYBRIDGE(dev)) 2175 return; 2176 2177 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2178 pixel_size, 2179 &sandybridge_display_srwm_info, 2180 SNB_READ_WM2_LATENCY() * 500, 2181 &sprite_wm); 2182 if (!ret) { 2183 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", 2184 pipe); 2185 return; 2186 } 2187 I915_WRITE(WM2S_LP_IVB, sprite_wm); 2188 2189 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2190 pixel_size, 2191 &sandybridge_display_srwm_info, 2192 SNB_READ_WM3_LATENCY() * 500, 2193 &sprite_wm); 2194 if (!ret) { 2195 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", 2196 pipe); 2197 return; 2198 } 2199 I915_WRITE(WM3S_LP_IVB, sprite_wm); 2200 } 2201 2202 /** 2203 * intel_update_watermarks - update FIFO watermark values based on current modes 2204 * 2205 * Calculate watermark values for the various WM regs based on current mode 2206 * and plane configuration. 2207 * 2208 * There are several cases to deal with here: 2209 * - normal (i.e. non-self-refresh) 2210 * - self-refresh (SR) mode 2211 * - lines are large relative to FIFO size (buffer can hold up to 2) 2212 * - lines are small relative to FIFO size (buffer can hold more than 2 2213 * lines), so need to account for TLB latency 2214 * 2215 * The normal calculation is: 2216 * watermark = dotclock * bytes per pixel * latency 2217 * where latency is platform & configuration dependent (we assume pessimal 2218 * values here). 2219 * 2220 * The SR calculation is: 2221 * watermark = (trunc(latency/line time)+1) * surface width * 2222 * bytes per pixel 2223 * where 2224 * line time = htotal / dotclock 2225 * surface width = hdisplay for normal plane and 64 for cursor 2226 * and latency is assumed to be high, as above. 2227 * 2228 * The final value programmed to the register should always be rounded up, 2229 * and include an extra 2 entries to account for clock crossings. 2230 * 2231 * We don't use the sprite, so we can ignore that. And on Crestline we have 2232 * to set the non-SR watermarks to 8. 2233 */ 2234 void intel_update_watermarks(struct drm_device *dev) 2235 { 2236 struct drm_i915_private *dev_priv = dev->dev_private; 2237 2238 if (dev_priv->display.update_wm) 2239 dev_priv->display.update_wm(dev); 2240 } 2241 2242 void intel_update_linetime_watermarks(struct drm_device *dev, 2243 int pipe, struct drm_display_mode *mode) 2244 { 2245 struct drm_i915_private *dev_priv = dev->dev_private; 2246 2247 if (dev_priv->display.update_linetime_wm) 2248 dev_priv->display.update_linetime_wm(dev, pipe, mode); 2249 } 2250 2251 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 2252 uint32_t sprite_width, int pixel_size) 2253 { 2254 struct drm_i915_private *dev_priv = dev->dev_private; 2255 2256 if (dev_priv->display.update_sprite_wm) 2257 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, 2258 pixel_size); 2259 } 2260 2261 static struct drm_i915_gem_object * 2262 intel_alloc_context_page(struct drm_device *dev) 2263 { 2264 struct drm_i915_gem_object *ctx; 2265 int ret; 2266 2267 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2268 2269 ctx = i915_gem_alloc_object(dev, 4096); 2270 if (!ctx) { 2271 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 2272 return NULL; 2273 } 2274 2275 ret = i915_gem_object_pin(ctx, 4096, true, false); 2276 if (ret) { 2277 DRM_ERROR("failed to pin power context: %d\n", ret); 2278 goto err_unref; 2279 } 2280 2281 ret = i915_gem_object_set_to_gtt_domain(ctx, 1); 2282 if (ret) { 2283 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 2284 goto err_unpin; 2285 } 2286 2287 return ctx; 2288 2289 err_unpin: 2290 i915_gem_object_unpin(ctx); 2291 err_unref: 2292 drm_gem_object_unreference(&ctx->base); 2293 return NULL; 2294 } 2295 2296 /** 2297 * Lock protecting IPS related data structures 2298 */ 2299 struct lock mchdev_lock; 2300 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE); 2301 2302 /* Global for IPS driver to get at the current i915 device. Protected by 2303 * mchdev_lock. */ 2304 static struct drm_i915_private *i915_mch_dev; 2305 2306 bool ironlake_set_drps(struct drm_device *dev, u8 val) 2307 { 2308 struct drm_i915_private *dev_priv = dev->dev_private; 2309 u16 rgvswctl; 2310 2311 rgvswctl = I915_READ16(MEMSWCTL); 2312 if (rgvswctl & MEMCTL_CMD_STS) { 2313 DRM_DEBUG("gpu busy, RCS change rejected\n"); 2314 return false; /* still busy with another command */ 2315 } 2316 2317 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 2318 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 2319 I915_WRITE16(MEMSWCTL, rgvswctl); 2320 POSTING_READ16(MEMSWCTL); 2321 2322 rgvswctl |= MEMCTL_CMD_STS; 2323 I915_WRITE16(MEMSWCTL, rgvswctl); 2324 2325 return true; 2326 } 2327 2328 static void ironlake_enable_drps(struct drm_device *dev) 2329 { 2330 struct drm_i915_private *dev_priv = dev->dev_private; 2331 u32 rgvmodectl = I915_READ(MEMMODECTL); 2332 u8 fmax, fmin, fstart, vstart; 2333 2334 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2335 2336 /* Enable temp reporting */ 2337 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 2338 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 2339 2340 /* 100ms RC evaluation intervals */ 2341 I915_WRITE(RCUPEI, 100000); 2342 I915_WRITE(RCDNEI, 100000); 2343 2344 /* Set max/min thresholds to 90ms and 80ms respectively */ 2345 I915_WRITE(RCBMAXAVG, 90000); 2346 I915_WRITE(RCBMINAVG, 80000); 2347 2348 I915_WRITE(MEMIHYST, 1); 2349 2350 /* Set up min, max, and cur for interrupt handling */ 2351 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 2352 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 2353 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 2354 MEMMODE_FSTART_SHIFT; 2355 2356 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> 2357 PXVFREQ_PX_SHIFT; 2358 2359 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 2360 dev_priv->ips.fstart = fstart; 2361 2362 dev_priv->ips.max_delay = fstart; 2363 dev_priv->ips.min_delay = fmin; 2364 dev_priv->ips.cur_delay = fstart; 2365 2366 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 2367 fmax, fmin, fstart); 2368 2369 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 2370 2371 /* 2372 * Interrupts will be enabled in ironlake_irq_postinstall 2373 */ 2374 2375 I915_WRITE(VIDSTART, vstart); 2376 POSTING_READ(VIDSTART); 2377 2378 rgvmodectl |= MEMMODE_SWMODE_EN; 2379 I915_WRITE(MEMMODECTL, rgvmodectl); 2380 2381 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 2382 DRM_ERROR("stuck trying to change perf mode\n"); 2383 mdelay(1); 2384 2385 ironlake_set_drps(dev, fstart); 2386 2387 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + 2388 I915_READ(0x112e0); 2389 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 2390 dev_priv->ips.last_count2 = I915_READ(0x112f4); 2391 getrawmonotonic(&dev_priv->ips.last_time2); 2392 2393 lockmgr(&mchdev_lock, LK_RELEASE); 2394 } 2395 2396 static void ironlake_disable_drps(struct drm_device *dev) 2397 { 2398 struct drm_i915_private *dev_priv = dev->dev_private; 2399 u16 rgvswctl; 2400 2401 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2402 2403 rgvswctl = I915_READ16(MEMSWCTL); 2404 2405 /* Ack interrupts, disable EFC interrupt */ 2406 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 2407 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 2408 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 2409 I915_WRITE(DEIIR, DE_PCU_EVENT); 2410 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 2411 2412 /* Go back to the starting frequency */ 2413 ironlake_set_drps(dev, dev_priv->ips.fstart); 2414 mdelay(1); 2415 rgvswctl |= MEMCTL_CMD_STS; 2416 I915_WRITE(MEMSWCTL, rgvswctl); 2417 mdelay(1); 2418 2419 lockmgr(&mchdev_lock, LK_RELEASE); 2420 } 2421 2422 /* There's a funny hw issue where the hw returns all 0 when reading from 2423 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 2424 * ourselves, instead of doing a rmw cycle (which might result in us clearing 2425 * all limits and the gpu stuck at whatever frequency it is at atm). 2426 */ 2427 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) 2428 { 2429 u32 limits; 2430 2431 limits = 0; 2432 2433 if (*val >= dev_priv->rps.max_delay) 2434 *val = dev_priv->rps.max_delay; 2435 limits |= dev_priv->rps.max_delay << 24; 2436 2437 /* Only set the down limit when we've reached the lowest level to avoid 2438 * getting more interrupts, otherwise leave this clear. This prevents a 2439 * race in the hw when coming out of rc6: There's a tiny window where 2440 * the hw runs at the minimal clock before selecting the desired 2441 * frequency, if the down threshold expires in that window we will not 2442 * receive a down interrupt. */ 2443 if (*val <= dev_priv->rps.min_delay) { 2444 *val = dev_priv->rps.min_delay; 2445 limits |= dev_priv->rps.min_delay << 16; 2446 } 2447 2448 return limits; 2449 } 2450 2451 void gen6_set_rps(struct drm_device *dev, u8 val) 2452 { 2453 struct drm_i915_private *dev_priv = dev->dev_private; 2454 u32 limits = gen6_rps_limits(dev_priv, &val); 2455 2456 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2457 WARN_ON(val > dev_priv->rps.max_delay); 2458 WARN_ON(val < dev_priv->rps.min_delay); 2459 2460 if (val == dev_priv->rps.cur_delay) 2461 return; 2462 2463 if (IS_HASWELL(dev)) 2464 I915_WRITE(GEN6_RPNSWREQ, 2465 HSW_FREQUENCY(val)); 2466 else 2467 I915_WRITE(GEN6_RPNSWREQ, 2468 GEN6_FREQUENCY(val) | 2469 GEN6_OFFSET(0) | 2470 GEN6_AGGRESSIVE_TURBO); 2471 2472 /* Make sure we continue to get interrupts 2473 * until we hit the minimum or maximum frequencies. 2474 */ 2475 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); 2476 2477 POSTING_READ(GEN6_RPNSWREQ); 2478 2479 dev_priv->rps.cur_delay = val; 2480 2481 trace_intel_gpu_freq_change(val * 50); 2482 } 2483 2484 static void gen6_disable_rps(struct drm_device *dev) 2485 { 2486 struct drm_i915_private *dev_priv = dev->dev_private; 2487 2488 I915_WRITE(GEN6_RC_CONTROL, 0); 2489 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 2490 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 2491 I915_WRITE(GEN6_PMIER, 0); 2492 /* Complete PM interrupt masking here doesn't race with the rps work 2493 * item again unmasking PM interrupts because that is using a different 2494 * register (PMIMR) to mask PM interrupts. The only risk is in leaving 2495 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ 2496 2497 spin_lock(&dev_priv->rps.lock); 2498 dev_priv->rps.pm_iir = 0; 2499 spin_unlock(&dev_priv->rps.lock); 2500 2501 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); 2502 } 2503 2504 int intel_enable_rc6(const struct drm_device *dev) 2505 { 2506 /* Respect the kernel parameter if it is set */ 2507 if (i915_enable_rc6 >= 0) 2508 return i915_enable_rc6; 2509 2510 /* Disable RC6 on Ironlake */ 2511 if (INTEL_INFO(dev)->gen == 5) 2512 return 0; 2513 2514 if (IS_HASWELL(dev)) { 2515 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); 2516 return INTEL_RC6_ENABLE; 2517 } 2518 2519 /* snb/ivb have more than one rc6 state. */ 2520 if (INTEL_INFO(dev)->gen == 6) { 2521 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); 2522 return INTEL_RC6_ENABLE; 2523 } 2524 2525 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); 2526 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 2527 } 2528 2529 static void gen6_enable_rps(struct drm_device *dev) 2530 { 2531 struct drm_i915_private *dev_priv = dev->dev_private; 2532 struct intel_ring_buffer *ring; 2533 u32 rp_state_cap; 2534 u32 gt_perf_status; 2535 u32 rc6vids, pcu_mbox, rc6_mask = 0; 2536 u32 gtfifodbg; 2537 int rc6_mode; 2538 int i, ret; 2539 2540 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2541 2542 /* Here begins a magic sequence of register writes to enable 2543 * auto-downclocking. 2544 * 2545 * Perhaps there might be some value in exposing these to 2546 * userspace... 2547 */ 2548 I915_WRITE(GEN6_RC_STATE, 0); 2549 2550 /* Clear the DBG now so we don't confuse earlier errors */ 2551 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 2552 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 2553 I915_WRITE(GTFIFODBG, gtfifodbg); 2554 } 2555 2556 gen6_gt_force_wake_get(dev_priv); 2557 2558 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 2559 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 2560 2561 /* In units of 50MHz */ 2562 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff; 2563 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; 2564 dev_priv->rps.cur_delay = 0; 2565 2566 /* disable the counters and set deterministic thresholds */ 2567 I915_WRITE(GEN6_RC_CONTROL, 0); 2568 2569 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 2570 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 2571 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 2572 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 2573 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 2574 2575 for_each_ring(ring, dev_priv, i) 2576 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 2577 2578 I915_WRITE(GEN6_RC_SLEEP, 0); 2579 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 2580 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 2581 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); 2582 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 2583 2584 /* Check if we are enabling RC6 */ 2585 rc6_mode = intel_enable_rc6(dev_priv->dev); 2586 if (rc6_mode & INTEL_RC6_ENABLE) 2587 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 2588 2589 /* We don't use those on Haswell */ 2590 if (!IS_HASWELL(dev)) { 2591 if (rc6_mode & INTEL_RC6p_ENABLE) 2592 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 2593 2594 if (rc6_mode & INTEL_RC6pp_ENABLE) 2595 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 2596 } 2597 2598 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", 2599 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 2600 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 2601 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 2602 2603 I915_WRITE(GEN6_RC_CONTROL, 2604 rc6_mask | 2605 GEN6_RC_CTL_EI_MODE(1) | 2606 GEN6_RC_CTL_HW_ENABLE); 2607 2608 if (IS_HASWELL(dev)) { 2609 I915_WRITE(GEN6_RPNSWREQ, 2610 HSW_FREQUENCY(10)); 2611 I915_WRITE(GEN6_RC_VIDEO_FREQ, 2612 HSW_FREQUENCY(12)); 2613 } else { 2614 I915_WRITE(GEN6_RPNSWREQ, 2615 GEN6_FREQUENCY(10) | 2616 GEN6_OFFSET(0) | 2617 GEN6_AGGRESSIVE_TURBO); 2618 I915_WRITE(GEN6_RC_VIDEO_FREQ, 2619 GEN6_FREQUENCY(12)); 2620 } 2621 2622 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 2623 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 2624 dev_priv->rps.max_delay << 24 | 2625 dev_priv->rps.min_delay << 16); 2626 2627 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 2628 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 2629 I915_WRITE(GEN6_RP_UP_EI, 66000); 2630 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 2631 2632 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 2633 I915_WRITE(GEN6_RP_CONTROL, 2634 GEN6_RP_MEDIA_TURBO | 2635 GEN6_RP_MEDIA_HW_NORMAL_MODE | 2636 GEN6_RP_MEDIA_IS_GFX | 2637 GEN6_RP_ENABLE | 2638 GEN6_RP_UP_BUSY_AVG | 2639 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); 2640 2641 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 2642 if (!ret) { 2643 pcu_mbox = 0; 2644 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 2645 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ 2646 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", 2647 (dev_priv->rps.max_delay & 0xff) * 50, 2648 (pcu_mbox & 0xff) * 50); 2649 dev_priv->rps.hw_max = pcu_mbox & 0xff; 2650 } 2651 } else { 2652 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 2653 } 2654 2655 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); 2656 2657 /* requires MSI enabled */ 2658 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); 2659 spin_lock(&dev_priv->rps.lock); 2660 WARN_ON(dev_priv->rps.pm_iir != 0); 2661 I915_WRITE(GEN6_PMIMR, 0); 2662 spin_unlock(&dev_priv->rps.lock); 2663 /* enable all PM interrupts */ 2664 I915_WRITE(GEN6_PMINTRMSK, 0); 2665 2666 rc6vids = 0; 2667 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 2668 if (IS_GEN6(dev) && ret) { 2669 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 2670 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 2671 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 2672 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 2673 rc6vids &= 0xffff00; 2674 rc6vids |= GEN6_ENCODE_RC6_VID(450); 2675 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 2676 if (ret) 2677 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 2678 } 2679 2680 gen6_gt_force_wake_put(dev_priv); 2681 } 2682 2683 static void gen6_update_ring_freq(struct drm_device *dev) 2684 { 2685 struct drm_i915_private *dev_priv = dev->dev_private; 2686 int min_freq = 15; 2687 unsigned int gpu_freq; 2688 unsigned int max_ia_freq, min_ring_freq; 2689 int scaling_factor = 180; 2690 2691 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2692 2693 #if 0 2694 max_ia_freq = cpufreq_quick_get_max(0); 2695 /* 2696 * Default to measured freq if none found, PCU will ensure we don't go 2697 * over 2698 */ 2699 if (!max_ia_freq) 2700 max_ia_freq = tsc_khz; 2701 #else 2702 max_ia_freq = tsc_frequency / 1000; 2703 #endif 2704 2705 /* Convert from kHz to MHz */ 2706 max_ia_freq /= 1000; 2707 2708 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK); 2709 /* convert DDR frequency from units of 133.3MHz to bandwidth */ 2710 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3; 2711 2712 /* 2713 * For each potential GPU frequency, load a ring frequency we'd like 2714 * to use for memory access. We do this by specifying the IA frequency 2715 * the PCU should use as a reference to determine the ring frequency. 2716 */ 2717 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; 2718 gpu_freq--) { 2719 int diff = dev_priv->rps.max_delay - gpu_freq; 2720 unsigned int ia_freq = 0, ring_freq = 0; 2721 2722 if (IS_HASWELL(dev)) { 2723 ring_freq = (gpu_freq * 5 + 3) / 4; 2724 ring_freq = max(min_ring_freq, ring_freq); 2725 /* leave ia_freq as the default, chosen by cpufreq */ 2726 } else { 2727 /* On older processors, there is no separate ring 2728 * clock domain, so in order to boost the bandwidth 2729 * of the ring, we need to upclock the CPU (ia_freq). 2730 * 2731 * For GPU frequencies less than 750MHz, 2732 * just use the lowest ring freq. 2733 */ 2734 if (gpu_freq < min_freq) 2735 ia_freq = 800; 2736 else 2737 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 2738 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 2739 } 2740 2741 sandybridge_pcode_write(dev_priv, 2742 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 2743 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 2744 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 2745 gpu_freq); 2746 } 2747 } 2748 2749 void ironlake_teardown_rc6(struct drm_device *dev) 2750 { 2751 struct drm_i915_private *dev_priv = dev->dev_private; 2752 2753 if (dev_priv->ips.renderctx) { 2754 i915_gem_object_unpin(dev_priv->ips.renderctx); 2755 drm_gem_object_unreference(&dev_priv->ips.renderctx->base); 2756 dev_priv->ips.renderctx = NULL; 2757 } 2758 2759 if (dev_priv->ips.pwrctx) { 2760 i915_gem_object_unpin(dev_priv->ips.pwrctx); 2761 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); 2762 dev_priv->ips.pwrctx = NULL; 2763 } 2764 } 2765 2766 static void ironlake_disable_rc6(struct drm_device *dev) 2767 { 2768 struct drm_i915_private *dev_priv = dev->dev_private; 2769 2770 if (I915_READ(PWRCTXA)) { 2771 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ 2772 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); 2773 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), 2774 50); 2775 2776 I915_WRITE(PWRCTXA, 0); 2777 POSTING_READ(PWRCTXA); 2778 2779 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 2780 POSTING_READ(RSTDBYCTL); 2781 } 2782 } 2783 2784 static int ironlake_setup_rc6(struct drm_device *dev) 2785 { 2786 struct drm_i915_private *dev_priv = dev->dev_private; 2787 2788 if (dev_priv->ips.renderctx == NULL) 2789 dev_priv->ips.renderctx = intel_alloc_context_page(dev); 2790 if (!dev_priv->ips.renderctx) 2791 return -ENOMEM; 2792 2793 if (dev_priv->ips.pwrctx == NULL) 2794 dev_priv->ips.pwrctx = intel_alloc_context_page(dev); 2795 if (!dev_priv->ips.pwrctx) { 2796 ironlake_teardown_rc6(dev); 2797 return -ENOMEM; 2798 } 2799 2800 return 0; 2801 } 2802 2803 static void ironlake_enable_rc6(struct drm_device *dev) 2804 { 2805 struct drm_i915_private *dev_priv = dev->dev_private; 2806 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 2807 bool was_interruptible; 2808 int ret; 2809 2810 /* rc6 disabled by default due to repeated reports of hanging during 2811 * boot and resume. 2812 */ 2813 if (!intel_enable_rc6(dev)) 2814 return; 2815 2816 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2817 2818 ret = ironlake_setup_rc6(dev); 2819 if (ret) 2820 return; 2821 2822 was_interruptible = dev_priv->mm.interruptible; 2823 dev_priv->mm.interruptible = false; 2824 2825 /* 2826 * GPU can automatically power down the render unit if given a page 2827 * to save state. 2828 */ 2829 ret = intel_ring_begin(ring, 6); 2830 if (ret) { 2831 ironlake_teardown_rc6(dev); 2832 dev_priv->mm.interruptible = was_interruptible; 2833 return; 2834 } 2835 2836 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); 2837 intel_ring_emit(ring, MI_SET_CONTEXT); 2838 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | 2839 MI_MM_SPACE_GTT | 2840 MI_SAVE_EXT_STATE_EN | 2841 MI_RESTORE_EXT_STATE_EN | 2842 MI_RESTORE_INHIBIT); 2843 intel_ring_emit(ring, MI_SUSPEND_FLUSH); 2844 intel_ring_emit(ring, MI_NOOP); 2845 intel_ring_emit(ring, MI_FLUSH); 2846 intel_ring_advance(ring); 2847 2848 /* 2849 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW 2850 * does an implicit flush, combined with MI_FLUSH above, it should be 2851 * safe to assume that renderctx is valid 2852 */ 2853 ret = intel_ring_idle(ring); 2854 dev_priv->mm.interruptible = was_interruptible; 2855 if (ret) { 2856 DRM_ERROR("failed to enable ironlake power savings\n"); 2857 ironlake_teardown_rc6(dev); 2858 return; 2859 } 2860 2861 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); 2862 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 2863 } 2864 2865 static unsigned long intel_pxfreq(u32 vidfreq) 2866 { 2867 unsigned long freq; 2868 int div = (vidfreq & 0x3f0000) >> 16; 2869 int post = (vidfreq & 0x3000) >> 12; 2870 int pre = (vidfreq & 0x7); 2871 2872 if (!pre) 2873 return 0; 2874 2875 freq = ((div * 133333) / ((1<<post) * pre)); 2876 2877 return freq; 2878 } 2879 2880 static const struct cparams { 2881 u16 i; 2882 u16 t; 2883 u16 m; 2884 u16 c; 2885 } cparams[] = { 2886 { 1, 1333, 301, 28664 }, 2887 { 1, 1066, 294, 24460 }, 2888 { 1, 800, 294, 25192 }, 2889 { 0, 1333, 276, 27605 }, 2890 { 0, 1066, 276, 27605 }, 2891 { 0, 800, 231, 23784 }, 2892 }; 2893 2894 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 2895 { 2896 u64 total_count, diff, ret; 2897 u32 count1, count2, count3, m = 0, c = 0; 2898 unsigned long now = jiffies_to_msecs(jiffies), diff1; 2899 int i; 2900 2901 diff1 = now - dev_priv->ips.last_time1; 2902 2903 /* Prevent division-by-zero if we are asking too fast. 2904 * Also, we don't get interesting results if we are polling 2905 * faster than once in 10ms, so just return the saved value 2906 * in such cases. 2907 */ 2908 if (diff1 <= 10) 2909 return dev_priv->ips.chipset_power; 2910 2911 count1 = I915_READ(DMIEC); 2912 count2 = I915_READ(DDREC); 2913 count3 = I915_READ(CSIEC); 2914 2915 total_count = count1 + count2 + count3; 2916 2917 /* FIXME: handle per-counter overflow */ 2918 if (total_count < dev_priv->ips.last_count1) { 2919 diff = ~0UL - dev_priv->ips.last_count1; 2920 diff += total_count; 2921 } else { 2922 diff = total_count - dev_priv->ips.last_count1; 2923 } 2924 2925 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 2926 if (cparams[i].i == dev_priv->ips.c_m && 2927 cparams[i].t == dev_priv->ips.r_t) { 2928 m = cparams[i].m; 2929 c = cparams[i].c; 2930 break; 2931 } 2932 } 2933 2934 diff = div_u64(diff, diff1); 2935 ret = ((m * diff) + c); 2936 ret = div_u64(ret, 10); 2937 2938 dev_priv->ips.last_count1 = total_count; 2939 dev_priv->ips.last_time1 = now; 2940 2941 dev_priv->ips.chipset_power = ret; 2942 2943 return ret; 2944 } 2945 2946 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 2947 { 2948 unsigned long val; 2949 2950 if (dev_priv->info->gen != 5) 2951 return 0; 2952 2953 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2954 2955 val = __i915_chipset_val(dev_priv); 2956 2957 lockmgr(&mchdev_lock, LK_RELEASE); 2958 2959 return val; 2960 } 2961 2962 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 2963 { 2964 unsigned long m, x, b; 2965 u32 tsfs; 2966 2967 tsfs = I915_READ(TSFS); 2968 2969 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 2970 x = I915_READ8(TR1); 2971 2972 b = tsfs & TSFS_INTR_MASK; 2973 2974 return ((m * x) / 127) - b; 2975 } 2976 2977 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 2978 { 2979 static const struct v_table { 2980 u16 vd; /* in .1 mil */ 2981 u16 vm; /* in .1 mil */ 2982 } v_table[] = { 2983 { 0, 0, }, 2984 { 375, 0, }, 2985 { 500, 0, }, 2986 { 625, 0, }, 2987 { 750, 0, }, 2988 { 875, 0, }, 2989 { 1000, 0, }, 2990 { 1125, 0, }, 2991 { 4125, 3000, }, 2992 { 4125, 3000, }, 2993 { 4125, 3000, }, 2994 { 4125, 3000, }, 2995 { 4125, 3000, }, 2996 { 4125, 3000, }, 2997 { 4125, 3000, }, 2998 { 4125, 3000, }, 2999 { 4125, 3000, }, 3000 { 4125, 3000, }, 3001 { 4125, 3000, }, 3002 { 4125, 3000, }, 3003 { 4125, 3000, }, 3004 { 4125, 3000, }, 3005 { 4125, 3000, }, 3006 { 4125, 3000, }, 3007 { 4125, 3000, }, 3008 { 4125, 3000, }, 3009 { 4125, 3000, }, 3010 { 4125, 3000, }, 3011 { 4125, 3000, }, 3012 { 4125, 3000, }, 3013 { 4125, 3000, }, 3014 { 4125, 3000, }, 3015 { 4250, 3125, }, 3016 { 4375, 3250, }, 3017 { 4500, 3375, }, 3018 { 4625, 3500, }, 3019 { 4750, 3625, }, 3020 { 4875, 3750, }, 3021 { 5000, 3875, }, 3022 { 5125, 4000, }, 3023 { 5250, 4125, }, 3024 { 5375, 4250, }, 3025 { 5500, 4375, }, 3026 { 5625, 4500, }, 3027 { 5750, 4625, }, 3028 { 5875, 4750, }, 3029 { 6000, 4875, }, 3030 { 6125, 5000, }, 3031 { 6250, 5125, }, 3032 { 6375, 5250, }, 3033 { 6500, 5375, }, 3034 { 6625, 5500, }, 3035 { 6750, 5625, }, 3036 { 6875, 5750, }, 3037 { 7000, 5875, }, 3038 { 7125, 6000, }, 3039 { 7250, 6125, }, 3040 { 7375, 6250, }, 3041 { 7500, 6375, }, 3042 { 7625, 6500, }, 3043 { 7750, 6625, }, 3044 { 7875, 6750, }, 3045 { 8000, 6875, }, 3046 { 8125, 7000, }, 3047 { 8250, 7125, }, 3048 { 8375, 7250, }, 3049 { 8500, 7375, }, 3050 { 8625, 7500, }, 3051 { 8750, 7625, }, 3052 { 8875, 7750, }, 3053 { 9000, 7875, }, 3054 { 9125, 8000, }, 3055 { 9250, 8125, }, 3056 { 9375, 8250, }, 3057 { 9500, 8375, }, 3058 { 9625, 8500, }, 3059 { 9750, 8625, }, 3060 { 9875, 8750, }, 3061 { 10000, 8875, }, 3062 { 10125, 9000, }, 3063 { 10250, 9125, }, 3064 { 10375, 9250, }, 3065 { 10500, 9375, }, 3066 { 10625, 9500, }, 3067 { 10750, 9625, }, 3068 { 10875, 9750, }, 3069 { 11000, 9875, }, 3070 { 11125, 10000, }, 3071 { 11250, 10125, }, 3072 { 11375, 10250, }, 3073 { 11500, 10375, }, 3074 { 11625, 10500, }, 3075 { 11750, 10625, }, 3076 { 11875, 10750, }, 3077 { 12000, 10875, }, 3078 { 12125, 11000, }, 3079 { 12250, 11125, }, 3080 { 12375, 11250, }, 3081 { 12500, 11375, }, 3082 { 12625, 11500, }, 3083 { 12750, 11625, }, 3084 { 12875, 11750, }, 3085 { 13000, 11875, }, 3086 { 13125, 12000, }, 3087 { 13250, 12125, }, 3088 { 13375, 12250, }, 3089 { 13500, 12375, }, 3090 { 13625, 12500, }, 3091 { 13750, 12625, }, 3092 { 13875, 12750, }, 3093 { 14000, 12875, }, 3094 { 14125, 13000, }, 3095 { 14250, 13125, }, 3096 { 14375, 13250, }, 3097 { 14500, 13375, }, 3098 { 14625, 13500, }, 3099 { 14750, 13625, }, 3100 { 14875, 13750, }, 3101 { 15000, 13875, }, 3102 { 15125, 14000, }, 3103 { 15250, 14125, }, 3104 { 15375, 14250, }, 3105 { 15500, 14375, }, 3106 { 15625, 14500, }, 3107 { 15750, 14625, }, 3108 { 15875, 14750, }, 3109 { 16000, 14875, }, 3110 { 16125, 15000, }, 3111 }; 3112 if (dev_priv->info->is_mobile) 3113 return v_table[pxvid].vm; 3114 else 3115 return v_table[pxvid].vd; 3116 } 3117 3118 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 3119 { 3120 struct timespec now, diff1; 3121 u64 diff; 3122 unsigned long diffms; 3123 u32 count; 3124 3125 getrawmonotonic(&now); 3126 diff1 = timespec_sub(now, dev_priv->ips.last_time2); 3127 3128 /* Don't divide by 0 */ 3129 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; 3130 if (!diffms) 3131 return; 3132 3133 count = I915_READ(GFXEC); 3134 3135 if (count < dev_priv->ips.last_count2) { 3136 diff = ~0UL - dev_priv->ips.last_count2; 3137 diff += count; 3138 } else { 3139 diff = count - dev_priv->ips.last_count2; 3140 } 3141 3142 dev_priv->ips.last_count2 = count; 3143 dev_priv->ips.last_time2 = now; 3144 3145 /* More magic constants... */ 3146 diff = diff * 1181; 3147 diff = div_u64(diff, diffms * 10); 3148 dev_priv->ips.gfx_power = diff; 3149 } 3150 3151 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 3152 { 3153 if (dev_priv->info->gen != 5) 3154 return; 3155 3156 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3157 3158 __i915_update_gfx_val(dev_priv); 3159 3160 lockmgr(&mchdev_lock, LK_RELEASE); 3161 } 3162 3163 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 3164 { 3165 unsigned long t, corr, state1, corr2, state2; 3166 u32 pxvid, ext_v; 3167 3168 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); 3169 pxvid = (pxvid >> 24) & 0x7f; 3170 ext_v = pvid_to_extvid(dev_priv, pxvid); 3171 3172 state1 = ext_v; 3173 3174 t = i915_mch_val(dev_priv); 3175 3176 /* Revel in the empirically derived constants */ 3177 3178 /* Correction factor in 1/100000 units */ 3179 if (t > 80) 3180 corr = ((t * 2349) + 135940); 3181 else if (t >= 50) 3182 corr = ((t * 964) + 29317); 3183 else /* < 50 */ 3184 corr = ((t * 301) + 1004); 3185 3186 corr = corr * ((150142 * state1) / 10000 - 78642); 3187 corr /= 100000; 3188 corr2 = (corr * dev_priv->ips.corr); 3189 3190 state2 = (corr2 * state1) / 10000; 3191 state2 /= 100; /* convert to mW */ 3192 3193 __i915_update_gfx_val(dev_priv); 3194 3195 return dev_priv->ips.gfx_power + state2; 3196 } 3197 3198 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 3199 { 3200 unsigned long val; 3201 3202 if (dev_priv->info->gen != 5) 3203 return 0; 3204 3205 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3206 3207 val = __i915_gfx_val(dev_priv); 3208 3209 lockmgr(&mchdev_lock, LK_RELEASE); 3210 3211 return val; 3212 } 3213 3214 /** 3215 * i915_read_mch_val - return value for IPS use 3216 * 3217 * Calculate and return a value for the IPS driver to use when deciding whether 3218 * we have thermal and power headroom to increase CPU or GPU power budget. 3219 */ 3220 unsigned long i915_read_mch_val(void) 3221 { 3222 struct drm_i915_private *dev_priv; 3223 unsigned long chipset_val, graphics_val, ret = 0; 3224 3225 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3226 if (!i915_mch_dev) 3227 goto out_unlock; 3228 dev_priv = i915_mch_dev; 3229 3230 chipset_val = __i915_chipset_val(dev_priv); 3231 graphics_val = __i915_gfx_val(dev_priv); 3232 3233 ret = chipset_val + graphics_val; 3234 3235 out_unlock: 3236 lockmgr(&mchdev_lock, LK_RELEASE); 3237 3238 return ret; 3239 } 3240 3241 /** 3242 * i915_gpu_raise - raise GPU frequency limit 3243 * 3244 * Raise the limit; IPS indicates we have thermal headroom. 3245 */ 3246 bool i915_gpu_raise(void) 3247 { 3248 struct drm_i915_private *dev_priv; 3249 bool ret = true; 3250 3251 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3252 if (!i915_mch_dev) { 3253 ret = false; 3254 goto out_unlock; 3255 } 3256 dev_priv = i915_mch_dev; 3257 3258 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 3259 dev_priv->ips.max_delay--; 3260 3261 out_unlock: 3262 lockmgr(&mchdev_lock, LK_RELEASE); 3263 3264 return ret; 3265 } 3266 3267 /** 3268 * i915_gpu_lower - lower GPU frequency limit 3269 * 3270 * IPS indicates we're close to a thermal limit, so throttle back the GPU 3271 * frequency maximum. 3272 */ 3273 bool i915_gpu_lower(void) 3274 { 3275 struct drm_i915_private *dev_priv; 3276 bool ret = true; 3277 3278 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3279 if (!i915_mch_dev) { 3280 ret = false; 3281 goto out_unlock; 3282 } 3283 dev_priv = i915_mch_dev; 3284 3285 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 3286 dev_priv->ips.max_delay++; 3287 3288 out_unlock: 3289 lockmgr(&mchdev_lock, LK_RELEASE); 3290 3291 return ret; 3292 } 3293 3294 /** 3295 * i915_gpu_busy - indicate GPU business to IPS 3296 * 3297 * Tell the IPS driver whether or not the GPU is busy. 3298 */ 3299 bool i915_gpu_busy(void) 3300 { 3301 struct drm_i915_private *dev_priv; 3302 struct intel_ring_buffer *ring; 3303 bool ret = false; 3304 int i; 3305 3306 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3307 if (!i915_mch_dev) 3308 goto out_unlock; 3309 dev_priv = i915_mch_dev; 3310 3311 for_each_ring(ring, dev_priv, i) 3312 ret |= !list_empty(&ring->request_list); 3313 3314 out_unlock: 3315 lockmgr(&mchdev_lock, LK_RELEASE); 3316 3317 return ret; 3318 } 3319 3320 /** 3321 * i915_gpu_turbo_disable - disable graphics turbo 3322 * 3323 * Disable graphics turbo by resetting the max frequency and setting the 3324 * current frequency to the default. 3325 */ 3326 bool i915_gpu_turbo_disable(void) 3327 { 3328 struct drm_i915_private *dev_priv; 3329 bool ret = true; 3330 3331 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3332 if (!i915_mch_dev) { 3333 ret = false; 3334 goto out_unlock; 3335 } 3336 dev_priv = i915_mch_dev; 3337 3338 dev_priv->ips.max_delay = dev_priv->ips.fstart; 3339 3340 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 3341 ret = false; 3342 3343 out_unlock: 3344 lockmgr(&mchdev_lock, LK_RELEASE); 3345 3346 return ret; 3347 } 3348 3349 #if 0 3350 /** 3351 * Tells the intel_ips driver that the i915 driver is now loaded, if 3352 * IPS got loaded first. 3353 * 3354 * This awkward dance is so that neither module has to depend on the 3355 * other in order for IPS to do the appropriate communication of 3356 * GPU turbo limits to i915. 3357 */ 3358 static void 3359 ips_ping_for_i915_load(void) 3360 { 3361 void (*link)(void); 3362 3363 link = symbol_get(ips_link_to_i915_driver); 3364 if (link) { 3365 link(); 3366 symbol_put(ips_link_to_i915_driver); 3367 } 3368 } 3369 #endif 3370 3371 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 3372 { 3373 /* We only register the i915 ips part with intel-ips once everything is 3374 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 3375 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3376 i915_mch_dev = dev_priv; 3377 lockmgr(&mchdev_lock, LK_RELEASE); 3378 } 3379 3380 void intel_gpu_ips_teardown(void) 3381 { 3382 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3383 i915_mch_dev = NULL; 3384 lockmgr(&mchdev_lock, LK_RELEASE); 3385 } 3386 static void intel_init_emon(struct drm_device *dev) 3387 { 3388 struct drm_i915_private *dev_priv = dev->dev_private; 3389 u32 lcfuse; 3390 u8 pxw[16]; 3391 int i; 3392 3393 /* Disable to program */ 3394 I915_WRITE(ECR, 0); 3395 POSTING_READ(ECR); 3396 3397 /* Program energy weights for various events */ 3398 I915_WRITE(SDEW, 0x15040d00); 3399 I915_WRITE(CSIEW0, 0x007f0000); 3400 I915_WRITE(CSIEW1, 0x1e220004); 3401 I915_WRITE(CSIEW2, 0x04000004); 3402 3403 for (i = 0; i < 5; i++) 3404 I915_WRITE(PEW + (i * 4), 0); 3405 for (i = 0; i < 3; i++) 3406 I915_WRITE(DEW + (i * 4), 0); 3407 3408 /* Program P-state weights to account for frequency power adjustment */ 3409 for (i = 0; i < 16; i++) { 3410 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); 3411 unsigned long freq = intel_pxfreq(pxvidfreq); 3412 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 3413 PXVFREQ_PX_SHIFT; 3414 unsigned long val; 3415 3416 val = vid * vid; 3417 val *= (freq / 1000); 3418 val *= 255; 3419 val /= (127*127*900); 3420 if (val > 0xff) 3421 DRM_ERROR("bad pxval: %ld\n", val); 3422 pxw[i] = val; 3423 } 3424 /* Render standby states get 0 weight */ 3425 pxw[14] = 0; 3426 pxw[15] = 0; 3427 3428 for (i = 0; i < 4; i++) { 3429 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | 3430 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); 3431 I915_WRITE(PXW + (i * 4), val); 3432 } 3433 3434 /* Adjust magic regs to magic values (more experimental results) */ 3435 I915_WRITE(OGW0, 0); 3436 I915_WRITE(OGW1, 0); 3437 I915_WRITE(EG0, 0x00007f00); 3438 I915_WRITE(EG1, 0x0000000e); 3439 I915_WRITE(EG2, 0x000e0000); 3440 I915_WRITE(EG3, 0x68000300); 3441 I915_WRITE(EG4, 0x42000000); 3442 I915_WRITE(EG5, 0x00140031); 3443 I915_WRITE(EG6, 0); 3444 I915_WRITE(EG7, 0); 3445 3446 for (i = 0; i < 8; i++) 3447 I915_WRITE(PXWL + (i * 4), 0); 3448 3449 /* Enable PMON + select events */ 3450 I915_WRITE(ECR, 0x80000019); 3451 3452 lcfuse = I915_READ(LCFUSE02); 3453 3454 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 3455 } 3456 3457 void intel_disable_gt_powersave(struct drm_device *dev) 3458 { 3459 struct drm_i915_private *dev_priv = dev->dev_private; 3460 3461 if (IS_IRONLAKE_M(dev)) { 3462 ironlake_disable_drps(dev); 3463 ironlake_disable_rc6(dev); 3464 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { 3465 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); 3466 mutex_lock(&dev_priv->rps.hw_lock); 3467 gen6_disable_rps(dev); 3468 mutex_unlock(&dev_priv->rps.hw_lock); 3469 } 3470 } 3471 3472 static void intel_gen6_powersave_work(struct work_struct *work) 3473 { 3474 struct drm_i915_private *dev_priv = 3475 container_of(work, struct drm_i915_private, 3476 rps.delayed_resume_work.work); 3477 struct drm_device *dev = dev_priv->dev; 3478 3479 mutex_lock(&dev_priv->rps.hw_lock); 3480 gen6_enable_rps(dev); 3481 gen6_update_ring_freq(dev); 3482 mutex_unlock(&dev_priv->rps.hw_lock); 3483 } 3484 3485 void intel_enable_gt_powersave(struct drm_device *dev) 3486 { 3487 struct drm_i915_private *dev_priv = dev->dev_private; 3488 3489 if (IS_IRONLAKE_M(dev)) { 3490 ironlake_enable_drps(dev); 3491 ironlake_enable_rc6(dev); 3492 intel_init_emon(dev); 3493 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { 3494 /* 3495 * PCU communication is slow and this doesn't need to be 3496 * done at any specific time, so do this out of our fast path 3497 * to make resume and init faster. 3498 */ 3499 schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 3500 round_jiffies_up_relative(HZ)); 3501 } 3502 } 3503 3504 static void ibx_init_clock_gating(struct drm_device *dev) 3505 { 3506 struct drm_i915_private *dev_priv = dev->dev_private; 3507 3508 /* 3509 * On Ibex Peak and Cougar Point, we need to disable clock 3510 * gating for the panel power sequencer or it will fail to 3511 * start up when no ports are active. 3512 */ 3513 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 3514 } 3515 3516 static void ironlake_init_clock_gating(struct drm_device *dev) 3517 { 3518 struct drm_i915_private *dev_priv = dev->dev_private; 3519 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 3520 3521 /* Required for FBC */ 3522 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 3523 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 3524 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 3525 3526 I915_WRITE(PCH_3DCGDIS0, 3527 MARIUNIT_CLOCK_GATE_DISABLE | 3528 SVSMUNIT_CLOCK_GATE_DISABLE); 3529 I915_WRITE(PCH_3DCGDIS1, 3530 VFMUNIT_CLOCK_GATE_DISABLE); 3531 3532 /* 3533 * According to the spec the following bits should be set in 3534 * order to enable memory self-refresh 3535 * The bit 22/21 of 0x42004 3536 * The bit 5 of 0x42020 3537 * The bit 15 of 0x45000 3538 */ 3539 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3540 (I915_READ(ILK_DISPLAY_CHICKEN2) | 3541 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 3542 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 3543 I915_WRITE(DISP_ARB_CTL, 3544 (I915_READ(DISP_ARB_CTL) | 3545 DISP_FBC_WM_DIS)); 3546 I915_WRITE(WM3_LP_ILK, 0); 3547 I915_WRITE(WM2_LP_ILK, 0); 3548 I915_WRITE(WM1_LP_ILK, 0); 3549 3550 /* 3551 * Based on the document from hardware guys the following bits 3552 * should be set unconditionally in order to enable FBC. 3553 * The bit 22 of 0x42000 3554 * The bit 22 of 0x42004 3555 * The bit 7,8,9 of 0x42020. 3556 */ 3557 if (IS_IRONLAKE_M(dev)) { 3558 I915_WRITE(ILK_DISPLAY_CHICKEN1, 3559 I915_READ(ILK_DISPLAY_CHICKEN1) | 3560 ILK_FBCQ_DIS); 3561 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3562 I915_READ(ILK_DISPLAY_CHICKEN2) | 3563 ILK_DPARB_GATE); 3564 } 3565 3566 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 3567 3568 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3569 I915_READ(ILK_DISPLAY_CHICKEN2) | 3570 ILK_ELPIN_409_SELECT); 3571 I915_WRITE(_3D_CHICKEN2, 3572 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 3573 _3D_CHICKEN2_WM_READ_PIPELINED); 3574 3575 /* WaDisableRenderCachePipelinedFlush */ 3576 I915_WRITE(CACHE_MODE_0, 3577 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 3578 3579 ibx_init_clock_gating(dev); 3580 } 3581 3582 static void cpt_init_clock_gating(struct drm_device *dev) 3583 { 3584 struct drm_i915_private *dev_priv = dev->dev_private; 3585 int pipe; 3586 uint32_t val; 3587 3588 /* 3589 * On Ibex Peak and Cougar Point, we need to disable clock 3590 * gating for the panel power sequencer or it will fail to 3591 * start up when no ports are active. 3592 */ 3593 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 3594 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 3595 DPLS_EDP_PPS_FIX_DIS); 3596 /* The below fixes the weird display corruption, a few pixels shifted 3597 * downward, on (only) LVDS of some HP laptops with IVY. 3598 */ 3599 for_each_pipe(pipe) { 3600 val = I915_READ(TRANS_CHICKEN2(pipe)); 3601 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 3602 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 3603 if (dev_priv->fdi_rx_polarity_inverted) 3604 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 3605 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 3606 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 3607 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 3608 I915_WRITE(TRANS_CHICKEN2(pipe), val); 3609 } 3610 /* WADP0ClockGatingDisable */ 3611 for_each_pipe(pipe) { 3612 I915_WRITE(TRANS_CHICKEN1(pipe), 3613 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 3614 } 3615 } 3616 3617 static void gen6_check_mch_setup(struct drm_device *dev) 3618 { 3619 struct drm_i915_private *dev_priv = dev->dev_private; 3620 uint32_t tmp; 3621 3622 tmp = I915_READ(MCH_SSKPD); 3623 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { 3624 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); 3625 DRM_INFO("This can cause pipe underruns and display issues.\n"); 3626 DRM_INFO("Please upgrade your BIOS to fix this.\n"); 3627 } 3628 } 3629 3630 static void gen6_init_clock_gating(struct drm_device *dev) 3631 { 3632 struct drm_i915_private *dev_priv = dev->dev_private; 3633 int pipe; 3634 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 3635 3636 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 3637 3638 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3639 I915_READ(ILK_DISPLAY_CHICKEN2) | 3640 ILK_ELPIN_409_SELECT); 3641 3642 /* WaDisableHiZPlanesWhenMSAAEnabled */ 3643 I915_WRITE(_3D_CHICKEN, 3644 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 3645 3646 /* WaSetupGtModeTdRowDispatch */ 3647 if (IS_SNB_GT1(dev)) 3648 I915_WRITE(GEN6_GT_MODE, 3649 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); 3650 3651 I915_WRITE(WM3_LP_ILK, 0); 3652 I915_WRITE(WM2_LP_ILK, 0); 3653 I915_WRITE(WM1_LP_ILK, 0); 3654 3655 I915_WRITE(CACHE_MODE_0, 3656 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 3657 3658 I915_WRITE(GEN6_UCGCTL1, 3659 I915_READ(GEN6_UCGCTL1) | 3660 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 3661 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 3662 3663 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3664 * gating disable must be set. Failure to set it results in 3665 * flickering pixels due to Z write ordering failures after 3666 * some amount of runtime in the Mesa "fire" demo, and Unigine 3667 * Sanctuary and Tropics, and apparently anything else with 3668 * alpha test or pixel discard. 3669 * 3670 * According to the spec, bit 11 (RCCUNIT) must also be set, 3671 * but we didn't debug actual testcases to find it out. 3672 * 3673 * Also apply WaDisableVDSUnitClockGating and 3674 * WaDisableRCPBUnitClockGating. 3675 */ 3676 I915_WRITE(GEN6_UCGCTL2, 3677 GEN7_VDSUNIT_CLOCK_GATE_DISABLE | 3678 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 3679 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3680 3681 /* Bspec says we need to always set all mask bits. */ 3682 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | 3683 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); 3684 3685 /* 3686 * According to the spec the following bits should be 3687 * set in order to enable memory self-refresh and fbc: 3688 * The bit21 and bit22 of 0x42000 3689 * The bit21 and bit22 of 0x42004 3690 * The bit5 and bit7 of 0x42020 3691 * The bit14 of 0x70180 3692 * The bit14 of 0x71180 3693 */ 3694 I915_WRITE(ILK_DISPLAY_CHICKEN1, 3695 I915_READ(ILK_DISPLAY_CHICKEN1) | 3696 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 3697 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3698 I915_READ(ILK_DISPLAY_CHICKEN2) | 3699 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 3700 I915_WRITE(ILK_DSPCLK_GATE_D, 3701 I915_READ(ILK_DSPCLK_GATE_D) | 3702 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 3703 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 3704 3705 /* WaMbcDriverBootEnable */ 3706 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3707 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3708 3709 for_each_pipe(pipe) { 3710 I915_WRITE(DSPCNTR(pipe), 3711 I915_READ(DSPCNTR(pipe)) | 3712 DISPPLANE_TRICKLE_FEED_DISABLE); 3713 intel_flush_display_plane(dev_priv, pipe); 3714 } 3715 3716 /* The default value should be 0x200 according to docs, but the two 3717 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ 3718 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); 3719 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); 3720 3721 cpt_init_clock_gating(dev); 3722 3723 gen6_check_mch_setup(dev); 3724 } 3725 3726 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 3727 { 3728 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 3729 3730 reg &= ~GEN7_FF_SCHED_MASK; 3731 reg |= GEN7_FF_TS_SCHED_HW; 3732 reg |= GEN7_FF_VS_SCHED_HW; 3733 reg |= GEN7_FF_DS_SCHED_HW; 3734 3735 /* WaVSRefCountFullforceMissDisable */ 3736 if (IS_HASWELL(dev_priv->dev)) 3737 reg &= ~GEN7_FF_VS_REF_CNT_FFME; 3738 3739 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 3740 } 3741 3742 static void lpt_init_clock_gating(struct drm_device *dev) 3743 { 3744 struct drm_i915_private *dev_priv = dev->dev_private; 3745 3746 /* 3747 * TODO: this bit should only be enabled when really needed, then 3748 * disabled when not needed anymore in order to save power. 3749 */ 3750 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) 3751 I915_WRITE(SOUTH_DSPCLK_GATE_D, 3752 I915_READ(SOUTH_DSPCLK_GATE_D) | 3753 PCH_LP_PARTITION_LEVEL_DISABLE); 3754 } 3755 3756 static void haswell_init_clock_gating(struct drm_device *dev) 3757 { 3758 struct drm_i915_private *dev_priv = dev->dev_private; 3759 int pipe; 3760 3761 I915_WRITE(WM3_LP_ILK, 0); 3762 I915_WRITE(WM2_LP_ILK, 0); 3763 I915_WRITE(WM1_LP_ILK, 0); 3764 3765 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3766 * This implements the WaDisableRCZUnitClockGating workaround. 3767 */ 3768 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 3769 3770 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3771 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3772 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3773 3774 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3775 I915_WRITE(GEN7_L3CNTLREG1, 3776 GEN7_WA_FOR_GEN7_L3_CONTROL); 3777 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 3778 GEN7_WA_L3_CHICKEN_MODE); 3779 3780 /* This is required by WaCatErrorRejectionIssue */ 3781 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3782 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3783 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3784 3785 for_each_pipe(pipe) { 3786 I915_WRITE(DSPCNTR(pipe), 3787 I915_READ(DSPCNTR(pipe)) | 3788 DISPPLANE_TRICKLE_FEED_DISABLE); 3789 intel_flush_display_plane(dev_priv, pipe); 3790 } 3791 3792 gen7_setup_fixed_func_scheduler(dev_priv); 3793 3794 /* WaDisable4x2SubspanOptimization */ 3795 I915_WRITE(CACHE_MODE_1, 3796 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3797 3798 /* WaMbcDriverBootEnable */ 3799 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3800 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3801 3802 /* WaSwitchSolVfFArbitrationPriority */ 3803 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 3804 3805 /* XXX: This is a workaround for early silicon revisions and should be 3806 * removed later. 3807 */ 3808 I915_WRITE(WM_DBG, 3809 I915_READ(WM_DBG) | 3810 WM_DBG_DISALLOW_MULTIPLE_LP | 3811 WM_DBG_DISALLOW_SPRITE | 3812 WM_DBG_DISALLOW_MAXFIFO); 3813 3814 lpt_init_clock_gating(dev); 3815 } 3816 3817 static void ivybridge_init_clock_gating(struct drm_device *dev) 3818 { 3819 struct drm_i915_private *dev_priv = dev->dev_private; 3820 int pipe; 3821 uint32_t snpcr; 3822 3823 I915_WRITE(WM3_LP_ILK, 0); 3824 I915_WRITE(WM2_LP_ILK, 0); 3825 I915_WRITE(WM1_LP_ILK, 0); 3826 3827 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 3828 3829 /* WaDisableEarlyCull */ 3830 I915_WRITE(_3D_CHICKEN3, 3831 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 3832 3833 /* WaDisableBackToBackFlipFix */ 3834 I915_WRITE(IVB_CHICKEN3, 3835 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 3836 CHICKEN3_DGMG_DONE_FIX_DISABLE); 3837 3838 /* WaDisablePSDDualDispatchEnable */ 3839 if (IS_IVB_GT1(dev)) 3840 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 3841 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3842 else 3843 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, 3844 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3845 3846 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3847 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3848 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3849 3850 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3851 I915_WRITE(GEN7_L3CNTLREG1, 3852 GEN7_WA_FOR_GEN7_L3_CONTROL); 3853 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 3854 GEN7_WA_L3_CHICKEN_MODE); 3855 if (IS_IVB_GT1(dev)) 3856 I915_WRITE(GEN7_ROW_CHICKEN2, 3857 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3858 else 3859 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 3860 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3861 3862 3863 /* WaForceL3Serialization */ 3864 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3865 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3866 3867 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3868 * gating disable must be set. Failure to set it results in 3869 * flickering pixels due to Z write ordering failures after 3870 * some amount of runtime in the Mesa "fire" demo, and Unigine 3871 * Sanctuary and Tropics, and apparently anything else with 3872 * alpha test or pixel discard. 3873 * 3874 * According to the spec, bit 11 (RCCUNIT) must also be set, 3875 * but we didn't debug actual testcases to find it out. 3876 * 3877 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3878 * This implements the WaDisableRCZUnitClockGating workaround. 3879 */ 3880 I915_WRITE(GEN6_UCGCTL2, 3881 GEN6_RCZUNIT_CLOCK_GATE_DISABLE | 3882 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3883 3884 /* This is required by WaCatErrorRejectionIssue */ 3885 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3886 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3887 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3888 3889 for_each_pipe(pipe) { 3890 I915_WRITE(DSPCNTR(pipe), 3891 I915_READ(DSPCNTR(pipe)) | 3892 DISPPLANE_TRICKLE_FEED_DISABLE); 3893 intel_flush_display_plane(dev_priv, pipe); 3894 } 3895 3896 /* WaMbcDriverBootEnable */ 3897 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3898 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3899 3900 gen7_setup_fixed_func_scheduler(dev_priv); 3901 3902 /* WaDisable4x2SubspanOptimization */ 3903 I915_WRITE(CACHE_MODE_1, 3904 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3905 3906 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 3907 snpcr &= ~GEN6_MBC_SNPCR_MASK; 3908 snpcr |= GEN6_MBC_SNPCR_MED; 3909 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 3910 3911 if (!HAS_PCH_NOP(dev)) 3912 cpt_init_clock_gating(dev); 3913 3914 gen6_check_mch_setup(dev); 3915 } 3916 3917 static void valleyview_init_clock_gating(struct drm_device *dev) 3918 { 3919 struct drm_i915_private *dev_priv = dev->dev_private; 3920 int pipe; 3921 3922 I915_WRITE(WM3_LP_ILK, 0); 3923 I915_WRITE(WM2_LP_ILK, 0); 3924 I915_WRITE(WM1_LP_ILK, 0); 3925 3926 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 3927 3928 /* WaDisableEarlyCull */ 3929 I915_WRITE(_3D_CHICKEN3, 3930 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 3931 3932 /* WaDisableBackToBackFlipFix */ 3933 I915_WRITE(IVB_CHICKEN3, 3934 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 3935 CHICKEN3_DGMG_DONE_FIX_DISABLE); 3936 3937 /* WaDisablePSDDualDispatchEnable */ 3938 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 3939 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | 3940 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3941 3942 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3943 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3944 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3945 3946 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3947 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); 3948 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 3949 3950 /* WaForceL3Serialization */ 3951 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3952 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3953 3954 /* WaDisableDopClockGating */ 3955 I915_WRITE(GEN7_ROW_CHICKEN2, 3956 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3957 3958 /* WaForceL3Serialization */ 3959 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3960 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3961 3962 /* This is required by WaCatErrorRejectionIssue */ 3963 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3964 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3965 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3966 3967 /* WaMbcDriverBootEnable */ 3968 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3969 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3970 3971 3972 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3973 * gating disable must be set. Failure to set it results in 3974 * flickering pixels due to Z write ordering failures after 3975 * some amount of runtime in the Mesa "fire" demo, and Unigine 3976 * Sanctuary and Tropics, and apparently anything else with 3977 * alpha test or pixel discard. 3978 * 3979 * According to the spec, bit 11 (RCCUNIT) must also be set, 3980 * but we didn't debug actual testcases to find it out. 3981 * 3982 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3983 * This implements the WaDisableRCZUnitClockGating workaround. 3984 * 3985 * Also apply WaDisableVDSUnitClockGating and 3986 * WaDisableRCPBUnitClockGating. 3987 */ 3988 I915_WRITE(GEN6_UCGCTL2, 3989 GEN7_VDSUNIT_CLOCK_GATE_DISABLE | 3990 GEN7_TDLUNIT_CLOCK_GATE_DISABLE | 3991 GEN6_RCZUNIT_CLOCK_GATE_DISABLE | 3992 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 3993 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3994 3995 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 3996 3997 for_each_pipe(pipe) { 3998 I915_WRITE(DSPCNTR(pipe), 3999 I915_READ(DSPCNTR(pipe)) | 4000 DISPPLANE_TRICKLE_FEED_DISABLE); 4001 intel_flush_display_plane(dev_priv, pipe); 4002 } 4003 4004 I915_WRITE(CACHE_MODE_1, 4005 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 4006 4007 /* 4008 * WaDisableVLVClockGating_VBIIssue 4009 * Disable clock gating on th GCFG unit to prevent a delay 4010 * in the reporting of vblank events. 4011 */ 4012 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff); 4013 4014 /* Conservative clock gating settings for now */ 4015 I915_WRITE(0x9400, 0xffffffff); 4016 I915_WRITE(0x9404, 0xffffffff); 4017 I915_WRITE(0x9408, 0xffffffff); 4018 I915_WRITE(0x940c, 0xffffffff); 4019 I915_WRITE(0x9410, 0xffffffff); 4020 I915_WRITE(0x9414, 0xffffffff); 4021 I915_WRITE(0x9418, 0xffffffff); 4022 } 4023 4024 static void g4x_init_clock_gating(struct drm_device *dev) 4025 { 4026 struct drm_i915_private *dev_priv = dev->dev_private; 4027 uint32_t dspclk_gate; 4028 4029 I915_WRITE(RENCLK_GATE_D1, 0); 4030 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 4031 GS_UNIT_CLOCK_GATE_DISABLE | 4032 CL_UNIT_CLOCK_GATE_DISABLE); 4033 I915_WRITE(RAMCLK_GATE_D, 0); 4034 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 4035 OVRUNIT_CLOCK_GATE_DISABLE | 4036 OVCUNIT_CLOCK_GATE_DISABLE; 4037 if (IS_GM45(dev)) 4038 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 4039 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 4040 4041 /* WaDisableRenderCachePipelinedFlush */ 4042 I915_WRITE(CACHE_MODE_0, 4043 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 4044 } 4045 4046 static void crestline_init_clock_gating(struct drm_device *dev) 4047 { 4048 struct drm_i915_private *dev_priv = dev->dev_private; 4049 4050 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 4051 I915_WRITE(RENCLK_GATE_D2, 0); 4052 I915_WRITE(DSPCLK_GATE_D, 0); 4053 I915_WRITE(RAMCLK_GATE_D, 0); 4054 I915_WRITE16(DEUC, 0); 4055 } 4056 4057 static void broadwater_init_clock_gating(struct drm_device *dev) 4058 { 4059 struct drm_i915_private *dev_priv = dev->dev_private; 4060 4061 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 4062 I965_RCC_CLOCK_GATE_DISABLE | 4063 I965_RCPB_CLOCK_GATE_DISABLE | 4064 I965_ISC_CLOCK_GATE_DISABLE | 4065 I965_FBC_CLOCK_GATE_DISABLE); 4066 I915_WRITE(RENCLK_GATE_D2, 0); 4067 } 4068 4069 static void gen3_init_clock_gating(struct drm_device *dev) 4070 { 4071 struct drm_i915_private *dev_priv = dev->dev_private; 4072 u32 dstate = I915_READ(D_STATE); 4073 4074 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 4075 DSTATE_DOT_CLOCK_GATING; 4076 I915_WRITE(D_STATE, dstate); 4077 4078 if (IS_PINEVIEW(dev)) 4079 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 4080 4081 /* IIR "flip pending" means done if this bit is set */ 4082 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 4083 } 4084 4085 static void i85x_init_clock_gating(struct drm_device *dev) 4086 { 4087 struct drm_i915_private *dev_priv = dev->dev_private; 4088 4089 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 4090 } 4091 4092 static void i830_init_clock_gating(struct drm_device *dev) 4093 { 4094 struct drm_i915_private *dev_priv = dev->dev_private; 4095 4096 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 4097 } 4098 4099 void intel_init_clock_gating(struct drm_device *dev) 4100 { 4101 struct drm_i915_private *dev_priv = dev->dev_private; 4102 4103 dev_priv->display.init_clock_gating(dev); 4104 } 4105 4106 /** 4107 * We should only use the power well if we explicitly asked the hardware to 4108 * enable it, so check if it's enabled and also check if we've requested it to 4109 * be enabled. 4110 */ 4111 bool intel_using_power_well(struct drm_device *dev) 4112 { 4113 struct drm_i915_private *dev_priv = dev->dev_private; 4114 4115 if (IS_HASWELL(dev)) 4116 return I915_READ(HSW_PWR_WELL_DRIVER) == 4117 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE); 4118 else 4119 return true; 4120 } 4121 4122 void intel_set_power_well(struct drm_device *dev, bool enable) 4123 { 4124 struct drm_i915_private *dev_priv = dev->dev_private; 4125 bool is_enabled, enable_requested; 4126 uint32_t tmp; 4127 4128 if (!HAS_POWER_WELL(dev)) 4129 return; 4130 4131 if (!i915_disable_power_well && !enable) 4132 return; 4133 4134 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 4135 is_enabled = tmp & HSW_PWR_WELL_STATE; 4136 enable_requested = tmp & HSW_PWR_WELL_ENABLE; 4137 4138 if (enable) { 4139 if (!enable_requested) 4140 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE); 4141 4142 if (!is_enabled) { 4143 DRM_DEBUG_KMS("Enabling power well\n"); 4144 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 4145 HSW_PWR_WELL_STATE), 20)) 4146 DRM_ERROR("Timeout enabling power well\n"); 4147 } 4148 } else { 4149 if (enable_requested) { 4150 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 4151 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 4152 } 4153 } 4154 } 4155 4156 /* 4157 * Starting with Haswell, we have a "Power Down Well" that can be turned off 4158 * when not needed anymore. We have 4 registers that can request the power well 4159 * to be enabled, and it will only be disabled if none of the registers is 4160 * requesting it to be enabled. 4161 */ 4162 void intel_init_power_well(struct drm_device *dev) 4163 { 4164 struct drm_i915_private *dev_priv = dev->dev_private; 4165 4166 if (!HAS_POWER_WELL(dev)) 4167 return; 4168 4169 /* For now, we need the power well to be always enabled. */ 4170 intel_set_power_well(dev, true); 4171 4172 /* We're taking over the BIOS, so clear any requests made by it since 4173 * the driver is in charge now. */ 4174 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE) 4175 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 4176 } 4177 4178 /* Set up chip specific power management-related functions */ 4179 void intel_init_pm(struct drm_device *dev) 4180 { 4181 struct drm_i915_private *dev_priv = dev->dev_private; 4182 4183 if (I915_HAS_FBC(dev)) { 4184 if (HAS_PCH_SPLIT(dev)) { 4185 dev_priv->display.fbc_enabled = ironlake_fbc_enabled; 4186 dev_priv->display.enable_fbc = ironlake_enable_fbc; 4187 dev_priv->display.disable_fbc = ironlake_disable_fbc; 4188 } else if (IS_GM45(dev)) { 4189 dev_priv->display.fbc_enabled = g4x_fbc_enabled; 4190 dev_priv->display.enable_fbc = g4x_enable_fbc; 4191 dev_priv->display.disable_fbc = g4x_disable_fbc; 4192 } else if (IS_CRESTLINE(dev)) { 4193 dev_priv->display.fbc_enabled = i8xx_fbc_enabled; 4194 dev_priv->display.enable_fbc = i8xx_enable_fbc; 4195 dev_priv->display.disable_fbc = i8xx_disable_fbc; 4196 } 4197 /* 855GM needs testing */ 4198 } 4199 4200 /* For cxsr */ 4201 if (IS_PINEVIEW(dev)) 4202 i915_pineview_get_mem_freq(dev); 4203 else if (IS_GEN5(dev)) 4204 i915_ironlake_get_mem_freq(dev); 4205 4206 /* For FIFO watermark updates */ 4207 if (HAS_PCH_SPLIT(dev)) { 4208 if (IS_GEN5(dev)) { 4209 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) 4210 dev_priv->display.update_wm = ironlake_update_wm; 4211 else { 4212 DRM_DEBUG_KMS("Failed to get proper latency. " 4213 "Disable CxSR\n"); 4214 dev_priv->display.update_wm = NULL; 4215 } 4216 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 4217 } else if (IS_GEN6(dev)) { 4218 if (SNB_READ_WM0_LATENCY()) { 4219 dev_priv->display.update_wm = sandybridge_update_wm; 4220 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4221 } else { 4222 DRM_DEBUG_KMS("Failed to read display plane latency. " 4223 "Disable CxSR\n"); 4224 dev_priv->display.update_wm = NULL; 4225 } 4226 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 4227 } else if (IS_IVYBRIDGE(dev)) { 4228 if (SNB_READ_WM0_LATENCY()) { 4229 dev_priv->display.update_wm = ivybridge_update_wm; 4230 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4231 } else { 4232 DRM_DEBUG_KMS("Failed to read display plane latency. " 4233 "Disable CxSR\n"); 4234 dev_priv->display.update_wm = NULL; 4235 } 4236 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 4237 } else if (IS_HASWELL(dev)) { 4238 if (SNB_READ_WM0_LATENCY()) { 4239 dev_priv->display.update_wm = sandybridge_update_wm; 4240 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4241 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; 4242 } else { 4243 DRM_DEBUG_KMS("Failed to read display plane latency. " 4244 "Disable CxSR\n"); 4245 dev_priv->display.update_wm = NULL; 4246 } 4247 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 4248 } else 4249 dev_priv->display.update_wm = NULL; 4250 } else if (IS_VALLEYVIEW(dev)) { 4251 dev_priv->display.update_wm = valleyview_update_wm; 4252 dev_priv->display.init_clock_gating = 4253 valleyview_init_clock_gating; 4254 } else if (IS_PINEVIEW(dev)) { 4255 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 4256 dev_priv->is_ddr3, 4257 dev_priv->fsb_freq, 4258 dev_priv->mem_freq)) { 4259 DRM_INFO("failed to find known CxSR latency " 4260 "(found ddr%s fsb freq %d, mem freq %d), " 4261 "disabling CxSR\n", 4262 (dev_priv->is_ddr3 == 1) ? "3" : "2", 4263 dev_priv->fsb_freq, dev_priv->mem_freq); 4264 /* Disable CxSR and never update its watermark again */ 4265 pineview_disable_cxsr(dev); 4266 dev_priv->display.update_wm = NULL; 4267 } else 4268 dev_priv->display.update_wm = pineview_update_wm; 4269 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 4270 } else if (IS_G4X(dev)) { 4271 dev_priv->display.update_wm = g4x_update_wm; 4272 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 4273 } else if (IS_GEN4(dev)) { 4274 dev_priv->display.update_wm = i965_update_wm; 4275 if (IS_CRESTLINE(dev)) 4276 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 4277 else if (IS_BROADWATER(dev)) 4278 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 4279 } else if (IS_GEN3(dev)) { 4280 dev_priv->display.update_wm = i9xx_update_wm; 4281 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 4282 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 4283 } else if (IS_I865G(dev)) { 4284 dev_priv->display.update_wm = i830_update_wm; 4285 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 4286 dev_priv->display.get_fifo_size = i830_get_fifo_size; 4287 } else if (IS_I85X(dev)) { 4288 dev_priv->display.update_wm = i9xx_update_wm; 4289 dev_priv->display.get_fifo_size = i85x_get_fifo_size; 4290 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 4291 } else { 4292 dev_priv->display.update_wm = i830_update_wm; 4293 dev_priv->display.init_clock_gating = i830_init_clock_gating; 4294 if (IS_845G(dev)) 4295 dev_priv->display.get_fifo_size = i845_get_fifo_size; 4296 else 4297 dev_priv->display.get_fifo_size = i830_get_fifo_size; 4298 } 4299 } 4300 4301 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) 4302 { 4303 u32 gt_thread_status_mask; 4304 4305 if (IS_HASWELL(dev_priv->dev)) 4306 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; 4307 else 4308 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; 4309 4310 /* w/a for a sporadic read returning 0 by waiting for the GT 4311 * thread to wake up. 4312 */ 4313 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) 4314 DRM_ERROR("GT thread status wait timed out\n"); 4315 } 4316 4317 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) 4318 { 4319 I915_WRITE_NOTRACE(FORCEWAKE, 0); 4320 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ 4321 } 4322 4323 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 4324 { 4325 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0, 4326 FORCEWAKE_ACK_TIMEOUT_MS)) 4327 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4328 4329 I915_WRITE_NOTRACE(FORCEWAKE, 1); 4330 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ 4331 4332 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1), 4333 FORCEWAKE_ACK_TIMEOUT_MS)) 4334 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4335 4336 __gen6_gt_wait_for_thread_c0(dev_priv); 4337 } 4338 4339 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) 4340 { 4341 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); 4342 /* something from same cacheline, but !FORCEWAKE_MT */ 4343 POSTING_READ(ECOBUS); 4344 } 4345 4346 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) 4347 { 4348 u32 forcewake_ack; 4349 4350 if (IS_HASWELL(dev_priv->dev)) 4351 forcewake_ack = FORCEWAKE_ACK_HSW; 4352 else 4353 forcewake_ack = FORCEWAKE_MT_ACK; 4354 4355 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0, 4356 FORCEWAKE_ACK_TIMEOUT_MS)) 4357 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4358 4359 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 4360 /* something from same cacheline, but !FORCEWAKE_MT */ 4361 POSTING_READ(ECOBUS); 4362 4363 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL), 4364 FORCEWAKE_ACK_TIMEOUT_MS)) 4365 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4366 4367 __gen6_gt_wait_for_thread_c0(dev_priv); 4368 } 4369 4370 /* 4371 * Generally this is called implicitly by the register read function. However, 4372 * if some sequence requires the GT to not power down then this function should 4373 * be called at the beginning of the sequence followed by a call to 4374 * gen6_gt_force_wake_put() at the end of the sequence. 4375 */ 4376 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 4377 { 4378 4379 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); 4380 if (dev_priv->forcewake_count++ == 0) 4381 dev_priv->gt.force_wake_get(dev_priv); 4382 lockmgr(&dev_priv->gt_lock, LK_RELEASE); 4383 } 4384 4385 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) 4386 { 4387 u32 gtfifodbg; 4388 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); 4389 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, 4390 "MMIO read or write has been dropped %x\n", gtfifodbg)) 4391 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); 4392 } 4393 4394 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 4395 { 4396 I915_WRITE_NOTRACE(FORCEWAKE, 0); 4397 /* something from same cacheline, but !FORCEWAKE */ 4398 POSTING_READ(ECOBUS); 4399 gen6_gt_check_fifodbg(dev_priv); 4400 } 4401 4402 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) 4403 { 4404 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 4405 /* something from same cacheline, but !FORCEWAKE_MT */ 4406 POSTING_READ(ECOBUS); 4407 gen6_gt_check_fifodbg(dev_priv); 4408 } 4409 4410 /* 4411 * see gen6_gt_force_wake_get() 4412 */ 4413 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 4414 { 4415 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); 4416 if (--dev_priv->forcewake_count == 0) 4417 dev_priv->gt.force_wake_put(dev_priv); 4418 lockmgr(&dev_priv->gt_lock, LK_RELEASE); 4419 } 4420 4421 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 4422 { 4423 int ret = 0; 4424 4425 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 4426 int loop = 500; 4427 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 4428 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 4429 udelay(10); 4430 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 4431 } 4432 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) 4433 ++ret; 4434 dev_priv->gt_fifo_count = fifo; 4435 } 4436 dev_priv->gt_fifo_count--; 4437 4438 return ret; 4439 } 4440 4441 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) 4442 { 4443 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); 4444 /* something from same cacheline, but !FORCEWAKE_VLV */ 4445 POSTING_READ(FORCEWAKE_ACK_VLV); 4446 } 4447 4448 static void vlv_force_wake_get(struct drm_i915_private *dev_priv) 4449 { 4450 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0, 4451 FORCEWAKE_ACK_TIMEOUT_MS)) 4452 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4453 4454 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 4455 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, 4456 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 4457 4458 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL), 4459 FORCEWAKE_ACK_TIMEOUT_MS)) 4460 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n"); 4461 4462 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) & 4463 FORCEWAKE_KERNEL), 4464 FORCEWAKE_ACK_TIMEOUT_MS)) 4465 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n"); 4466 4467 __gen6_gt_wait_for_thread_c0(dev_priv); 4468 } 4469 4470 static void vlv_force_wake_put(struct drm_i915_private *dev_priv) 4471 { 4472 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 4473 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, 4474 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 4475 /* The below doubles as a POSTING_READ */ 4476 gen6_gt_check_fifodbg(dev_priv); 4477 } 4478 4479 void intel_gt_reset(struct drm_device *dev) 4480 { 4481 struct drm_i915_private *dev_priv = dev->dev_private; 4482 4483 if (IS_VALLEYVIEW(dev)) { 4484 vlv_force_wake_reset(dev_priv); 4485 } else if (INTEL_INFO(dev)->gen >= 6) { 4486 __gen6_gt_force_wake_reset(dev_priv); 4487 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 4488 __gen6_gt_force_wake_mt_reset(dev_priv); 4489 } 4490 } 4491 4492 void intel_gt_init(struct drm_device *dev) 4493 { 4494 struct drm_i915_private *dev_priv = dev->dev_private; 4495 4496 lockinit(&dev_priv->gt_lock, "915gt", 0, LK_CANRECURSE); 4497 4498 intel_gt_reset(dev); 4499 4500 if (IS_VALLEYVIEW(dev)) { 4501 dev_priv->gt.force_wake_get = vlv_force_wake_get; 4502 dev_priv->gt.force_wake_put = vlv_force_wake_put; 4503 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { 4504 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; 4505 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; 4506 } else if (IS_GEN6(dev)) { 4507 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; 4508 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; 4509 } 4510 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 4511 intel_gen6_powersave_work); 4512 } 4513 4514 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) 4515 { 4516 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4517 4518 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 4519 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 4520 return -EAGAIN; 4521 } 4522 4523 I915_WRITE(GEN6_PCODE_DATA, *val); 4524 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 4525 4526 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 4527 500)) { 4528 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 4529 return -ETIMEDOUT; 4530 } 4531 4532 *val = I915_READ(GEN6_PCODE_DATA); 4533 I915_WRITE(GEN6_PCODE_DATA, 0); 4534 4535 return 0; 4536 } 4537 4538 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) 4539 { 4540 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4541 4542 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 4543 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 4544 return -EAGAIN; 4545 } 4546 4547 I915_WRITE(GEN6_PCODE_DATA, val); 4548 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 4549 4550 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 4551 500)) { 4552 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 4553 return -ETIMEDOUT; 4554 } 4555 4556 I915_WRITE(GEN6_PCODE_DATA, 0); 4557 4558 return 0; 4559 } 4560 4561 static int vlv_punit_rw(struct drm_i915_private *dev_priv, u8 opcode, 4562 u8 addr, u32 *val) 4563 { 4564 u32 cmd, devfn, port, be, bar; 4565 4566 bar = 0; 4567 be = 0xf; 4568 port = IOSF_PORT_PUNIT; 4569 devfn = PCI_DEVFN(2, 0); 4570 4571 cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | 4572 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | 4573 (bar << IOSF_BAR_SHIFT); 4574 4575 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4576 4577 if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) { 4578 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n", 4579 opcode == PUNIT_OPCODE_REG_READ ? 4580 "read" : "write"); 4581 return -EAGAIN; 4582 } 4583 4584 I915_WRITE(VLV_IOSF_ADDR, addr); 4585 if (opcode == PUNIT_OPCODE_REG_WRITE) 4586 I915_WRITE(VLV_IOSF_DATA, *val); 4587 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); 4588 4589 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 4590 500)) { 4591 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n", 4592 opcode == PUNIT_OPCODE_REG_READ ? "read" : "write", 4593 addr); 4594 return -ETIMEDOUT; 4595 } 4596 4597 if (opcode == PUNIT_OPCODE_REG_READ) 4598 *val = I915_READ(VLV_IOSF_DATA); 4599 I915_WRITE(VLV_IOSF_DATA, 0); 4600 4601 return 0; 4602 } 4603 4604 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val) 4605 { 4606 return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_READ, addr, val); 4607 } 4608 4609 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) 4610 { 4611 return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_WRITE, addr, &val); 4612 } 4613