1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <linux/module.h> 31 #include <machine/clock.h> 32 33 #define FORCEWAKE_ACK_TIMEOUT_MS 2 34 35 /* FBC, or Frame Buffer Compression, is a technique employed to compress the 36 * framebuffer contents in-memory, aiming at reducing the required bandwidth 37 * during in-memory transfers and, therefore, reduce the power packet. 38 * 39 * The benefits of FBC are mostly visible with solid backgrounds and 40 * variation-less patterns. 41 * 42 * FBC-related functionality can be enabled by the means of the 43 * i915.i915_enable_fbc parameter 44 */ 45 46 static bool intel_crtc_active(struct drm_crtc *crtc) 47 { 48 /* Be paranoid as we can arrive here with only partial 49 * state retrieved from the hardware during setup. 50 */ 51 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock; 52 } 53 54 static void i8xx_disable_fbc(struct drm_device *dev) 55 { 56 struct drm_i915_private *dev_priv = dev->dev_private; 57 u32 fbc_ctl; 58 59 /* Disable compression */ 60 fbc_ctl = I915_READ(FBC_CONTROL); 61 if ((fbc_ctl & FBC_CTL_EN) == 0) 62 return; 63 64 fbc_ctl &= ~FBC_CTL_EN; 65 I915_WRITE(FBC_CONTROL, fbc_ctl); 66 67 /* Wait for compressing bit to clear */ 68 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { 69 DRM_DEBUG_KMS("FBC idle timed out\n"); 70 return; 71 } 72 73 DRM_DEBUG_KMS("disabled FBC\n"); 74 } 75 76 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 77 { 78 struct drm_device *dev = crtc->dev; 79 struct drm_i915_private *dev_priv = dev->dev_private; 80 struct drm_framebuffer *fb = crtc->fb; 81 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 82 struct drm_i915_gem_object *obj = intel_fb->obj; 83 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 84 int cfb_pitch; 85 int plane, i; 86 u32 fbc_ctl, fbc_ctl2; 87 88 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; 89 if (fb->pitches[0] < cfb_pitch) 90 cfb_pitch = fb->pitches[0]; 91 92 /* FBC_CTL wants 64B units */ 93 cfb_pitch = (cfb_pitch / 64) - 1; 94 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; 95 96 /* Clear old tags */ 97 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 98 I915_WRITE(FBC_TAG + (i * 4), 0); 99 100 /* Set it up... */ 101 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; 102 fbc_ctl2 |= plane; 103 I915_WRITE(FBC_CONTROL2, fbc_ctl2); 104 I915_WRITE(FBC_FENCE_OFF, crtc->y); 105 106 /* enable it... */ 107 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; 108 if (IS_I945GM(dev)) 109 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 110 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 111 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; 112 fbc_ctl |= obj->fence_reg; 113 I915_WRITE(FBC_CONTROL, fbc_ctl); 114 115 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", 116 cfb_pitch, crtc->y, intel_crtc->plane); 117 } 118 119 static bool i8xx_fbc_enabled(struct drm_device *dev) 120 { 121 struct drm_i915_private *dev_priv = dev->dev_private; 122 123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; 124 } 125 126 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 127 { 128 struct drm_device *dev = crtc->dev; 129 struct drm_i915_private *dev_priv = dev->dev_private; 130 struct drm_framebuffer *fb = crtc->fb; 131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 132 struct drm_i915_gem_object *obj = intel_fb->obj; 133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 134 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; 135 unsigned long stall_watermark = 200; 136 u32 dpfc_ctl; 137 138 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; 139 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; 140 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); 141 142 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 143 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | 144 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); 145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y); 146 147 /* enable it... */ 148 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); 149 150 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 151 } 152 153 static void g4x_disable_fbc(struct drm_device *dev) 154 { 155 struct drm_i915_private *dev_priv = dev->dev_private; 156 u32 dpfc_ctl; 157 158 /* Disable compression */ 159 dpfc_ctl = I915_READ(DPFC_CONTROL); 160 if (dpfc_ctl & DPFC_CTL_EN) { 161 dpfc_ctl &= ~DPFC_CTL_EN; 162 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 163 164 DRM_DEBUG_KMS("disabled FBC\n"); 165 } 166 } 167 168 static bool g4x_fbc_enabled(struct drm_device *dev) 169 { 170 struct drm_i915_private *dev_priv = dev->dev_private; 171 172 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; 173 } 174 175 static void sandybridge_blit_fbc_update(struct drm_device *dev) 176 { 177 struct drm_i915_private *dev_priv = dev->dev_private; 178 u32 blt_ecoskpd; 179 180 /* Make sure blitter notifies FBC of writes */ 181 gen6_gt_force_wake_get(dev_priv); 182 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); 183 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << 184 GEN6_BLITTER_LOCK_SHIFT; 185 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; 187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 188 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << 189 GEN6_BLITTER_LOCK_SHIFT); 190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 191 POSTING_READ(GEN6_BLITTER_ECOSKPD); 192 gen6_gt_force_wake_put(dev_priv); 193 } 194 195 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 196 { 197 struct drm_device *dev = crtc->dev; 198 struct drm_i915_private *dev_priv = dev->dev_private; 199 struct drm_framebuffer *fb = crtc->fb; 200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 201 struct drm_i915_gem_object *obj = intel_fb->obj; 202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 203 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; 204 unsigned long stall_watermark = 200; 205 u32 dpfc_ctl; 206 207 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 208 dpfc_ctl &= DPFC_RESERVED; 209 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); 210 /* Set persistent mode for front-buffer rendering, ala X. */ 211 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; 212 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); 213 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); 214 215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | 217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); 218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); 219 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); 220 /* enable it... */ 221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 222 223 if (IS_GEN6(dev)) { 224 I915_WRITE(SNB_DPFC_CTL_SA, 225 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 226 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); 227 sandybridge_blit_fbc_update(dev); 228 } 229 230 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 231 } 232 233 static void ironlake_disable_fbc(struct drm_device *dev) 234 { 235 struct drm_i915_private *dev_priv = dev->dev_private; 236 u32 dpfc_ctl; 237 238 /* Disable compression */ 239 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 240 if (dpfc_ctl & DPFC_CTL_EN) { 241 dpfc_ctl &= ~DPFC_CTL_EN; 242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 243 244 DRM_DEBUG_KMS("disabled FBC\n"); 245 } 246 } 247 248 static bool ironlake_fbc_enabled(struct drm_device *dev) 249 { 250 struct drm_i915_private *dev_priv = dev->dev_private; 251 252 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; 253 } 254 255 bool intel_fbc_enabled(struct drm_device *dev) 256 { 257 struct drm_i915_private *dev_priv = dev->dev_private; 258 259 if (!dev_priv->display.fbc_enabled) 260 return false; 261 262 return dev_priv->display.fbc_enabled(dev); 263 } 264 265 static void intel_fbc_work_fn(struct work_struct *__work) 266 { 267 struct intel_fbc_work *work = 268 container_of(to_delayed_work(__work), 269 struct intel_fbc_work, work); 270 struct drm_device *dev = work->crtc->dev; 271 struct drm_i915_private *dev_priv = dev->dev_private; 272 273 mutex_lock(&dev->struct_mutex); 274 if (work == dev_priv->fbc_work) { 275 /* Double check that we haven't switched fb without cancelling 276 * the prior work. 277 */ 278 if (work->crtc->fb == work->fb) { 279 dev_priv->display.enable_fbc(work->crtc, 280 work->interval); 281 282 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; 283 dev_priv->cfb_fb = work->crtc->fb->base.id; 284 dev_priv->cfb_y = work->crtc->y; 285 } 286 287 dev_priv->fbc_work = NULL; 288 } 289 mutex_unlock(&dev->struct_mutex); 290 291 kfree(work, M_DRM); 292 } 293 294 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) 295 { 296 if (dev_priv->fbc_work == NULL) 297 return; 298 299 DRM_DEBUG_KMS("cancelling pending FBC enable\n"); 300 301 /* Synchronisation is provided by struct_mutex and checking of 302 * dev_priv->fbc_work, so we can perform the cancellation 303 * entirely asynchronously. 304 */ 305 if (cancel_delayed_work(&dev_priv->fbc_work->work)) 306 /* tasklet was killed before being run, clean up */ 307 kfree(dev_priv->fbc_work, M_DRM); 308 309 /* Mark the work as no longer wanted so that if it does 310 * wake-up (because the work was already running and waiting 311 * for our mutex), it will discover that is no longer 312 * necessary to run. 313 */ 314 dev_priv->fbc_work = NULL; 315 } 316 317 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 318 { 319 struct intel_fbc_work *work; 320 struct drm_device *dev = crtc->dev; 321 struct drm_i915_private *dev_priv = dev->dev_private; 322 323 if (!dev_priv->display.enable_fbc) 324 return; 325 326 intel_cancel_fbc_work(dev_priv); 327 328 work = kmalloc(sizeof(*work), M_DRM, M_WAITOK | M_ZERO); 329 if (work == NULL) { 330 dev_priv->display.enable_fbc(crtc, interval); 331 return; 332 } 333 334 work->crtc = crtc; 335 work->fb = crtc->fb; 336 work->interval = interval; 337 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); 338 339 dev_priv->fbc_work = work; 340 341 DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); 342 343 /* Delay the actual enabling to let pageflipping cease and the 344 * display to settle before starting the compression. Note that 345 * this delay also serves a second purpose: it allows for a 346 * vblank to pass after disabling the FBC before we attempt 347 * to modify the control registers. 348 * 349 * A more complicated solution would involve tracking vblanks 350 * following the termination of the page-flipping sequence 351 * and indeed performing the enable as a co-routine and not 352 * waiting synchronously upon the vblank. 353 */ 354 schedule_delayed_work(&work->work, msecs_to_jiffies(50)); 355 } 356 357 void intel_disable_fbc(struct drm_device *dev) 358 { 359 struct drm_i915_private *dev_priv = dev->dev_private; 360 361 intel_cancel_fbc_work(dev_priv); 362 363 if (!dev_priv->display.disable_fbc) 364 return; 365 366 dev_priv->display.disable_fbc(dev); 367 dev_priv->cfb_plane = -1; 368 } 369 370 /** 371 * intel_update_fbc - enable/disable FBC as needed 372 * @dev: the drm_device 373 * 374 * Set up the framebuffer compression hardware at mode set time. We 375 * enable it if possible: 376 * - plane A only (on pre-965) 377 * - no pixel mulitply/line duplication 378 * - no alpha buffer discard 379 * - no dual wide 380 * - framebuffer <= 2048 in width, 1536 in height 381 * 382 * We can't assume that any compression will take place (worst case), 383 * so the compressed buffer has to be the same size as the uncompressed 384 * one. It also must reside (along with the line length buffer) in 385 * stolen memory. 386 * 387 * We need to enable/disable FBC on a global basis. 388 */ 389 void intel_update_fbc(struct drm_device *dev) 390 { 391 struct drm_i915_private *dev_priv = dev->dev_private; 392 struct drm_crtc *crtc = NULL, *tmp_crtc; 393 struct intel_crtc *intel_crtc; 394 struct drm_framebuffer *fb; 395 struct intel_framebuffer *intel_fb; 396 struct drm_i915_gem_object *obj; 397 int enable_fbc; 398 399 if (!i915_powersave) 400 return; 401 402 if (!I915_HAS_FBC(dev)) 403 return; 404 405 /* 406 * If FBC is already on, we just have to verify that we can 407 * keep it that way... 408 * Need to disable if: 409 * - more than one pipe is active 410 * - changing FBC params (stride, fence, mode) 411 * - new fb is too large to fit in compressed buffer 412 * - going to an unsupported config (interlace, pixel multiply, etc.) 413 */ 414 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { 415 if (intel_crtc_active(tmp_crtc) && 416 !to_intel_crtc(tmp_crtc)->primary_disabled) { 417 if (crtc) { 418 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); 419 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; 420 goto out_disable; 421 } 422 crtc = tmp_crtc; 423 } 424 } 425 426 if (!crtc || crtc->fb == NULL) { 427 DRM_DEBUG_KMS("no output, disabling\n"); 428 dev_priv->no_fbc_reason = FBC_NO_OUTPUT; 429 goto out_disable; 430 } 431 432 intel_crtc = to_intel_crtc(crtc); 433 fb = crtc->fb; 434 intel_fb = to_intel_framebuffer(fb); 435 obj = intel_fb->obj; 436 437 enable_fbc = i915_enable_fbc; 438 if (enable_fbc < 0) { 439 DRM_DEBUG_KMS("fbc set to per-chip default\n"); 440 enable_fbc = 1; 441 if (INTEL_INFO(dev)->gen <= 6) 442 enable_fbc = 0; 443 } 444 if (!enable_fbc) { 445 DRM_DEBUG_KMS("fbc disabled per module param\n"); 446 dev_priv->no_fbc_reason = FBC_MODULE_PARAM; 447 goto out_disable; 448 } 449 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || 450 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { 451 DRM_DEBUG_KMS("mode incompatible with compression, " 452 "disabling\n"); 453 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; 454 goto out_disable; 455 } 456 if ((crtc->mode.hdisplay > 2048) || 457 (crtc->mode.vdisplay > 1536)) { 458 DRM_DEBUG_KMS("mode too large for compression, disabling\n"); 459 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; 460 goto out_disable; 461 } 462 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { 463 DRM_DEBUG_KMS("plane not 0, disabling compression\n"); 464 dev_priv->no_fbc_reason = FBC_BAD_PLANE; 465 goto out_disable; 466 } 467 468 /* The use of a CPU fence is mandatory in order to detect writes 469 * by the CPU to the scanout and trigger updates to the FBC. 470 */ 471 if (obj->tiling_mode != I915_TILING_X || 472 obj->fence_reg == I915_FENCE_REG_NONE) { 473 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); 474 dev_priv->no_fbc_reason = FBC_NOT_TILED; 475 goto out_disable; 476 } 477 478 #ifdef DDB 479 /* If the kernel debugger is active, always disable compression */ 480 if (db_active) 481 goto out_disable; 482 #endif 483 484 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) { 485 DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb->obj->base.size); 486 DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n"); 487 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); 488 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; 489 goto out_disable; 490 } 491 492 /* If the scanout has not changed, don't modify the FBC settings. 493 * Note that we make the fundamental assumption that the fb->obj 494 * cannot be unpinned (and have its GTT offset and fence revoked) 495 * without first being decoupled from the scanout and FBC disabled. 496 */ 497 if (dev_priv->cfb_plane == intel_crtc->plane && 498 dev_priv->cfb_fb == fb->base.id && 499 dev_priv->cfb_y == crtc->y) 500 return; 501 502 if (intel_fbc_enabled(dev)) { 503 /* We update FBC along two paths, after changing fb/crtc 504 * configuration (modeswitching) and after page-flipping 505 * finishes. For the latter, we know that not only did 506 * we disable the FBC at the start of the page-flip 507 * sequence, but also more than one vblank has passed. 508 * 509 * For the former case of modeswitching, it is possible 510 * to switch between two FBC valid configurations 511 * instantaneously so we do need to disable the FBC 512 * before we can modify its control registers. We also 513 * have to wait for the next vblank for that to take 514 * effect. However, since we delay enabling FBC we can 515 * assume that a vblank has passed since disabling and 516 * that we can safely alter the registers in the deferred 517 * callback. 518 * 519 * In the scenario that we go from a valid to invalid 520 * and then back to valid FBC configuration we have 521 * no strict enforcement that a vblank occurred since 522 * disabling the FBC. However, along all current pipe 523 * disabling paths we do need to wait for a vblank at 524 * some point. And we wait before enabling FBC anyway. 525 */ 526 DRM_DEBUG_KMS("disabling active FBC for update\n"); 527 intel_disable_fbc(dev); 528 } 529 530 intel_enable_fbc(crtc, 500); 531 return; 532 533 out_disable: 534 /* Multiple disables should be harmless */ 535 if (intel_fbc_enabled(dev)) { 536 DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); 537 intel_disable_fbc(dev); 538 } 539 i915_gem_stolen_cleanup_compression(dev); 540 } 541 542 static void i915_pineview_get_mem_freq(struct drm_device *dev) 543 { 544 drm_i915_private_t *dev_priv = dev->dev_private; 545 u32 tmp; 546 547 tmp = I915_READ(CLKCFG); 548 549 switch (tmp & CLKCFG_FSB_MASK) { 550 case CLKCFG_FSB_533: 551 dev_priv->fsb_freq = 533; /* 133*4 */ 552 break; 553 case CLKCFG_FSB_800: 554 dev_priv->fsb_freq = 800; /* 200*4 */ 555 break; 556 case CLKCFG_FSB_667: 557 dev_priv->fsb_freq = 667; /* 167*4 */ 558 break; 559 case CLKCFG_FSB_400: 560 dev_priv->fsb_freq = 400; /* 100*4 */ 561 break; 562 } 563 564 switch (tmp & CLKCFG_MEM_MASK) { 565 case CLKCFG_MEM_533: 566 dev_priv->mem_freq = 533; 567 break; 568 case CLKCFG_MEM_667: 569 dev_priv->mem_freq = 667; 570 break; 571 case CLKCFG_MEM_800: 572 dev_priv->mem_freq = 800; 573 break; 574 } 575 576 /* detect pineview DDR3 setting */ 577 tmp = I915_READ(CSHRDDR3CTL); 578 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 579 } 580 581 static void i915_ironlake_get_mem_freq(struct drm_device *dev) 582 { 583 drm_i915_private_t *dev_priv = dev->dev_private; 584 u16 ddrpll, csipll; 585 586 ddrpll = I915_READ16(DDRMPLL1); 587 csipll = I915_READ16(CSIPLL0); 588 589 switch (ddrpll & 0xff) { 590 case 0xc: 591 dev_priv->mem_freq = 800; 592 break; 593 case 0x10: 594 dev_priv->mem_freq = 1066; 595 break; 596 case 0x14: 597 dev_priv->mem_freq = 1333; 598 break; 599 case 0x18: 600 dev_priv->mem_freq = 1600; 601 break; 602 default: 603 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 604 ddrpll & 0xff); 605 dev_priv->mem_freq = 0; 606 break; 607 } 608 609 dev_priv->ips.r_t = dev_priv->mem_freq; 610 611 switch (csipll & 0x3ff) { 612 case 0x00c: 613 dev_priv->fsb_freq = 3200; 614 break; 615 case 0x00e: 616 dev_priv->fsb_freq = 3733; 617 break; 618 case 0x010: 619 dev_priv->fsb_freq = 4266; 620 break; 621 case 0x012: 622 dev_priv->fsb_freq = 4800; 623 break; 624 case 0x014: 625 dev_priv->fsb_freq = 5333; 626 break; 627 case 0x016: 628 dev_priv->fsb_freq = 5866; 629 break; 630 case 0x018: 631 dev_priv->fsb_freq = 6400; 632 break; 633 default: 634 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 635 csipll & 0x3ff); 636 dev_priv->fsb_freq = 0; 637 break; 638 } 639 640 if (dev_priv->fsb_freq == 3200) { 641 dev_priv->ips.c_m = 0; 642 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 643 dev_priv->ips.c_m = 1; 644 } else { 645 dev_priv->ips.c_m = 2; 646 } 647 } 648 649 static const struct cxsr_latency cxsr_latency_table[] = { 650 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 651 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 652 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 653 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 654 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 655 656 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 657 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 658 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 659 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 660 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 661 662 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 663 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 664 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 665 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 666 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 667 668 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 669 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 670 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 671 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 672 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 673 674 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 675 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 676 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 677 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 678 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 679 680 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 681 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 682 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 683 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 684 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 685 }; 686 687 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 688 int is_ddr3, 689 int fsb, 690 int mem) 691 { 692 const struct cxsr_latency *latency; 693 int i; 694 695 if (fsb == 0 || mem == 0) 696 return NULL; 697 698 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 699 latency = &cxsr_latency_table[i]; 700 if (is_desktop == latency->is_desktop && 701 is_ddr3 == latency->is_ddr3 && 702 fsb == latency->fsb_freq && mem == latency->mem_freq) 703 return latency; 704 } 705 706 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 707 708 return NULL; 709 } 710 711 static void pineview_disable_cxsr(struct drm_device *dev) 712 { 713 struct drm_i915_private *dev_priv = dev->dev_private; 714 715 /* deactivate cxsr */ 716 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); 717 } 718 719 /* 720 * Latency for FIFO fetches is dependent on several factors: 721 * - memory configuration (speed, channels) 722 * - chipset 723 * - current MCH state 724 * It can be fairly high in some situations, so here we assume a fairly 725 * pessimal value. It's a tradeoff between extra memory fetches (if we 726 * set this value too high, the FIFO will fetch frequently to stay full) 727 * and power consumption (set it too low to save power and we might see 728 * FIFO underruns and display "flicker"). 729 * 730 * A value of 5us seems to be a good balance; safe for very low end 731 * platforms but not overly aggressive on lower latency configs. 732 */ 733 static const int latency_ns = 5000; 734 735 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 736 { 737 struct drm_i915_private *dev_priv = dev->dev_private; 738 uint32_t dsparb = I915_READ(DSPARB); 739 int size; 740 741 size = dsparb & 0x7f; 742 if (plane) 743 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 744 745 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 746 plane ? "B" : "A", size); 747 748 return size; 749 } 750 751 static int i85x_get_fifo_size(struct drm_device *dev, int plane) 752 { 753 struct drm_i915_private *dev_priv = dev->dev_private; 754 uint32_t dsparb = I915_READ(DSPARB); 755 int size; 756 757 size = dsparb & 0x1ff; 758 if (plane) 759 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 760 size >>= 1; /* Convert to cachelines */ 761 762 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 763 plane ? "B" : "A", size); 764 765 return size; 766 } 767 768 static int i845_get_fifo_size(struct drm_device *dev, int plane) 769 { 770 struct drm_i915_private *dev_priv = dev->dev_private; 771 uint32_t dsparb = I915_READ(DSPARB); 772 int size; 773 774 size = dsparb & 0x7f; 775 size >>= 2; /* Convert to cachelines */ 776 777 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 778 plane ? "B" : "A", 779 size); 780 781 return size; 782 } 783 784 static int i830_get_fifo_size(struct drm_device *dev, int plane) 785 { 786 struct drm_i915_private *dev_priv = dev->dev_private; 787 uint32_t dsparb = I915_READ(DSPARB); 788 int size; 789 790 size = dsparb & 0x7f; 791 size >>= 1; /* Convert to cachelines */ 792 793 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 794 plane ? "B" : "A", size); 795 796 return size; 797 } 798 799 /* Pineview has different values for various configs */ 800 static const struct intel_watermark_params pineview_display_wm = { 801 PINEVIEW_DISPLAY_FIFO, 802 PINEVIEW_MAX_WM, 803 PINEVIEW_DFT_WM, 804 PINEVIEW_GUARD_WM, 805 PINEVIEW_FIFO_LINE_SIZE 806 }; 807 static const struct intel_watermark_params pineview_display_hplloff_wm = { 808 PINEVIEW_DISPLAY_FIFO, 809 PINEVIEW_MAX_WM, 810 PINEVIEW_DFT_HPLLOFF_WM, 811 PINEVIEW_GUARD_WM, 812 PINEVIEW_FIFO_LINE_SIZE 813 }; 814 static const struct intel_watermark_params pineview_cursor_wm = { 815 PINEVIEW_CURSOR_FIFO, 816 PINEVIEW_CURSOR_MAX_WM, 817 PINEVIEW_CURSOR_DFT_WM, 818 PINEVIEW_CURSOR_GUARD_WM, 819 PINEVIEW_FIFO_LINE_SIZE, 820 }; 821 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 822 PINEVIEW_CURSOR_FIFO, 823 PINEVIEW_CURSOR_MAX_WM, 824 PINEVIEW_CURSOR_DFT_WM, 825 PINEVIEW_CURSOR_GUARD_WM, 826 PINEVIEW_FIFO_LINE_SIZE 827 }; 828 static const struct intel_watermark_params g4x_wm_info = { 829 G4X_FIFO_SIZE, 830 G4X_MAX_WM, 831 G4X_MAX_WM, 832 2, 833 G4X_FIFO_LINE_SIZE, 834 }; 835 static const struct intel_watermark_params g4x_cursor_wm_info = { 836 I965_CURSOR_FIFO, 837 I965_CURSOR_MAX_WM, 838 I965_CURSOR_DFT_WM, 839 2, 840 G4X_FIFO_LINE_SIZE, 841 }; 842 static const struct intel_watermark_params valleyview_wm_info = { 843 VALLEYVIEW_FIFO_SIZE, 844 VALLEYVIEW_MAX_WM, 845 VALLEYVIEW_MAX_WM, 846 2, 847 G4X_FIFO_LINE_SIZE, 848 }; 849 static const struct intel_watermark_params valleyview_cursor_wm_info = { 850 I965_CURSOR_FIFO, 851 VALLEYVIEW_CURSOR_MAX_WM, 852 I965_CURSOR_DFT_WM, 853 2, 854 G4X_FIFO_LINE_SIZE, 855 }; 856 static const struct intel_watermark_params i965_cursor_wm_info = { 857 I965_CURSOR_FIFO, 858 I965_CURSOR_MAX_WM, 859 I965_CURSOR_DFT_WM, 860 2, 861 I915_FIFO_LINE_SIZE, 862 }; 863 static const struct intel_watermark_params i945_wm_info = { 864 I945_FIFO_SIZE, 865 I915_MAX_WM, 866 1, 867 2, 868 I915_FIFO_LINE_SIZE 869 }; 870 static const struct intel_watermark_params i915_wm_info = { 871 I915_FIFO_SIZE, 872 I915_MAX_WM, 873 1, 874 2, 875 I915_FIFO_LINE_SIZE 876 }; 877 static const struct intel_watermark_params i855_wm_info = { 878 I855GM_FIFO_SIZE, 879 I915_MAX_WM, 880 1, 881 2, 882 I830_FIFO_LINE_SIZE 883 }; 884 static const struct intel_watermark_params i830_wm_info = { 885 I830_FIFO_SIZE, 886 I915_MAX_WM, 887 1, 888 2, 889 I830_FIFO_LINE_SIZE 890 }; 891 892 static const struct intel_watermark_params ironlake_display_wm_info = { 893 ILK_DISPLAY_FIFO, 894 ILK_DISPLAY_MAXWM, 895 ILK_DISPLAY_DFTWM, 896 2, 897 ILK_FIFO_LINE_SIZE 898 }; 899 static const struct intel_watermark_params ironlake_cursor_wm_info = { 900 ILK_CURSOR_FIFO, 901 ILK_CURSOR_MAXWM, 902 ILK_CURSOR_DFTWM, 903 2, 904 ILK_FIFO_LINE_SIZE 905 }; 906 static const struct intel_watermark_params ironlake_display_srwm_info = { 907 ILK_DISPLAY_SR_FIFO, 908 ILK_DISPLAY_MAX_SRWM, 909 ILK_DISPLAY_DFT_SRWM, 910 2, 911 ILK_FIFO_LINE_SIZE 912 }; 913 static const struct intel_watermark_params ironlake_cursor_srwm_info = { 914 ILK_CURSOR_SR_FIFO, 915 ILK_CURSOR_MAX_SRWM, 916 ILK_CURSOR_DFT_SRWM, 917 2, 918 ILK_FIFO_LINE_SIZE 919 }; 920 921 static const struct intel_watermark_params sandybridge_display_wm_info = { 922 SNB_DISPLAY_FIFO, 923 SNB_DISPLAY_MAXWM, 924 SNB_DISPLAY_DFTWM, 925 2, 926 SNB_FIFO_LINE_SIZE 927 }; 928 static const struct intel_watermark_params sandybridge_cursor_wm_info = { 929 SNB_CURSOR_FIFO, 930 SNB_CURSOR_MAXWM, 931 SNB_CURSOR_DFTWM, 932 2, 933 SNB_FIFO_LINE_SIZE 934 }; 935 static const struct intel_watermark_params sandybridge_display_srwm_info = { 936 SNB_DISPLAY_SR_FIFO, 937 SNB_DISPLAY_MAX_SRWM, 938 SNB_DISPLAY_DFT_SRWM, 939 2, 940 SNB_FIFO_LINE_SIZE 941 }; 942 static const struct intel_watermark_params sandybridge_cursor_srwm_info = { 943 SNB_CURSOR_SR_FIFO, 944 SNB_CURSOR_MAX_SRWM, 945 SNB_CURSOR_DFT_SRWM, 946 2, 947 SNB_FIFO_LINE_SIZE 948 }; 949 950 951 /** 952 * intel_calculate_wm - calculate watermark level 953 * @clock_in_khz: pixel clock 954 * @wm: chip FIFO params 955 * @pixel_size: display pixel size 956 * @latency_ns: memory latency for the platform 957 * 958 * Calculate the watermark level (the level at which the display plane will 959 * start fetching from memory again). Each chip has a different display 960 * FIFO size and allocation, so the caller needs to figure that out and pass 961 * in the correct intel_watermark_params structure. 962 * 963 * As the pixel clock runs, the FIFO will be drained at a rate that depends 964 * on the pixel size. When it reaches the watermark level, it'll start 965 * fetching FIFO line sized based chunks from memory until the FIFO fills 966 * past the watermark point. If the FIFO drains completely, a FIFO underrun 967 * will occur, and a display engine hang could result. 968 */ 969 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 970 const struct intel_watermark_params *wm, 971 int fifo_size, 972 int pixel_size, 973 unsigned long latency_ns) 974 { 975 long entries_required, wm_size; 976 977 /* 978 * Note: we need to make sure we don't overflow for various clock & 979 * latency values. 980 * clocks go from a few thousand to several hundred thousand. 981 * latency is usually a few thousand 982 */ 983 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 984 1000; 985 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 986 987 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 988 989 wm_size = fifo_size - (entries_required + wm->guard_size); 990 991 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 992 993 /* Don't promote wm_size to unsigned... */ 994 if (wm_size > (long)wm->max_wm) 995 wm_size = wm->max_wm; 996 if (wm_size <= 0) 997 wm_size = wm->default_wm; 998 return wm_size; 999 } 1000 1001 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 1002 { 1003 struct drm_crtc *crtc, *enabled = NULL; 1004 1005 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1006 if (intel_crtc_active(crtc)) { 1007 if (enabled) 1008 return NULL; 1009 enabled = crtc; 1010 } 1011 } 1012 1013 return enabled; 1014 } 1015 1016 static void pineview_update_wm(struct drm_device *dev) 1017 { 1018 struct drm_i915_private *dev_priv = dev->dev_private; 1019 struct drm_crtc *crtc; 1020 const struct cxsr_latency *latency; 1021 u32 reg; 1022 unsigned long wm; 1023 1024 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 1025 dev_priv->fsb_freq, dev_priv->mem_freq); 1026 if (!latency) { 1027 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 1028 pineview_disable_cxsr(dev); 1029 return; 1030 } 1031 1032 crtc = single_enabled_crtc(dev); 1033 if (crtc) { 1034 int clock = crtc->mode.clock; 1035 int pixel_size = crtc->fb->bits_per_pixel / 8; 1036 1037 /* Display SR */ 1038 wm = intel_calculate_wm(clock, &pineview_display_wm, 1039 pineview_display_wm.fifo_size, 1040 pixel_size, latency->display_sr); 1041 reg = I915_READ(DSPFW1); 1042 reg &= ~DSPFW_SR_MASK; 1043 reg |= wm << DSPFW_SR_SHIFT; 1044 I915_WRITE(DSPFW1, reg); 1045 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 1046 1047 /* cursor SR */ 1048 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 1049 pineview_display_wm.fifo_size, 1050 pixel_size, latency->cursor_sr); 1051 reg = I915_READ(DSPFW3); 1052 reg &= ~DSPFW_CURSOR_SR_MASK; 1053 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; 1054 I915_WRITE(DSPFW3, reg); 1055 1056 /* Display HPLL off SR */ 1057 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 1058 pineview_display_hplloff_wm.fifo_size, 1059 pixel_size, latency->display_hpll_disable); 1060 reg = I915_READ(DSPFW3); 1061 reg &= ~DSPFW_HPLL_SR_MASK; 1062 reg |= wm & DSPFW_HPLL_SR_MASK; 1063 I915_WRITE(DSPFW3, reg); 1064 1065 /* cursor HPLL off SR */ 1066 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 1067 pineview_display_hplloff_wm.fifo_size, 1068 pixel_size, latency->cursor_hpll_disable); 1069 reg = I915_READ(DSPFW3); 1070 reg &= ~DSPFW_HPLL_CURSOR_MASK; 1071 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; 1072 I915_WRITE(DSPFW3, reg); 1073 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 1074 1075 /* activate cxsr */ 1076 I915_WRITE(DSPFW3, 1077 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); 1078 DRM_DEBUG_KMS("Self-refresh is enabled\n"); 1079 } else { 1080 pineview_disable_cxsr(dev); 1081 DRM_DEBUG_KMS("Self-refresh is disabled\n"); 1082 } 1083 } 1084 1085 static bool g4x_compute_wm0(struct drm_device *dev, 1086 int plane, 1087 const struct intel_watermark_params *display, 1088 int display_latency_ns, 1089 const struct intel_watermark_params *cursor, 1090 int cursor_latency_ns, 1091 int *plane_wm, 1092 int *cursor_wm) 1093 { 1094 struct drm_crtc *crtc; 1095 int htotal, hdisplay, clock, pixel_size; 1096 int line_time_us, line_count; 1097 int entries, tlb_miss; 1098 1099 crtc = intel_get_crtc_for_plane(dev, plane); 1100 if (!intel_crtc_active(crtc)) { 1101 *cursor_wm = cursor->guard_size; 1102 *plane_wm = display->guard_size; 1103 return false; 1104 } 1105 1106 htotal = crtc->mode.htotal; 1107 hdisplay = crtc->mode.hdisplay; 1108 clock = crtc->mode.clock; 1109 pixel_size = crtc->fb->bits_per_pixel / 8; 1110 1111 /* Use the small buffer method to calculate plane watermark */ 1112 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 1113 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 1114 if (tlb_miss > 0) 1115 entries += tlb_miss; 1116 entries = DIV_ROUND_UP(entries, display->cacheline_size); 1117 *plane_wm = entries + display->guard_size; 1118 if (*plane_wm > (int)display->max_wm) 1119 *plane_wm = display->max_wm; 1120 1121 /* Use the large buffer method to calculate cursor watermark */ 1122 line_time_us = ((htotal * 1000) / clock); 1123 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 1124 entries = line_count * 64 * pixel_size; 1125 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 1126 if (tlb_miss > 0) 1127 entries += tlb_miss; 1128 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1129 *cursor_wm = entries + cursor->guard_size; 1130 if (*cursor_wm > (int)cursor->max_wm) 1131 *cursor_wm = (int)cursor->max_wm; 1132 1133 return true; 1134 } 1135 1136 /* 1137 * Check the wm result. 1138 * 1139 * If any calculated watermark values is larger than the maximum value that 1140 * can be programmed into the associated watermark register, that watermark 1141 * must be disabled. 1142 */ 1143 static bool g4x_check_srwm(struct drm_device *dev, 1144 int display_wm, int cursor_wm, 1145 const struct intel_watermark_params *display, 1146 const struct intel_watermark_params *cursor) 1147 { 1148 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 1149 display_wm, cursor_wm); 1150 1151 if (display_wm > display->max_wm) { 1152 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 1153 display_wm, display->max_wm); 1154 return false; 1155 } 1156 1157 if (cursor_wm > cursor->max_wm) { 1158 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 1159 cursor_wm, cursor->max_wm); 1160 return false; 1161 } 1162 1163 if (!(display_wm || cursor_wm)) { 1164 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 1165 return false; 1166 } 1167 1168 return true; 1169 } 1170 1171 static bool g4x_compute_srwm(struct drm_device *dev, 1172 int plane, 1173 int latency_ns, 1174 const struct intel_watermark_params *display, 1175 const struct intel_watermark_params *cursor, 1176 int *display_wm, int *cursor_wm) 1177 { 1178 struct drm_crtc *crtc; 1179 int hdisplay, htotal, pixel_size, clock; 1180 unsigned long line_time_us; 1181 int line_count, line_size; 1182 int small, large; 1183 int entries; 1184 1185 if (!latency_ns) { 1186 *display_wm = *cursor_wm = 0; 1187 return false; 1188 } 1189 1190 crtc = intel_get_crtc_for_plane(dev, plane); 1191 hdisplay = crtc->mode.hdisplay; 1192 htotal = crtc->mode.htotal; 1193 clock = crtc->mode.clock; 1194 pixel_size = crtc->fb->bits_per_pixel / 8; 1195 1196 line_time_us = (htotal * 1000) / clock; 1197 line_count = (latency_ns / line_time_us + 1000) / 1000; 1198 line_size = hdisplay * pixel_size; 1199 1200 /* Use the minimum of the small and large buffer method for primary */ 1201 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1202 large = line_count * line_size; 1203 1204 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 1205 *display_wm = entries + display->guard_size; 1206 1207 /* calculate the self-refresh watermark for display cursor */ 1208 entries = line_count * pixel_size * 64; 1209 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1210 *cursor_wm = entries + cursor->guard_size; 1211 1212 return g4x_check_srwm(dev, 1213 *display_wm, *cursor_wm, 1214 display, cursor); 1215 } 1216 1217 static bool vlv_compute_drain_latency(struct drm_device *dev, 1218 int plane, 1219 int *plane_prec_mult, 1220 int *plane_dl, 1221 int *cursor_prec_mult, 1222 int *cursor_dl) 1223 { 1224 struct drm_crtc *crtc; 1225 int clock, pixel_size; 1226 int entries; 1227 1228 crtc = intel_get_crtc_for_plane(dev, plane); 1229 if (!intel_crtc_active(crtc)) 1230 return false; 1231 1232 clock = crtc->mode.clock; /* VESA DOT Clock */ 1233 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ 1234 1235 entries = (clock / 1000) * pixel_size; 1236 *plane_prec_mult = (entries > 256) ? 1237 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; 1238 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * 1239 pixel_size); 1240 1241 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ 1242 *cursor_prec_mult = (entries > 256) ? 1243 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; 1244 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); 1245 1246 return true; 1247 } 1248 1249 /* 1250 * Update drain latency registers of memory arbiter 1251 * 1252 * Valleyview SoC has a new memory arbiter and needs drain latency registers 1253 * to be programmed. Each plane has a drain latency multiplier and a drain 1254 * latency value. 1255 */ 1256 1257 static void vlv_update_drain_latency(struct drm_device *dev) 1258 { 1259 struct drm_i915_private *dev_priv = dev->dev_private; 1260 int planea_prec, planea_dl, planeb_prec, planeb_dl; 1261 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; 1262 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is 1263 either 16 or 32 */ 1264 1265 /* For plane A, Cursor A */ 1266 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, 1267 &cursor_prec_mult, &cursora_dl)) { 1268 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1269 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; 1270 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1271 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; 1272 1273 I915_WRITE(VLV_DDL1, cursora_prec | 1274 (cursora_dl << DDL_CURSORA_SHIFT) | 1275 planea_prec | planea_dl); 1276 } 1277 1278 /* For plane B, Cursor B */ 1279 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, 1280 &cursor_prec_mult, &cursorb_dl)) { 1281 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1282 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; 1283 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? 1284 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; 1285 1286 I915_WRITE(VLV_DDL2, cursorb_prec | 1287 (cursorb_dl << DDL_CURSORB_SHIFT) | 1288 planeb_prec | planeb_dl); 1289 } 1290 } 1291 1292 #define single_plane_enabled(mask) is_power_of_2(mask) 1293 1294 static void valleyview_update_wm(struct drm_device *dev) 1295 { 1296 static const int sr_latency_ns = 12000; 1297 struct drm_i915_private *dev_priv = dev->dev_private; 1298 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1299 int plane_sr, cursor_sr; 1300 int ignore_plane_sr, ignore_cursor_sr; 1301 unsigned int enabled = 0; 1302 1303 vlv_update_drain_latency(dev); 1304 1305 if (g4x_compute_wm0(dev, 0, 1306 &valleyview_wm_info, latency_ns, 1307 &valleyview_cursor_wm_info, latency_ns, 1308 &planea_wm, &cursora_wm)) 1309 enabled |= 1; 1310 1311 if (g4x_compute_wm0(dev, 1, 1312 &valleyview_wm_info, latency_ns, 1313 &valleyview_cursor_wm_info, latency_ns, 1314 &planeb_wm, &cursorb_wm)) 1315 enabled |= 2; 1316 1317 if (single_plane_enabled(enabled) && 1318 g4x_compute_srwm(dev, ffs(enabled) - 1, 1319 sr_latency_ns, 1320 &valleyview_wm_info, 1321 &valleyview_cursor_wm_info, 1322 &plane_sr, &ignore_cursor_sr) && 1323 g4x_compute_srwm(dev, ffs(enabled) - 1, 1324 2*sr_latency_ns, 1325 &valleyview_wm_info, 1326 &valleyview_cursor_wm_info, 1327 &ignore_plane_sr, &cursor_sr)) { 1328 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); 1329 } else { 1330 I915_WRITE(FW_BLC_SELF_VLV, 1331 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); 1332 plane_sr = cursor_sr = 0; 1333 } 1334 1335 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1336 planea_wm, cursora_wm, 1337 planeb_wm, cursorb_wm, 1338 plane_sr, cursor_sr); 1339 1340 I915_WRITE(DSPFW1, 1341 (plane_sr << DSPFW_SR_SHIFT) | 1342 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1343 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1344 planea_wm); 1345 I915_WRITE(DSPFW2, 1346 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1347 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1348 I915_WRITE(DSPFW3, 1349 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | 1350 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1351 } 1352 1353 static void g4x_update_wm(struct drm_device *dev) 1354 { 1355 static const int sr_latency_ns = 12000; 1356 struct drm_i915_private *dev_priv = dev->dev_private; 1357 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1358 int plane_sr, cursor_sr; 1359 unsigned int enabled = 0; 1360 1361 if (g4x_compute_wm0(dev, 0, 1362 &g4x_wm_info, latency_ns, 1363 &g4x_cursor_wm_info, latency_ns, 1364 &planea_wm, &cursora_wm)) 1365 enabled |= 1; 1366 1367 if (g4x_compute_wm0(dev, 1, 1368 &g4x_wm_info, latency_ns, 1369 &g4x_cursor_wm_info, latency_ns, 1370 &planeb_wm, &cursorb_wm)) 1371 enabled |= 2; 1372 1373 if (single_plane_enabled(enabled) && 1374 g4x_compute_srwm(dev, ffs(enabled) - 1, 1375 sr_latency_ns, 1376 &g4x_wm_info, 1377 &g4x_cursor_wm_info, 1378 &plane_sr, &cursor_sr)) { 1379 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1380 } else { 1381 I915_WRITE(FW_BLC_SELF, 1382 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); 1383 plane_sr = cursor_sr = 0; 1384 } 1385 1386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1387 planea_wm, cursora_wm, 1388 planeb_wm, cursorb_wm, 1389 plane_sr, cursor_sr); 1390 1391 I915_WRITE(DSPFW1, 1392 (plane_sr << DSPFW_SR_SHIFT) | 1393 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1394 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1395 planea_wm); 1396 I915_WRITE(DSPFW2, 1397 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1398 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1399 /* HPLL off in SR has some issues on G4x... disable it */ 1400 I915_WRITE(DSPFW3, 1401 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1402 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1403 } 1404 1405 static void i965_update_wm(struct drm_device *dev) 1406 { 1407 struct drm_i915_private *dev_priv = dev->dev_private; 1408 struct drm_crtc *crtc; 1409 int srwm = 1; 1410 int cursor_sr = 16; 1411 1412 /* Calc sr entries for one plane configs */ 1413 crtc = single_enabled_crtc(dev); 1414 if (crtc) { 1415 /* self-refresh has much higher latency */ 1416 static const int sr_latency_ns = 12000; 1417 int clock = crtc->mode.clock; 1418 int htotal = crtc->mode.htotal; 1419 int hdisplay = crtc->mode.hdisplay; 1420 int pixel_size = crtc->fb->bits_per_pixel / 8; 1421 unsigned long line_time_us; 1422 int entries; 1423 1424 line_time_us = ((htotal * 1000) / clock); 1425 1426 /* Use ns/us then divide to preserve precision */ 1427 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1428 pixel_size * hdisplay; 1429 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1430 srwm = I965_FIFO_SIZE - entries; 1431 if (srwm < 0) 1432 srwm = 1; 1433 srwm &= 0x1ff; 1434 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1435 entries, srwm); 1436 1437 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1438 pixel_size * 64; 1439 entries = DIV_ROUND_UP(entries, 1440 i965_cursor_wm_info.cacheline_size); 1441 cursor_sr = i965_cursor_wm_info.fifo_size - 1442 (entries + i965_cursor_wm_info.guard_size); 1443 1444 if (cursor_sr > i965_cursor_wm_info.max_wm) 1445 cursor_sr = i965_cursor_wm_info.max_wm; 1446 1447 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1448 "cursor %d\n", srwm, cursor_sr); 1449 1450 if (IS_CRESTLINE(dev)) 1451 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1452 } else { 1453 /* Turn off self refresh if both pipes are enabled */ 1454 if (IS_CRESTLINE(dev)) 1455 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) 1456 & ~FW_BLC_SELF_EN); 1457 } 1458 1459 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1460 srwm); 1461 1462 /* 965 has limitations... */ 1463 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | 1464 (8 << 16) | (8 << 8) | (8 << 0)); 1465 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 1466 /* update cursor SR watermark */ 1467 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1468 } 1469 1470 static void i9xx_update_wm(struct drm_device *dev) 1471 { 1472 struct drm_i915_private *dev_priv = dev->dev_private; 1473 const struct intel_watermark_params *wm_info; 1474 uint32_t fwater_lo; 1475 uint32_t fwater_hi; 1476 int cwm, srwm = 1; 1477 int fifo_size; 1478 int planea_wm, planeb_wm; 1479 struct drm_crtc *crtc, *enabled = NULL; 1480 1481 if (IS_I945GM(dev)) 1482 wm_info = &i945_wm_info; 1483 else if (!IS_GEN2(dev)) 1484 wm_info = &i915_wm_info; 1485 else 1486 wm_info = &i855_wm_info; 1487 1488 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1489 crtc = intel_get_crtc_for_plane(dev, 0); 1490 if (intel_crtc_active(crtc)) { 1491 int cpp = crtc->fb->bits_per_pixel / 8; 1492 if (IS_GEN2(dev)) 1493 cpp = 4; 1494 1495 planea_wm = intel_calculate_wm(crtc->mode.clock, 1496 wm_info, fifo_size, cpp, 1497 latency_ns); 1498 enabled = crtc; 1499 } else 1500 planea_wm = fifo_size - wm_info->guard_size; 1501 1502 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1503 crtc = intel_get_crtc_for_plane(dev, 1); 1504 if (intel_crtc_active(crtc)) { 1505 int cpp = crtc->fb->bits_per_pixel / 8; 1506 if (IS_GEN2(dev)) 1507 cpp = 4; 1508 1509 planeb_wm = intel_calculate_wm(crtc->mode.clock, 1510 wm_info, fifo_size, cpp, 1511 latency_ns); 1512 if (enabled == NULL) 1513 enabled = crtc; 1514 else 1515 enabled = NULL; 1516 } else 1517 planeb_wm = fifo_size - wm_info->guard_size; 1518 1519 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1520 1521 /* 1522 * Overlay gets an aggressive default since video jitter is bad. 1523 */ 1524 cwm = 2; 1525 1526 /* Play safe and disable self-refresh before adjusting watermarks. */ 1527 if (IS_I945G(dev) || IS_I945GM(dev)) 1528 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); 1529 else if (IS_I915GM(dev)) 1530 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); 1531 1532 /* Calc sr entries for one plane configs */ 1533 if (HAS_FW_BLC(dev) && enabled) { 1534 /* self-refresh has much higher latency */ 1535 static const int sr_latency_ns = 6000; 1536 int clock = enabled->mode.clock; 1537 int htotal = enabled->mode.htotal; 1538 int hdisplay = enabled->mode.hdisplay; 1539 int pixel_size = enabled->fb->bits_per_pixel / 8; 1540 unsigned long line_time_us; 1541 int entries; 1542 1543 line_time_us = (htotal * 1000) / clock; 1544 1545 /* Use ns/us then divide to preserve precision */ 1546 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1547 pixel_size * hdisplay; 1548 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1549 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1550 srwm = wm_info->fifo_size - entries; 1551 if (srwm < 0) 1552 srwm = 1; 1553 1554 if (IS_I945G(dev) || IS_I945GM(dev)) 1555 I915_WRITE(FW_BLC_SELF, 1556 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1557 else if (IS_I915GM(dev)) 1558 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1559 } 1560 1561 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1562 planea_wm, planeb_wm, cwm, srwm); 1563 1564 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1565 fwater_hi = (cwm & 0x1f); 1566 1567 /* Set request length to 8 cachelines per fetch */ 1568 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1569 fwater_hi = fwater_hi | (1 << 8); 1570 1571 I915_WRITE(FW_BLC, fwater_lo); 1572 I915_WRITE(FW_BLC2, fwater_hi); 1573 1574 if (HAS_FW_BLC(dev)) { 1575 if (enabled) { 1576 if (IS_I945G(dev) || IS_I945GM(dev)) 1577 I915_WRITE(FW_BLC_SELF, 1578 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); 1579 else if (IS_I915GM(dev)) 1580 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); 1581 DRM_DEBUG_KMS("memory self refresh enabled\n"); 1582 } else 1583 DRM_DEBUG_KMS("memory self refresh disabled\n"); 1584 } 1585 } 1586 1587 static void i830_update_wm(struct drm_device *dev) 1588 { 1589 struct drm_i915_private *dev_priv = dev->dev_private; 1590 struct drm_crtc *crtc; 1591 uint32_t fwater_lo; 1592 int planea_wm; 1593 1594 crtc = single_enabled_crtc(dev); 1595 if (crtc == NULL) 1596 return; 1597 1598 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, 1599 dev_priv->display.get_fifo_size(dev, 0), 1600 4, latency_ns); 1601 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1602 fwater_lo |= (3<<8) | planea_wm; 1603 1604 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1605 1606 I915_WRITE(FW_BLC, fwater_lo); 1607 } 1608 1609 #define ILK_LP0_PLANE_LATENCY 700 1610 #define ILK_LP0_CURSOR_LATENCY 1300 1611 1612 /* 1613 * Check the wm result. 1614 * 1615 * If any calculated watermark values is larger than the maximum value that 1616 * can be programmed into the associated watermark register, that watermark 1617 * must be disabled. 1618 */ 1619 static bool ironlake_check_srwm(struct drm_device *dev, int level, 1620 int fbc_wm, int display_wm, int cursor_wm, 1621 const struct intel_watermark_params *display, 1622 const struct intel_watermark_params *cursor) 1623 { 1624 struct drm_i915_private *dev_priv = dev->dev_private; 1625 1626 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," 1627 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); 1628 1629 if (fbc_wm > SNB_FBC_MAX_SRWM) { 1630 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", 1631 fbc_wm, SNB_FBC_MAX_SRWM, level); 1632 1633 /* fbc has it's own way to disable FBC WM */ 1634 I915_WRITE(DISP_ARB_CTL, 1635 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); 1636 return false; 1637 } 1638 1639 if (display_wm > display->max_wm) { 1640 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", 1641 display_wm, SNB_DISPLAY_MAX_SRWM, level); 1642 return false; 1643 } 1644 1645 if (cursor_wm > cursor->max_wm) { 1646 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", 1647 cursor_wm, SNB_CURSOR_MAX_SRWM, level); 1648 return false; 1649 } 1650 1651 if (!(fbc_wm || display_wm || cursor_wm)) { 1652 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); 1653 return false; 1654 } 1655 1656 return true; 1657 } 1658 1659 /* 1660 * Compute watermark values of WM[1-3], 1661 */ 1662 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, 1663 int latency_ns, 1664 const struct intel_watermark_params *display, 1665 const struct intel_watermark_params *cursor, 1666 int *fbc_wm, int *display_wm, int *cursor_wm) 1667 { 1668 struct drm_crtc *crtc; 1669 unsigned long line_time_us; 1670 int hdisplay, htotal, pixel_size, clock; 1671 int line_count, line_size; 1672 int small, large; 1673 int entries; 1674 1675 if (!latency_ns) { 1676 *fbc_wm = *display_wm = *cursor_wm = 0; 1677 return false; 1678 } 1679 1680 crtc = intel_get_crtc_for_plane(dev, plane); 1681 hdisplay = crtc->mode.hdisplay; 1682 htotal = crtc->mode.htotal; 1683 clock = crtc->mode.clock; 1684 pixel_size = crtc->fb->bits_per_pixel / 8; 1685 1686 line_time_us = (htotal * 1000) / clock; 1687 line_count = (latency_ns / line_time_us + 1000) / 1000; 1688 line_size = hdisplay * pixel_size; 1689 1690 /* Use the minimum of the small and large buffer method for primary */ 1691 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1692 large = line_count * line_size; 1693 1694 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 1695 *display_wm = entries + display->guard_size; 1696 1697 /* 1698 * Spec says: 1699 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 1700 */ 1701 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; 1702 1703 /* calculate the self-refresh watermark for display cursor */ 1704 entries = line_count * pixel_size * 64; 1705 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 1706 *cursor_wm = entries + cursor->guard_size; 1707 1708 return ironlake_check_srwm(dev, level, 1709 *fbc_wm, *display_wm, *cursor_wm, 1710 display, cursor); 1711 } 1712 1713 static void ironlake_update_wm(struct drm_device *dev) 1714 { 1715 struct drm_i915_private *dev_priv = dev->dev_private; 1716 int fbc_wm, plane_wm, cursor_wm; 1717 unsigned int enabled; 1718 1719 enabled = 0; 1720 if (g4x_compute_wm0(dev, 0, 1721 &ironlake_display_wm_info, 1722 ILK_LP0_PLANE_LATENCY, 1723 &ironlake_cursor_wm_info, 1724 ILK_LP0_CURSOR_LATENCY, 1725 &plane_wm, &cursor_wm)) { 1726 I915_WRITE(WM0_PIPEA_ILK, 1727 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); 1728 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1729 " plane %d, " "cursor: %d\n", 1730 plane_wm, cursor_wm); 1731 enabled |= 1; 1732 } 1733 1734 if (g4x_compute_wm0(dev, 1, 1735 &ironlake_display_wm_info, 1736 ILK_LP0_PLANE_LATENCY, 1737 &ironlake_cursor_wm_info, 1738 ILK_LP0_CURSOR_LATENCY, 1739 &plane_wm, &cursor_wm)) { 1740 I915_WRITE(WM0_PIPEB_ILK, 1741 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); 1742 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1743 " plane %d, cursor: %d\n", 1744 plane_wm, cursor_wm); 1745 enabled |= 2; 1746 } 1747 1748 /* 1749 * Calculate and update the self-refresh watermark only when one 1750 * display plane is used. 1751 */ 1752 I915_WRITE(WM3_LP_ILK, 0); 1753 I915_WRITE(WM2_LP_ILK, 0); 1754 I915_WRITE(WM1_LP_ILK, 0); 1755 1756 if (!single_plane_enabled(enabled)) 1757 return; 1758 enabled = ffs(enabled) - 1; 1759 1760 /* WM1 */ 1761 if (!ironlake_compute_srwm(dev, 1, enabled, 1762 ILK_READ_WM1_LATENCY() * 500, 1763 &ironlake_display_srwm_info, 1764 &ironlake_cursor_srwm_info, 1765 &fbc_wm, &plane_wm, &cursor_wm)) 1766 return; 1767 1768 I915_WRITE(WM1_LP_ILK, 1769 WM1_LP_SR_EN | 1770 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1771 (fbc_wm << WM1_LP_FBC_SHIFT) | 1772 (plane_wm << WM1_LP_SR_SHIFT) | 1773 cursor_wm); 1774 1775 /* WM2 */ 1776 if (!ironlake_compute_srwm(dev, 2, enabled, 1777 ILK_READ_WM2_LATENCY() * 500, 1778 &ironlake_display_srwm_info, 1779 &ironlake_cursor_srwm_info, 1780 &fbc_wm, &plane_wm, &cursor_wm)) 1781 return; 1782 1783 I915_WRITE(WM2_LP_ILK, 1784 WM2_LP_EN | 1785 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1786 (fbc_wm << WM1_LP_FBC_SHIFT) | 1787 (plane_wm << WM1_LP_SR_SHIFT) | 1788 cursor_wm); 1789 1790 /* 1791 * WM3 is unsupported on ILK, probably because we don't have latency 1792 * data for that power state 1793 */ 1794 } 1795 1796 static void sandybridge_update_wm(struct drm_device *dev) 1797 { 1798 struct drm_i915_private *dev_priv = dev->dev_private; 1799 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 1800 u32 val; 1801 int fbc_wm, plane_wm, cursor_wm; 1802 unsigned int enabled; 1803 1804 enabled = 0; 1805 if (g4x_compute_wm0(dev, 0, 1806 &sandybridge_display_wm_info, latency, 1807 &sandybridge_cursor_wm_info, latency, 1808 &plane_wm, &cursor_wm)) { 1809 val = I915_READ(WM0_PIPEA_ILK); 1810 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1811 I915_WRITE(WM0_PIPEA_ILK, val | 1812 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1813 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1814 " plane %d, " "cursor: %d\n", 1815 plane_wm, cursor_wm); 1816 enabled |= 1; 1817 } 1818 1819 if (g4x_compute_wm0(dev, 1, 1820 &sandybridge_display_wm_info, latency, 1821 &sandybridge_cursor_wm_info, latency, 1822 &plane_wm, &cursor_wm)) { 1823 val = I915_READ(WM0_PIPEB_ILK); 1824 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1825 I915_WRITE(WM0_PIPEB_ILK, val | 1826 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1827 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1828 " plane %d, cursor: %d\n", 1829 plane_wm, cursor_wm); 1830 enabled |= 2; 1831 } 1832 1833 /* 1834 * Calculate and update the self-refresh watermark only when one 1835 * display plane is used. 1836 * 1837 * SNB support 3 levels of watermark. 1838 * 1839 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, 1840 * and disabled in the descending order 1841 * 1842 */ 1843 I915_WRITE(WM3_LP_ILK, 0); 1844 I915_WRITE(WM2_LP_ILK, 0); 1845 I915_WRITE(WM1_LP_ILK, 0); 1846 1847 if (!single_plane_enabled(enabled) || 1848 dev_priv->sprite_scaling_enabled) 1849 return; 1850 enabled = ffs(enabled) - 1; 1851 1852 /* WM1 */ 1853 if (!ironlake_compute_srwm(dev, 1, enabled, 1854 SNB_READ_WM1_LATENCY() * 500, 1855 &sandybridge_display_srwm_info, 1856 &sandybridge_cursor_srwm_info, 1857 &fbc_wm, &plane_wm, &cursor_wm)) 1858 return; 1859 1860 I915_WRITE(WM1_LP_ILK, 1861 WM1_LP_SR_EN | 1862 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1863 (fbc_wm << WM1_LP_FBC_SHIFT) | 1864 (plane_wm << WM1_LP_SR_SHIFT) | 1865 cursor_wm); 1866 1867 /* WM2 */ 1868 if (!ironlake_compute_srwm(dev, 2, enabled, 1869 SNB_READ_WM2_LATENCY() * 500, 1870 &sandybridge_display_srwm_info, 1871 &sandybridge_cursor_srwm_info, 1872 &fbc_wm, &plane_wm, &cursor_wm)) 1873 return; 1874 1875 I915_WRITE(WM2_LP_ILK, 1876 WM2_LP_EN | 1877 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1878 (fbc_wm << WM1_LP_FBC_SHIFT) | 1879 (plane_wm << WM1_LP_SR_SHIFT) | 1880 cursor_wm); 1881 1882 /* WM3 */ 1883 if (!ironlake_compute_srwm(dev, 3, enabled, 1884 SNB_READ_WM3_LATENCY() * 500, 1885 &sandybridge_display_srwm_info, 1886 &sandybridge_cursor_srwm_info, 1887 &fbc_wm, &plane_wm, &cursor_wm)) 1888 return; 1889 1890 I915_WRITE(WM3_LP_ILK, 1891 WM3_LP_EN | 1892 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1893 (fbc_wm << WM1_LP_FBC_SHIFT) | 1894 (plane_wm << WM1_LP_SR_SHIFT) | 1895 cursor_wm); 1896 } 1897 1898 static void ivybridge_update_wm(struct drm_device *dev) 1899 { 1900 struct drm_i915_private *dev_priv = dev->dev_private; 1901 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 1902 u32 val; 1903 int fbc_wm, plane_wm, cursor_wm; 1904 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm; 1905 unsigned int enabled; 1906 1907 enabled = 0; 1908 if (g4x_compute_wm0(dev, 0, 1909 &sandybridge_display_wm_info, latency, 1910 &sandybridge_cursor_wm_info, latency, 1911 &plane_wm, &cursor_wm)) { 1912 val = I915_READ(WM0_PIPEA_ILK); 1913 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1914 I915_WRITE(WM0_PIPEA_ILK, val | 1915 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1916 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1917 " plane %d, " "cursor: %d\n", 1918 plane_wm, cursor_wm); 1919 enabled |= 1; 1920 } 1921 1922 if (g4x_compute_wm0(dev, 1, 1923 &sandybridge_display_wm_info, latency, 1924 &sandybridge_cursor_wm_info, latency, 1925 &plane_wm, &cursor_wm)) { 1926 val = I915_READ(WM0_PIPEB_ILK); 1927 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1928 I915_WRITE(WM0_PIPEB_ILK, val | 1929 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1930 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1931 " plane %d, cursor: %d\n", 1932 plane_wm, cursor_wm); 1933 enabled |= 2; 1934 } 1935 1936 if (g4x_compute_wm0(dev, 2, 1937 &sandybridge_display_wm_info, latency, 1938 &sandybridge_cursor_wm_info, latency, 1939 &plane_wm, &cursor_wm)) { 1940 val = I915_READ(WM0_PIPEC_IVB); 1941 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1942 I915_WRITE(WM0_PIPEC_IVB, val | 1943 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1944 DRM_DEBUG_KMS("FIFO watermarks For pipe C -" 1945 " plane %d, cursor: %d\n", 1946 plane_wm, cursor_wm); 1947 enabled |= 3; 1948 } 1949 1950 /* 1951 * Calculate and update the self-refresh watermark only when one 1952 * display plane is used. 1953 * 1954 * SNB support 3 levels of watermark. 1955 * 1956 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, 1957 * and disabled in the descending order 1958 * 1959 */ 1960 I915_WRITE(WM3_LP_ILK, 0); 1961 I915_WRITE(WM2_LP_ILK, 0); 1962 I915_WRITE(WM1_LP_ILK, 0); 1963 1964 if (!single_plane_enabled(enabled) || 1965 dev_priv->sprite_scaling_enabled) 1966 return; 1967 enabled = ffs(enabled) - 1; 1968 1969 /* WM1 */ 1970 if (!ironlake_compute_srwm(dev, 1, enabled, 1971 SNB_READ_WM1_LATENCY() * 500, 1972 &sandybridge_display_srwm_info, 1973 &sandybridge_cursor_srwm_info, 1974 &fbc_wm, &plane_wm, &cursor_wm)) 1975 return; 1976 1977 I915_WRITE(WM1_LP_ILK, 1978 WM1_LP_SR_EN | 1979 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1980 (fbc_wm << WM1_LP_FBC_SHIFT) | 1981 (plane_wm << WM1_LP_SR_SHIFT) | 1982 cursor_wm); 1983 1984 /* WM2 */ 1985 if (!ironlake_compute_srwm(dev, 2, enabled, 1986 SNB_READ_WM2_LATENCY() * 500, 1987 &sandybridge_display_srwm_info, 1988 &sandybridge_cursor_srwm_info, 1989 &fbc_wm, &plane_wm, &cursor_wm)) 1990 return; 1991 1992 I915_WRITE(WM2_LP_ILK, 1993 WM2_LP_EN | 1994 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1995 (fbc_wm << WM1_LP_FBC_SHIFT) | 1996 (plane_wm << WM1_LP_SR_SHIFT) | 1997 cursor_wm); 1998 1999 /* WM3, note we have to correct the cursor latency */ 2000 if (!ironlake_compute_srwm(dev, 3, enabled, 2001 SNB_READ_WM3_LATENCY() * 500, 2002 &sandybridge_display_srwm_info, 2003 &sandybridge_cursor_srwm_info, 2004 &fbc_wm, &plane_wm, &ignore_cursor_wm) || 2005 !ironlake_compute_srwm(dev, 3, enabled, 2006 2 * SNB_READ_WM3_LATENCY() * 500, 2007 &sandybridge_display_srwm_info, 2008 &sandybridge_cursor_srwm_info, 2009 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm)) 2010 return; 2011 2012 I915_WRITE(WM3_LP_ILK, 2013 WM3_LP_EN | 2014 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | 2015 (fbc_wm << WM1_LP_FBC_SHIFT) | 2016 (plane_wm << WM1_LP_SR_SHIFT) | 2017 cursor_wm); 2018 } 2019 2020 static void 2021 haswell_update_linetime_wm(struct drm_device *dev, int pipe, 2022 struct drm_display_mode *mode) 2023 { 2024 struct drm_i915_private *dev_priv = dev->dev_private; 2025 u32 temp; 2026 2027 temp = I915_READ(PIPE_WM_LINETIME(pipe)); 2028 temp &= ~PIPE_WM_LINETIME_MASK; 2029 2030 /* The WM are computed with base on how long it takes to fill a single 2031 * row at the given clock rate, multiplied by 8. 2032 * */ 2033 temp |= PIPE_WM_LINETIME_TIME( 2034 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8); 2035 2036 /* IPS watermarks are only used by pipe A, and are ignored by 2037 * pipes B and C. They are calculated similarly to the common 2038 * linetime values, except that we are using CD clock frequency 2039 * in MHz instead of pixel rate for the division. 2040 * 2041 * This is a placeholder for the IPS watermark calculation code. 2042 */ 2043 2044 I915_WRITE(PIPE_WM_LINETIME(pipe), temp); 2045 } 2046 2047 static bool 2048 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, 2049 uint32_t sprite_width, int pixel_size, 2050 const struct intel_watermark_params *display, 2051 int display_latency_ns, int *sprite_wm) 2052 { 2053 struct drm_crtc *crtc; 2054 int clock; 2055 int entries, tlb_miss; 2056 2057 crtc = intel_get_crtc_for_plane(dev, plane); 2058 if (!intel_crtc_active(crtc)) { 2059 *sprite_wm = display->guard_size; 2060 return false; 2061 } 2062 2063 clock = crtc->mode.clock; 2064 2065 /* Use the small buffer method to calculate the sprite watermark */ 2066 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 2067 tlb_miss = display->fifo_size*display->cacheline_size - 2068 sprite_width * 8; 2069 if (tlb_miss > 0) 2070 entries += tlb_miss; 2071 entries = DIV_ROUND_UP(entries, display->cacheline_size); 2072 *sprite_wm = entries + display->guard_size; 2073 if (*sprite_wm > (int)display->max_wm) 2074 *sprite_wm = display->max_wm; 2075 2076 return true; 2077 } 2078 2079 static bool 2080 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, 2081 uint32_t sprite_width, int pixel_size, 2082 const struct intel_watermark_params *display, 2083 int latency_ns, int *sprite_wm) 2084 { 2085 struct drm_crtc *crtc; 2086 unsigned long line_time_us; 2087 int clock; 2088 int line_count, line_size; 2089 int small, large; 2090 int entries; 2091 2092 if (!latency_ns) { 2093 *sprite_wm = 0; 2094 return false; 2095 } 2096 2097 crtc = intel_get_crtc_for_plane(dev, plane); 2098 clock = crtc->mode.clock; 2099 if (!clock) { 2100 *sprite_wm = 0; 2101 return false; 2102 } 2103 2104 line_time_us = (sprite_width * 1000) / clock; 2105 if (!line_time_us) { 2106 *sprite_wm = 0; 2107 return false; 2108 } 2109 2110 line_count = (latency_ns / line_time_us + 1000) / 1000; 2111 line_size = sprite_width * pixel_size; 2112 2113 /* Use the minimum of the small and large buffer method for primary */ 2114 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 2115 large = line_count * line_size; 2116 2117 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 2118 *sprite_wm = entries + display->guard_size; 2119 2120 return *sprite_wm > 0x3ff ? false : true; 2121 } 2122 2123 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, 2124 uint32_t sprite_width, int pixel_size) 2125 { 2126 struct drm_i915_private *dev_priv = dev->dev_private; 2127 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 2128 u32 val; 2129 int sprite_wm, reg; 2130 int ret; 2131 2132 switch (pipe) { 2133 case 0: 2134 reg = WM0_PIPEA_ILK; 2135 break; 2136 case 1: 2137 reg = WM0_PIPEB_ILK; 2138 break; 2139 case 2: 2140 reg = WM0_PIPEC_IVB; 2141 break; 2142 default: 2143 return; /* bad pipe */ 2144 } 2145 2146 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, 2147 &sandybridge_display_wm_info, 2148 latency, &sprite_wm); 2149 if (!ret) { 2150 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", 2151 pipe); 2152 return; 2153 } 2154 2155 val = I915_READ(reg); 2156 val &= ~WM0_PIPE_SPRITE_MASK; 2157 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); 2158 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); 2159 2160 2161 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2162 pixel_size, 2163 &sandybridge_display_srwm_info, 2164 SNB_READ_WM1_LATENCY() * 500, 2165 &sprite_wm); 2166 if (!ret) { 2167 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", 2168 pipe); 2169 return; 2170 } 2171 I915_WRITE(WM1S_LP_ILK, sprite_wm); 2172 2173 /* Only IVB has two more LP watermarks for sprite */ 2174 if (!IS_IVYBRIDGE(dev)) 2175 return; 2176 2177 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2178 pixel_size, 2179 &sandybridge_display_srwm_info, 2180 SNB_READ_WM2_LATENCY() * 500, 2181 &sprite_wm); 2182 if (!ret) { 2183 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", 2184 pipe); 2185 return; 2186 } 2187 I915_WRITE(WM2S_LP_IVB, sprite_wm); 2188 2189 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 2190 pixel_size, 2191 &sandybridge_display_srwm_info, 2192 SNB_READ_WM3_LATENCY() * 500, 2193 &sprite_wm); 2194 if (!ret) { 2195 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", 2196 pipe); 2197 return; 2198 } 2199 I915_WRITE(WM3S_LP_IVB, sprite_wm); 2200 } 2201 2202 /** 2203 * intel_update_watermarks - update FIFO watermark values based on current modes 2204 * 2205 * Calculate watermark values for the various WM regs based on current mode 2206 * and plane configuration. 2207 * 2208 * There are several cases to deal with here: 2209 * - normal (i.e. non-self-refresh) 2210 * - self-refresh (SR) mode 2211 * - lines are large relative to FIFO size (buffer can hold up to 2) 2212 * - lines are small relative to FIFO size (buffer can hold more than 2 2213 * lines), so need to account for TLB latency 2214 * 2215 * The normal calculation is: 2216 * watermark = dotclock * bytes per pixel * latency 2217 * where latency is platform & configuration dependent (we assume pessimal 2218 * values here). 2219 * 2220 * The SR calculation is: 2221 * watermark = (trunc(latency/line time)+1) * surface width * 2222 * bytes per pixel 2223 * where 2224 * line time = htotal / dotclock 2225 * surface width = hdisplay for normal plane and 64 for cursor 2226 * and latency is assumed to be high, as above. 2227 * 2228 * The final value programmed to the register should always be rounded up, 2229 * and include an extra 2 entries to account for clock crossings. 2230 * 2231 * We don't use the sprite, so we can ignore that. And on Crestline we have 2232 * to set the non-SR watermarks to 8. 2233 */ 2234 void intel_update_watermarks(struct drm_device *dev) 2235 { 2236 struct drm_i915_private *dev_priv = dev->dev_private; 2237 2238 if (dev_priv->display.update_wm) 2239 dev_priv->display.update_wm(dev); 2240 } 2241 2242 void intel_update_linetime_watermarks(struct drm_device *dev, 2243 int pipe, struct drm_display_mode *mode) 2244 { 2245 struct drm_i915_private *dev_priv = dev->dev_private; 2246 2247 if (dev_priv->display.update_linetime_wm) 2248 dev_priv->display.update_linetime_wm(dev, pipe, mode); 2249 } 2250 2251 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 2252 uint32_t sprite_width, int pixel_size) 2253 { 2254 struct drm_i915_private *dev_priv = dev->dev_private; 2255 2256 if (dev_priv->display.update_sprite_wm) 2257 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, 2258 pixel_size); 2259 } 2260 2261 static struct drm_i915_gem_object * 2262 intel_alloc_context_page(struct drm_device *dev) 2263 { 2264 struct drm_i915_gem_object *ctx; 2265 int ret; 2266 2267 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2268 2269 ctx = i915_gem_alloc_object(dev, 4096); 2270 if (!ctx) { 2271 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 2272 return NULL; 2273 } 2274 2275 ret = i915_gem_object_pin(ctx, 4096, true, false); 2276 if (ret) { 2277 DRM_ERROR("failed to pin power context: %d\n", ret); 2278 goto err_unref; 2279 } 2280 2281 ret = i915_gem_object_set_to_gtt_domain(ctx, 1); 2282 if (ret) { 2283 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 2284 goto err_unpin; 2285 } 2286 2287 return ctx; 2288 2289 err_unpin: 2290 i915_gem_object_unpin(ctx); 2291 err_unref: 2292 drm_gem_object_unreference(&ctx->base); 2293 return NULL; 2294 } 2295 2296 /** 2297 * Lock protecting IPS related data structures 2298 */ 2299 struct lock mchdev_lock; 2300 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE); 2301 2302 /* Global for IPS driver to get at the current i915 device. Protected by 2303 * mchdev_lock. */ 2304 static struct drm_i915_private *i915_mch_dev; 2305 2306 bool ironlake_set_drps(struct drm_device *dev, u8 val) 2307 { 2308 struct drm_i915_private *dev_priv = dev->dev_private; 2309 u16 rgvswctl; 2310 2311 rgvswctl = I915_READ16(MEMSWCTL); 2312 if (rgvswctl & MEMCTL_CMD_STS) { 2313 DRM_DEBUG("gpu busy, RCS change rejected\n"); 2314 return false; /* still busy with another command */ 2315 } 2316 2317 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 2318 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 2319 I915_WRITE16(MEMSWCTL, rgvswctl); 2320 POSTING_READ16(MEMSWCTL); 2321 2322 rgvswctl |= MEMCTL_CMD_STS; 2323 I915_WRITE16(MEMSWCTL, rgvswctl); 2324 2325 return true; 2326 } 2327 2328 static void ironlake_enable_drps(struct drm_device *dev) 2329 { 2330 struct drm_i915_private *dev_priv = dev->dev_private; 2331 u32 rgvmodectl = I915_READ(MEMMODECTL); 2332 u8 fmax, fmin, fstart, vstart; 2333 2334 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2335 2336 /* Enable temp reporting */ 2337 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 2338 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 2339 2340 /* 100ms RC evaluation intervals */ 2341 I915_WRITE(RCUPEI, 100000); 2342 I915_WRITE(RCDNEI, 100000); 2343 2344 /* Set max/min thresholds to 90ms and 80ms respectively */ 2345 I915_WRITE(RCBMAXAVG, 90000); 2346 I915_WRITE(RCBMINAVG, 80000); 2347 2348 I915_WRITE(MEMIHYST, 1); 2349 2350 /* Set up min, max, and cur for interrupt handling */ 2351 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 2352 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 2353 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 2354 MEMMODE_FSTART_SHIFT; 2355 2356 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> 2357 PXVFREQ_PX_SHIFT; 2358 2359 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 2360 dev_priv->ips.fstart = fstart; 2361 2362 dev_priv->ips.max_delay = fstart; 2363 dev_priv->ips.min_delay = fmin; 2364 dev_priv->ips.cur_delay = fstart; 2365 2366 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 2367 fmax, fmin, fstart); 2368 2369 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 2370 2371 /* 2372 * Interrupts will be enabled in ironlake_irq_postinstall 2373 */ 2374 2375 I915_WRITE(VIDSTART, vstart); 2376 POSTING_READ(VIDSTART); 2377 2378 rgvmodectl |= MEMMODE_SWMODE_EN; 2379 I915_WRITE(MEMMODECTL, rgvmodectl); 2380 2381 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 2382 DRM_ERROR("stuck trying to change perf mode\n"); 2383 mdelay(1); 2384 2385 ironlake_set_drps(dev, fstart); 2386 2387 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + 2388 I915_READ(0x112e0); 2389 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 2390 dev_priv->ips.last_count2 = I915_READ(0x112f4); 2391 getrawmonotonic(&dev_priv->ips.last_time2); 2392 2393 lockmgr(&mchdev_lock, LK_RELEASE); 2394 } 2395 2396 static void ironlake_disable_drps(struct drm_device *dev) 2397 { 2398 struct drm_i915_private *dev_priv = dev->dev_private; 2399 u16 rgvswctl; 2400 2401 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2402 2403 rgvswctl = I915_READ16(MEMSWCTL); 2404 2405 /* Ack interrupts, disable EFC interrupt */ 2406 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 2407 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 2408 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 2409 I915_WRITE(DEIIR, DE_PCU_EVENT); 2410 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 2411 2412 /* Go back to the starting frequency */ 2413 ironlake_set_drps(dev, dev_priv->ips.fstart); 2414 mdelay(1); 2415 rgvswctl |= MEMCTL_CMD_STS; 2416 I915_WRITE(MEMSWCTL, rgvswctl); 2417 mdelay(1); 2418 2419 lockmgr(&mchdev_lock, LK_RELEASE); 2420 } 2421 2422 /* There's a funny hw issue where the hw returns all 0 when reading from 2423 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 2424 * ourselves, instead of doing a rmw cycle (which might result in us clearing 2425 * all limits and the gpu stuck at whatever frequency it is at atm). 2426 */ 2427 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) 2428 { 2429 u32 limits; 2430 2431 limits = 0; 2432 2433 if (*val >= dev_priv->rps.max_delay) 2434 *val = dev_priv->rps.max_delay; 2435 limits |= dev_priv->rps.max_delay << 24; 2436 2437 /* Only set the down limit when we've reached the lowest level to avoid 2438 * getting more interrupts, otherwise leave this clear. This prevents a 2439 * race in the hw when coming out of rc6: There's a tiny window where 2440 * the hw runs at the minimal clock before selecting the desired 2441 * frequency, if the down threshold expires in that window we will not 2442 * receive a down interrupt. */ 2443 if (*val <= dev_priv->rps.min_delay) { 2444 *val = dev_priv->rps.min_delay; 2445 limits |= dev_priv->rps.min_delay << 16; 2446 } 2447 2448 return limits; 2449 } 2450 2451 void gen6_set_rps(struct drm_device *dev, u8 val) 2452 { 2453 struct drm_i915_private *dev_priv = dev->dev_private; 2454 u32 limits = gen6_rps_limits(dev_priv, &val); 2455 2456 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2457 WARN_ON(val > dev_priv->rps.max_delay); 2458 WARN_ON(val < dev_priv->rps.min_delay); 2459 2460 if (val == dev_priv->rps.cur_delay) 2461 return; 2462 2463 I915_WRITE(GEN6_RPNSWREQ, 2464 GEN6_FREQUENCY(val) | 2465 GEN6_OFFSET(0) | 2466 GEN6_AGGRESSIVE_TURBO); 2467 2468 /* Make sure we continue to get interrupts 2469 * until we hit the minimum or maximum frequencies. 2470 */ 2471 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); 2472 2473 POSTING_READ(GEN6_RPNSWREQ); 2474 2475 dev_priv->rps.cur_delay = val; 2476 2477 trace_intel_gpu_freq_change(val * 50); 2478 } 2479 2480 static void gen6_disable_rps(struct drm_device *dev) 2481 { 2482 struct drm_i915_private *dev_priv = dev->dev_private; 2483 2484 I915_WRITE(GEN6_RC_CONTROL, 0); 2485 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 2486 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 2487 I915_WRITE(GEN6_PMIER, 0); 2488 /* Complete PM interrupt masking here doesn't race with the rps work 2489 * item again unmasking PM interrupts because that is using a different 2490 * register (PMIMR) to mask PM interrupts. The only risk is in leaving 2491 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ 2492 2493 spin_lock(&dev_priv->rps.lock); 2494 dev_priv->rps.pm_iir = 0; 2495 spin_unlock(&dev_priv->rps.lock); 2496 2497 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); 2498 } 2499 2500 int intel_enable_rc6(const struct drm_device *dev) 2501 { 2502 /* Respect the kernel parameter if it is set */ 2503 if (i915_enable_rc6 >= 0) 2504 return i915_enable_rc6; 2505 2506 /* Disable RC6 on Ironlake */ 2507 if (INTEL_INFO(dev)->gen == 5) 2508 return 0; 2509 2510 if (IS_HASWELL(dev)) { 2511 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); 2512 return INTEL_RC6_ENABLE; 2513 } 2514 2515 /* snb/ivb have more than one rc6 state. */ 2516 if (INTEL_INFO(dev)->gen == 6) { 2517 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); 2518 return INTEL_RC6_ENABLE; 2519 } 2520 2521 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); 2522 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 2523 } 2524 2525 static void gen6_enable_rps(struct drm_device *dev) 2526 { 2527 struct drm_i915_private *dev_priv = dev->dev_private; 2528 struct intel_ring_buffer *ring; 2529 u32 rp_state_cap; 2530 u32 gt_perf_status; 2531 u32 rc6vids, pcu_mbox, rc6_mask = 0; 2532 u32 gtfifodbg; 2533 int rc6_mode; 2534 int i, ret; 2535 2536 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2537 2538 /* Here begins a magic sequence of register writes to enable 2539 * auto-downclocking. 2540 * 2541 * Perhaps there might be some value in exposing these to 2542 * userspace... 2543 */ 2544 I915_WRITE(GEN6_RC_STATE, 0); 2545 2546 /* Clear the DBG now so we don't confuse earlier errors */ 2547 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 2548 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 2549 I915_WRITE(GTFIFODBG, gtfifodbg); 2550 } 2551 2552 gen6_gt_force_wake_get(dev_priv); 2553 2554 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 2555 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 2556 2557 /* In units of 100MHz */ 2558 dev_priv->rps.max_delay = rp_state_cap & 0xff; 2559 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; 2560 dev_priv->rps.cur_delay = 0; 2561 2562 /* disable the counters and set deterministic thresholds */ 2563 I915_WRITE(GEN6_RC_CONTROL, 0); 2564 2565 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 2566 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 2567 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 2568 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 2569 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 2570 2571 for_each_ring(ring, dev_priv, i) 2572 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 2573 2574 I915_WRITE(GEN6_RC_SLEEP, 0); 2575 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 2576 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 2577 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); 2578 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 2579 2580 /* Check if we are enabling RC6 */ 2581 rc6_mode = intel_enable_rc6(dev_priv->dev); 2582 if (rc6_mode & INTEL_RC6_ENABLE) 2583 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 2584 2585 /* We don't use those on Haswell */ 2586 if (!IS_HASWELL(dev)) { 2587 if (rc6_mode & INTEL_RC6p_ENABLE) 2588 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 2589 2590 if (rc6_mode & INTEL_RC6pp_ENABLE) 2591 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 2592 } 2593 2594 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", 2595 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 2596 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 2597 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 2598 2599 I915_WRITE(GEN6_RC_CONTROL, 2600 rc6_mask | 2601 GEN6_RC_CTL_EI_MODE(1) | 2602 GEN6_RC_CTL_HW_ENABLE); 2603 2604 I915_WRITE(GEN6_RPNSWREQ, 2605 GEN6_FREQUENCY(10) | 2606 GEN6_OFFSET(0) | 2607 GEN6_AGGRESSIVE_TURBO); 2608 I915_WRITE(GEN6_RC_VIDEO_FREQ, 2609 GEN6_FREQUENCY(12)); 2610 2611 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 2612 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 2613 dev_priv->rps.max_delay << 24 | 2614 dev_priv->rps.min_delay << 16); 2615 2616 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 2617 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 2618 I915_WRITE(GEN6_RP_UP_EI, 66000); 2619 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 2620 2621 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 2622 I915_WRITE(GEN6_RP_CONTROL, 2623 GEN6_RP_MEDIA_TURBO | 2624 GEN6_RP_MEDIA_HW_NORMAL_MODE | 2625 GEN6_RP_MEDIA_IS_GFX | 2626 GEN6_RP_ENABLE | 2627 GEN6_RP_UP_BUSY_AVG | 2628 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); 2629 2630 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 2631 if (!ret) { 2632 pcu_mbox = 0; 2633 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 2634 if (ret && pcu_mbox & (1<<31)) { /* OC supported */ 2635 dev_priv->rps.max_delay = pcu_mbox & 0xff; 2636 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); 2637 } 2638 } else { 2639 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 2640 } 2641 2642 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); 2643 2644 /* requires MSI enabled */ 2645 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); 2646 spin_lock(&dev_priv->rps.lock); 2647 WARN_ON(dev_priv->rps.pm_iir != 0); 2648 I915_WRITE(GEN6_PMIMR, 0); 2649 spin_unlock(&dev_priv->rps.lock); 2650 /* enable all PM interrupts */ 2651 I915_WRITE(GEN6_PMINTRMSK, 0); 2652 2653 rc6vids = 0; 2654 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 2655 if (IS_GEN6(dev) && ret) { 2656 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 2657 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 2658 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 2659 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 2660 rc6vids &= 0xffff00; 2661 rc6vids |= GEN6_ENCODE_RC6_VID(450); 2662 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 2663 if (ret) 2664 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 2665 } 2666 2667 gen6_gt_force_wake_put(dev_priv); 2668 } 2669 2670 static void gen6_update_ring_freq(struct drm_device *dev) 2671 { 2672 struct drm_i915_private *dev_priv = dev->dev_private; 2673 int min_freq = 15; 2674 int gpu_freq; 2675 unsigned int ia_freq, max_ia_freq; 2676 int scaling_factor = 180; 2677 2678 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 2679 2680 #if 0 2681 max_ia_freq = cpufreq_quick_get_max(0); 2682 /* 2683 * Default to measured freq if none found, PCU will ensure we don't go 2684 * over 2685 */ 2686 if (!max_ia_freq) 2687 max_ia_freq = tsc_khz; 2688 #else 2689 max_ia_freq = tsc_frequency / 1000; 2690 #endif 2691 2692 /* Convert from kHz to MHz */ 2693 max_ia_freq /= 1000; 2694 2695 /* 2696 * For each potential GPU frequency, load a ring frequency we'd like 2697 * to use for memory access. We do this by specifying the IA frequency 2698 * the PCU should use as a reference to determine the ring frequency. 2699 */ 2700 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; 2701 gpu_freq--) { 2702 int diff = dev_priv->rps.max_delay - gpu_freq; 2703 2704 /* 2705 * For GPU frequencies less than 750MHz, just use the lowest 2706 * ring freq. 2707 */ 2708 if (gpu_freq < min_freq) 2709 ia_freq = 800; 2710 else 2711 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 2712 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 2713 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT; 2714 2715 sandybridge_pcode_write(dev_priv, 2716 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 2717 ia_freq | gpu_freq); 2718 } 2719 } 2720 2721 void ironlake_teardown_rc6(struct drm_device *dev) 2722 { 2723 struct drm_i915_private *dev_priv = dev->dev_private; 2724 2725 if (dev_priv->ips.renderctx) { 2726 i915_gem_object_unpin(dev_priv->ips.renderctx); 2727 drm_gem_object_unreference(&dev_priv->ips.renderctx->base); 2728 dev_priv->ips.renderctx = NULL; 2729 } 2730 2731 if (dev_priv->ips.pwrctx) { 2732 i915_gem_object_unpin(dev_priv->ips.pwrctx); 2733 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); 2734 dev_priv->ips.pwrctx = NULL; 2735 } 2736 } 2737 2738 static void ironlake_disable_rc6(struct drm_device *dev) 2739 { 2740 struct drm_i915_private *dev_priv = dev->dev_private; 2741 2742 if (I915_READ(PWRCTXA)) { 2743 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ 2744 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); 2745 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), 2746 50); 2747 2748 I915_WRITE(PWRCTXA, 0); 2749 POSTING_READ(PWRCTXA); 2750 2751 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 2752 POSTING_READ(RSTDBYCTL); 2753 } 2754 } 2755 2756 static int ironlake_setup_rc6(struct drm_device *dev) 2757 { 2758 struct drm_i915_private *dev_priv = dev->dev_private; 2759 2760 if (dev_priv->ips.renderctx == NULL) 2761 dev_priv->ips.renderctx = intel_alloc_context_page(dev); 2762 if (!dev_priv->ips.renderctx) 2763 return -ENOMEM; 2764 2765 if (dev_priv->ips.pwrctx == NULL) 2766 dev_priv->ips.pwrctx = intel_alloc_context_page(dev); 2767 if (!dev_priv->ips.pwrctx) { 2768 ironlake_teardown_rc6(dev); 2769 return -ENOMEM; 2770 } 2771 2772 return 0; 2773 } 2774 2775 static void ironlake_enable_rc6(struct drm_device *dev) 2776 { 2777 struct drm_i915_private *dev_priv = dev->dev_private; 2778 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 2779 bool was_interruptible; 2780 int ret; 2781 2782 /* rc6 disabled by default due to repeated reports of hanging during 2783 * boot and resume. 2784 */ 2785 if (!intel_enable_rc6(dev)) 2786 return; 2787 2788 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 2789 2790 ret = ironlake_setup_rc6(dev); 2791 if (ret) 2792 return; 2793 2794 was_interruptible = dev_priv->mm.interruptible; 2795 dev_priv->mm.interruptible = false; 2796 2797 /* 2798 * GPU can automatically power down the render unit if given a page 2799 * to save state. 2800 */ 2801 ret = intel_ring_begin(ring, 6); 2802 if (ret) { 2803 ironlake_teardown_rc6(dev); 2804 dev_priv->mm.interruptible = was_interruptible; 2805 return; 2806 } 2807 2808 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); 2809 intel_ring_emit(ring, MI_SET_CONTEXT); 2810 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | 2811 MI_MM_SPACE_GTT | 2812 MI_SAVE_EXT_STATE_EN | 2813 MI_RESTORE_EXT_STATE_EN | 2814 MI_RESTORE_INHIBIT); 2815 intel_ring_emit(ring, MI_SUSPEND_FLUSH); 2816 intel_ring_emit(ring, MI_NOOP); 2817 intel_ring_emit(ring, MI_FLUSH); 2818 intel_ring_advance(ring); 2819 2820 /* 2821 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW 2822 * does an implicit flush, combined with MI_FLUSH above, it should be 2823 * safe to assume that renderctx is valid 2824 */ 2825 ret = intel_ring_idle(ring); 2826 dev_priv->mm.interruptible = was_interruptible; 2827 if (ret) { 2828 DRM_ERROR("failed to enable ironlake power power savings\n"); 2829 ironlake_teardown_rc6(dev); 2830 return; 2831 } 2832 2833 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); 2834 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 2835 } 2836 2837 static unsigned long intel_pxfreq(u32 vidfreq) 2838 { 2839 unsigned long freq; 2840 int div = (vidfreq & 0x3f0000) >> 16; 2841 int post = (vidfreq & 0x3000) >> 12; 2842 int pre = (vidfreq & 0x7); 2843 2844 if (!pre) 2845 return 0; 2846 2847 freq = ((div * 133333) / ((1<<post) * pre)); 2848 2849 return freq; 2850 } 2851 2852 static const struct cparams { 2853 u16 i; 2854 u16 t; 2855 u16 m; 2856 u16 c; 2857 } cparams[] = { 2858 { 1, 1333, 301, 28664 }, 2859 { 1, 1066, 294, 24460 }, 2860 { 1, 800, 294, 25192 }, 2861 { 0, 1333, 276, 27605 }, 2862 { 0, 1066, 276, 27605 }, 2863 { 0, 800, 231, 23784 }, 2864 }; 2865 2866 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 2867 { 2868 u64 total_count, diff, ret; 2869 u32 count1, count2, count3, m = 0, c = 0; 2870 unsigned long now = jiffies_to_msecs(jiffies), diff1; 2871 int i; 2872 2873 diff1 = now - dev_priv->ips.last_time1; 2874 2875 /* Prevent division-by-zero if we are asking too fast. 2876 * Also, we don't get interesting results if we are polling 2877 * faster than once in 10ms, so just return the saved value 2878 * in such cases. 2879 */ 2880 if (diff1 <= 10) 2881 return dev_priv->ips.chipset_power; 2882 2883 count1 = I915_READ(DMIEC); 2884 count2 = I915_READ(DDREC); 2885 count3 = I915_READ(CSIEC); 2886 2887 total_count = count1 + count2 + count3; 2888 2889 /* FIXME: handle per-counter overflow */ 2890 if (total_count < dev_priv->ips.last_count1) { 2891 diff = ~0UL - dev_priv->ips.last_count1; 2892 diff += total_count; 2893 } else { 2894 diff = total_count - dev_priv->ips.last_count1; 2895 } 2896 2897 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 2898 if (cparams[i].i == dev_priv->ips.c_m && 2899 cparams[i].t == dev_priv->ips.r_t) { 2900 m = cparams[i].m; 2901 c = cparams[i].c; 2902 break; 2903 } 2904 } 2905 2906 diff = div_u64(diff, diff1); 2907 ret = ((m * diff) + c); 2908 ret = div_u64(ret, 10); 2909 2910 dev_priv->ips.last_count1 = total_count; 2911 dev_priv->ips.last_time1 = now; 2912 2913 dev_priv->ips.chipset_power = ret; 2914 2915 return ret; 2916 } 2917 2918 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 2919 { 2920 unsigned long val; 2921 2922 if (dev_priv->info->gen != 5) 2923 return 0; 2924 2925 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2926 2927 val = __i915_chipset_val(dev_priv); 2928 2929 lockmgr(&mchdev_lock, LK_RELEASE); 2930 2931 return val; 2932 } 2933 2934 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 2935 { 2936 unsigned long m, x, b; 2937 u32 tsfs; 2938 2939 tsfs = I915_READ(TSFS); 2940 2941 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 2942 x = I915_READ8(TR1); 2943 2944 b = tsfs & TSFS_INTR_MASK; 2945 2946 return ((m * x) / 127) - b; 2947 } 2948 2949 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 2950 { 2951 static const struct v_table { 2952 u16 vd; /* in .1 mil */ 2953 u16 vm; /* in .1 mil */ 2954 } v_table[] = { 2955 { 0, 0, }, 2956 { 375, 0, }, 2957 { 500, 0, }, 2958 { 625, 0, }, 2959 { 750, 0, }, 2960 { 875, 0, }, 2961 { 1000, 0, }, 2962 { 1125, 0, }, 2963 { 4125, 3000, }, 2964 { 4125, 3000, }, 2965 { 4125, 3000, }, 2966 { 4125, 3000, }, 2967 { 4125, 3000, }, 2968 { 4125, 3000, }, 2969 { 4125, 3000, }, 2970 { 4125, 3000, }, 2971 { 4125, 3000, }, 2972 { 4125, 3000, }, 2973 { 4125, 3000, }, 2974 { 4125, 3000, }, 2975 { 4125, 3000, }, 2976 { 4125, 3000, }, 2977 { 4125, 3000, }, 2978 { 4125, 3000, }, 2979 { 4125, 3000, }, 2980 { 4125, 3000, }, 2981 { 4125, 3000, }, 2982 { 4125, 3000, }, 2983 { 4125, 3000, }, 2984 { 4125, 3000, }, 2985 { 4125, 3000, }, 2986 { 4125, 3000, }, 2987 { 4250, 3125, }, 2988 { 4375, 3250, }, 2989 { 4500, 3375, }, 2990 { 4625, 3500, }, 2991 { 4750, 3625, }, 2992 { 4875, 3750, }, 2993 { 5000, 3875, }, 2994 { 5125, 4000, }, 2995 { 5250, 4125, }, 2996 { 5375, 4250, }, 2997 { 5500, 4375, }, 2998 { 5625, 4500, }, 2999 { 5750, 4625, }, 3000 { 5875, 4750, }, 3001 { 6000, 4875, }, 3002 { 6125, 5000, }, 3003 { 6250, 5125, }, 3004 { 6375, 5250, }, 3005 { 6500, 5375, }, 3006 { 6625, 5500, }, 3007 { 6750, 5625, }, 3008 { 6875, 5750, }, 3009 { 7000, 5875, }, 3010 { 7125, 6000, }, 3011 { 7250, 6125, }, 3012 { 7375, 6250, }, 3013 { 7500, 6375, }, 3014 { 7625, 6500, }, 3015 { 7750, 6625, }, 3016 { 7875, 6750, }, 3017 { 8000, 6875, }, 3018 { 8125, 7000, }, 3019 { 8250, 7125, }, 3020 { 8375, 7250, }, 3021 { 8500, 7375, }, 3022 { 8625, 7500, }, 3023 { 8750, 7625, }, 3024 { 8875, 7750, }, 3025 { 9000, 7875, }, 3026 { 9125, 8000, }, 3027 { 9250, 8125, }, 3028 { 9375, 8250, }, 3029 { 9500, 8375, }, 3030 { 9625, 8500, }, 3031 { 9750, 8625, }, 3032 { 9875, 8750, }, 3033 { 10000, 8875, }, 3034 { 10125, 9000, }, 3035 { 10250, 9125, }, 3036 { 10375, 9250, }, 3037 { 10500, 9375, }, 3038 { 10625, 9500, }, 3039 { 10750, 9625, }, 3040 { 10875, 9750, }, 3041 { 11000, 9875, }, 3042 { 11125, 10000, }, 3043 { 11250, 10125, }, 3044 { 11375, 10250, }, 3045 { 11500, 10375, }, 3046 { 11625, 10500, }, 3047 { 11750, 10625, }, 3048 { 11875, 10750, }, 3049 { 12000, 10875, }, 3050 { 12125, 11000, }, 3051 { 12250, 11125, }, 3052 { 12375, 11250, }, 3053 { 12500, 11375, }, 3054 { 12625, 11500, }, 3055 { 12750, 11625, }, 3056 { 12875, 11750, }, 3057 { 13000, 11875, }, 3058 { 13125, 12000, }, 3059 { 13250, 12125, }, 3060 { 13375, 12250, }, 3061 { 13500, 12375, }, 3062 { 13625, 12500, }, 3063 { 13750, 12625, }, 3064 { 13875, 12750, }, 3065 { 14000, 12875, }, 3066 { 14125, 13000, }, 3067 { 14250, 13125, }, 3068 { 14375, 13250, }, 3069 { 14500, 13375, }, 3070 { 14625, 13500, }, 3071 { 14750, 13625, }, 3072 { 14875, 13750, }, 3073 { 15000, 13875, }, 3074 { 15125, 14000, }, 3075 { 15250, 14125, }, 3076 { 15375, 14250, }, 3077 { 15500, 14375, }, 3078 { 15625, 14500, }, 3079 { 15750, 14625, }, 3080 { 15875, 14750, }, 3081 { 16000, 14875, }, 3082 { 16125, 15000, }, 3083 }; 3084 if (dev_priv->info->is_mobile) 3085 return v_table[pxvid].vm; 3086 else 3087 return v_table[pxvid].vd; 3088 } 3089 3090 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 3091 { 3092 struct timespec now, diff1; 3093 u64 diff; 3094 unsigned long diffms; 3095 u32 count; 3096 3097 getrawmonotonic(&now); 3098 diff1 = timespec_sub(now, dev_priv->ips.last_time2); 3099 3100 /* Don't divide by 0 */ 3101 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; 3102 if (!diffms) 3103 return; 3104 3105 count = I915_READ(GFXEC); 3106 3107 if (count < dev_priv->ips.last_count2) { 3108 diff = ~0UL - dev_priv->ips.last_count2; 3109 diff += count; 3110 } else { 3111 diff = count - dev_priv->ips.last_count2; 3112 } 3113 3114 dev_priv->ips.last_count2 = count; 3115 dev_priv->ips.last_time2 = now; 3116 3117 /* More magic constants... */ 3118 diff = diff * 1181; 3119 diff = div_u64(diff, diffms * 10); 3120 dev_priv->ips.gfx_power = diff; 3121 } 3122 3123 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 3124 { 3125 if (dev_priv->info->gen != 5) 3126 return; 3127 3128 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3129 3130 __i915_update_gfx_val(dev_priv); 3131 3132 lockmgr(&mchdev_lock, LK_RELEASE); 3133 } 3134 3135 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 3136 { 3137 unsigned long t, corr, state1, corr2, state2; 3138 u32 pxvid, ext_v; 3139 3140 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); 3141 pxvid = (pxvid >> 24) & 0x7f; 3142 ext_v = pvid_to_extvid(dev_priv, pxvid); 3143 3144 state1 = ext_v; 3145 3146 t = i915_mch_val(dev_priv); 3147 3148 /* Revel in the empirically derived constants */ 3149 3150 /* Correction factor in 1/100000 units */ 3151 if (t > 80) 3152 corr = ((t * 2349) + 135940); 3153 else if (t >= 50) 3154 corr = ((t * 964) + 29317); 3155 else /* < 50 */ 3156 corr = ((t * 301) + 1004); 3157 3158 corr = corr * ((150142 * state1) / 10000 - 78642); 3159 corr /= 100000; 3160 corr2 = (corr * dev_priv->ips.corr); 3161 3162 state2 = (corr2 * state1) / 10000; 3163 state2 /= 100; /* convert to mW */ 3164 3165 __i915_update_gfx_val(dev_priv); 3166 3167 return dev_priv->ips.gfx_power + state2; 3168 } 3169 3170 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 3171 { 3172 unsigned long val; 3173 3174 if (dev_priv->info->gen != 5) 3175 return 0; 3176 3177 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3178 3179 val = __i915_gfx_val(dev_priv); 3180 3181 lockmgr(&mchdev_lock, LK_RELEASE); 3182 3183 return val; 3184 } 3185 3186 /** 3187 * i915_read_mch_val - return value for IPS use 3188 * 3189 * Calculate and return a value for the IPS driver to use when deciding whether 3190 * we have thermal and power headroom to increase CPU or GPU power budget. 3191 */ 3192 unsigned long i915_read_mch_val(void) 3193 { 3194 struct drm_i915_private *dev_priv; 3195 unsigned long chipset_val, graphics_val, ret = 0; 3196 3197 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3198 if (!i915_mch_dev) 3199 goto out_unlock; 3200 dev_priv = i915_mch_dev; 3201 3202 chipset_val = __i915_chipset_val(dev_priv); 3203 graphics_val = __i915_gfx_val(dev_priv); 3204 3205 ret = chipset_val + graphics_val; 3206 3207 out_unlock: 3208 lockmgr(&mchdev_lock, LK_RELEASE); 3209 3210 return ret; 3211 } 3212 3213 /** 3214 * i915_gpu_raise - raise GPU frequency limit 3215 * 3216 * Raise the limit; IPS indicates we have thermal headroom. 3217 */ 3218 bool i915_gpu_raise(void) 3219 { 3220 struct drm_i915_private *dev_priv; 3221 bool ret = true; 3222 3223 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3224 if (!i915_mch_dev) { 3225 ret = false; 3226 goto out_unlock; 3227 } 3228 dev_priv = i915_mch_dev; 3229 3230 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 3231 dev_priv->ips.max_delay--; 3232 3233 out_unlock: 3234 lockmgr(&mchdev_lock, LK_RELEASE); 3235 3236 return ret; 3237 } 3238 3239 /** 3240 * i915_gpu_lower - lower GPU frequency limit 3241 * 3242 * IPS indicates we're close to a thermal limit, so throttle back the GPU 3243 * frequency maximum. 3244 */ 3245 bool i915_gpu_lower(void) 3246 { 3247 struct drm_i915_private *dev_priv; 3248 bool ret = true; 3249 3250 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3251 if (!i915_mch_dev) { 3252 ret = false; 3253 goto out_unlock; 3254 } 3255 dev_priv = i915_mch_dev; 3256 3257 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 3258 dev_priv->ips.max_delay++; 3259 3260 out_unlock: 3261 lockmgr(&mchdev_lock, LK_RELEASE); 3262 3263 return ret; 3264 } 3265 3266 /** 3267 * i915_gpu_busy - indicate GPU business to IPS 3268 * 3269 * Tell the IPS driver whether or not the GPU is busy. 3270 */ 3271 bool i915_gpu_busy(void) 3272 { 3273 struct drm_i915_private *dev_priv; 3274 struct intel_ring_buffer *ring; 3275 bool ret = false; 3276 int i; 3277 3278 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3279 if (!i915_mch_dev) 3280 goto out_unlock; 3281 dev_priv = i915_mch_dev; 3282 3283 for_each_ring(ring, dev_priv, i) 3284 ret |= !list_empty(&ring->request_list); 3285 3286 out_unlock: 3287 lockmgr(&mchdev_lock, LK_RELEASE); 3288 3289 return ret; 3290 } 3291 3292 /** 3293 * i915_gpu_turbo_disable - disable graphics turbo 3294 * 3295 * Disable graphics turbo by resetting the max frequency and setting the 3296 * current frequency to the default. 3297 */ 3298 bool i915_gpu_turbo_disable(void) 3299 { 3300 struct drm_i915_private *dev_priv; 3301 bool ret = true; 3302 3303 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3304 if (!i915_mch_dev) { 3305 ret = false; 3306 goto out_unlock; 3307 } 3308 dev_priv = i915_mch_dev; 3309 3310 dev_priv->ips.max_delay = dev_priv->ips.fstart; 3311 3312 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 3313 ret = false; 3314 3315 out_unlock: 3316 lockmgr(&mchdev_lock, LK_RELEASE); 3317 3318 return ret; 3319 } 3320 3321 #if 0 3322 /** 3323 * Tells the intel_ips driver that the i915 driver is now loaded, if 3324 * IPS got loaded first. 3325 * 3326 * This awkward dance is so that neither module has to depend on the 3327 * other in order for IPS to do the appropriate communication of 3328 * GPU turbo limits to i915. 3329 */ 3330 static void 3331 ips_ping_for_i915_load(void) 3332 { 3333 void (*link)(void); 3334 3335 link = symbol_get(ips_link_to_i915_driver); 3336 if (link) { 3337 link(); 3338 symbol_put(ips_link_to_i915_driver); 3339 } 3340 } 3341 #endif 3342 3343 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 3344 { 3345 /* We only register the i915 ips part with intel-ips once everything is 3346 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 3347 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3348 i915_mch_dev = dev_priv; 3349 lockmgr(&mchdev_lock, LK_RELEASE); 3350 } 3351 3352 void intel_gpu_ips_teardown(void) 3353 { 3354 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 3355 i915_mch_dev = NULL; 3356 lockmgr(&mchdev_lock, LK_RELEASE); 3357 } 3358 static void intel_init_emon(struct drm_device *dev) 3359 { 3360 struct drm_i915_private *dev_priv = dev->dev_private; 3361 u32 lcfuse; 3362 u8 pxw[16]; 3363 int i; 3364 3365 /* Disable to program */ 3366 I915_WRITE(ECR, 0); 3367 POSTING_READ(ECR); 3368 3369 /* Program energy weights for various events */ 3370 I915_WRITE(SDEW, 0x15040d00); 3371 I915_WRITE(CSIEW0, 0x007f0000); 3372 I915_WRITE(CSIEW1, 0x1e220004); 3373 I915_WRITE(CSIEW2, 0x04000004); 3374 3375 for (i = 0; i < 5; i++) 3376 I915_WRITE(PEW + (i * 4), 0); 3377 for (i = 0; i < 3; i++) 3378 I915_WRITE(DEW + (i * 4), 0); 3379 3380 /* Program P-state weights to account for frequency power adjustment */ 3381 for (i = 0; i < 16; i++) { 3382 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); 3383 unsigned long freq = intel_pxfreq(pxvidfreq); 3384 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 3385 PXVFREQ_PX_SHIFT; 3386 unsigned long val; 3387 3388 val = vid * vid; 3389 val *= (freq / 1000); 3390 val *= 255; 3391 val /= (127*127*900); 3392 if (val > 0xff) 3393 DRM_ERROR("bad pxval: %ld\n", val); 3394 pxw[i] = val; 3395 } 3396 /* Render standby states get 0 weight */ 3397 pxw[14] = 0; 3398 pxw[15] = 0; 3399 3400 for (i = 0; i < 4; i++) { 3401 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | 3402 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); 3403 I915_WRITE(PXW + (i * 4), val); 3404 } 3405 3406 /* Adjust magic regs to magic values (more experimental results) */ 3407 I915_WRITE(OGW0, 0); 3408 I915_WRITE(OGW1, 0); 3409 I915_WRITE(EG0, 0x00007f00); 3410 I915_WRITE(EG1, 0x0000000e); 3411 I915_WRITE(EG2, 0x000e0000); 3412 I915_WRITE(EG3, 0x68000300); 3413 I915_WRITE(EG4, 0x42000000); 3414 I915_WRITE(EG5, 0x00140031); 3415 I915_WRITE(EG6, 0); 3416 I915_WRITE(EG7, 0); 3417 3418 for (i = 0; i < 8; i++) 3419 I915_WRITE(PXWL + (i * 4), 0); 3420 3421 /* Enable PMON + select events */ 3422 I915_WRITE(ECR, 0x80000019); 3423 3424 lcfuse = I915_READ(LCFUSE02); 3425 3426 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 3427 } 3428 3429 void intel_disable_gt_powersave(struct drm_device *dev) 3430 { 3431 struct drm_i915_private *dev_priv = dev->dev_private; 3432 3433 if (IS_IRONLAKE_M(dev)) { 3434 ironlake_disable_drps(dev); 3435 ironlake_disable_rc6(dev); 3436 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { 3437 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); 3438 mutex_lock(&dev_priv->rps.hw_lock); 3439 gen6_disable_rps(dev); 3440 mutex_unlock(&dev_priv->rps.hw_lock); 3441 } 3442 } 3443 3444 static void intel_gen6_powersave_work(struct work_struct *work) 3445 { 3446 struct drm_i915_private *dev_priv = 3447 container_of(work, struct drm_i915_private, 3448 rps.delayed_resume_work.work); 3449 struct drm_device *dev = dev_priv->dev; 3450 3451 mutex_lock(&dev_priv->rps.hw_lock); 3452 gen6_enable_rps(dev); 3453 gen6_update_ring_freq(dev); 3454 mutex_unlock(&dev_priv->rps.hw_lock); 3455 } 3456 3457 void intel_enable_gt_powersave(struct drm_device *dev) 3458 { 3459 struct drm_i915_private *dev_priv = dev->dev_private; 3460 3461 if (IS_IRONLAKE_M(dev)) { 3462 ironlake_enable_drps(dev); 3463 ironlake_enable_rc6(dev); 3464 intel_init_emon(dev); 3465 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { 3466 /* 3467 * PCU communication is slow and this doesn't need to be 3468 * done at any specific time, so do this out of our fast path 3469 * to make resume and init faster. 3470 */ 3471 schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 3472 round_jiffies_up_relative(HZ)); 3473 } 3474 } 3475 3476 static void ibx_init_clock_gating(struct drm_device *dev) 3477 { 3478 struct drm_i915_private *dev_priv = dev->dev_private; 3479 3480 /* 3481 * On Ibex Peak and Cougar Point, we need to disable clock 3482 * gating for the panel power sequencer or it will fail to 3483 * start up when no ports are active. 3484 */ 3485 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 3486 } 3487 3488 static void ironlake_init_clock_gating(struct drm_device *dev) 3489 { 3490 struct drm_i915_private *dev_priv = dev->dev_private; 3491 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 3492 3493 /* Required for FBC */ 3494 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 3495 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 3496 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 3497 3498 I915_WRITE(PCH_3DCGDIS0, 3499 MARIUNIT_CLOCK_GATE_DISABLE | 3500 SVSMUNIT_CLOCK_GATE_DISABLE); 3501 I915_WRITE(PCH_3DCGDIS1, 3502 VFMUNIT_CLOCK_GATE_DISABLE); 3503 3504 /* 3505 * According to the spec the following bits should be set in 3506 * order to enable memory self-refresh 3507 * The bit 22/21 of 0x42004 3508 * The bit 5 of 0x42020 3509 * The bit 15 of 0x45000 3510 */ 3511 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3512 (I915_READ(ILK_DISPLAY_CHICKEN2) | 3513 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 3514 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 3515 I915_WRITE(DISP_ARB_CTL, 3516 (I915_READ(DISP_ARB_CTL) | 3517 DISP_FBC_WM_DIS)); 3518 I915_WRITE(WM3_LP_ILK, 0); 3519 I915_WRITE(WM2_LP_ILK, 0); 3520 I915_WRITE(WM1_LP_ILK, 0); 3521 3522 /* 3523 * Based on the document from hardware guys the following bits 3524 * should be set unconditionally in order to enable FBC. 3525 * The bit 22 of 0x42000 3526 * The bit 22 of 0x42004 3527 * The bit 7,8,9 of 0x42020. 3528 */ 3529 if (IS_IRONLAKE_M(dev)) { 3530 I915_WRITE(ILK_DISPLAY_CHICKEN1, 3531 I915_READ(ILK_DISPLAY_CHICKEN1) | 3532 ILK_FBCQ_DIS); 3533 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3534 I915_READ(ILK_DISPLAY_CHICKEN2) | 3535 ILK_DPARB_GATE); 3536 } 3537 3538 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 3539 3540 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3541 I915_READ(ILK_DISPLAY_CHICKEN2) | 3542 ILK_ELPIN_409_SELECT); 3543 I915_WRITE(_3D_CHICKEN2, 3544 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 3545 _3D_CHICKEN2_WM_READ_PIPELINED); 3546 3547 /* WaDisableRenderCachePipelinedFlush */ 3548 I915_WRITE(CACHE_MODE_0, 3549 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 3550 3551 ibx_init_clock_gating(dev); 3552 } 3553 3554 static void cpt_init_clock_gating(struct drm_device *dev) 3555 { 3556 struct drm_i915_private *dev_priv = dev->dev_private; 3557 int pipe; 3558 uint32_t val; 3559 3560 /* 3561 * On Ibex Peak and Cougar Point, we need to disable clock 3562 * gating for the panel power sequencer or it will fail to 3563 * start up when no ports are active. 3564 */ 3565 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 3566 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 3567 DPLS_EDP_PPS_FIX_DIS); 3568 /* The below fixes the weird display corruption, a few pixels shifted 3569 * downward, on (only) LVDS of some HP laptops with IVY. 3570 */ 3571 for_each_pipe(pipe) { 3572 val = TRANS_CHICKEN2_TIMING_OVERRIDE; 3573 if (dev_priv->fdi_rx_polarity_inverted) 3574 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 3575 I915_WRITE(TRANS_CHICKEN2(pipe), val); 3576 } 3577 /* WADP0ClockGatingDisable */ 3578 for_each_pipe(pipe) { 3579 I915_WRITE(TRANS_CHICKEN1(pipe), 3580 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 3581 } 3582 } 3583 3584 static void gen6_check_mch_setup(struct drm_device *dev) 3585 { 3586 struct drm_i915_private *dev_priv = dev->dev_private; 3587 uint32_t tmp; 3588 3589 tmp = I915_READ(MCH_SSKPD); 3590 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { 3591 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); 3592 DRM_INFO("This can cause pipe underruns and display issues.\n"); 3593 DRM_INFO("Please upgrade your BIOS to fix this.\n"); 3594 } 3595 } 3596 3597 static void gen6_init_clock_gating(struct drm_device *dev) 3598 { 3599 struct drm_i915_private *dev_priv = dev->dev_private; 3600 int pipe; 3601 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 3602 3603 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 3604 3605 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3606 I915_READ(ILK_DISPLAY_CHICKEN2) | 3607 ILK_ELPIN_409_SELECT); 3608 3609 /* WaDisableHiZPlanesWhenMSAAEnabled */ 3610 I915_WRITE(_3D_CHICKEN, 3611 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 3612 3613 /* WaSetupGtModeTdRowDispatch */ 3614 if (IS_SNB_GT1(dev)) 3615 I915_WRITE(GEN6_GT_MODE, 3616 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); 3617 3618 I915_WRITE(WM3_LP_ILK, 0); 3619 I915_WRITE(WM2_LP_ILK, 0); 3620 I915_WRITE(WM1_LP_ILK, 0); 3621 3622 I915_WRITE(CACHE_MODE_0, 3623 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 3624 3625 I915_WRITE(GEN6_UCGCTL1, 3626 I915_READ(GEN6_UCGCTL1) | 3627 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 3628 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 3629 3630 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3631 * gating disable must be set. Failure to set it results in 3632 * flickering pixels due to Z write ordering failures after 3633 * some amount of runtime in the Mesa "fire" demo, and Unigine 3634 * Sanctuary and Tropics, and apparently anything else with 3635 * alpha test or pixel discard. 3636 * 3637 * According to the spec, bit 11 (RCCUNIT) must also be set, 3638 * but we didn't debug actual testcases to find it out. 3639 * 3640 * Also apply WaDisableVDSUnitClockGating and 3641 * WaDisableRCPBUnitClockGating. 3642 */ 3643 I915_WRITE(GEN6_UCGCTL2, 3644 GEN7_VDSUNIT_CLOCK_GATE_DISABLE | 3645 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 3646 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3647 3648 /* Bspec says we need to always set all mask bits. */ 3649 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | 3650 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); 3651 3652 /* 3653 * According to the spec the following bits should be 3654 * set in order to enable memory self-refresh and fbc: 3655 * The bit21 and bit22 of 0x42000 3656 * The bit21 and bit22 of 0x42004 3657 * The bit5 and bit7 of 0x42020 3658 * The bit14 of 0x70180 3659 * The bit14 of 0x71180 3660 */ 3661 I915_WRITE(ILK_DISPLAY_CHICKEN1, 3662 I915_READ(ILK_DISPLAY_CHICKEN1) | 3663 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 3664 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3665 I915_READ(ILK_DISPLAY_CHICKEN2) | 3666 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 3667 I915_WRITE(ILK_DSPCLK_GATE_D, 3668 I915_READ(ILK_DSPCLK_GATE_D) | 3669 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 3670 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 3671 3672 /* WaMbcDriverBootEnable */ 3673 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3674 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3675 3676 for_each_pipe(pipe) { 3677 I915_WRITE(DSPCNTR(pipe), 3678 I915_READ(DSPCNTR(pipe)) | 3679 DISPPLANE_TRICKLE_FEED_DISABLE); 3680 intel_flush_display_plane(dev_priv, pipe); 3681 } 3682 3683 /* The default value should be 0x200 according to docs, but the two 3684 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ 3685 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); 3686 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); 3687 3688 cpt_init_clock_gating(dev); 3689 3690 gen6_check_mch_setup(dev); 3691 } 3692 3693 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 3694 { 3695 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 3696 3697 reg &= ~GEN7_FF_SCHED_MASK; 3698 reg |= GEN7_FF_TS_SCHED_HW; 3699 reg |= GEN7_FF_VS_SCHED_HW; 3700 reg |= GEN7_FF_DS_SCHED_HW; 3701 3702 /* WaVSRefCountFullforceMissDisable */ 3703 if (IS_HASWELL(dev_priv->dev)) 3704 reg &= ~GEN7_FF_VS_REF_CNT_FFME; 3705 3706 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 3707 } 3708 3709 static void lpt_init_clock_gating(struct drm_device *dev) 3710 { 3711 struct drm_i915_private *dev_priv = dev->dev_private; 3712 3713 /* 3714 * TODO: this bit should only be enabled when really needed, then 3715 * disabled when not needed anymore in order to save power. 3716 */ 3717 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) 3718 I915_WRITE(SOUTH_DSPCLK_GATE_D, 3719 I915_READ(SOUTH_DSPCLK_GATE_D) | 3720 PCH_LP_PARTITION_LEVEL_DISABLE); 3721 } 3722 3723 static void haswell_init_clock_gating(struct drm_device *dev) 3724 { 3725 struct drm_i915_private *dev_priv = dev->dev_private; 3726 int pipe; 3727 3728 I915_WRITE(WM3_LP_ILK, 0); 3729 I915_WRITE(WM2_LP_ILK, 0); 3730 I915_WRITE(WM1_LP_ILK, 0); 3731 3732 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3733 * This implements the WaDisableRCZUnitClockGating workaround. 3734 */ 3735 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 3736 3737 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3738 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3739 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3740 3741 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3742 I915_WRITE(GEN7_L3CNTLREG1, 3743 GEN7_WA_FOR_GEN7_L3_CONTROL); 3744 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 3745 GEN7_WA_L3_CHICKEN_MODE); 3746 3747 /* This is required by WaCatErrorRejectionIssue */ 3748 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3749 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3750 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3751 3752 for_each_pipe(pipe) { 3753 I915_WRITE(DSPCNTR(pipe), 3754 I915_READ(DSPCNTR(pipe)) | 3755 DISPPLANE_TRICKLE_FEED_DISABLE); 3756 intel_flush_display_plane(dev_priv, pipe); 3757 } 3758 3759 gen7_setup_fixed_func_scheduler(dev_priv); 3760 3761 /* WaDisable4x2SubspanOptimization */ 3762 I915_WRITE(CACHE_MODE_1, 3763 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3764 3765 /* WaMbcDriverBootEnable */ 3766 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3767 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3768 3769 /* XXX: This is a workaround for early silicon revisions and should be 3770 * removed later. 3771 */ 3772 I915_WRITE(WM_DBG, 3773 I915_READ(WM_DBG) | 3774 WM_DBG_DISALLOW_MULTIPLE_LP | 3775 WM_DBG_DISALLOW_SPRITE | 3776 WM_DBG_DISALLOW_MAXFIFO); 3777 3778 lpt_init_clock_gating(dev); 3779 } 3780 3781 static void ivybridge_init_clock_gating(struct drm_device *dev) 3782 { 3783 struct drm_i915_private *dev_priv = dev->dev_private; 3784 int pipe; 3785 uint32_t snpcr; 3786 3787 I915_WRITE(WM3_LP_ILK, 0); 3788 I915_WRITE(WM2_LP_ILK, 0); 3789 I915_WRITE(WM1_LP_ILK, 0); 3790 3791 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 3792 3793 /* WaDisableEarlyCull */ 3794 I915_WRITE(_3D_CHICKEN3, 3795 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 3796 3797 /* WaDisableBackToBackFlipFix */ 3798 I915_WRITE(IVB_CHICKEN3, 3799 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 3800 CHICKEN3_DGMG_DONE_FIX_DISABLE); 3801 3802 /* WaDisablePSDDualDispatchEnable */ 3803 if (IS_IVB_GT1(dev)) 3804 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 3805 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3806 else 3807 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, 3808 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3809 3810 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3811 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3812 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3813 3814 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3815 I915_WRITE(GEN7_L3CNTLREG1, 3816 GEN7_WA_FOR_GEN7_L3_CONTROL); 3817 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 3818 GEN7_WA_L3_CHICKEN_MODE); 3819 if (IS_IVB_GT1(dev)) 3820 I915_WRITE(GEN7_ROW_CHICKEN2, 3821 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3822 else 3823 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 3824 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3825 3826 3827 /* WaForceL3Serialization */ 3828 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3829 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3830 3831 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3832 * gating disable must be set. Failure to set it results in 3833 * flickering pixels due to Z write ordering failures after 3834 * some amount of runtime in the Mesa "fire" demo, and Unigine 3835 * Sanctuary and Tropics, and apparently anything else with 3836 * alpha test or pixel discard. 3837 * 3838 * According to the spec, bit 11 (RCCUNIT) must also be set, 3839 * but we didn't debug actual testcases to find it out. 3840 * 3841 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3842 * This implements the WaDisableRCZUnitClockGating workaround. 3843 */ 3844 I915_WRITE(GEN6_UCGCTL2, 3845 GEN6_RCZUNIT_CLOCK_GATE_DISABLE | 3846 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3847 3848 /* This is required by WaCatErrorRejectionIssue */ 3849 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3850 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3851 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3852 3853 for_each_pipe(pipe) { 3854 I915_WRITE(DSPCNTR(pipe), 3855 I915_READ(DSPCNTR(pipe)) | 3856 DISPPLANE_TRICKLE_FEED_DISABLE); 3857 intel_flush_display_plane(dev_priv, pipe); 3858 } 3859 3860 /* WaMbcDriverBootEnable */ 3861 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3862 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3863 3864 gen7_setup_fixed_func_scheduler(dev_priv); 3865 3866 /* WaDisable4x2SubspanOptimization */ 3867 I915_WRITE(CACHE_MODE_1, 3868 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3869 3870 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 3871 snpcr &= ~GEN6_MBC_SNPCR_MASK; 3872 snpcr |= GEN6_MBC_SNPCR_MED; 3873 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 3874 3875 cpt_init_clock_gating(dev); 3876 3877 gen6_check_mch_setup(dev); 3878 } 3879 3880 static void valleyview_init_clock_gating(struct drm_device *dev) 3881 { 3882 struct drm_i915_private *dev_priv = dev->dev_private; 3883 int pipe; 3884 3885 I915_WRITE(WM3_LP_ILK, 0); 3886 I915_WRITE(WM2_LP_ILK, 0); 3887 I915_WRITE(WM1_LP_ILK, 0); 3888 3889 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 3890 3891 /* WaDisableEarlyCull */ 3892 I915_WRITE(_3D_CHICKEN3, 3893 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 3894 3895 /* WaDisableBackToBackFlipFix */ 3896 I915_WRITE(IVB_CHICKEN3, 3897 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 3898 CHICKEN3_DGMG_DONE_FIX_DISABLE); 3899 3900 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 3901 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 3902 3903 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3904 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3905 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3906 3907 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3908 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); 3909 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); 3910 3911 /* WaForceL3Serialization */ 3912 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3913 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3914 3915 /* WaDisableDopClockGating */ 3916 I915_WRITE(GEN7_ROW_CHICKEN2, 3917 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 3918 3919 /* WaForceL3Serialization */ 3920 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 3921 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 3922 3923 /* This is required by WaCatErrorRejectionIssue */ 3924 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3925 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3926 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3927 3928 /* WaMbcDriverBootEnable */ 3929 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3930 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3931 3932 3933 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3934 * gating disable must be set. Failure to set it results in 3935 * flickering pixels due to Z write ordering failures after 3936 * some amount of runtime in the Mesa "fire" demo, and Unigine 3937 * Sanctuary and Tropics, and apparently anything else with 3938 * alpha test or pixel discard. 3939 * 3940 * According to the spec, bit 11 (RCCUNIT) must also be set, 3941 * but we didn't debug actual testcases to find it out. 3942 * 3943 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3944 * This implements the WaDisableRCZUnitClockGating workaround. 3945 * 3946 * Also apply WaDisableVDSUnitClockGating and 3947 * WaDisableRCPBUnitClockGating. 3948 */ 3949 I915_WRITE(GEN6_UCGCTL2, 3950 GEN7_VDSUNIT_CLOCK_GATE_DISABLE | 3951 GEN7_TDLUNIT_CLOCK_GATE_DISABLE | 3952 GEN6_RCZUNIT_CLOCK_GATE_DISABLE | 3953 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 3954 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3955 3956 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 3957 3958 for_each_pipe(pipe) { 3959 I915_WRITE(DSPCNTR(pipe), 3960 I915_READ(DSPCNTR(pipe)) | 3961 DISPPLANE_TRICKLE_FEED_DISABLE); 3962 intel_flush_display_plane(dev_priv, pipe); 3963 } 3964 3965 I915_WRITE(CACHE_MODE_1, 3966 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 3967 3968 /* 3969 * On ValleyView, the GUnit needs to signal the GT 3970 * when flip and other events complete. So enable 3971 * all the GUnit->GT interrupts here 3972 */ 3973 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN | 3974 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN | 3975 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN | 3976 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN | 3977 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN | 3978 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN | 3979 PLANEA_FLIPDONE_INT_EN); 3980 3981 /* 3982 * WaDisableVLVClockGating_VBIIssue 3983 * Disable clock gating on th GCFG unit to prevent a delay 3984 * in the reporting of vblank events. 3985 */ 3986 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 3987 } 3988 3989 static void g4x_init_clock_gating(struct drm_device *dev) 3990 { 3991 struct drm_i915_private *dev_priv = dev->dev_private; 3992 uint32_t dspclk_gate; 3993 3994 I915_WRITE(RENCLK_GATE_D1, 0); 3995 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 3996 GS_UNIT_CLOCK_GATE_DISABLE | 3997 CL_UNIT_CLOCK_GATE_DISABLE); 3998 I915_WRITE(RAMCLK_GATE_D, 0); 3999 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 4000 OVRUNIT_CLOCK_GATE_DISABLE | 4001 OVCUNIT_CLOCK_GATE_DISABLE; 4002 if (IS_GM45(dev)) 4003 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 4004 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 4005 4006 /* WaDisableRenderCachePipelinedFlush */ 4007 I915_WRITE(CACHE_MODE_0, 4008 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 4009 } 4010 4011 static void crestline_init_clock_gating(struct drm_device *dev) 4012 { 4013 struct drm_i915_private *dev_priv = dev->dev_private; 4014 4015 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 4016 I915_WRITE(RENCLK_GATE_D2, 0); 4017 I915_WRITE(DSPCLK_GATE_D, 0); 4018 I915_WRITE(RAMCLK_GATE_D, 0); 4019 I915_WRITE16(DEUC, 0); 4020 } 4021 4022 static void broadwater_init_clock_gating(struct drm_device *dev) 4023 { 4024 struct drm_i915_private *dev_priv = dev->dev_private; 4025 4026 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 4027 I965_RCC_CLOCK_GATE_DISABLE | 4028 I965_RCPB_CLOCK_GATE_DISABLE | 4029 I965_ISC_CLOCK_GATE_DISABLE | 4030 I965_FBC_CLOCK_GATE_DISABLE); 4031 I915_WRITE(RENCLK_GATE_D2, 0); 4032 } 4033 4034 static void gen3_init_clock_gating(struct drm_device *dev) 4035 { 4036 struct drm_i915_private *dev_priv = dev->dev_private; 4037 u32 dstate = I915_READ(D_STATE); 4038 4039 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 4040 DSTATE_DOT_CLOCK_GATING; 4041 I915_WRITE(D_STATE, dstate); 4042 4043 if (IS_PINEVIEW(dev)) 4044 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 4045 4046 /* IIR "flip pending" means done if this bit is set */ 4047 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 4048 } 4049 4050 static void i85x_init_clock_gating(struct drm_device *dev) 4051 { 4052 struct drm_i915_private *dev_priv = dev->dev_private; 4053 4054 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 4055 } 4056 4057 static void i830_init_clock_gating(struct drm_device *dev) 4058 { 4059 struct drm_i915_private *dev_priv = dev->dev_private; 4060 4061 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 4062 } 4063 4064 void intel_init_clock_gating(struct drm_device *dev) 4065 { 4066 struct drm_i915_private *dev_priv = dev->dev_private; 4067 4068 dev_priv->display.init_clock_gating(dev); 4069 } 4070 4071 void intel_set_power_well(struct drm_device *dev, bool enable) 4072 { 4073 struct drm_i915_private *dev_priv = dev->dev_private; 4074 bool is_enabled, enable_requested; 4075 uint32_t tmp; 4076 4077 if (!IS_HASWELL(dev)) 4078 return; 4079 4080 if (!i915_disable_power_well && !enable) 4081 return; 4082 4083 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 4084 is_enabled = tmp & HSW_PWR_WELL_STATE; 4085 enable_requested = tmp & HSW_PWR_WELL_ENABLE; 4086 4087 if (enable) { 4088 if (!enable_requested) 4089 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE); 4090 4091 if (!is_enabled) { 4092 DRM_DEBUG_KMS("Enabling power well\n"); 4093 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 4094 HSW_PWR_WELL_STATE), 20)) 4095 DRM_ERROR("Timeout enabling power well\n"); 4096 } 4097 } else { 4098 if (enable_requested) { 4099 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 4100 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 4101 } 4102 } 4103 } 4104 4105 /* 4106 * Starting with Haswell, we have a "Power Down Well" that can be turned off 4107 * when not needed anymore. We have 4 registers that can request the power well 4108 * to be enabled, and it will only be disabled if none of the registers is 4109 * requesting it to be enabled. 4110 */ 4111 void intel_init_power_well(struct drm_device *dev) 4112 { 4113 struct drm_i915_private *dev_priv = dev->dev_private; 4114 4115 if (!IS_HASWELL(dev)) 4116 return; 4117 4118 /* For now, we need the power well to be always enabled. */ 4119 intel_set_power_well(dev, true); 4120 4121 /* We're taking over the BIOS, so clear any requests made by it since 4122 * the driver is in charge now. */ 4123 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE) 4124 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 4125 } 4126 4127 /* Set up chip specific power management-related functions */ 4128 void intel_init_pm(struct drm_device *dev) 4129 { 4130 struct drm_i915_private *dev_priv = dev->dev_private; 4131 4132 if (I915_HAS_FBC(dev)) { 4133 if (HAS_PCH_SPLIT(dev)) { 4134 dev_priv->display.fbc_enabled = ironlake_fbc_enabled; 4135 dev_priv->display.enable_fbc = ironlake_enable_fbc; 4136 dev_priv->display.disable_fbc = ironlake_disable_fbc; 4137 } else if (IS_GM45(dev)) { 4138 dev_priv->display.fbc_enabled = g4x_fbc_enabled; 4139 dev_priv->display.enable_fbc = g4x_enable_fbc; 4140 dev_priv->display.disable_fbc = g4x_disable_fbc; 4141 } else if (IS_CRESTLINE(dev)) { 4142 dev_priv->display.fbc_enabled = i8xx_fbc_enabled; 4143 dev_priv->display.enable_fbc = i8xx_enable_fbc; 4144 dev_priv->display.disable_fbc = i8xx_disable_fbc; 4145 } 4146 /* 855GM needs testing */ 4147 } 4148 4149 /* For cxsr */ 4150 if (IS_PINEVIEW(dev)) 4151 i915_pineview_get_mem_freq(dev); 4152 else if (IS_GEN5(dev)) 4153 i915_ironlake_get_mem_freq(dev); 4154 4155 /* For FIFO watermark updates */ 4156 if (HAS_PCH_SPLIT(dev)) { 4157 if (IS_GEN5(dev)) { 4158 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) 4159 dev_priv->display.update_wm = ironlake_update_wm; 4160 else { 4161 DRM_DEBUG_KMS("Failed to get proper latency. " 4162 "Disable CxSR\n"); 4163 dev_priv->display.update_wm = NULL; 4164 } 4165 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 4166 } else if (IS_GEN6(dev)) { 4167 if (SNB_READ_WM0_LATENCY()) { 4168 dev_priv->display.update_wm = sandybridge_update_wm; 4169 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4170 } else { 4171 DRM_DEBUG_KMS("Failed to read display plane latency. " 4172 "Disable CxSR\n"); 4173 dev_priv->display.update_wm = NULL; 4174 } 4175 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 4176 } else if (IS_IVYBRIDGE(dev)) { 4177 /* FIXME: detect B0+ stepping and use auto training */ 4178 if (SNB_READ_WM0_LATENCY()) { 4179 dev_priv->display.update_wm = ivybridge_update_wm; 4180 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4181 } else { 4182 DRM_DEBUG_KMS("Failed to read display plane latency. " 4183 "Disable CxSR\n"); 4184 dev_priv->display.update_wm = NULL; 4185 } 4186 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 4187 } else if (IS_HASWELL(dev)) { 4188 if (SNB_READ_WM0_LATENCY()) { 4189 dev_priv->display.update_wm = sandybridge_update_wm; 4190 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; 4191 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; 4192 } else { 4193 DRM_DEBUG_KMS("Failed to read display plane latency. " 4194 "Disable CxSR\n"); 4195 dev_priv->display.update_wm = NULL; 4196 } 4197 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 4198 } else 4199 dev_priv->display.update_wm = NULL; 4200 } else if (IS_VALLEYVIEW(dev)) { 4201 dev_priv->display.update_wm = valleyview_update_wm; 4202 dev_priv->display.init_clock_gating = 4203 valleyview_init_clock_gating; 4204 } else if (IS_PINEVIEW(dev)) { 4205 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 4206 dev_priv->is_ddr3, 4207 dev_priv->fsb_freq, 4208 dev_priv->mem_freq)) { 4209 DRM_INFO("failed to find known CxSR latency " 4210 "(found ddr%s fsb freq %d, mem freq %d), " 4211 "disabling CxSR\n", 4212 (dev_priv->is_ddr3 == 1) ? "3" : "2", 4213 dev_priv->fsb_freq, dev_priv->mem_freq); 4214 /* Disable CxSR and never update its watermark again */ 4215 pineview_disable_cxsr(dev); 4216 dev_priv->display.update_wm = NULL; 4217 } else 4218 dev_priv->display.update_wm = pineview_update_wm; 4219 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 4220 } else if (IS_G4X(dev)) { 4221 dev_priv->display.update_wm = g4x_update_wm; 4222 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 4223 } else if (IS_GEN4(dev)) { 4224 dev_priv->display.update_wm = i965_update_wm; 4225 if (IS_CRESTLINE(dev)) 4226 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 4227 else if (IS_BROADWATER(dev)) 4228 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 4229 } else if (IS_GEN3(dev)) { 4230 dev_priv->display.update_wm = i9xx_update_wm; 4231 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 4232 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 4233 } else if (IS_I865G(dev)) { 4234 dev_priv->display.update_wm = i830_update_wm; 4235 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 4236 dev_priv->display.get_fifo_size = i830_get_fifo_size; 4237 } else if (IS_I85X(dev)) { 4238 dev_priv->display.update_wm = i9xx_update_wm; 4239 dev_priv->display.get_fifo_size = i85x_get_fifo_size; 4240 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 4241 } else { 4242 dev_priv->display.update_wm = i830_update_wm; 4243 dev_priv->display.init_clock_gating = i830_init_clock_gating; 4244 if (IS_845G(dev)) 4245 dev_priv->display.get_fifo_size = i845_get_fifo_size; 4246 else 4247 dev_priv->display.get_fifo_size = i830_get_fifo_size; 4248 } 4249 } 4250 4251 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) 4252 { 4253 u32 gt_thread_status_mask; 4254 4255 if (IS_HASWELL(dev_priv->dev)) 4256 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; 4257 else 4258 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; 4259 4260 /* w/a for a sporadic read returning 0 by waiting for the GT 4261 * thread to wake up. 4262 */ 4263 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) 4264 DRM_ERROR("GT thread status wait timed out\n"); 4265 } 4266 4267 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) 4268 { 4269 I915_WRITE_NOTRACE(FORCEWAKE, 0); 4270 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ 4271 } 4272 4273 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 4274 { 4275 u32 forcewake_ack; 4276 4277 if (IS_HASWELL(dev_priv->dev)) 4278 forcewake_ack = FORCEWAKE_ACK_HSW; 4279 else 4280 forcewake_ack = FORCEWAKE_ACK; 4281 4282 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 4283 FORCEWAKE_ACK_TIMEOUT_MS)) 4284 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4285 4286 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL); 4287 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ 4288 4289 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), 4290 FORCEWAKE_ACK_TIMEOUT_MS)) 4291 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4292 4293 __gen6_gt_wait_for_thread_c0(dev_priv); 4294 } 4295 4296 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) 4297 { 4298 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); 4299 /* something from same cacheline, but !FORCEWAKE_MT */ 4300 POSTING_READ(ECOBUS); 4301 } 4302 4303 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) 4304 { 4305 u32 forcewake_ack; 4306 4307 if (IS_HASWELL(dev_priv->dev)) 4308 forcewake_ack = FORCEWAKE_ACK_HSW; 4309 else 4310 forcewake_ack = FORCEWAKE_MT_ACK; 4311 4312 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 4313 FORCEWAKE_ACK_TIMEOUT_MS)) 4314 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4315 4316 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 4317 /* something from same cacheline, but !FORCEWAKE_MT */ 4318 POSTING_READ(ECOBUS); 4319 4320 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), 4321 FORCEWAKE_ACK_TIMEOUT_MS)) 4322 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4323 4324 __gen6_gt_wait_for_thread_c0(dev_priv); 4325 } 4326 4327 /* 4328 * Generally this is called implicitly by the register read function. However, 4329 * if some sequence requires the GT to not power down then this function should 4330 * be called at the beginning of the sequence followed by a call to 4331 * gen6_gt_force_wake_put() at the end of the sequence. 4332 */ 4333 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 4334 { 4335 4336 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); 4337 if (dev_priv->forcewake_count++ == 0) 4338 dev_priv->gt.force_wake_get(dev_priv); 4339 lockmgr(&dev_priv->gt_lock, LK_RELEASE); 4340 } 4341 4342 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) 4343 { 4344 u32 gtfifodbg; 4345 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); 4346 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, 4347 "MMIO read or write has been dropped %x\n", gtfifodbg)) 4348 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); 4349 } 4350 4351 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 4352 { 4353 I915_WRITE_NOTRACE(FORCEWAKE, 0); 4354 /* something from same cacheline, but !FORCEWAKE */ 4355 POSTING_READ(ECOBUS); 4356 gen6_gt_check_fifodbg(dev_priv); 4357 } 4358 4359 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) 4360 { 4361 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 4362 /* something from same cacheline, but !FORCEWAKE_MT */ 4363 POSTING_READ(ECOBUS); 4364 gen6_gt_check_fifodbg(dev_priv); 4365 } 4366 4367 /* 4368 * see gen6_gt_force_wake_get() 4369 */ 4370 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 4371 { 4372 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); 4373 if (--dev_priv->forcewake_count == 0) 4374 dev_priv->gt.force_wake_put(dev_priv); 4375 lockmgr(&dev_priv->gt_lock, LK_RELEASE); 4376 } 4377 4378 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 4379 { 4380 int ret = 0; 4381 4382 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 4383 int loop = 500; 4384 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 4385 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 4386 udelay(10); 4387 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 4388 } 4389 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) 4390 ++ret; 4391 dev_priv->gt_fifo_count = fifo; 4392 } 4393 dev_priv->gt_fifo_count--; 4394 4395 return ret; 4396 } 4397 4398 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) 4399 { 4400 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); 4401 /* something from same cacheline, but !FORCEWAKE_VLV */ 4402 POSTING_READ(FORCEWAKE_ACK_VLV); 4403 } 4404 4405 static void vlv_force_wake_get(struct drm_i915_private *dev_priv) 4406 { 4407 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, 4408 FORCEWAKE_ACK_TIMEOUT_MS)) 4409 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 4410 4411 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 4412 4413 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 4414 FORCEWAKE_ACK_TIMEOUT_MS)) 4415 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 4416 4417 __gen6_gt_wait_for_thread_c0(dev_priv); 4418 } 4419 4420 static void vlv_force_wake_put(struct drm_i915_private *dev_priv) 4421 { 4422 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 4423 /* something from same cacheline, but !FORCEWAKE_VLV */ 4424 POSTING_READ(FORCEWAKE_ACK_VLV); 4425 gen6_gt_check_fifodbg(dev_priv); 4426 } 4427 4428 void intel_gt_reset(struct drm_device *dev) 4429 { 4430 struct drm_i915_private *dev_priv = dev->dev_private; 4431 4432 if (IS_VALLEYVIEW(dev)) { 4433 vlv_force_wake_reset(dev_priv); 4434 } else if (INTEL_INFO(dev)->gen >= 6) { 4435 __gen6_gt_force_wake_reset(dev_priv); 4436 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 4437 __gen6_gt_force_wake_mt_reset(dev_priv); 4438 } 4439 } 4440 4441 void intel_gt_init(struct drm_device *dev) 4442 { 4443 struct drm_i915_private *dev_priv = dev->dev_private; 4444 4445 lockinit(&dev_priv->gt_lock, "915gt", 0, LK_CANRECURSE); 4446 4447 intel_gt_reset(dev); 4448 4449 if (IS_VALLEYVIEW(dev)) { 4450 dev_priv->gt.force_wake_get = vlv_force_wake_get; 4451 dev_priv->gt.force_wake_put = vlv_force_wake_put; 4452 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { 4453 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; 4454 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; 4455 } else if (IS_GEN6(dev)) { 4456 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; 4457 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; 4458 } 4459 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 4460 intel_gen6_powersave_work); 4461 } 4462 4463 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) 4464 { 4465 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4466 4467 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 4468 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 4469 return -EAGAIN; 4470 } 4471 4472 I915_WRITE(GEN6_PCODE_DATA, *val); 4473 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 4474 4475 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 4476 500)) { 4477 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 4478 return -ETIMEDOUT; 4479 } 4480 4481 *val = I915_READ(GEN6_PCODE_DATA); 4482 I915_WRITE(GEN6_PCODE_DATA, 0); 4483 4484 return 0; 4485 } 4486 4487 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) 4488 { 4489 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4490 4491 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 4492 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 4493 return -EAGAIN; 4494 } 4495 4496 I915_WRITE(GEN6_PCODE_DATA, val); 4497 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 4498 4499 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 4500 500)) { 4501 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 4502 return -ETIMEDOUT; 4503 } 4504 4505 I915_WRITE(GEN6_PCODE_DATA, 0); 4506 4507 return 0; 4508 } 4509