1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Panel Self Refresh (PSR/SRD) 26 * 27 * Since Haswell Display controller supports Panel Self-Refresh on display 28 * panels witch have a remote frame buffer (RFB) implemented according to PSR 29 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 30 * when system is idle but display is on as it eliminates display refresh 31 * request to DDR memory completely as long as the frame buffer for that 32 * display is unchanged. 33 * 34 * Panel Self Refresh must be supported by both Hardware (source) and 35 * Panel (sink). 36 * 37 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 38 * to power down the link and memory controller. For DSI panels the same idea 39 * is called "manual mode". 40 * 41 * The implementation uses the hardware-based PSR support which automatically 42 * enters/exits self-refresh mode. The hardware takes care of sending the 43 * required DP aux message and could even retrain the link (that part isn't 44 * enabled yet though). The hardware also keeps track of any frontbuffer 45 * changes to know when to exit self-refresh mode again. Unfortunately that 46 * part doesn't work too well, hence why the i915 PSR support uses the 47 * software frontbuffer tracking to make sure it doesn't miss a screen 48 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 49 * get called by the frontbuffer tracking code. Note that because of locking 50 * issues the self-refresh re-enable code is done from a work queue, which 51 * must be correctly synchronized/cancelled when shutting down the pipe." 52 */ 53 54 #include <drm/drmP.h> 55 56 #include "intel_drv.h" 57 #include "i915_drv.h" 58 59 static bool is_edp_psr(struct intel_dp *intel_dp) 60 { 61 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; 62 } 63 64 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) 65 { 66 struct drm_i915_private *dev_priv = dev->dev_private; 67 uint32_t val; 68 69 val = I915_READ(VLV_PSRSTAT(pipe)) & 70 VLV_EDP_PSR_CURR_STATE_MASK; 71 return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 72 (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE); 73 } 74 75 static void intel_psr_write_vsc(struct intel_dp *intel_dp, 76 struct edp_vsc_psr *vsc_psr) 77 { 78 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 79 struct drm_device *dev = dig_port->base.base.dev; 80 struct drm_i915_private *dev_priv = dev->dev_private; 81 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 82 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder); 83 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder); 84 uint32_t *data = (uint32_t *) vsc_psr; 85 unsigned int i; 86 87 /* As per BSPec (Pipe Video Data Island Packet), we need to disable 88 the video DIP being updated before program video DIP data buffer 89 registers for DIP being updated. */ 90 I915_WRITE(ctl_reg, 0); 91 POSTING_READ(ctl_reg); 92 93 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { 94 if (i < sizeof(struct edp_vsc_psr)) 95 I915_WRITE(data_reg + i, *data++); 96 else 97 I915_WRITE(data_reg + i, 0); 98 } 99 100 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); 101 POSTING_READ(ctl_reg); 102 } 103 104 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp) 105 { 106 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 107 struct drm_device *dev = intel_dig_port->base.base.dev; 108 struct drm_i915_private *dev_priv = dev->dev_private; 109 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 110 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; 111 uint32_t val; 112 113 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */ 114 val = I915_READ(VLV_VSCSDP(pipe)); 115 val &= ~VLV_EDP_PSR_SDP_FREQ_MASK; 116 val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME; 117 I915_WRITE(VLV_VSCSDP(pipe), val); 118 } 119 120 static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp) 121 { 122 struct edp_vsc_psr psr_vsc; 123 124 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ 125 memset(&psr_vsc, 0, sizeof(psr_vsc)); 126 psr_vsc.sdp_header.HB0 = 0; 127 psr_vsc.sdp_header.HB1 = 0x7; 128 psr_vsc.sdp_header.HB2 = 0x3; 129 psr_vsc.sdp_header.HB3 = 0xb; 130 intel_psr_write_vsc(intel_dp, &psr_vsc); 131 } 132 133 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp) 134 { 135 struct edp_vsc_psr psr_vsc; 136 137 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 138 memset(&psr_vsc, 0, sizeof(psr_vsc)); 139 psr_vsc.sdp_header.HB0 = 0; 140 psr_vsc.sdp_header.HB1 = 0x7; 141 psr_vsc.sdp_header.HB2 = 0x2; 142 psr_vsc.sdp_header.HB3 = 0x8; 143 intel_psr_write_vsc(intel_dp, &psr_vsc); 144 } 145 146 static void vlv_psr_enable_sink(struct intel_dp *intel_dp) 147 { 148 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 149 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 150 } 151 152 static void hsw_psr_enable_sink(struct intel_dp *intel_dp) 153 { 154 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 155 struct drm_device *dev = dig_port->base.base.dev; 156 struct drm_i915_private *dev_priv = dev->dev_private; 157 uint32_t aux_clock_divider; 158 uint32_t aux_data_reg, aux_ctl_reg; 159 int precharge = 0x3; 160 static const uint8_t aux_msg[] = { 161 [0] = DP_AUX_NATIVE_WRITE << 4, 162 [1] = DP_SET_POWER >> 8, 163 [2] = DP_SET_POWER & 0xff, 164 [3] = 1 - 1, 165 [4] = DP_SET_POWER_D0, 166 }; 167 int i; 168 169 BUILD_BUG_ON(sizeof(aux_msg) > 20); 170 171 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 172 173 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 174 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); 175 176 /* Enable AUX frame sync at sink */ 177 if (dev_priv->psr.aux_frame_sync) 178 drm_dp_dpcd_writeb(&intel_dp->aux, 179 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, 180 DP_AUX_FRAME_SYNC_ENABLE); 181 182 aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ? 183 DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev); 184 aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ? 185 DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev); 186 187 /* Setup AUX registers */ 188 for (i = 0; i < sizeof(aux_msg); i += 4) 189 I915_WRITE(aux_data_reg + i, 190 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); 191 192 if (INTEL_INFO(dev)->gen >= 9) { 193 uint32_t val; 194 195 val = I915_READ(aux_ctl_reg); 196 val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK; 197 val |= DP_AUX_CH_CTL_TIME_OUT_1600us; 198 val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK; 199 val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 200 /* Use hardcoded data values for PSR, frame sync and GTC */ 201 val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL; 202 val &= ~DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL; 203 val &= ~DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL; 204 I915_WRITE(aux_ctl_reg, val); 205 } else { 206 I915_WRITE(aux_ctl_reg, 207 DP_AUX_CH_CTL_TIME_OUT_400us | 208 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 209 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 210 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); 211 } 212 213 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE); 214 } 215 216 static void vlv_psr_enable_source(struct intel_dp *intel_dp) 217 { 218 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 219 struct drm_device *dev = dig_port->base.base.dev; 220 struct drm_i915_private *dev_priv = dev->dev_private; 221 struct drm_crtc *crtc = dig_port->base.base.crtc; 222 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; 223 224 /* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */ 225 I915_WRITE(VLV_PSRCTL(pipe), 226 VLV_EDP_PSR_MODE_SW_TIMER | 227 VLV_EDP_PSR_SRC_TRANSMITTER_STATE | 228 VLV_EDP_PSR_ENABLE); 229 } 230 231 static void vlv_psr_activate(struct intel_dp *intel_dp) 232 { 233 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 234 struct drm_device *dev = dig_port->base.base.dev; 235 struct drm_i915_private *dev_priv = dev->dev_private; 236 struct drm_crtc *crtc = dig_port->base.base.crtc; 237 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; 238 239 /* Let's do the transition from PSR_state 1 to PSR_state 2 240 * that is PSR transition to active - static frame transmission. 241 * Then Hardware is responsible for the transition to PSR_state 3 242 * that is PSR active - no Remote Frame Buffer (RFB) update. 243 */ 244 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | 245 VLV_EDP_PSR_ACTIVE_ENTRY); 246 } 247 248 static void hsw_psr_enable_source(struct intel_dp *intel_dp) 249 { 250 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 251 struct drm_device *dev = dig_port->base.base.dev; 252 struct drm_i915_private *dev_priv = dev->dev_private; 253 254 uint32_t max_sleep_time = 0x1f; 255 /* Lately it was identified that depending on panel idle frame count 256 * calculated at HW can be off by 1. So let's use what came 257 * from VBT + 1 and at minimum 2 to be on the safe side. 258 */ 259 uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ? 260 dev_priv->vbt.psr.idle_frames + 1 : 2; 261 uint32_t val = 0x0; 262 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 263 264 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { 265 /* It doesn't mean we shouldn't send TPS patters, so let's 266 send the minimal TP1 possible and skip TP2. */ 267 val |= EDP_PSR_TP1_TIME_100us; 268 val |= EDP_PSR_TP2_TP3_TIME_0us; 269 val |= EDP_PSR_SKIP_AUX_EXIT; 270 /* Sink should be able to train with the 5 or 6 idle patterns */ 271 idle_frames += 4; 272 } 273 274 I915_WRITE(EDP_PSR_CTL(dev), val | 275 (IS_BROADWELL(dev) ? 0 : link_entry_time) | 276 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | 277 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | 278 EDP_PSR_ENABLE); 279 280 if (dev_priv->psr.psr2_support) 281 I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE | 282 EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100); 283 } 284 285 static bool intel_psr_match_conditions(struct intel_dp *intel_dp) 286 { 287 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 288 struct drm_device *dev = dig_port->base.base.dev; 289 struct drm_i915_private *dev_priv = dev->dev_private; 290 struct drm_crtc *crtc = dig_port->base.base.crtc; 291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 292 293 lockdep_assert_held(&dev_priv->psr.lock); 294 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 295 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 296 297 dev_priv->psr.source_ok = false; 298 299 if (IS_HASWELL(dev) && dig_port->port != PORT_A) { 300 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); 301 return false; 302 } 303 304 if (!i915.enable_psr) { 305 DRM_DEBUG_KMS("PSR disable by flag\n"); 306 return false; 307 } 308 309 if (IS_HASWELL(dev) && 310 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & 311 S3D_ENABLE) { 312 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 313 return false; 314 } 315 316 if (IS_HASWELL(dev) && 317 intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 318 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 319 return false; 320 } 321 322 if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) || 323 (dig_port->port != PORT_A))) { 324 DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n"); 325 return false; 326 } 327 328 dev_priv->psr.source_ok = true; 329 return true; 330 } 331 332 static void intel_psr_activate(struct intel_dp *intel_dp) 333 { 334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 335 struct drm_device *dev = intel_dig_port->base.base.dev; 336 struct drm_i915_private *dev_priv = dev->dev_private; 337 338 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); 339 WARN_ON(dev_priv->psr.active); 340 lockdep_assert_held(&dev_priv->psr.lock); 341 342 /* Enable/Re-enable PSR on the host */ 343 if (HAS_DDI(dev)) 344 /* On HSW+ after we enable PSR on source it will activate it 345 * as soon as it match configure idle_frame count. So 346 * we just actually enable it here on activation time. 347 */ 348 hsw_psr_enable_source(intel_dp); 349 else 350 vlv_psr_activate(intel_dp); 351 352 dev_priv->psr.active = true; 353 } 354 355 /** 356 * intel_psr_enable - Enable PSR 357 * @intel_dp: Intel DP 358 * 359 * This function can only be called after the pipe is fully trained and enabled. 360 */ 361 void intel_psr_enable(struct intel_dp *intel_dp) 362 { 363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 364 struct drm_device *dev = intel_dig_port->base.base.dev; 365 struct drm_i915_private *dev_priv = dev->dev_private; 366 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); 367 368 if (!HAS_PSR(dev)) { 369 DRM_DEBUG_KMS("PSR not supported on this platform\n"); 370 return; 371 } 372 373 if (!is_edp_psr(intel_dp)) { 374 DRM_DEBUG_KMS("PSR not supported by this panel\n"); 375 return; 376 } 377 378 mutex_lock(&dev_priv->psr.lock); 379 if (dev_priv->psr.enabled) { 380 DRM_DEBUG_KMS("PSR already in use\n"); 381 goto unlock; 382 } 383 384 if (!intel_psr_match_conditions(intel_dp)) 385 goto unlock; 386 387 dev_priv->psr.busy_frontbuffer_bits = 0; 388 389 if (HAS_DDI(dev)) { 390 hsw_psr_setup_vsc(intel_dp); 391 392 if (dev_priv->psr.psr2_support) { 393 /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */ 394 if (crtc->config->pipe_src_w > 3200 || 395 crtc->config->pipe_src_h > 2000) 396 dev_priv->psr.psr2_support = false; 397 else 398 skl_psr_setup_su_vsc(intel_dp); 399 } 400 401 /* Avoid continuous PSR exit by masking memup and hpd */ 402 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | 403 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); 404 405 /* Enable PSR on the panel */ 406 hsw_psr_enable_sink(intel_dp); 407 408 if (INTEL_INFO(dev)->gen >= 9) 409 intel_psr_activate(intel_dp); 410 } else { 411 vlv_psr_setup_vsc(intel_dp); 412 413 /* Enable PSR on the panel */ 414 vlv_psr_enable_sink(intel_dp); 415 416 /* On HSW+ enable_source also means go to PSR entry/active 417 * state as soon as idle_frame achieved and here would be 418 * to soon. However on VLV enable_source just enable PSR 419 * but let it on inactive state. So we might do this prior 420 * to active transition, i.e. here. 421 */ 422 vlv_psr_enable_source(intel_dp); 423 } 424 425 dev_priv->psr.enabled = intel_dp; 426 unlock: 427 mutex_unlock(&dev_priv->psr.lock); 428 } 429 430 static void vlv_psr_disable(struct intel_dp *intel_dp) 431 { 432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 433 struct drm_device *dev = intel_dig_port->base.base.dev; 434 struct drm_i915_private *dev_priv = dev->dev_private; 435 struct intel_crtc *intel_crtc = 436 to_intel_crtc(intel_dig_port->base.base.crtc); 437 uint32_t val; 438 439 if (dev_priv->psr.active) { 440 /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */ 441 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) & 442 VLV_EDP_PSR_IN_TRANS) == 0, 1)) 443 WARN(1, "PSR transition took longer than expected\n"); 444 445 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); 446 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; 447 val &= ~VLV_EDP_PSR_ENABLE; 448 val &= ~VLV_EDP_PSR_MODE_MASK; 449 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); 450 451 dev_priv->psr.active = false; 452 } else { 453 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe)); 454 } 455 } 456 457 static void hsw_psr_disable(struct intel_dp *intel_dp) 458 { 459 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 460 struct drm_device *dev = intel_dig_port->base.base.dev; 461 struct drm_i915_private *dev_priv = dev->dev_private; 462 463 if (dev_priv->psr.active) { 464 I915_WRITE(EDP_PSR_CTL(dev), 465 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); 466 467 /* Wait till PSR is idle */ 468 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & 469 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) 470 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 471 472 dev_priv->psr.active = false; 473 } else { 474 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); 475 } 476 } 477 478 /** 479 * intel_psr_disable - Disable PSR 480 * @intel_dp: Intel DP 481 * 482 * This function needs to be called before disabling pipe. 483 */ 484 void intel_psr_disable(struct intel_dp *intel_dp) 485 { 486 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 487 struct drm_device *dev = intel_dig_port->base.base.dev; 488 struct drm_i915_private *dev_priv = dev->dev_private; 489 490 mutex_lock(&dev_priv->psr.lock); 491 if (!dev_priv->psr.enabled) { 492 mutex_unlock(&dev_priv->psr.lock); 493 return; 494 } 495 496 if (HAS_DDI(dev)) 497 hsw_psr_disable(intel_dp); 498 else 499 vlv_psr_disable(intel_dp); 500 501 dev_priv->psr.enabled = NULL; 502 mutex_unlock(&dev_priv->psr.lock); 503 504 cancel_delayed_work_sync(&dev_priv->psr.work); 505 } 506 507 static void intel_psr_work(struct work_struct *work) 508 { 509 struct drm_i915_private *dev_priv = 510 container_of(work, typeof(*dev_priv), psr.work.work); 511 struct intel_dp *intel_dp = dev_priv->psr.enabled; 512 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 513 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; 514 515 /* We have to make sure PSR is ready for re-enable 516 * otherwise it keeps disabled until next full enable/disable cycle. 517 * PSR might take some time to get fully disabled 518 * and be ready for re-enable. 519 */ 520 if (HAS_DDI(dev_priv->dev)) { 521 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) & 522 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) { 523 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); 524 return; 525 } 526 } else { 527 if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) & 528 VLV_EDP_PSR_IN_TRANS) == 0, 1)) { 529 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); 530 return; 531 } 532 } 533 mutex_lock(&dev_priv->psr.lock); 534 intel_dp = dev_priv->psr.enabled; 535 536 if (!intel_dp) 537 goto unlock; 538 539 /* 540 * The delayed work can race with an invalidate hence we need to 541 * recheck. Since psr_flush first clears this and then reschedules we 542 * won't ever miss a flush when bailing out here. 543 */ 544 if (dev_priv->psr.busy_frontbuffer_bits) 545 goto unlock; 546 547 intel_psr_activate(intel_dp); 548 unlock: 549 mutex_unlock(&dev_priv->psr.lock); 550 } 551 552 static void intel_psr_exit(struct drm_device *dev) 553 { 554 struct drm_i915_private *dev_priv = dev->dev_private; 555 struct intel_dp *intel_dp = dev_priv->psr.enabled; 556 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 557 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; 558 u32 val; 559 560 if (!dev_priv->psr.active) 561 return; 562 563 if (HAS_DDI(dev)) { 564 val = I915_READ(EDP_PSR_CTL(dev)); 565 566 WARN_ON(!(val & EDP_PSR_ENABLE)); 567 568 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); 569 } else { 570 val = I915_READ(VLV_PSRCTL(pipe)); 571 572 /* Here we do the transition from PSR_state 3 to PSR_state 5 573 * directly once PSR State 4 that is active with single frame 574 * update can be skipped. PSR_state 5 that is PSR exit then 575 * Hardware is responsible to transition back to PSR_state 1 576 * that is PSR inactive. Same state after 577 * vlv_edp_psr_enable_source. 578 */ 579 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; 580 I915_WRITE(VLV_PSRCTL(pipe), val); 581 582 /* Send AUX wake up - Spec says after transitioning to PSR 583 * active we have to send AUX wake up by writing 01h in DPCD 584 * 600h of sink device. 585 * XXX: This might slow down the transition, but without this 586 * HW doesn't complete the transition to PSR_state 1 and we 587 * never get the screen updated. 588 */ 589 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 590 DP_SET_POWER_D0); 591 } 592 593 dev_priv->psr.active = false; 594 } 595 596 /** 597 * intel_psr_single_frame_update - Single Frame Update 598 * @dev: DRM device 599 * 600 * Some platforms support a single frame update feature that is used to 601 * send and update only one frame on Remote Frame Buffer. 602 * So far it is only implemented for Valleyview and Cherryview because 603 * hardware requires this to be done before a page flip. 604 */ 605 void intel_psr_single_frame_update(struct drm_device *dev) 606 { 607 struct drm_i915_private *dev_priv = dev->dev_private; 608 struct drm_crtc *crtc; 609 enum i915_pipe pipe; 610 u32 val; 611 612 /* 613 * Single frame update is already supported on BDW+ but it requires 614 * many W/A and it isn't really needed. 615 */ 616 if (!IS_VALLEYVIEW(dev)) 617 return; 618 619 mutex_lock(&dev_priv->psr.lock); 620 if (!dev_priv->psr.enabled) { 621 mutex_unlock(&dev_priv->psr.lock); 622 return; 623 } 624 625 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 626 pipe = to_intel_crtc(crtc)->pipe; 627 val = I915_READ(VLV_PSRCTL(pipe)); 628 629 /* 630 * We need to set this bit before writing registers for a flip. 631 * This bit will be self-clear when it gets to the PSR active state. 632 */ 633 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE); 634 635 mutex_unlock(&dev_priv->psr.lock); 636 } 637 638 /** 639 * intel_psr_invalidate - Invalidade PSR 640 * @dev: DRM device 641 * @frontbuffer_bits: frontbuffer plane tracking bits 642 * 643 * Since the hardware frontbuffer tracking has gaps we need to integrate 644 * with the software frontbuffer tracking. This function gets called every 645 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 646 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 647 * 648 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 649 */ 650 void intel_psr_invalidate(struct drm_device *dev, 651 unsigned frontbuffer_bits) 652 { 653 struct drm_i915_private *dev_priv = dev->dev_private; 654 struct drm_crtc *crtc; 655 enum i915_pipe pipe; 656 657 mutex_lock(&dev_priv->psr.lock); 658 if (!dev_priv->psr.enabled) { 659 mutex_unlock(&dev_priv->psr.lock); 660 return; 661 } 662 663 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 664 pipe = to_intel_crtc(crtc)->pipe; 665 666 intel_psr_exit(dev); 667 668 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 669 670 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; 671 mutex_unlock(&dev_priv->psr.lock); 672 } 673 674 /** 675 * intel_psr_flush - Flush PSR 676 * @dev: DRM device 677 * @frontbuffer_bits: frontbuffer plane tracking bits 678 * 679 * Since the hardware frontbuffer tracking has gaps we need to integrate 680 * with the software frontbuffer tracking. This function gets called every 681 * time frontbuffer rendering has completed and flushed out to memory. PSR 682 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 683 * 684 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 685 */ 686 void intel_psr_flush(struct drm_device *dev, 687 unsigned frontbuffer_bits) 688 { 689 struct drm_i915_private *dev_priv = dev->dev_private; 690 struct drm_crtc *crtc; 691 enum i915_pipe pipe; 692 693 mutex_lock(&dev_priv->psr.lock); 694 if (!dev_priv->psr.enabled) { 695 mutex_unlock(&dev_priv->psr.lock); 696 return; 697 } 698 699 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 700 pipe = to_intel_crtc(crtc)->pipe; 701 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; 702 703 /* 704 * On Haswell sprite plane updates don't result in a psr invalidating 705 * signal in the hardware. Which means we need to manually fake this in 706 * software for all flushes, not just when we've seen a preceding 707 * invalidation through frontbuffer rendering. 708 */ 709 if (IS_HASWELL(dev) && 710 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) 711 intel_psr_exit(dev); 712 713 /* 714 * On Valleyview and Cherryview we don't use hardware tracking so 715 * any plane updates or cursor moves don't result in a PSR 716 * invalidating. Which means we need to manually fake this in 717 * software for all flushes, not just when we've seen a preceding 718 * invalidation through frontbuffer rendering. */ 719 if (!HAS_DDI(dev)) 720 intel_psr_exit(dev); 721 722 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) 723 schedule_delayed_work(&dev_priv->psr.work, 724 msecs_to_jiffies(100)); 725 mutex_unlock(&dev_priv->psr.lock); 726 } 727 728 /** 729 * intel_psr_init - Init basic PSR work and mutex. 730 * @dev: DRM device 731 * 732 * This function is called only once at driver load to initialize basic 733 * PSR stuff. 734 */ 735 void intel_psr_init(struct drm_device *dev) 736 { 737 struct drm_i915_private *dev_priv = dev->dev_private; 738 739 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); 740 lockinit(&dev_priv->psr.lock, "i915dpl", 0, LK_CANRECURSE); 741 } 742