1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Panel Self Refresh (PSR/SRD) 26 * 27 * Since Haswell Display controller supports Panel Self-Refresh on display 28 * panels witch have a remote frame buffer (RFB) implemented according to PSR 29 * spec in eDP1.3. PSR feature allows the display to go to lower standby states 30 * when system is idle but display is on as it eliminates display refresh 31 * request to DDR memory completely as long as the frame buffer for that 32 * display is unchanged. 33 * 34 * Panel Self Refresh must be supported by both Hardware (source) and 35 * Panel (sink). 36 * 37 * PSR saves power by caching the framebuffer in the panel RFB, which allows us 38 * to power down the link and memory controller. For DSI panels the same idea 39 * is called "manual mode". 40 * 41 * The implementation uses the hardware-based PSR support which automatically 42 * enters/exits self-refresh mode. The hardware takes care of sending the 43 * required DP aux message and could even retrain the link (that part isn't 44 * enabled yet though). The hardware also keeps track of any frontbuffer 45 * changes to know when to exit self-refresh mode again. Unfortunately that 46 * part doesn't work too well, hence why the i915 PSR support uses the 47 * software frontbuffer tracking to make sure it doesn't miss a screen 48 * update. For this integration intel_psr_invalidate() and intel_psr_flush() 49 * get called by the frontbuffer tracking code. Note that because of locking 50 * issues the self-refresh re-enable code is done from a work queue, which 51 * must be correctly synchronized/cancelled when shutting down the pipe." 52 */ 53 54 #include <drm/drmP.h> 55 56 #include "intel_drv.h" 57 #include "i915_drv.h" 58 59 static bool is_edp_psr(struct intel_dp *intel_dp) 60 { 61 if (!intel_dp_is_edp(intel_dp)) 62 return false; 63 64 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; 65 } 66 67 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) 68 { 69 struct drm_i915_private *dev_priv = to_i915(dev); 70 uint32_t val; 71 72 val = I915_READ(VLV_PSRSTAT(pipe)) & 73 VLV_EDP_PSR_CURR_STATE_MASK; 74 return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) || 75 (val == VLV_EDP_PSR_ACTIVE_SF_UPDATE); 76 } 77 78 static void vlv_psr_setup_vsc(struct intel_dp *intel_dp, 79 const struct intel_crtc_state *crtc_state) 80 { 81 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 82 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 83 uint32_t val; 84 85 /* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */ 86 val = I915_READ(VLV_VSCSDP(crtc->pipe)); 87 val &= ~VLV_EDP_PSR_SDP_FREQ_MASK; 88 val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME; 89 I915_WRITE(VLV_VSCSDP(crtc->pipe), val); 90 } 91 92 static void hsw_psr_setup_vsc(struct intel_dp *intel_dp, 93 const struct intel_crtc_state *crtc_state) 94 { 95 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 96 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 97 struct edp_vsc_psr psr_vsc; 98 99 if (dev_priv->psr.psr2_support) { 100 /* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */ 101 memset(&psr_vsc, 0, sizeof(psr_vsc)); 102 psr_vsc.sdp_header.HB0 = 0; 103 psr_vsc.sdp_header.HB1 = 0x7; 104 if (dev_priv->psr.colorimetry_support && 105 dev_priv->psr.y_cord_support) { 106 psr_vsc.sdp_header.HB2 = 0x5; 107 psr_vsc.sdp_header.HB3 = 0x13; 108 } else if (dev_priv->psr.y_cord_support) { 109 psr_vsc.sdp_header.HB2 = 0x4; 110 psr_vsc.sdp_header.HB3 = 0xe; 111 } else { 112 psr_vsc.sdp_header.HB2 = 0x3; 113 psr_vsc.sdp_header.HB3 = 0xc; 114 } 115 } else { 116 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ 117 memset(&psr_vsc, 0, sizeof(psr_vsc)); 118 psr_vsc.sdp_header.HB0 = 0; 119 psr_vsc.sdp_header.HB1 = 0x7; 120 psr_vsc.sdp_header.HB2 = 0x2; 121 psr_vsc.sdp_header.HB3 = 0x8; 122 } 123 124 intel_dig_port->write_infoframe(&intel_dig_port->base.base, crtc_state, 125 DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc)); 126 } 127 128 static void vlv_psr_enable_sink(struct intel_dp *intel_dp) 129 { 130 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 131 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 132 } 133 134 static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv, 135 enum port port) 136 { 137 if (INTEL_INFO(dev_priv)->gen >= 9) 138 return DP_AUX_CH_CTL(port); 139 else 140 return EDP_PSR_AUX_CTL; 141 } 142 143 static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv, 144 enum port port, int index) 145 { 146 if (INTEL_INFO(dev_priv)->gen >= 9) 147 return DP_AUX_CH_DATA(port, index); 148 else 149 return EDP_PSR_AUX_DATA(index); 150 } 151 152 static void hsw_psr_enable_sink(struct intel_dp *intel_dp) 153 { 154 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 155 struct drm_device *dev = dig_port->base.base.dev; 156 struct drm_i915_private *dev_priv = to_i915(dev); 157 uint32_t aux_clock_divider; 158 i915_reg_t aux_ctl_reg; 159 static const uint8_t aux_msg[] = { 160 [0] = DP_AUX_NATIVE_WRITE << 4, 161 [1] = DP_SET_POWER >> 8, 162 [2] = DP_SET_POWER & 0xff, 163 [3] = 1 - 1, 164 [4] = DP_SET_POWER_D0, 165 }; 166 enum port port = dig_port->port; 167 u32 aux_ctl; 168 int i; 169 170 BUILD_BUG_ON(sizeof(aux_msg) > 20); 171 172 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); 173 174 /* Enable AUX frame sync at sink */ 175 if (dev_priv->psr.aux_frame_sync) 176 drm_dp_dpcd_writeb(&intel_dp->aux, 177 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, 178 DP_AUX_FRAME_SYNC_ENABLE); 179 /* Enable ALPM at sink for psr2 */ 180 if (dev_priv->psr.psr2_support && dev_priv->psr.alpm) 181 drm_dp_dpcd_writeb(&intel_dp->aux, 182 DP_RECEIVER_ALPM_CONFIG, 183 DP_ALPM_ENABLE); 184 if (dev_priv->psr.link_standby) 185 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 186 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); 187 else 188 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 189 DP_PSR_ENABLE); 190 191 aux_ctl_reg = psr_aux_ctl_reg(dev_priv, port); 192 193 /* Setup AUX registers */ 194 for (i = 0; i < sizeof(aux_msg); i += 4) 195 I915_WRITE(psr_aux_data_reg(dev_priv, port, i >> 2), 196 intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); 197 198 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, 0, sizeof(aux_msg), 199 aux_clock_divider); 200 I915_WRITE(aux_ctl_reg, aux_ctl); 201 } 202 203 static void vlv_psr_enable_source(struct intel_dp *intel_dp, 204 const struct intel_crtc_state *crtc_state) 205 { 206 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 207 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 208 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 209 210 /* Transition from PSR_state 0 (disabled) to PSR_state 1 (inactive) */ 211 I915_WRITE(VLV_PSRCTL(crtc->pipe), 212 VLV_EDP_PSR_MODE_SW_TIMER | 213 VLV_EDP_PSR_SRC_TRANSMITTER_STATE | 214 VLV_EDP_PSR_ENABLE); 215 } 216 217 static void vlv_psr_activate(struct intel_dp *intel_dp) 218 { 219 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 220 struct drm_device *dev = dig_port->base.base.dev; 221 struct drm_i915_private *dev_priv = to_i915(dev); 222 struct drm_crtc *crtc = dig_port->base.base.crtc; 223 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; 224 225 /* 226 * Let's do the transition from PSR_state 1 (inactive) to 227 * PSR_state 2 (transition to active - static frame transmission). 228 * Then Hardware is responsible for the transition to 229 * PSR_state 3 (active - no Remote Frame Buffer (RFB) update). 230 */ 231 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | 232 VLV_EDP_PSR_ACTIVE_ENTRY); 233 } 234 235 static void hsw_activate_psr1(struct intel_dp *intel_dp) 236 { 237 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 238 struct drm_device *dev = dig_port->base.base.dev; 239 struct drm_i915_private *dev_priv = to_i915(dev); 240 241 uint32_t max_sleep_time = 0x1f; 242 /* 243 * Let's respect VBT in case VBT asks a higher idle_frame value. 244 * Let's use 6 as the minimum to cover all known cases including 245 * the off-by-one issue that HW has in some cases. Also there are 246 * cases where sink should be able to train 247 * with the 5 or 6 idle patterns. 248 */ 249 uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 250 uint32_t val = EDP_PSR_ENABLE; 251 252 val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; 253 val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; 254 255 if (IS_HASWELL(dev_priv)) 256 val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; 257 258 if (dev_priv->psr.link_standby) 259 val |= EDP_PSR_LINK_STANDBY; 260 261 if (dev_priv->vbt.psr.tp1_wakeup_time > 5) 262 val |= EDP_PSR_TP1_TIME_2500us; 263 else if (dev_priv->vbt.psr.tp1_wakeup_time > 1) 264 val |= EDP_PSR_TP1_TIME_500us; 265 else if (dev_priv->vbt.psr.tp1_wakeup_time > 0) 266 val |= EDP_PSR_TP1_TIME_100us; 267 else 268 val |= EDP_PSR_TP1_TIME_0us; 269 270 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) 271 val |= EDP_PSR_TP2_TP3_TIME_2500us; 272 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) 273 val |= EDP_PSR_TP2_TP3_TIME_500us; 274 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) 275 val |= EDP_PSR_TP2_TP3_TIME_100us; 276 else 277 val |= EDP_PSR_TP2_TP3_TIME_0us; 278 279 if (intel_dp_source_supports_hbr2(intel_dp) && 280 drm_dp_tps3_supported(intel_dp->dpcd)) 281 val |= EDP_PSR_TP1_TP3_SEL; 282 else 283 val |= EDP_PSR_TP1_TP2_SEL; 284 285 val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; 286 I915_WRITE(EDP_PSR_CTL, val); 287 } 288 289 static void hsw_activate_psr2(struct intel_dp *intel_dp) 290 { 291 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 292 struct drm_device *dev = dig_port->base.base.dev; 293 struct drm_i915_private *dev_priv = to_i915(dev); 294 /* 295 * Let's respect VBT in case VBT asks a higher idle_frame value. 296 * Let's use 6 as the minimum to cover all known cases including 297 * the off-by-one issue that HW has in some cases. Also there are 298 * cases where sink should be able to train 299 * with the 5 or 6 idle patterns. 300 */ 301 uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); 302 uint32_t val; 303 uint8_t sink_latency; 304 305 val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; 306 307 /* FIXME: selective update is probably totally broken because it doesn't 308 * mesh at all with our frontbuffer tracking. And the hw alone isn't 309 * good enough. */ 310 val |= EDP_PSR2_ENABLE | 311 EDP_SU_TRACK_ENABLE; 312 313 if (drm_dp_dpcd_readb(&intel_dp->aux, 314 DP_SYNCHRONIZATION_LATENCY_IN_SINK, 315 &sink_latency) == 1) { 316 sink_latency &= DP_MAX_RESYNC_FRAME_COUNT_MASK; 317 } else { 318 sink_latency = 0; 319 } 320 val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1); 321 322 if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) 323 val |= EDP_PSR2_TP2_TIME_2500; 324 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1) 325 val |= EDP_PSR2_TP2_TIME_500; 326 else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0) 327 val |= EDP_PSR2_TP2_TIME_100; 328 else 329 val |= EDP_PSR2_TP2_TIME_50; 330 331 I915_WRITE(EDP_PSR2_CTL, val); 332 } 333 334 static void hsw_psr_activate(struct intel_dp *intel_dp) 335 { 336 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 337 struct drm_device *dev = dig_port->base.base.dev; 338 struct drm_i915_private *dev_priv = to_i915(dev); 339 340 /* On HSW+ after we enable PSR on source it will activate it 341 * as soon as it match configure idle_frame count. So 342 * we just actually enable it here on activation time. 343 */ 344 345 /* psr1 and psr2 are mutually exclusive.*/ 346 if (dev_priv->psr.psr2_support) 347 hsw_activate_psr2(intel_dp); 348 else 349 hsw_activate_psr1(intel_dp); 350 } 351 352 void intel_psr_compute_config(struct intel_dp *intel_dp, 353 struct intel_crtc_state *crtc_state) 354 { 355 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 356 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 357 const struct drm_display_mode *adjusted_mode = 358 &crtc_state->base.adjusted_mode; 359 int psr_setup_time; 360 361 if (!HAS_PSR(dev_priv)) 362 return; 363 364 if (!is_edp_psr(intel_dp)) 365 return; 366 367 if (!i915_modparams.enable_psr) { 368 DRM_DEBUG_KMS("PSR disable by flag\n"); 369 return; 370 } 371 372 /* 373 * HSW spec explicitly says PSR is tied to port A. 374 * BDW+ platforms with DDI implementation of PSR have different 375 * PSR registers per transcoder and we only implement transcoder EDP 376 * ones. Since by Display design transcoder EDP is tied to port A 377 * we can safely escape based on the port A. 378 */ 379 if (HAS_DDI(dev_priv) && dig_port->port != PORT_A) { 380 DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); 381 return; 382 } 383 384 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 385 !dev_priv->psr.link_standby) { 386 DRM_ERROR("PSR condition failed: Link off requested but not supported on this platform\n"); 387 return; 388 } 389 390 if (IS_HASWELL(dev_priv) && 391 I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) & 392 S3D_ENABLE) { 393 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); 394 return; 395 } 396 397 if (IS_HASWELL(dev_priv) && 398 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 399 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); 400 return; 401 } 402 403 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); 404 if (psr_setup_time < 0) { 405 DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", 406 intel_dp->psr_dpcd[1]); 407 return; 408 } 409 410 if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > 411 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { 412 DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", 413 psr_setup_time); 414 return; 415 } 416 417 /* 418 * FIXME psr2_support is messed up. It's both computed 419 * dynamically during PSR enable, and extracted from sink 420 * caps during eDP detection. 421 */ 422 if (!dev_priv->psr.psr2_support) { 423 crtc_state->has_psr = true; 424 return; 425 } 426 427 /* PSR2 is restricted to work with panel resolutions upto 3200x2000 */ 428 if (adjusted_mode->crtc_hdisplay > 3200 || 429 adjusted_mode->crtc_vdisplay > 2000) { 430 DRM_DEBUG_KMS("PSR2 disabled, panel resolution too big\n"); 431 return; 432 } 433 434 /* 435 * FIXME:enable psr2 only for y-cordinate psr2 panels 436 * After gtc implementation , remove this restriction. 437 */ 438 if (!dev_priv->psr.y_cord_support) { 439 DRM_DEBUG_KMS("PSR2 disabled, panel does not support Y coordinate\n"); 440 return; 441 } 442 443 crtc_state->has_psr = true; 444 crtc_state->has_psr2 = true; 445 } 446 447 static void intel_psr_activate(struct intel_dp *intel_dp) 448 { 449 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 450 struct drm_device *dev = intel_dig_port->base.base.dev; 451 struct drm_i915_private *dev_priv = to_i915(dev); 452 453 if (dev_priv->psr.psr2_support) 454 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); 455 else 456 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); 457 WARN_ON(dev_priv->psr.active); 458 lockdep_assert_held(&dev_priv->psr.lock); 459 460 dev_priv->psr.activate(intel_dp); 461 dev_priv->psr.active = true; 462 } 463 464 static void hsw_psr_enable_source(struct intel_dp *intel_dp, 465 const struct intel_crtc_state *crtc_state) 466 { 467 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 468 struct drm_device *dev = dig_port->base.base.dev; 469 struct drm_i915_private *dev_priv = to_i915(dev); 470 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 471 u32 chicken; 472 473 if (dev_priv->psr.psr2_support) { 474 chicken = PSR2_VSC_ENABLE_PROG_HEADER; 475 if (dev_priv->psr.y_cord_support) 476 chicken |= PSR2_ADD_VERTICAL_LINE_COUNT; 477 I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken); 478 479 I915_WRITE(EDP_PSR_DEBUG_CTL, 480 EDP_PSR_DEBUG_MASK_MEMUP | 481 EDP_PSR_DEBUG_MASK_HPD | 482 EDP_PSR_DEBUG_MASK_LPSP | 483 EDP_PSR_DEBUG_MASK_MAX_SLEEP | 484 EDP_PSR_DEBUG_MASK_DISP_REG_WRITE); 485 } else { 486 /* 487 * Per Spec: Avoid continuous PSR exit by masking MEMUP 488 * and HPD. also mask LPSP to avoid dependency on other 489 * drivers that might block runtime_pm besides 490 * preventing other hw tracking issues now we can rely 491 * on frontbuffer tracking. 492 */ 493 I915_WRITE(EDP_PSR_DEBUG_CTL, 494 EDP_PSR_DEBUG_MASK_MEMUP | 495 EDP_PSR_DEBUG_MASK_HPD | 496 EDP_PSR_DEBUG_MASK_LPSP); 497 } 498 } 499 500 /** 501 * intel_psr_enable - Enable PSR 502 * @intel_dp: Intel DP 503 * @crtc_state: new CRTC state 504 * 505 * This function can only be called after the pipe is fully trained and enabled. 506 */ 507 void intel_psr_enable(struct intel_dp *intel_dp, 508 const struct intel_crtc_state *crtc_state) 509 { 510 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 511 struct drm_device *dev = intel_dig_port->base.base.dev; 512 struct drm_i915_private *dev_priv = to_i915(dev); 513 514 if (!crtc_state->has_psr) 515 return; 516 517 WARN_ON(dev_priv->drrs.dp); 518 mutex_lock(&dev_priv->psr.lock); 519 if (dev_priv->psr.enabled) { 520 DRM_DEBUG_KMS("PSR already in use\n"); 521 goto unlock; 522 } 523 524 dev_priv->psr.psr2_support = crtc_state->has_psr2; 525 dev_priv->psr.source_ok = true; 526 527 dev_priv->psr.busy_frontbuffer_bits = 0; 528 529 dev_priv->psr.setup_vsc(intel_dp, crtc_state); 530 dev_priv->psr.enable_sink(intel_dp); 531 dev_priv->psr.enable_source(intel_dp, crtc_state); 532 dev_priv->psr.enabled = intel_dp; 533 534 if (INTEL_GEN(dev_priv) >= 9) { 535 intel_psr_activate(intel_dp); 536 } else { 537 /* 538 * FIXME: Activation should happen immediately since this 539 * function is just called after pipe is fully trained and 540 * enabled. 541 * However on some platforms we face issues when first 542 * activation follows a modeset so quickly. 543 * - On VLV/CHV we get bank screen on first activation 544 * - On HSW/BDW we get a recoverable frozen screen until 545 * next exit-activate sequence. 546 */ 547 schedule_delayed_work(&dev_priv->psr.work, 548 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 549 } 550 551 unlock: 552 mutex_unlock(&dev_priv->psr.lock); 553 } 554 555 static void vlv_psr_disable(struct intel_dp *intel_dp, 556 const struct intel_crtc_state *old_crtc_state) 557 { 558 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 559 struct drm_device *dev = intel_dig_port->base.base.dev; 560 struct drm_i915_private *dev_priv = to_i915(dev); 561 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 562 uint32_t val; 563 564 if (dev_priv->psr.active) { 565 /* Put VLV PSR back to PSR_state 0 (disabled). */ 566 if (intel_wait_for_register(dev_priv, 567 VLV_PSRSTAT(crtc->pipe), 568 VLV_EDP_PSR_IN_TRANS, 569 0, 570 1)) 571 WARN(1, "PSR transition took longer than expected\n"); 572 573 val = I915_READ(VLV_PSRCTL(crtc->pipe)); 574 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; 575 val &= ~VLV_EDP_PSR_ENABLE; 576 val &= ~VLV_EDP_PSR_MODE_MASK; 577 I915_WRITE(VLV_PSRCTL(crtc->pipe), val); 578 579 dev_priv->psr.active = false; 580 } else { 581 WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe)); 582 } 583 } 584 585 static void hsw_psr_disable(struct intel_dp *intel_dp, 586 const struct intel_crtc_state *old_crtc_state) 587 { 588 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 589 struct drm_device *dev = intel_dig_port->base.base.dev; 590 struct drm_i915_private *dev_priv = to_i915(dev); 591 592 if (dev_priv->psr.active) { 593 i915_reg_t psr_status; 594 u32 psr_status_mask; 595 596 if (dev_priv->psr.aux_frame_sync) 597 drm_dp_dpcd_writeb(&intel_dp->aux, 598 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, 599 0); 600 601 if (dev_priv->psr.psr2_support) { 602 psr_status = EDP_PSR2_STATUS_CTL; 603 psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; 604 605 I915_WRITE(EDP_PSR2_CTL, 606 I915_READ(EDP_PSR2_CTL) & 607 ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE)); 608 609 } else { 610 psr_status = EDP_PSR_STATUS_CTL; 611 psr_status_mask = EDP_PSR_STATUS_STATE_MASK; 612 613 I915_WRITE(EDP_PSR_CTL, 614 I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE); 615 } 616 617 /* Wait till PSR is idle */ 618 if (intel_wait_for_register(dev_priv, 619 psr_status, psr_status_mask, 0, 620 2000)) 621 DRM_ERROR("Timed out waiting for PSR Idle State\n"); 622 623 dev_priv->psr.active = false; 624 } else { 625 if (dev_priv->psr.psr2_support) 626 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); 627 else 628 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); 629 } 630 } 631 632 /** 633 * intel_psr_disable - Disable PSR 634 * @intel_dp: Intel DP 635 * @old_crtc_state: old CRTC state 636 * 637 * This function needs to be called before disabling pipe. 638 */ 639 void intel_psr_disable(struct intel_dp *intel_dp, 640 const struct intel_crtc_state *old_crtc_state) 641 { 642 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 643 struct drm_device *dev = intel_dig_port->base.base.dev; 644 struct drm_i915_private *dev_priv = to_i915(dev); 645 646 if (!old_crtc_state->has_psr) 647 return; 648 649 mutex_lock(&dev_priv->psr.lock); 650 if (!dev_priv->psr.enabled) { 651 mutex_unlock(&dev_priv->psr.lock); 652 return; 653 } 654 655 dev_priv->psr.disable_source(intel_dp, old_crtc_state); 656 657 /* Disable PSR on Sink */ 658 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); 659 660 dev_priv->psr.enabled = NULL; 661 mutex_unlock(&dev_priv->psr.lock); 662 663 cancel_delayed_work_sync(&dev_priv->psr.work); 664 } 665 666 static void intel_psr_work(struct work_struct *work) 667 { 668 struct drm_i915_private *dev_priv = 669 container_of(work, typeof(*dev_priv), psr.work.work); 670 struct intel_dp *intel_dp = dev_priv->psr.enabled; 671 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 672 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; 673 674 /* We have to make sure PSR is ready for re-enable 675 * otherwise it keeps disabled until next full enable/disable cycle. 676 * PSR might take some time to get fully disabled 677 * and be ready for re-enable. 678 */ 679 if (HAS_DDI(dev_priv)) { 680 if (dev_priv->psr.psr2_support) { 681 if (intel_wait_for_register(dev_priv, 682 EDP_PSR2_STATUS_CTL, 683 EDP_PSR2_STATUS_STATE_MASK, 684 0, 685 50)) { 686 DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n"); 687 return; 688 } 689 } else { 690 if (intel_wait_for_register(dev_priv, 691 EDP_PSR_STATUS_CTL, 692 EDP_PSR_STATUS_STATE_MASK, 693 0, 694 50)) { 695 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); 696 return; 697 } 698 } 699 } else { 700 if (intel_wait_for_register(dev_priv, 701 VLV_PSRSTAT(pipe), 702 VLV_EDP_PSR_IN_TRANS, 703 0, 704 1)) { 705 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); 706 return; 707 } 708 } 709 mutex_lock(&dev_priv->psr.lock); 710 intel_dp = dev_priv->psr.enabled; 711 712 if (!intel_dp) 713 goto unlock; 714 715 /* 716 * The delayed work can race with an invalidate hence we need to 717 * recheck. Since psr_flush first clears this and then reschedules we 718 * won't ever miss a flush when bailing out here. 719 */ 720 if (dev_priv->psr.busy_frontbuffer_bits) 721 goto unlock; 722 723 intel_psr_activate(intel_dp); 724 unlock: 725 mutex_unlock(&dev_priv->psr.lock); 726 } 727 728 static void intel_psr_exit(struct drm_i915_private *dev_priv) 729 { 730 struct intel_dp *intel_dp = dev_priv->psr.enabled; 731 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 732 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; 733 u32 val; 734 735 if (!dev_priv->psr.active) 736 return; 737 738 if (HAS_DDI(dev_priv)) { 739 if (dev_priv->psr.aux_frame_sync) 740 drm_dp_dpcd_writeb(&intel_dp->aux, 741 DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF, 742 0); 743 if (dev_priv->psr.psr2_support) { 744 val = I915_READ(EDP_PSR2_CTL); 745 WARN_ON(!(val & EDP_PSR2_ENABLE)); 746 I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); 747 } else { 748 val = I915_READ(EDP_PSR_CTL); 749 WARN_ON(!(val & EDP_PSR_ENABLE)); 750 I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE); 751 } 752 } else { 753 val = I915_READ(VLV_PSRCTL(pipe)); 754 755 /* 756 * Here we do the transition drirectly from 757 * PSR_state 3 (active - no Remote Frame Buffer (RFB) update) to 758 * PSR_state 5 (exit). 759 * PSR State 4 (active with single frame update) can be skipped. 760 * On PSR_state 5 (exit) Hardware is responsible to transition 761 * back to PSR_state 1 (inactive). 762 * Now we are at Same state after vlv_psr_enable_source. 763 */ 764 val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; 765 I915_WRITE(VLV_PSRCTL(pipe), val); 766 767 /* 768 * Send AUX wake up - Spec says after transitioning to PSR 769 * active we have to send AUX wake up by writing 01h in DPCD 770 * 600h of sink device. 771 * XXX: This might slow down the transition, but without this 772 * HW doesn't complete the transition to PSR_state 1 and we 773 * never get the screen updated. 774 */ 775 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 776 DP_SET_POWER_D0); 777 } 778 779 dev_priv->psr.active = false; 780 } 781 782 /** 783 * intel_psr_single_frame_update - Single Frame Update 784 * @dev_priv: i915 device 785 * @frontbuffer_bits: frontbuffer plane tracking bits 786 * 787 * Some platforms support a single frame update feature that is used to 788 * send and update only one frame on Remote Frame Buffer. 789 * So far it is only implemented for Valleyview and Cherryview because 790 * hardware requires this to be done before a page flip. 791 */ 792 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, 793 unsigned frontbuffer_bits) 794 { 795 struct drm_crtc *crtc; 796 enum i915_pipe pipe; 797 u32 val; 798 799 if (!HAS_PSR(dev_priv)) 800 return; 801 802 /* 803 * Single frame update is already supported on BDW+ but it requires 804 * many W/A and it isn't really needed. 805 */ 806 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 807 return; 808 809 mutex_lock(&dev_priv->psr.lock); 810 if (!dev_priv->psr.enabled) { 811 mutex_unlock(&dev_priv->psr.lock); 812 return; 813 } 814 815 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 816 pipe = to_intel_crtc(crtc)->pipe; 817 818 if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) { 819 val = I915_READ(VLV_PSRCTL(pipe)); 820 821 /* 822 * We need to set this bit before writing registers for a flip. 823 * This bit will be self-clear when it gets to the PSR active state. 824 */ 825 I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE); 826 } 827 mutex_unlock(&dev_priv->psr.lock); 828 } 829 830 /** 831 * intel_psr_invalidate - Invalidade PSR 832 * @dev_priv: i915 device 833 * @frontbuffer_bits: frontbuffer plane tracking bits 834 * 835 * Since the hardware frontbuffer tracking has gaps we need to integrate 836 * with the software frontbuffer tracking. This function gets called every 837 * time frontbuffer rendering starts and a buffer gets dirtied. PSR must be 838 * disabled if the frontbuffer mask contains a buffer relevant to PSR. 839 * 840 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits." 841 */ 842 void intel_psr_invalidate(struct drm_i915_private *dev_priv, 843 unsigned frontbuffer_bits) 844 { 845 struct drm_crtc *crtc; 846 enum i915_pipe pipe; 847 848 if (!HAS_PSR(dev_priv)) 849 return; 850 851 mutex_lock(&dev_priv->psr.lock); 852 if (!dev_priv->psr.enabled) { 853 mutex_unlock(&dev_priv->psr.lock); 854 return; 855 } 856 857 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 858 pipe = to_intel_crtc(crtc)->pipe; 859 860 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 861 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; 862 863 if (frontbuffer_bits) 864 intel_psr_exit(dev_priv); 865 866 mutex_unlock(&dev_priv->psr.lock); 867 } 868 869 /** 870 * intel_psr_flush - Flush PSR 871 * @dev_priv: i915 device 872 * @frontbuffer_bits: frontbuffer plane tracking bits 873 * @origin: which operation caused the flush 874 * 875 * Since the hardware frontbuffer tracking has gaps we need to integrate 876 * with the software frontbuffer tracking. This function gets called every 877 * time frontbuffer rendering has completed and flushed out to memory. PSR 878 * can be enabled again if no other frontbuffer relevant to PSR is dirty. 879 * 880 * Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits. 881 */ 882 void intel_psr_flush(struct drm_i915_private *dev_priv, 883 unsigned frontbuffer_bits, enum fb_op_origin origin) 884 { 885 struct drm_crtc *crtc; 886 enum i915_pipe pipe; 887 888 if (!HAS_PSR(dev_priv)) 889 return; 890 891 mutex_lock(&dev_priv->psr.lock); 892 if (!dev_priv->psr.enabled) { 893 mutex_unlock(&dev_priv->psr.lock); 894 return; 895 } 896 897 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; 898 pipe = to_intel_crtc(crtc)->pipe; 899 900 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 901 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; 902 903 /* By definition flush = invalidate + flush */ 904 if (frontbuffer_bits) 905 intel_psr_exit(dev_priv); 906 907 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) 908 if (!work_busy(&dev_priv->psr.work.work)) 909 schedule_delayed_work(&dev_priv->psr.work, 910 msecs_to_jiffies(100)); 911 mutex_unlock(&dev_priv->psr.lock); 912 } 913 914 /** 915 * intel_psr_init - Init basic PSR work and mutex. 916 * @dev_priv: i915 device private 917 * 918 * This function is called only once at driver load to initialize basic 919 * PSR stuff. 920 */ 921 void intel_psr_init(struct drm_i915_private *dev_priv) 922 { 923 if (!HAS_PSR(dev_priv)) 924 return; 925 926 dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ? 927 HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE; 928 929 /* Per platform default: all disabled. */ 930 if (i915_modparams.enable_psr == -1) 931 i915_modparams.enable_psr = 0; 932 933 /* Set link_standby x link_off defaults */ 934 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 935 /* HSW and BDW require workarounds that we don't implement. */ 936 dev_priv->psr.link_standby = false; 937 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 938 /* On VLV and CHV only standby mode is supported. */ 939 dev_priv->psr.link_standby = true; 940 else 941 /* For new platforms let's respect VBT back again */ 942 dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; 943 944 /* Override link_standby x link_off defaults */ 945 if (i915_modparams.enable_psr == 2 && !dev_priv->psr.link_standby) { 946 DRM_DEBUG_KMS("PSR: Forcing link standby\n"); 947 dev_priv->psr.link_standby = true; 948 } 949 if (i915_modparams.enable_psr == 3 && dev_priv->psr.link_standby) { 950 DRM_DEBUG_KMS("PSR: Forcing main link off\n"); 951 dev_priv->psr.link_standby = false; 952 } 953 954 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); 955 lockinit(&dev_priv->psr.lock, "i915dpl", 0, LK_CANRECURSE); 956 957 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 958 dev_priv->psr.enable_source = vlv_psr_enable_source; 959 dev_priv->psr.disable_source = vlv_psr_disable; 960 dev_priv->psr.enable_sink = vlv_psr_enable_sink; 961 dev_priv->psr.activate = vlv_psr_activate; 962 dev_priv->psr.setup_vsc = vlv_psr_setup_vsc; 963 } else { 964 dev_priv->psr.enable_source = hsw_psr_enable_source; 965 dev_priv->psr.disable_source = hsw_psr_disable; 966 dev_priv->psr.enable_sink = hsw_psr_enable_sink; 967 dev_priv->psr.activate = hsw_psr_activate; 968 dev_priv->psr.setup_vsc = hsw_psr_setup_vsc; 969 } 970 } 971