1 /* 2 * $FreeBSD: src/sys/dev/drm2/i915/intel_ringbuffer.h,v 1.1 2012/05/22 11:07:44 kib Exp $ 3 */ 4 5 #ifndef _INTEL_RINGBUFFER_H_ 6 #define _INTEL_RINGBUFFER_H_ 7 8 struct intel_hw_status_page { 9 uint32_t *page_addr; 10 unsigned int gfx_addr; 11 struct drm_i915_gem_object *obj; 12 }; 13 14 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) 15 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) 16 17 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) 18 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) 19 20 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) 21 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) 22 23 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) 24 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) 25 26 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) 27 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) 28 29 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base)) 30 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) 31 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) 32 33 struct intel_ring_buffer { 34 const char *name; 35 enum intel_ring_id { 36 RCS = 0x0, 37 VCS, 38 BCS, 39 } id; 40 #define I915_NUM_RINGS 3 41 uint32_t mmio_base; 42 void *virtual_start; 43 struct drm_device *dev; 44 struct drm_i915_gem_object *obj; 45 46 uint32_t head; 47 uint32_t tail; 48 int space; 49 int size; 50 int effective_size; 51 struct intel_hw_status_page status_page; 52 53 /** We track the position of the requests in the ring buffer, and 54 * when each is retired we increment last_retired_head as the GPU 55 * must have finished processing the request and so we know we 56 * can advance the ringbuffer up to that position. 57 * 58 * last_retired_head is set to -1 after the value is consumed so 59 * we can detect new retirements. 60 */ 61 u32 last_retired_head; 62 63 struct lock irq_lock; 64 uint32_t irq_refcount; 65 uint32_t irq_mask; 66 uint32_t irq_seqno; /* last seq seem at irq time */ 67 uint32_t trace_irq_seqno; 68 uint32_t waiting_seqno; 69 uint32_t sync_seqno[I915_NUM_RINGS-1]; 70 bool (*irq_get)(struct intel_ring_buffer *ring); 71 void (*irq_put)(struct intel_ring_buffer *ring); 72 73 int (*init)(struct intel_ring_buffer *ring); 74 75 void (*write_tail)(struct intel_ring_buffer *ring, 76 uint32_t value); 77 int (*flush)(struct intel_ring_buffer *ring, 78 uint32_t invalidate_domains, 79 uint32_t flush_domains); 80 int (*add_request)(struct intel_ring_buffer *ring, 81 uint32_t *seqno); 82 uint32_t (*get_seqno)(struct intel_ring_buffer *ring); 83 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, 84 uint32_t offset, uint32_t length); 85 void (*cleanup)(struct intel_ring_buffer *ring); 86 int (*sync_to)(struct intel_ring_buffer *ring, 87 struct intel_ring_buffer *to, 88 u32 seqno); 89 90 u32 semaphore_register[3]; /*our mbox written by others */ 91 u32 signal_mbox[2]; /* mboxes this ring signals to */ 92 93 /** 94 * List of objects currently involved in rendering from the 95 * ringbuffer. 96 * 97 * Includes buffers having the contents of their GPU caches 98 * flushed, not necessarily primitives. last_rendering_seqno 99 * represents when the rendering involved will be completed. 100 * 101 * A reference is held on the buffer while on this list. 102 */ 103 struct list_head active_list; 104 105 /** 106 * List of breadcrumbs associated with GPU requests currently 107 * outstanding. 108 */ 109 struct list_head request_list; 110 111 /** 112 * List of objects currently pending a GPU write flush. 113 * 114 * All elements on this list will belong to either the 115 * active_list or flushing_list, last_rendering_seqno can 116 * be used to differentiate between the two elements. 117 */ 118 struct list_head gpu_write_list; 119 120 /** 121 * Do we have some not yet emitted requests outstanding? 122 */ 123 uint32_t outstanding_lazy_request; 124 125 drm_local_map_t map; 126 127 void *private; 128 }; 129 130 static inline unsigned 131 intel_ring_flag(struct intel_ring_buffer *ring) 132 { 133 return 1 << ring->id; 134 } 135 136 static inline uint32_t 137 intel_ring_sync_index(struct intel_ring_buffer *ring, 138 struct intel_ring_buffer *other) 139 { 140 int idx; 141 142 /* 143 * cs -> 0 = vcs, 1 = bcs 144 * vcs -> 0 = bcs, 1 = cs, 145 * bcs -> 0 = cs, 1 = vcs. 146 */ 147 148 idx = (other - ring) - 1; 149 if (idx < 0) 150 idx += I915_NUM_RINGS; 151 152 return idx; 153 } 154 155 static inline uint32_t 156 intel_read_status_page(struct intel_ring_buffer *ring, int reg) 157 { 158 159 return (atomic_load_acq_32(ring->status_page.page_addr + reg)); 160 } 161 162 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); 163 164 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); 165 static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring) 166 { 167 168 return (intel_wait_ring_buffer(ring, ring->size - 8)); 169 } 170 171 int intel_ring_begin(struct intel_ring_buffer *ring, int n); 172 173 static inline void intel_ring_emit(struct intel_ring_buffer *ring, 174 uint32_t data) 175 { 176 *(volatile uint32_t *)((char *)ring->virtual_start + 177 ring->tail) = data; 178 ring->tail += 4; 179 } 180 181 void intel_ring_advance(struct intel_ring_buffer *ring); 182 183 uint32_t intel_ring_get_seqno(struct intel_ring_buffer *ring); 184 185 int intel_init_render_ring_buffer(struct drm_device *dev); 186 int intel_init_bsd_ring_buffer(struct drm_device *dev); 187 int intel_init_blt_ring_buffer(struct drm_device *dev); 188 189 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); 190 void intel_ring_setup_status_page(struct intel_ring_buffer *ring); 191 192 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) 193 { 194 return ring->tail; 195 } 196 197 void i915_trace_irq_get(struct intel_ring_buffer *ring, uint32_t seqno); 198 199 /* DRI warts */ 200 int intel_render_ring_init_dri(struct drm_device *dev, uint64_t start, 201 uint32_t size); 202 203 #endif /* _INTEL_RINGBUFFER_H_ */ 204