1 #ifndef _INTEL_RINGBUFFER_H_ 2 #define _INTEL_RINGBUFFER_H_ 3 4 #include <linux/io.h> 5 6 /* 7 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" 8 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" 9 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" 10 * 11 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same 12 * cacheline, the Head Pointer must not be greater than the Tail 13 * Pointer." 14 */ 15 #define I915_RING_FREE_SPACE 64 16 17 struct intel_hw_status_page { 18 u32 *page_addr; 19 unsigned int gfx_addr; 20 struct drm_i915_gem_object *obj; 21 }; 22 23 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) 24 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) 25 26 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) 27 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) 28 29 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) 30 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) 31 32 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) 33 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) 34 35 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) 36 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) 37 38 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base)) 39 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base)) 40 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base)) 41 42 struct intel_ring_buffer { 43 const char *name; 44 enum intel_ring_id { 45 RCS = 0x0, 46 VCS, 47 BCS, 48 } id; 49 #define I915_NUM_RINGS 3 50 u32 mmio_base; 51 void __iomem *virtual_start; 52 struct drm_device *dev; 53 struct drm_i915_gem_object *obj; 54 55 u32 head; 56 u32 tail; 57 int space; 58 int size; 59 int effective_size; 60 struct intel_hw_status_page status_page; 61 62 /** We track the position of the requests in the ring buffer, and 63 * when each is retired we increment last_retired_head as the GPU 64 * must have finished processing the request and so we know we 65 * can advance the ringbuffer up to that position. 66 * 67 * last_retired_head is set to -1 after the value is consumed so 68 * we can detect new retirements. 69 */ 70 u32 last_retired_head; 71 72 u32 irq_refcount; /* protected by dev_priv->irq_lock */ 73 u32 irq_enable_mask; /* bitmask to enable ring interrupt */ 74 u32 trace_irq_seqno; 75 u32 sync_seqno[I915_NUM_RINGS-1]; 76 bool __must_check (*irq_get)(struct intel_ring_buffer *ring); 77 void (*irq_put)(struct intel_ring_buffer *ring); 78 79 int (*init)(struct intel_ring_buffer *ring); 80 81 void (*write_tail)(struct intel_ring_buffer *ring, 82 u32 value); 83 int __must_check (*flush)(struct intel_ring_buffer *ring, 84 u32 invalidate_domains, 85 u32 flush_domains); 86 int (*add_request)(struct intel_ring_buffer *ring); 87 /* Some chipsets are not quite as coherent as advertised and need 88 * an expensive kick to force a true read of the up-to-date seqno. 89 * However, the up-to-date seqno is not always required and the last 90 * seen value is good enough. Note that the seqno will always be 91 * monotonic, even if not coherent. 92 */ 93 u32 (*get_seqno)(struct intel_ring_buffer *ring, 94 bool lazy_coherency); 95 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, 96 u32 offset, u32 length, 97 unsigned flags); 98 #define I915_DISPATCH_SECURE 0x1 99 #define I915_DISPATCH_PINNED 0x2 100 void (*cleanup)(struct intel_ring_buffer *ring); 101 int (*sync_to)(struct intel_ring_buffer *ring, 102 struct intel_ring_buffer *to, 103 u32 seqno); 104 105 u32 semaphore_register[3]; /*our mbox written by others */ 106 u32 signal_mbox[2]; /* mboxes this ring signals to */ 107 /** 108 * List of objects currently involved in rendering from the 109 * ringbuffer. 110 * 111 * Includes buffers having the contents of their GPU caches 112 * flushed, not necessarily primitives. last_rendering_seqno 113 * represents when the rendering involved will be completed. 114 * 115 * A reference is held on the buffer while on this list. 116 */ 117 struct list_head active_list; 118 119 /** 120 * List of breadcrumbs associated with GPU requests currently 121 * outstanding. 122 */ 123 struct list_head request_list; 124 125 struct list_head gpu_write_list; 126 127 /** 128 * Do we have some not yet emitted requests outstanding? 129 */ 130 u32 outstanding_lazy_request; 131 bool gpu_caches_dirty; 132 133 wait_queue_head_t irq_queue; 134 135 /** 136 * Do an explicit TLB flush before MI_SET_CONTEXT 137 */ 138 bool itlb_before_ctx_switch; 139 struct i915_hw_context *default_context; 140 struct drm_i915_gem_object *last_context_obj; 141 142 void *private; 143 }; 144 145 static inline bool 146 intel_ring_initialized(struct intel_ring_buffer *ring) 147 { 148 return ring->obj != NULL; 149 } 150 151 static inline unsigned 152 intel_ring_flag(struct intel_ring_buffer *ring) 153 { 154 return 1 << ring->id; 155 } 156 157 static inline u32 158 intel_ring_sync_index(struct intel_ring_buffer *ring, 159 struct intel_ring_buffer *other) 160 { 161 int idx; 162 163 /* 164 * cs -> 0 = vcs, 1 = bcs 165 * vcs -> 0 = bcs, 1 = cs, 166 * bcs -> 0 = cs, 1 = vcs. 167 */ 168 169 idx = (other - ring) - 1; 170 if (idx < 0) 171 idx += I915_NUM_RINGS; 172 173 return idx; 174 } 175 176 static inline u32 177 intel_read_status_page(struct intel_ring_buffer *ring, 178 int reg) 179 { 180 /* Ensure that the compiler doesn't optimize away the load. */ 181 cpu_ccfence(); 182 return ring->status_page.page_addr[reg]; 183 } 184 185 /** 186 * Reads a dword out of the status page, which is written to from the command 187 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 188 * MI_STORE_DATA_IMM. 189 * 190 * The following dwords have a reserved meaning: 191 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 192 * 0x04: ring 0 head pointer 193 * 0x05: ring 1 head pointer (915-class) 194 * 0x06: ring 2 head pointer (915-class) 195 * 0x10-0x1b: Context status DWords (GM45) 196 * 0x1f: Last written status offset. (GM45) 197 * 198 * The area from dword 0x20 to 0x3ff is available for driver usage. 199 */ 200 #define I915_GEM_HWS_INDEX 0x20 201 #define I915_GEM_HWS_SCRATCH_INDEX 0x30 202 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) 203 204 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); 205 206 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); 207 static inline void intel_ring_emit(struct intel_ring_buffer *ring, 208 u32 data) 209 { 210 iowrite32(data, ring->virtual_start + ring->tail); 211 ring->tail += 4; 212 } 213 void intel_ring_advance(struct intel_ring_buffer *ring); 214 int __must_check intel_ring_idle(struct intel_ring_buffer *ring); 215 216 int intel_ring_flush_all_caches(struct intel_ring_buffer *ring); 217 int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring); 218 219 int intel_init_render_ring_buffer(struct drm_device *dev); 220 int intel_init_bsd_ring_buffer(struct drm_device *dev); 221 int intel_init_blt_ring_buffer(struct drm_device *dev); 222 223 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); 224 void intel_ring_setup_status_page(struct intel_ring_buffer *ring); 225 226 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) 227 { 228 return ring->tail; 229 } 230 231 static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring) 232 { 233 BUG_ON(ring->outstanding_lazy_request == 0); 234 return ring->outstanding_lazy_request; 235 } 236 237 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) 238 { 239 if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) 240 ring->trace_irq_seqno = seqno; 241 } 242 243 /* DRI warts */ 244 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); 245 246 #endif /* _INTEL_RINGBUFFER_H_ */ 247