1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 53 for (i = 0; \ 54 i < (power_domains)->power_well_count && \ 55 ((power_well) = &(power_domains)->power_wells[i]); \ 56 i++) \ 57 for_each_if ((power_well)->domains & (domain_mask)) 58 59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 60 for (i = (power_domains)->power_well_count - 1; \ 61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 62 i--) \ 63 for_each_if ((power_well)->domains & (domain_mask)) 64 65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 66 int power_well_id); 67 68 static struct i915_power_well * 69 lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id); 70 71 const char * 72 intel_display_power_domain_str(enum intel_display_power_domain domain) 73 { 74 switch (domain) { 75 case POWER_DOMAIN_PIPE_A: 76 return "PIPE_A"; 77 case POWER_DOMAIN_PIPE_B: 78 return "PIPE_B"; 79 case POWER_DOMAIN_PIPE_C: 80 return "PIPE_C"; 81 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 82 return "PIPE_A_PANEL_FITTER"; 83 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 84 return "PIPE_B_PANEL_FITTER"; 85 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 86 return "PIPE_C_PANEL_FITTER"; 87 case POWER_DOMAIN_TRANSCODER_A: 88 return "TRANSCODER_A"; 89 case POWER_DOMAIN_TRANSCODER_B: 90 return "TRANSCODER_B"; 91 case POWER_DOMAIN_TRANSCODER_C: 92 return "TRANSCODER_C"; 93 case POWER_DOMAIN_TRANSCODER_EDP: 94 return "TRANSCODER_EDP"; 95 case POWER_DOMAIN_TRANSCODER_DSI_A: 96 return "TRANSCODER_DSI_A"; 97 case POWER_DOMAIN_TRANSCODER_DSI_C: 98 return "TRANSCODER_DSI_C"; 99 case POWER_DOMAIN_PORT_DDI_A_LANES: 100 return "PORT_DDI_A_LANES"; 101 case POWER_DOMAIN_PORT_DDI_B_LANES: 102 return "PORT_DDI_B_LANES"; 103 case POWER_DOMAIN_PORT_DDI_C_LANES: 104 return "PORT_DDI_C_LANES"; 105 case POWER_DOMAIN_PORT_DDI_D_LANES: 106 return "PORT_DDI_D_LANES"; 107 case POWER_DOMAIN_PORT_DDI_E_LANES: 108 return "PORT_DDI_E_LANES"; 109 case POWER_DOMAIN_PORT_DSI: 110 return "PORT_DSI"; 111 case POWER_DOMAIN_PORT_CRT: 112 return "PORT_CRT"; 113 case POWER_DOMAIN_PORT_OTHER: 114 return "PORT_OTHER"; 115 case POWER_DOMAIN_VGA: 116 return "VGA"; 117 case POWER_DOMAIN_AUDIO: 118 return "AUDIO"; 119 case POWER_DOMAIN_PLLS: 120 return "PLLS"; 121 case POWER_DOMAIN_AUX_A: 122 return "AUX_A"; 123 case POWER_DOMAIN_AUX_B: 124 return "AUX_B"; 125 case POWER_DOMAIN_AUX_C: 126 return "AUX_C"; 127 case POWER_DOMAIN_AUX_D: 128 return "AUX_D"; 129 case POWER_DOMAIN_GMBUS: 130 return "GMBUS"; 131 case POWER_DOMAIN_INIT: 132 return "INIT"; 133 case POWER_DOMAIN_MODESET: 134 return "MODESET"; 135 default: 136 MISSING_CASE(domain); 137 return "?"; 138 } 139 } 140 141 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 142 struct i915_power_well *power_well) 143 { 144 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 145 power_well->ops->enable(dev_priv, power_well); 146 power_well->hw_enabled = true; 147 } 148 149 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 150 struct i915_power_well *power_well) 151 { 152 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 153 power_well->hw_enabled = false; 154 power_well->ops->disable(dev_priv, power_well); 155 } 156 157 static void intel_power_well_get(struct drm_i915_private *dev_priv, 158 struct i915_power_well *power_well) 159 { 160 if (!power_well->count++) 161 intel_power_well_enable(dev_priv, power_well); 162 } 163 164 static void intel_power_well_put(struct drm_i915_private *dev_priv, 165 struct i915_power_well *power_well) 166 { 167 WARN(!power_well->count, "Use count on power well %s is already zero", 168 power_well->name); 169 170 if (!--power_well->count) 171 intel_power_well_disable(dev_priv, power_well); 172 } 173 174 /* 175 * We should only use the power well if we explicitly asked the hardware to 176 * enable it, so check if it's enabled and also check if we've requested it to 177 * be enabled. 178 */ 179 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 180 struct i915_power_well *power_well) 181 { 182 return I915_READ(HSW_PWR_WELL_DRIVER) == 183 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 184 } 185 186 /** 187 * __intel_display_power_is_enabled - unlocked check for a power domain 188 * @dev_priv: i915 device instance 189 * @domain: power domain to check 190 * 191 * This is the unlocked version of intel_display_power_is_enabled() and should 192 * only be used from error capture and recovery code where deadlocks are 193 * possible. 194 * 195 * Returns: 196 * True when the power domain is enabled, false otherwise. 197 */ 198 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 199 enum intel_display_power_domain domain) 200 { 201 struct i915_power_domains *power_domains; 202 struct i915_power_well *power_well; 203 bool is_enabled; 204 int i; 205 206 if (dev_priv->pm.suspended) 207 return false; 208 209 power_domains = &dev_priv->power_domains; 210 211 is_enabled = true; 212 213 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 214 if (power_well->always_on) 215 continue; 216 217 if (!power_well->hw_enabled) { 218 is_enabled = false; 219 break; 220 } 221 } 222 223 return is_enabled; 224 } 225 226 /** 227 * intel_display_power_is_enabled - check for a power domain 228 * @dev_priv: i915 device instance 229 * @domain: power domain to check 230 * 231 * This function can be used to check the hw power domain state. It is mostly 232 * used in hardware state readout functions. Everywhere else code should rely 233 * upon explicit power domain reference counting to ensure that the hardware 234 * block is powered up before accessing it. 235 * 236 * Callers must hold the relevant modesetting locks to ensure that concurrent 237 * threads can't disable the power well while the caller tries to read a few 238 * registers. 239 * 240 * Returns: 241 * True when the power domain is enabled, false otherwise. 242 */ 243 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 244 enum intel_display_power_domain domain) 245 { 246 struct i915_power_domains *power_domains; 247 bool ret; 248 249 power_domains = &dev_priv->power_domains; 250 251 mutex_lock(&power_domains->lock); 252 ret = __intel_display_power_is_enabled(dev_priv, domain); 253 mutex_unlock(&power_domains->lock); 254 255 return ret; 256 } 257 258 /** 259 * intel_display_set_init_power - set the initial power domain state 260 * @dev_priv: i915 device instance 261 * @enable: whether to enable or disable the initial power domain state 262 * 263 * For simplicity our driver load/unload and system suspend/resume code assumes 264 * that all power domains are always enabled. This functions controls the state 265 * of this little hack. While the initial power domain state is enabled runtime 266 * pm is effectively disabled. 267 */ 268 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 269 bool enable) 270 { 271 if (dev_priv->power_domains.init_power_on == enable) 272 return; 273 274 if (enable) 275 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 276 else 277 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 278 279 dev_priv->power_domains.init_power_on = enable; 280 } 281 282 /* 283 * Starting with Haswell, we have a "Power Down Well" that can be turned off 284 * when not needed anymore. We have 4 registers that can request the power well 285 * to be enabled, and it will only be disabled if none of the registers is 286 * requesting it to be enabled. 287 */ 288 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 289 { 290 struct drm_device *dev = &dev_priv->drm; 291 292 /* 293 * After we re-enable the power well, if we touch VGA register 0x3d5 294 * we'll get unclaimed register interrupts. This stops after we write 295 * anything to the VGA MSR register. The vgacon module uses this 296 * register all the time, so if we unbind our driver and, as a 297 * consequence, bind vgacon, we'll get stuck in an infinite loop at 298 * console_unlock(). So make here we touch the VGA MSR register, making 299 * sure vgacon can keep working normally without triggering interrupts 300 * and error messages. 301 */ 302 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 303 #if 0 304 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 305 #endif 306 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 307 308 if (IS_BROADWELL(dev)) 309 gen8_irq_power_well_post_enable(dev_priv, 310 1 << PIPE_C | 1 << PIPE_B); 311 } 312 313 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv) 314 { 315 if (IS_BROADWELL(dev_priv)) 316 gen8_irq_power_well_pre_disable(dev_priv, 317 1 << PIPE_C | 1 << PIPE_B); 318 } 319 320 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, 321 struct i915_power_well *power_well) 322 { 323 struct drm_device *dev = &dev_priv->drm; 324 325 /* 326 * After we re-enable the power well, if we touch VGA register 0x3d5 327 * we'll get unclaimed register interrupts. This stops after we write 328 * anything to the VGA MSR register. The vgacon module uses this 329 * register all the time, so if we unbind our driver and, as a 330 * consequence, bind vgacon, we'll get stuck in an infinite loop at 331 * console_unlock(). So make here we touch the VGA MSR register, making 332 * sure vgacon can keep working normally without triggering interrupts 333 * and error messages. 334 */ 335 if (power_well->data == SKL_DISP_PW_2) { 336 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 337 #if 0 338 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 339 #endif 340 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 341 342 gen8_irq_power_well_post_enable(dev_priv, 343 1 << PIPE_C | 1 << PIPE_B); 344 } 345 } 346 347 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, 348 struct i915_power_well *power_well) 349 { 350 if (power_well->data == SKL_DISP_PW_2) 351 gen8_irq_power_well_pre_disable(dev_priv, 352 1 << PIPE_C | 1 << PIPE_B); 353 } 354 355 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 356 struct i915_power_well *power_well, bool enable) 357 { 358 bool is_enabled, enable_requested; 359 uint32_t tmp; 360 361 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 362 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 363 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 364 365 if (enable) { 366 if (!enable_requested) 367 I915_WRITE(HSW_PWR_WELL_DRIVER, 368 HSW_PWR_WELL_ENABLE_REQUEST); 369 370 if (!is_enabled) { 371 DRM_DEBUG_KMS("Enabling power well\n"); 372 if (intel_wait_for_register(dev_priv, 373 HSW_PWR_WELL_DRIVER, 374 HSW_PWR_WELL_STATE_ENABLED, 375 HSW_PWR_WELL_STATE_ENABLED, 376 20)) 377 DRM_ERROR("Timeout enabling power well\n"); 378 hsw_power_well_post_enable(dev_priv); 379 } 380 381 } else { 382 if (enable_requested) { 383 hsw_power_well_pre_disable(dev_priv); 384 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 385 POSTING_READ(HSW_PWR_WELL_DRIVER); 386 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 387 } 388 } 389 } 390 391 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 392 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 393 BIT(POWER_DOMAIN_PIPE_B) | \ 394 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 395 BIT(POWER_DOMAIN_PIPE_C) | \ 396 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 397 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 398 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 399 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 400 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 401 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 402 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 403 BIT(POWER_DOMAIN_AUX_B) | \ 404 BIT(POWER_DOMAIN_AUX_C) | \ 405 BIT(POWER_DOMAIN_AUX_D) | \ 406 BIT(POWER_DOMAIN_AUDIO) | \ 407 BIT(POWER_DOMAIN_VGA) | \ 408 BIT(POWER_DOMAIN_INIT)) 409 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ 410 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 411 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 412 BIT(POWER_DOMAIN_INIT)) 413 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ 414 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 415 BIT(POWER_DOMAIN_INIT)) 416 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ 417 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 418 BIT(POWER_DOMAIN_INIT)) 419 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ 420 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 421 BIT(POWER_DOMAIN_INIT)) 422 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 423 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 424 BIT(POWER_DOMAIN_MODESET) | \ 425 BIT(POWER_DOMAIN_AUX_A) | \ 426 BIT(POWER_DOMAIN_INIT)) 427 428 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 429 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 430 BIT(POWER_DOMAIN_PIPE_B) | \ 431 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 432 BIT(POWER_DOMAIN_PIPE_C) | \ 433 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 434 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 435 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 436 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 437 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 438 BIT(POWER_DOMAIN_AUX_B) | \ 439 BIT(POWER_DOMAIN_AUX_C) | \ 440 BIT(POWER_DOMAIN_AUDIO) | \ 441 BIT(POWER_DOMAIN_VGA) | \ 442 BIT(POWER_DOMAIN_GMBUS) | \ 443 BIT(POWER_DOMAIN_INIT)) 444 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 445 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 446 BIT(POWER_DOMAIN_MODESET) | \ 447 BIT(POWER_DOMAIN_AUX_A) | \ 448 BIT(POWER_DOMAIN_INIT)) 449 #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ 450 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 451 BIT(POWER_DOMAIN_AUX_A) | \ 452 BIT(POWER_DOMAIN_INIT)) 453 #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ 454 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 455 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 456 BIT(POWER_DOMAIN_AUX_B) | \ 457 BIT(POWER_DOMAIN_AUX_C) | \ 458 BIT(POWER_DOMAIN_INIT)) 459 460 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 461 { 462 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 463 "DC9 already programmed to be enabled.\n"); 464 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 465 "DC5 still not disabled to enable DC9.\n"); 466 WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); 467 WARN_ONCE(intel_irqs_enabled(dev_priv), 468 "Interrupts not disabled yet.\n"); 469 470 /* 471 * TODO: check for the following to verify the conditions to enter DC9 472 * state are satisfied: 473 * 1] Check relevant display engine registers to verify if mode set 474 * disable sequence was followed. 475 * 2] Check if display uninitialize sequence is initialized. 476 */ 477 } 478 479 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 480 { 481 WARN_ONCE(intel_irqs_enabled(dev_priv), 482 "Interrupts not disabled yet.\n"); 483 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 484 "DC5 still not disabled.\n"); 485 486 /* 487 * TODO: check for the following to verify DC9 state was indeed 488 * entered before programming to disable it: 489 * 1] Check relevant display engine registers to verify if mode 490 * set disable sequence was followed. 491 * 2] Check if display uninitialize sequence is initialized. 492 */ 493 } 494 495 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 496 u32 state) 497 { 498 int rewrites = 0; 499 int rereads = 0; 500 u32 v; 501 502 I915_WRITE(DC_STATE_EN, state); 503 504 /* It has been observed that disabling the dc6 state sometimes 505 * doesn't stick and dmc keeps returning old value. Make sure 506 * the write really sticks enough times and also force rewrite until 507 * we are confident that state is exactly what we want. 508 */ 509 do { 510 v = I915_READ(DC_STATE_EN); 511 512 if (v != state) { 513 I915_WRITE(DC_STATE_EN, state); 514 rewrites++; 515 rereads = 0; 516 } else if (rereads++ > 5) { 517 break; 518 } 519 520 } while (rewrites < 100); 521 522 if (v != state) 523 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", 524 state, v); 525 526 /* Most of the times we need one retry, avoid spam */ 527 if (rewrites > 1) 528 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", 529 state, rewrites); 530 } 531 532 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) 533 { 534 u32 mask; 535 536 mask = DC_STATE_EN_UPTO_DC5; 537 if (IS_BROXTON(dev_priv)) 538 mask |= DC_STATE_EN_DC9; 539 else 540 mask |= DC_STATE_EN_UPTO_DC6; 541 542 return mask; 543 } 544 545 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) 546 { 547 u32 val; 548 549 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); 550 551 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", 552 dev_priv->csr.dc_state, val); 553 dev_priv->csr.dc_state = val; 554 } 555 556 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 557 { 558 uint32_t val; 559 uint32_t mask; 560 561 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) 562 state &= dev_priv->csr.allowed_dc_mask; 563 564 val = I915_READ(DC_STATE_EN); 565 mask = gen9_dc_mask(dev_priv); 566 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 567 val & mask, state); 568 569 /* Check if DMC is ignoring our DC state requests */ 570 if ((val & mask) != dev_priv->csr.dc_state) 571 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", 572 dev_priv->csr.dc_state, val & mask); 573 574 val &= ~mask; 575 val |= state; 576 577 gen9_write_dc_state(dev_priv, val); 578 579 dev_priv->csr.dc_state = val & mask; 580 } 581 582 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 583 { 584 assert_can_enable_dc9(dev_priv); 585 586 DRM_DEBUG_KMS("Enabling DC9\n"); 587 588 intel_power_sequencer_reset(dev_priv); 589 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 590 } 591 592 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 593 { 594 assert_can_disable_dc9(dev_priv); 595 596 DRM_DEBUG_KMS("Disabling DC9\n"); 597 598 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 599 } 600 601 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 602 { 603 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 604 "CSR program storage start is NULL\n"); 605 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 606 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 607 } 608 609 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 610 { 611 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 612 SKL_DISP_PW_2); 613 614 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 615 616 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 617 "DC5 already programmed to be enabled.\n"); 618 assert_rpm_wakelock_held(dev_priv); 619 620 assert_csr_loaded(dev_priv); 621 } 622 623 void gen9_enable_dc5(struct drm_i915_private *dev_priv) 624 { 625 assert_can_enable_dc5(dev_priv); 626 627 DRM_DEBUG_KMS("Enabling DC5\n"); 628 629 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 630 } 631 632 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 633 { 634 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 635 "Backlight is not disabled.\n"); 636 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 637 "DC6 already programmed to be enabled.\n"); 638 639 assert_csr_loaded(dev_priv); 640 } 641 642 void skl_enable_dc6(struct drm_i915_private *dev_priv) 643 { 644 assert_can_enable_dc6(dev_priv); 645 646 DRM_DEBUG_KMS("Enabling DC6\n"); 647 648 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 649 650 } 651 652 void skl_disable_dc6(struct drm_i915_private *dev_priv) 653 { 654 DRM_DEBUG_KMS("Disabling DC6\n"); 655 656 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 657 } 658 659 static void 660 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv, 661 struct i915_power_well *power_well) 662 { 663 enum skl_disp_power_wells power_well_id = power_well->data; 664 u32 val; 665 u32 mask; 666 667 mask = SKL_POWER_WELL_REQ(power_well_id); 668 669 val = I915_READ(HSW_PWR_WELL_KVMR); 670 if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n", 671 power_well->name)) 672 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask); 673 674 val = I915_READ(HSW_PWR_WELL_BIOS); 675 val |= I915_READ(HSW_PWR_WELL_DEBUG); 676 677 if (!(val & mask)) 678 return; 679 680 /* 681 * DMC is known to force on the request bits for power well 1 on SKL 682 * and BXT and the misc IO power well on SKL but we don't expect any 683 * other request bits to be set, so WARN for those. 684 */ 685 if (power_well_id == SKL_DISP_PW_1 || 686 ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && 687 power_well_id == SKL_DISP_PW_MISC_IO)) 688 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on " 689 "by DMC\n", power_well->name); 690 else 691 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n", 692 power_well->name); 693 694 I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask); 695 I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask); 696 } 697 698 static void skl_set_power_well(struct drm_i915_private *dev_priv, 699 struct i915_power_well *power_well, bool enable) 700 { 701 uint32_t tmp, fuse_status; 702 uint32_t req_mask, state_mask; 703 bool is_enabled, enable_requested, check_fuse_status = false; 704 705 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 706 fuse_status = I915_READ(SKL_FUSE_STATUS); 707 708 switch (power_well->data) { 709 case SKL_DISP_PW_1: 710 if (intel_wait_for_register(dev_priv, 711 SKL_FUSE_STATUS, 712 SKL_FUSE_PG0_DIST_STATUS, 713 SKL_FUSE_PG0_DIST_STATUS, 714 1)) { 715 DRM_ERROR("PG0 not enabled\n"); 716 return; 717 } 718 break; 719 case SKL_DISP_PW_2: 720 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { 721 DRM_ERROR("PG1 in disabled state\n"); 722 return; 723 } 724 break; 725 case SKL_DISP_PW_DDI_A_E: 726 case SKL_DISP_PW_DDI_B: 727 case SKL_DISP_PW_DDI_C: 728 case SKL_DISP_PW_DDI_D: 729 case SKL_DISP_PW_MISC_IO: 730 break; 731 default: 732 WARN(1, "Unknown power well %lu\n", power_well->data); 733 return; 734 } 735 736 req_mask = SKL_POWER_WELL_REQ(power_well->data); 737 enable_requested = tmp & req_mask; 738 state_mask = SKL_POWER_WELL_STATE(power_well->data); 739 is_enabled = tmp & state_mask; 740 741 if (!enable && enable_requested) 742 skl_power_well_pre_disable(dev_priv, power_well); 743 744 if (enable) { 745 if (!enable_requested) { 746 WARN((tmp & state_mask) && 747 !I915_READ(HSW_PWR_WELL_BIOS), 748 "Invalid for power well status to be enabled, unless done by the BIOS, \ 749 when request is to disable!\n"); 750 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); 751 } 752 753 if (!is_enabled) { 754 DRM_DEBUG_KMS("Enabling %s\n", power_well->name); 755 check_fuse_status = true; 756 } 757 } else { 758 if (enable_requested) { 759 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); 760 POSTING_READ(HSW_PWR_WELL_DRIVER); 761 DRM_DEBUG_KMS("Disabling %s\n", power_well->name); 762 } 763 764 if (IS_GEN9(dev_priv)) 765 gen9_sanitize_power_well_requests(dev_priv, power_well); 766 } 767 768 if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable, 769 1)) 770 DRM_ERROR("%s %s timeout\n", 771 power_well->name, enable ? "enable" : "disable"); 772 773 if (check_fuse_status) { 774 if (power_well->data == SKL_DISP_PW_1) { 775 if (intel_wait_for_register(dev_priv, 776 SKL_FUSE_STATUS, 777 SKL_FUSE_PG1_DIST_STATUS, 778 SKL_FUSE_PG1_DIST_STATUS, 779 1)) 780 DRM_ERROR("PG1 distributing status timeout\n"); 781 } else if (power_well->data == SKL_DISP_PW_2) { 782 if (intel_wait_for_register(dev_priv, 783 SKL_FUSE_STATUS, 784 SKL_FUSE_PG2_DIST_STATUS, 785 SKL_FUSE_PG2_DIST_STATUS, 786 1)) 787 DRM_ERROR("PG2 distributing status timeout\n"); 788 } 789 } 790 791 if (enable && !is_enabled) 792 skl_power_well_post_enable(dev_priv, power_well); 793 } 794 795 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 796 struct i915_power_well *power_well) 797 { 798 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 799 800 /* 801 * We're taking over the BIOS, so clear any requests made by it since 802 * the driver is in charge now. 803 */ 804 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 805 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 806 } 807 808 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 809 struct i915_power_well *power_well) 810 { 811 hsw_set_power_well(dev_priv, power_well, true); 812 } 813 814 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 815 struct i915_power_well *power_well) 816 { 817 hsw_set_power_well(dev_priv, power_well, false); 818 } 819 820 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, 821 struct i915_power_well *power_well) 822 { 823 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | 824 SKL_POWER_WELL_STATE(power_well->data); 825 826 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; 827 } 828 829 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, 830 struct i915_power_well *power_well) 831 { 832 skl_set_power_well(dev_priv, power_well, power_well->count > 0); 833 834 /* Clear any request made by BIOS as driver is taking over */ 835 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 836 } 837 838 static void skl_power_well_enable(struct drm_i915_private *dev_priv, 839 struct i915_power_well *power_well) 840 { 841 skl_set_power_well(dev_priv, power_well, true); 842 } 843 844 static void skl_power_well_disable(struct drm_i915_private *dev_priv, 845 struct i915_power_well *power_well) 846 { 847 skl_set_power_well(dev_priv, power_well, false); 848 } 849 850 static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well) 851 { 852 enum skl_disp_power_wells power_well_id = power_well->data; 853 854 return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0; 855 } 856 857 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 858 struct i915_power_well *power_well) 859 { 860 enum skl_disp_power_wells power_well_id = power_well->data; 861 struct i915_power_well *cmn_a_well; 862 863 if (power_well_id == BXT_DPIO_CMN_BC) { 864 /* 865 * We need to copy the GRC calibration value from the eDP PHY, 866 * so make sure it's powered up. 867 */ 868 cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); 869 intel_power_well_get(dev_priv, cmn_a_well); 870 } 871 872 bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well)); 873 874 if (power_well_id == BXT_DPIO_CMN_BC) 875 intel_power_well_put(dev_priv, cmn_a_well); 876 } 877 878 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 879 struct i915_power_well *power_well) 880 { 881 bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well)); 882 } 883 884 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 885 struct i915_power_well *power_well) 886 { 887 return bxt_ddi_phy_is_enabled(dev_priv, 888 bxt_power_well_to_phy(power_well)); 889 } 890 891 static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv, 892 struct i915_power_well *power_well) 893 { 894 if (power_well->count > 0) 895 bxt_dpio_cmn_power_well_enable(dev_priv, power_well); 896 else 897 bxt_dpio_cmn_power_well_disable(dev_priv, power_well); 898 } 899 900 901 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 902 { 903 struct i915_power_well *power_well; 904 905 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); 906 if (power_well->count > 0) 907 bxt_ddi_phy_verify_state(dev_priv, 908 bxt_power_well_to_phy(power_well)); 909 910 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); 911 if (power_well->count > 0) 912 bxt_ddi_phy_verify_state(dev_priv, 913 bxt_power_well_to_phy(power_well)); 914 } 915 916 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 917 struct i915_power_well *power_well) 918 { 919 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 920 } 921 922 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 923 { 924 u32 tmp = I915_READ(DBUF_CTL); 925 926 WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) != 927 (DBUF_POWER_STATE | DBUF_POWER_REQUEST), 928 "Unexpected DBuf power power state (0x%08x)\n", tmp); 929 } 930 931 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 932 struct i915_power_well *power_well) 933 { 934 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 935 936 WARN_ON(dev_priv->cdclk_freq != 937 dev_priv->display.get_display_clock_speed(&dev_priv->drm)); 938 939 gen9_assert_dbuf_enabled(dev_priv); 940 941 if (IS_BROXTON(dev_priv)) 942 bxt_verify_ddi_phy_power_wells(dev_priv); 943 } 944 945 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 946 struct i915_power_well *power_well) 947 { 948 if (!dev_priv->csr.dmc_payload) 949 return; 950 951 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 952 skl_enable_dc6(dev_priv); 953 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 954 gen9_enable_dc5(dev_priv); 955 } 956 957 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv, 958 struct i915_power_well *power_well) 959 { 960 if (power_well->count > 0) 961 gen9_dc_off_power_well_enable(dev_priv, power_well); 962 else 963 gen9_dc_off_power_well_disable(dev_priv, power_well); 964 } 965 966 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 967 struct i915_power_well *power_well) 968 { 969 } 970 971 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 972 struct i915_power_well *power_well) 973 { 974 return true; 975 } 976 977 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 978 struct i915_power_well *power_well, bool enable) 979 { 980 enum punit_power_well power_well_id = power_well->data; 981 u32 mask; 982 u32 state; 983 u32 ctrl; 984 985 mask = PUNIT_PWRGT_MASK(power_well_id); 986 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 987 PUNIT_PWRGT_PWR_GATE(power_well_id); 988 989 mutex_lock(&dev_priv->rps.hw_lock); 990 991 #define COND \ 992 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 993 994 if (COND) 995 goto out; 996 997 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 998 ctrl &= ~mask; 999 ctrl |= state; 1000 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 1001 1002 if (wait_for(COND, 100)) 1003 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1004 state, 1005 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 1006 1007 #undef COND 1008 1009 out: 1010 mutex_unlock(&dev_priv->rps.hw_lock); 1011 } 1012 1013 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 1014 struct i915_power_well *power_well) 1015 { 1016 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 1017 } 1018 1019 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 1020 struct i915_power_well *power_well) 1021 { 1022 vlv_set_power_well(dev_priv, power_well, true); 1023 } 1024 1025 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 1026 struct i915_power_well *power_well) 1027 { 1028 vlv_set_power_well(dev_priv, power_well, false); 1029 } 1030 1031 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 1032 struct i915_power_well *power_well) 1033 { 1034 int power_well_id = power_well->data; 1035 bool enabled = false; 1036 u32 mask; 1037 u32 state; 1038 u32 ctrl; 1039 1040 mask = PUNIT_PWRGT_MASK(power_well_id); 1041 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 1042 1043 mutex_lock(&dev_priv->rps.hw_lock); 1044 1045 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 1046 /* 1047 * We only ever set the power-on and power-gate states, anything 1048 * else is unexpected. 1049 */ 1050 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 1051 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 1052 if (state == ctrl) 1053 enabled = true; 1054 1055 /* 1056 * A transient state at this point would mean some unexpected party 1057 * is poking at the power controls too. 1058 */ 1059 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 1060 WARN_ON(ctrl != state); 1061 1062 mutex_unlock(&dev_priv->rps.hw_lock); 1063 1064 return enabled; 1065 } 1066 1067 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 1068 { 1069 u32 val; 1070 1071 /* 1072 * On driver load, a pipe may be active and driving a DSI display. 1073 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1074 * (and never recovering) in this case. intel_dsi_post_disable() will 1075 * clear it when we turn off the display. 1076 */ 1077 val = I915_READ(DSPCLK_GATE_D); 1078 val &= DPOUNIT_CLOCK_GATE_DISABLE; 1079 val |= VRHUNIT_CLOCK_GATE_DISABLE; 1080 I915_WRITE(DSPCLK_GATE_D, val); 1081 1082 /* 1083 * Disable trickle feed and enable pnd deadline calculation 1084 */ 1085 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1086 I915_WRITE(CBR1_VLV, 0); 1087 1088 WARN_ON(dev_priv->rawclk_freq == 0); 1089 1090 I915_WRITE(RAWCLK_FREQ_VLV, 1091 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); 1092 } 1093 1094 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 1095 { 1096 struct intel_encoder *encoder; 1097 enum i915_pipe pipe; 1098 1099 /* 1100 * Enable the CRI clock source so we can get at the 1101 * display and the reference clock for VGA 1102 * hotplug / manual detection. Supposedly DSI also 1103 * needs the ref clock up and running. 1104 * 1105 * CHV DPLL B/C have some issues if VGA mode is enabled. 1106 */ 1107 for_each_pipe(&dev_priv->drm, pipe) { 1108 u32 val = I915_READ(DPLL(pipe)); 1109 1110 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1111 if (pipe != PIPE_A) 1112 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1113 1114 I915_WRITE(DPLL(pipe), val); 1115 } 1116 1117 vlv_init_display_clock_gating(dev_priv); 1118 1119 spin_lock_irq(&dev_priv->irq_lock); 1120 valleyview_enable_display_irqs(dev_priv); 1121 spin_unlock_irq(&dev_priv->irq_lock); 1122 1123 /* 1124 * During driver initialization/resume we can avoid restoring the 1125 * part of the HW/SW state that will be inited anyway explicitly. 1126 */ 1127 if (dev_priv->power_domains.initializing) 1128 return; 1129 1130 intel_hpd_init(dev_priv); 1131 1132 /* Re-enable the ADPA, if we have one */ 1133 for_each_intel_encoder(&dev_priv->drm, encoder) { 1134 if (encoder->type == INTEL_OUTPUT_ANALOG) 1135 intel_crt_reset(&encoder->base); 1136 } 1137 1138 i915_redisable_vga_power_on(&dev_priv->drm); 1139 } 1140 1141 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 1142 { 1143 spin_lock_irq(&dev_priv->irq_lock); 1144 valleyview_disable_display_irqs(dev_priv); 1145 spin_unlock_irq(&dev_priv->irq_lock); 1146 1147 /* make sure we're done processing display irqs */ 1148 synchronize_irq(dev_priv->drm.irq); 1149 1150 intel_power_sequencer_reset(dev_priv); 1151 1152 intel_hpd_poll_init(dev_priv); 1153 } 1154 1155 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 1156 struct i915_power_well *power_well) 1157 { 1158 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 1159 1160 vlv_set_power_well(dev_priv, power_well, true); 1161 1162 vlv_display_power_well_init(dev_priv); 1163 } 1164 1165 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1166 struct i915_power_well *power_well) 1167 { 1168 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 1169 1170 vlv_display_power_well_deinit(dev_priv); 1171 1172 vlv_set_power_well(dev_priv, power_well, false); 1173 } 1174 1175 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1176 struct i915_power_well *power_well) 1177 { 1178 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1179 1180 /* since ref/cri clock was enabled */ 1181 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1182 1183 vlv_set_power_well(dev_priv, power_well, true); 1184 1185 /* 1186 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1187 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1188 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1189 * b. The other bits such as sfr settings / modesel may all 1190 * be set to 0. 1191 * 1192 * This should only be done on init and resume from S3 with 1193 * both PLLs disabled, or we risk losing DPIO and PLL 1194 * synchronization. 1195 */ 1196 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 1197 } 1198 1199 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1200 struct i915_power_well *power_well) 1201 { 1202 enum i915_pipe pipe; 1203 1204 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1205 1206 for_each_pipe(dev_priv, pipe) 1207 assert_pll_disabled(dev_priv, pipe); 1208 1209 /* Assert common reset */ 1210 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1211 1212 vlv_set_power_well(dev_priv, power_well, false); 1213 } 1214 1215 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 1216 1217 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1218 int power_well_id) 1219 { 1220 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1221 int i; 1222 1223 for (i = 0; i < power_domains->power_well_count; i++) { 1224 struct i915_power_well *power_well; 1225 1226 power_well = &power_domains->power_wells[i]; 1227 if (power_well->data == power_well_id) 1228 return power_well; 1229 } 1230 1231 return NULL; 1232 } 1233 1234 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1235 1236 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1237 { 1238 struct i915_power_well *cmn_bc = 1239 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1240 struct i915_power_well *cmn_d = 1241 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1242 u32 phy_control = dev_priv->chv_phy_control; 1243 u32 phy_status = 0; 1244 u32 phy_status_mask = 0xffffffff; 1245 1246 /* 1247 * The BIOS can leave the PHY is some weird state 1248 * where it doesn't fully power down some parts. 1249 * Disable the asserts until the PHY has been fully 1250 * reset (ie. the power well has been disabled at 1251 * least once). 1252 */ 1253 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1254 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1255 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1256 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1257 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1258 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1259 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1260 1261 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1262 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1263 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1264 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1265 1266 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1267 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1268 1269 /* this assumes override is only used to enable lanes */ 1270 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1271 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1272 1273 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1274 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1275 1276 /* CL1 is on whenever anything is on in either channel */ 1277 if (BITS_SET(phy_control, 1278 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1279 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1280 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1281 1282 /* 1283 * The DPLLB check accounts for the pipe B + port A usage 1284 * with CL2 powered up but all the lanes in the second channel 1285 * powered down. 1286 */ 1287 if (BITS_SET(phy_control, 1288 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1289 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1290 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1291 1292 if (BITS_SET(phy_control, 1293 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1294 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1295 if (BITS_SET(phy_control, 1296 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1297 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1298 1299 if (BITS_SET(phy_control, 1300 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1301 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1302 if (BITS_SET(phy_control, 1303 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1304 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1305 } 1306 1307 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1308 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1309 1310 /* this assumes override is only used to enable lanes */ 1311 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1312 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1313 1314 if (BITS_SET(phy_control, 1315 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1316 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1317 1318 if (BITS_SET(phy_control, 1319 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1320 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1321 if (BITS_SET(phy_control, 1322 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1323 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1324 } 1325 1326 phy_status &= phy_status_mask; 1327 1328 /* 1329 * The PHY may be busy with some initial calibration and whatnot, 1330 * so the power state can take a while to actually change. 1331 */ 1332 if (intel_wait_for_register(dev_priv, 1333 DISPLAY_PHY_STATUS, 1334 phy_status_mask, 1335 phy_status, 1336 10)) 1337 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1338 I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, 1339 phy_status, dev_priv->chv_phy_control); 1340 } 1341 1342 #undef BITS_SET 1343 1344 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1345 struct i915_power_well *power_well) 1346 { 1347 enum dpio_phy phy; 1348 enum i915_pipe pipe; 1349 uint32_t tmp; 1350 1351 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1352 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1353 1354 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1355 pipe = PIPE_A; 1356 phy = DPIO_PHY0; 1357 } else { 1358 pipe = PIPE_C; 1359 phy = DPIO_PHY1; 1360 } 1361 1362 /* since ref/cri clock was enabled */ 1363 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1364 vlv_set_power_well(dev_priv, power_well, true); 1365 1366 /* Poll for phypwrgood signal */ 1367 if (intel_wait_for_register(dev_priv, 1368 DISPLAY_PHY_STATUS, 1369 PHY_POWERGOOD(phy), 1370 PHY_POWERGOOD(phy), 1371 1)) 1372 DRM_ERROR("Display PHY %d is not power up\n", phy); 1373 1374 mutex_lock(&dev_priv->sb_lock); 1375 1376 /* Enable dynamic power down */ 1377 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1378 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1379 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1380 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1381 1382 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1383 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1384 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1385 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1386 } else { 1387 /* 1388 * Force the non-existing CL2 off. BXT does this 1389 * too, so maybe it saves some power even though 1390 * CL2 doesn't exist? 1391 */ 1392 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1393 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1394 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1395 } 1396 1397 mutex_unlock(&dev_priv->sb_lock); 1398 1399 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1400 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1401 1402 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1403 phy, dev_priv->chv_phy_control); 1404 1405 assert_chv_phy_status(dev_priv); 1406 } 1407 1408 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1409 struct i915_power_well *power_well) 1410 { 1411 enum dpio_phy phy; 1412 1413 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1414 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1415 1416 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1417 phy = DPIO_PHY0; 1418 assert_pll_disabled(dev_priv, PIPE_A); 1419 assert_pll_disabled(dev_priv, PIPE_B); 1420 } else { 1421 phy = DPIO_PHY1; 1422 assert_pll_disabled(dev_priv, PIPE_C); 1423 } 1424 1425 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1426 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1427 1428 vlv_set_power_well(dev_priv, power_well, false); 1429 1430 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1431 phy, dev_priv->chv_phy_control); 1432 1433 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1434 dev_priv->chv_phy_assert[phy] = true; 1435 1436 assert_chv_phy_status(dev_priv); 1437 } 1438 1439 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1440 enum dpio_channel ch, bool override, unsigned int mask) 1441 { 1442 enum i915_pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1443 u32 reg, val, expected, actual; 1444 1445 /* 1446 * The BIOS can leave the PHY is some weird state 1447 * where it doesn't fully power down some parts. 1448 * Disable the asserts until the PHY has been fully 1449 * reset (ie. the power well has been disabled at 1450 * least once). 1451 */ 1452 if (!dev_priv->chv_phy_assert[phy]) 1453 return; 1454 1455 if (ch == DPIO_CH0) 1456 reg = _CHV_CMN_DW0_CH0; 1457 else 1458 reg = _CHV_CMN_DW6_CH1; 1459 1460 mutex_lock(&dev_priv->sb_lock); 1461 val = vlv_dpio_read(dev_priv, pipe, reg); 1462 mutex_unlock(&dev_priv->sb_lock); 1463 1464 /* 1465 * This assumes !override is only used when the port is disabled. 1466 * All lanes should power down even without the override when 1467 * the port is disabled. 1468 */ 1469 if (!override || mask == 0xf) { 1470 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1471 /* 1472 * If CH1 common lane is not active anymore 1473 * (eg. for pipe B DPLL) the entire channel will 1474 * shut down, which causes the common lane registers 1475 * to read as 0. That means we can't actually check 1476 * the lane power down status bits, but as the entire 1477 * register reads as 0 it's a good indication that the 1478 * channel is indeed entirely powered down. 1479 */ 1480 if (ch == DPIO_CH1 && val == 0) 1481 expected = 0; 1482 } else if (mask != 0x0) { 1483 expected = DPIO_ANYDL_POWERDOWN; 1484 } else { 1485 expected = 0; 1486 } 1487 1488 if (ch == DPIO_CH0) 1489 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1490 else 1491 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1492 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1493 1494 WARN(actual != expected, 1495 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1496 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1497 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1498 reg, val); 1499 } 1500 1501 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1502 enum dpio_channel ch, bool override) 1503 { 1504 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1505 bool was_override; 1506 1507 mutex_lock(&power_domains->lock); 1508 1509 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1510 1511 if (override == was_override) 1512 goto out; 1513 1514 if (override) 1515 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1516 else 1517 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1518 1519 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1520 1521 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1522 phy, ch, dev_priv->chv_phy_control); 1523 1524 assert_chv_phy_status(dev_priv); 1525 1526 out: 1527 mutex_unlock(&power_domains->lock); 1528 1529 return was_override; 1530 } 1531 1532 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1533 bool override, unsigned int mask) 1534 { 1535 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1536 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1537 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1538 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1539 1540 mutex_lock(&power_domains->lock); 1541 1542 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1543 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1544 1545 if (override) 1546 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1547 else 1548 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1549 1550 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1551 1552 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1553 phy, ch, mask, dev_priv->chv_phy_control); 1554 1555 assert_chv_phy_status(dev_priv); 1556 1557 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1558 1559 mutex_unlock(&power_domains->lock); 1560 } 1561 1562 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1563 struct i915_power_well *power_well) 1564 { 1565 enum i915_pipe pipe = power_well->data; 1566 bool enabled; 1567 u32 state, ctrl; 1568 1569 mutex_lock(&dev_priv->rps.hw_lock); 1570 1571 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1572 /* 1573 * We only ever set the power-on and power-gate states, anything 1574 * else is unexpected. 1575 */ 1576 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1577 enabled = state == DP_SSS_PWR_ON(pipe); 1578 1579 /* 1580 * A transient state at this point would mean some unexpected party 1581 * is poking at the power controls too. 1582 */ 1583 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1584 WARN_ON(ctrl << 16 != state); 1585 1586 mutex_unlock(&dev_priv->rps.hw_lock); 1587 1588 return enabled; 1589 } 1590 1591 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1592 struct i915_power_well *power_well, 1593 bool enable) 1594 { 1595 enum i915_pipe pipe = power_well->data; 1596 u32 state; 1597 u32 ctrl; 1598 1599 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1600 1601 mutex_lock(&dev_priv->rps.hw_lock); 1602 1603 #define COND \ 1604 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1605 1606 if (COND) 1607 goto out; 1608 1609 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1610 ctrl &= ~DP_SSC_MASK(pipe); 1611 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1612 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1613 1614 if (wait_for(COND, 100)) 1615 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1616 state, 1617 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1618 1619 #undef COND 1620 1621 out: 1622 mutex_unlock(&dev_priv->rps.hw_lock); 1623 } 1624 1625 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1626 struct i915_power_well *power_well) 1627 { 1628 WARN_ON_ONCE(power_well->data != PIPE_A); 1629 1630 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 1631 } 1632 1633 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1634 struct i915_power_well *power_well) 1635 { 1636 WARN_ON_ONCE(power_well->data != PIPE_A); 1637 1638 chv_set_pipe_power_well(dev_priv, power_well, true); 1639 1640 vlv_display_power_well_init(dev_priv); 1641 } 1642 1643 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1644 struct i915_power_well *power_well) 1645 { 1646 WARN_ON_ONCE(power_well->data != PIPE_A); 1647 1648 vlv_display_power_well_deinit(dev_priv); 1649 1650 chv_set_pipe_power_well(dev_priv, power_well, false); 1651 } 1652 1653 static void 1654 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 1655 enum intel_display_power_domain domain) 1656 { 1657 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1658 struct i915_power_well *power_well; 1659 int i; 1660 1661 for_each_power_well(i, power_well, BIT(domain), power_domains) 1662 intel_power_well_get(dev_priv, power_well); 1663 1664 power_domains->domain_use_count[domain]++; 1665 } 1666 1667 /** 1668 * intel_display_power_get - grab a power domain reference 1669 * @dev_priv: i915 device instance 1670 * @domain: power domain to reference 1671 * 1672 * This function grabs a power domain reference for @domain and ensures that the 1673 * power domain and all its parents are powered up. Therefore users should only 1674 * grab a reference to the innermost power domain they need. 1675 * 1676 * Any power domain reference obtained by this function must have a symmetric 1677 * call to intel_display_power_put() to release the reference again. 1678 */ 1679 void intel_display_power_get(struct drm_i915_private *dev_priv, 1680 enum intel_display_power_domain domain) 1681 { 1682 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1683 1684 intel_runtime_pm_get(dev_priv); 1685 1686 mutex_lock(&power_domains->lock); 1687 1688 __intel_display_power_get_domain(dev_priv, domain); 1689 1690 mutex_unlock(&power_domains->lock); 1691 } 1692 1693 /** 1694 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 1695 * @dev_priv: i915 device instance 1696 * @domain: power domain to reference 1697 * 1698 * This function grabs a power domain reference for @domain and ensures that the 1699 * power domain and all its parents are powered up. Therefore users should only 1700 * grab a reference to the innermost power domain they need. 1701 * 1702 * Any power domain reference obtained by this function must have a symmetric 1703 * call to intel_display_power_put() to release the reference again. 1704 */ 1705 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1706 enum intel_display_power_domain domain) 1707 { 1708 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1709 bool is_enabled; 1710 1711 if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1712 return false; 1713 1714 mutex_lock(&power_domains->lock); 1715 1716 if (__intel_display_power_is_enabled(dev_priv, domain)) { 1717 __intel_display_power_get_domain(dev_priv, domain); 1718 is_enabled = true; 1719 } else { 1720 is_enabled = false; 1721 } 1722 1723 mutex_unlock(&power_domains->lock); 1724 1725 if (!is_enabled) 1726 intel_runtime_pm_put(dev_priv); 1727 1728 return is_enabled; 1729 } 1730 1731 /** 1732 * intel_display_power_put - release a power domain reference 1733 * @dev_priv: i915 device instance 1734 * @domain: power domain to reference 1735 * 1736 * This function drops the power domain reference obtained by 1737 * intel_display_power_get() and might power down the corresponding hardware 1738 * block right away if this is the last reference. 1739 */ 1740 void intel_display_power_put(struct drm_i915_private *dev_priv, 1741 enum intel_display_power_domain domain) 1742 { 1743 struct i915_power_domains *power_domains; 1744 struct i915_power_well *power_well; 1745 int i; 1746 1747 power_domains = &dev_priv->power_domains; 1748 1749 mutex_lock(&power_domains->lock); 1750 1751 WARN(!power_domains->domain_use_count[domain], 1752 "Use count on domain %s is already zero\n", 1753 intel_display_power_domain_str(domain)); 1754 power_domains->domain_use_count[domain]--; 1755 1756 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) 1757 intel_power_well_put(dev_priv, power_well); 1758 1759 mutex_unlock(&power_domains->lock); 1760 1761 intel_runtime_pm_put(dev_priv); 1762 } 1763 1764 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1765 BIT(POWER_DOMAIN_PIPE_B) | \ 1766 BIT(POWER_DOMAIN_PIPE_C) | \ 1767 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1768 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1769 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1770 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1771 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1772 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 1773 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1774 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1775 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1776 BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1777 BIT(POWER_DOMAIN_VGA) | \ 1778 BIT(POWER_DOMAIN_AUDIO) | \ 1779 BIT(POWER_DOMAIN_INIT)) 1780 1781 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1782 BIT(POWER_DOMAIN_PIPE_B) | \ 1783 BIT(POWER_DOMAIN_PIPE_C) | \ 1784 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1785 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1786 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1787 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1788 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 1789 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1790 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1791 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1792 BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1793 BIT(POWER_DOMAIN_VGA) | \ 1794 BIT(POWER_DOMAIN_AUDIO) | \ 1795 BIT(POWER_DOMAIN_INIT)) 1796 1797 #define VLV_DISPLAY_POWER_DOMAINS ( \ 1798 BIT(POWER_DOMAIN_PIPE_A) | \ 1799 BIT(POWER_DOMAIN_PIPE_B) | \ 1800 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1801 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1802 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1803 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1804 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1805 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1806 BIT(POWER_DOMAIN_PORT_DSI) | \ 1807 BIT(POWER_DOMAIN_PORT_CRT) | \ 1808 BIT(POWER_DOMAIN_VGA) | \ 1809 BIT(POWER_DOMAIN_AUDIO) | \ 1810 BIT(POWER_DOMAIN_AUX_B) | \ 1811 BIT(POWER_DOMAIN_AUX_C) | \ 1812 BIT(POWER_DOMAIN_GMBUS) | \ 1813 BIT(POWER_DOMAIN_INIT)) 1814 1815 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1816 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1817 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1818 BIT(POWER_DOMAIN_PORT_CRT) | \ 1819 BIT(POWER_DOMAIN_AUX_B) | \ 1820 BIT(POWER_DOMAIN_AUX_C) | \ 1821 BIT(POWER_DOMAIN_INIT)) 1822 1823 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1824 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1825 BIT(POWER_DOMAIN_AUX_B) | \ 1826 BIT(POWER_DOMAIN_INIT)) 1827 1828 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1829 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1830 BIT(POWER_DOMAIN_AUX_B) | \ 1831 BIT(POWER_DOMAIN_INIT)) 1832 1833 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1834 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1835 BIT(POWER_DOMAIN_AUX_C) | \ 1836 BIT(POWER_DOMAIN_INIT)) 1837 1838 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1839 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1840 BIT(POWER_DOMAIN_AUX_C) | \ 1841 BIT(POWER_DOMAIN_INIT)) 1842 1843 #define CHV_DISPLAY_POWER_DOMAINS ( \ 1844 BIT(POWER_DOMAIN_PIPE_A) | \ 1845 BIT(POWER_DOMAIN_PIPE_B) | \ 1846 BIT(POWER_DOMAIN_PIPE_C) | \ 1847 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1848 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1849 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1850 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1851 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1852 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 1853 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1854 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1855 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1856 BIT(POWER_DOMAIN_PORT_DSI) | \ 1857 BIT(POWER_DOMAIN_VGA) | \ 1858 BIT(POWER_DOMAIN_AUDIO) | \ 1859 BIT(POWER_DOMAIN_AUX_B) | \ 1860 BIT(POWER_DOMAIN_AUX_C) | \ 1861 BIT(POWER_DOMAIN_AUX_D) | \ 1862 BIT(POWER_DOMAIN_GMBUS) | \ 1863 BIT(POWER_DOMAIN_INIT)) 1864 1865 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1866 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1867 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1868 BIT(POWER_DOMAIN_AUX_B) | \ 1869 BIT(POWER_DOMAIN_AUX_C) | \ 1870 BIT(POWER_DOMAIN_INIT)) 1871 1872 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1873 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1874 BIT(POWER_DOMAIN_AUX_D) | \ 1875 BIT(POWER_DOMAIN_INIT)) 1876 1877 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1878 .sync_hw = i9xx_always_on_power_well_noop, 1879 .enable = i9xx_always_on_power_well_noop, 1880 .disable = i9xx_always_on_power_well_noop, 1881 .is_enabled = i9xx_always_on_power_well_enabled, 1882 }; 1883 1884 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1885 .sync_hw = chv_pipe_power_well_sync_hw, 1886 .enable = chv_pipe_power_well_enable, 1887 .disable = chv_pipe_power_well_disable, 1888 .is_enabled = chv_pipe_power_well_enabled, 1889 }; 1890 1891 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1892 .sync_hw = vlv_power_well_sync_hw, 1893 .enable = chv_dpio_cmn_power_well_enable, 1894 .disable = chv_dpio_cmn_power_well_disable, 1895 .is_enabled = vlv_power_well_enabled, 1896 }; 1897 1898 static struct i915_power_well i9xx_always_on_power_well[] = { 1899 { 1900 .name = "always-on", 1901 .always_on = 1, 1902 .domains = POWER_DOMAIN_MASK, 1903 .ops = &i9xx_always_on_power_well_ops, 1904 }, 1905 }; 1906 1907 static const struct i915_power_well_ops hsw_power_well_ops = { 1908 .sync_hw = hsw_power_well_sync_hw, 1909 .enable = hsw_power_well_enable, 1910 .disable = hsw_power_well_disable, 1911 .is_enabled = hsw_power_well_enabled, 1912 }; 1913 1914 static const struct i915_power_well_ops skl_power_well_ops = { 1915 .sync_hw = skl_power_well_sync_hw, 1916 .enable = skl_power_well_enable, 1917 .disable = skl_power_well_disable, 1918 .is_enabled = skl_power_well_enabled, 1919 }; 1920 1921 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1922 .sync_hw = gen9_dc_off_power_well_sync_hw, 1923 .enable = gen9_dc_off_power_well_enable, 1924 .disable = gen9_dc_off_power_well_disable, 1925 .is_enabled = gen9_dc_off_power_well_enabled, 1926 }; 1927 1928 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1929 .sync_hw = bxt_dpio_cmn_power_well_sync_hw, 1930 .enable = bxt_dpio_cmn_power_well_enable, 1931 .disable = bxt_dpio_cmn_power_well_disable, 1932 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1933 }; 1934 1935 static struct i915_power_well hsw_power_wells[] = { 1936 { 1937 .name = "always-on", 1938 .always_on = 1, 1939 .domains = POWER_DOMAIN_MASK, 1940 .ops = &i9xx_always_on_power_well_ops, 1941 }, 1942 { 1943 .name = "display", 1944 .domains = HSW_DISPLAY_POWER_DOMAINS, 1945 .ops = &hsw_power_well_ops, 1946 }, 1947 }; 1948 1949 static struct i915_power_well bdw_power_wells[] = { 1950 { 1951 .name = "always-on", 1952 .always_on = 1, 1953 .domains = POWER_DOMAIN_MASK, 1954 .ops = &i9xx_always_on_power_well_ops, 1955 }, 1956 { 1957 .name = "display", 1958 .domains = BDW_DISPLAY_POWER_DOMAINS, 1959 .ops = &hsw_power_well_ops, 1960 }, 1961 }; 1962 1963 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1964 .sync_hw = vlv_power_well_sync_hw, 1965 .enable = vlv_display_power_well_enable, 1966 .disable = vlv_display_power_well_disable, 1967 .is_enabled = vlv_power_well_enabled, 1968 }; 1969 1970 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1971 .sync_hw = vlv_power_well_sync_hw, 1972 .enable = vlv_dpio_cmn_power_well_enable, 1973 .disable = vlv_dpio_cmn_power_well_disable, 1974 .is_enabled = vlv_power_well_enabled, 1975 }; 1976 1977 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1978 .sync_hw = vlv_power_well_sync_hw, 1979 .enable = vlv_power_well_enable, 1980 .disable = vlv_power_well_disable, 1981 .is_enabled = vlv_power_well_enabled, 1982 }; 1983 1984 static struct i915_power_well vlv_power_wells[] = { 1985 { 1986 .name = "always-on", 1987 .always_on = 1, 1988 .domains = POWER_DOMAIN_MASK, 1989 .ops = &i9xx_always_on_power_well_ops, 1990 .data = PUNIT_POWER_WELL_ALWAYS_ON, 1991 }, 1992 { 1993 .name = "display", 1994 .domains = VLV_DISPLAY_POWER_DOMAINS, 1995 .data = PUNIT_POWER_WELL_DISP2D, 1996 .ops = &vlv_display_power_well_ops, 1997 }, 1998 { 1999 .name = "dpio-tx-b-01", 2000 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2001 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2002 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2003 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2004 .ops = &vlv_dpio_power_well_ops, 2005 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 2006 }, 2007 { 2008 .name = "dpio-tx-b-23", 2009 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2010 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2011 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2012 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2013 .ops = &vlv_dpio_power_well_ops, 2014 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 2015 }, 2016 { 2017 .name = "dpio-tx-c-01", 2018 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2019 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2020 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2021 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2022 .ops = &vlv_dpio_power_well_ops, 2023 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 2024 }, 2025 { 2026 .name = "dpio-tx-c-23", 2027 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2028 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2029 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2030 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2031 .ops = &vlv_dpio_power_well_ops, 2032 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 2033 }, 2034 { 2035 .name = "dpio-common", 2036 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 2037 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 2038 .ops = &vlv_dpio_cmn_power_well_ops, 2039 }, 2040 }; 2041 2042 static struct i915_power_well chv_power_wells[] = { 2043 { 2044 .name = "always-on", 2045 .always_on = 1, 2046 .domains = POWER_DOMAIN_MASK, 2047 .ops = &i9xx_always_on_power_well_ops, 2048 }, 2049 { 2050 .name = "display", 2051 /* 2052 * Pipe A power well is the new disp2d well. Pipe B and C 2053 * power wells don't actually exist. Pipe A power well is 2054 * required for any pipe to work. 2055 */ 2056 .domains = CHV_DISPLAY_POWER_DOMAINS, 2057 .data = PIPE_A, 2058 .ops = &chv_pipe_power_well_ops, 2059 }, 2060 { 2061 .name = "dpio-common-bc", 2062 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 2063 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 2064 .ops = &chv_dpio_cmn_power_well_ops, 2065 }, 2066 { 2067 .name = "dpio-common-d", 2068 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 2069 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 2070 .ops = &chv_dpio_cmn_power_well_ops, 2071 }, 2072 }; 2073 2074 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 2075 int power_well_id) 2076 { 2077 struct i915_power_well *power_well; 2078 bool ret; 2079 2080 power_well = lookup_power_well(dev_priv, power_well_id); 2081 ret = power_well->ops->is_enabled(dev_priv, power_well); 2082 2083 return ret; 2084 } 2085 2086 static struct i915_power_well skl_power_wells[] = { 2087 { 2088 .name = "always-on", 2089 .always_on = 1, 2090 .domains = POWER_DOMAIN_MASK, 2091 .ops = &i9xx_always_on_power_well_ops, 2092 .data = SKL_DISP_PW_ALWAYS_ON, 2093 }, 2094 { 2095 .name = "power well 1", 2096 /* Handled by the DMC firmware */ 2097 .domains = 0, 2098 .ops = &skl_power_well_ops, 2099 .data = SKL_DISP_PW_1, 2100 }, 2101 { 2102 .name = "MISC IO power well", 2103 /* Handled by the DMC firmware */ 2104 .domains = 0, 2105 .ops = &skl_power_well_ops, 2106 .data = SKL_DISP_PW_MISC_IO, 2107 }, 2108 { 2109 .name = "DC off", 2110 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 2111 .ops = &gen9_dc_off_power_well_ops, 2112 .data = SKL_DISP_PW_DC_OFF, 2113 }, 2114 { 2115 .name = "power well 2", 2116 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2117 .ops = &skl_power_well_ops, 2118 .data = SKL_DISP_PW_2, 2119 }, 2120 { 2121 .name = "DDI A/E power well", 2122 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, 2123 .ops = &skl_power_well_ops, 2124 .data = SKL_DISP_PW_DDI_A_E, 2125 }, 2126 { 2127 .name = "DDI B power well", 2128 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, 2129 .ops = &skl_power_well_ops, 2130 .data = SKL_DISP_PW_DDI_B, 2131 }, 2132 { 2133 .name = "DDI C power well", 2134 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, 2135 .ops = &skl_power_well_ops, 2136 .data = SKL_DISP_PW_DDI_C, 2137 }, 2138 { 2139 .name = "DDI D power well", 2140 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, 2141 .ops = &skl_power_well_ops, 2142 .data = SKL_DISP_PW_DDI_D, 2143 }, 2144 }; 2145 2146 static struct i915_power_well bxt_power_wells[] = { 2147 { 2148 .name = "always-on", 2149 .always_on = 1, 2150 .domains = POWER_DOMAIN_MASK, 2151 .ops = &i9xx_always_on_power_well_ops, 2152 }, 2153 { 2154 .name = "power well 1", 2155 .domains = 0, 2156 .ops = &skl_power_well_ops, 2157 .data = SKL_DISP_PW_1, 2158 }, 2159 { 2160 .name = "DC off", 2161 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 2162 .ops = &gen9_dc_off_power_well_ops, 2163 .data = SKL_DISP_PW_DC_OFF, 2164 }, 2165 { 2166 .name = "power well 2", 2167 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2168 .ops = &skl_power_well_ops, 2169 .data = SKL_DISP_PW_2, 2170 }, 2171 { 2172 .name = "dpio-common-a", 2173 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, 2174 .ops = &bxt_dpio_cmn_power_well_ops, 2175 .data = BXT_DPIO_CMN_A, 2176 }, 2177 { 2178 .name = "dpio-common-bc", 2179 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, 2180 .ops = &bxt_dpio_cmn_power_well_ops, 2181 .data = BXT_DPIO_CMN_BC, 2182 }, 2183 }; 2184 2185 static int 2186 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 2187 int disable_power_well) 2188 { 2189 if (disable_power_well >= 0) 2190 return !!disable_power_well; 2191 2192 return 1; 2193 } 2194 2195 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 2196 int enable_dc) 2197 { 2198 uint32_t mask; 2199 int requested_dc; 2200 int max_dc; 2201 2202 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 2203 max_dc = 2; 2204 mask = 0; 2205 } else if (IS_BROXTON(dev_priv)) { 2206 max_dc = 1; 2207 /* 2208 * DC9 has a separate HW flow from the rest of the DC states, 2209 * not depending on the DMC firmware. It's needed by system 2210 * suspend/resume, so allow it unconditionally. 2211 */ 2212 mask = DC_STATE_EN_DC9; 2213 } else { 2214 max_dc = 0; 2215 mask = 0; 2216 } 2217 2218 if (!i915.disable_power_well) 2219 max_dc = 0; 2220 2221 if (enable_dc >= 0 && enable_dc <= max_dc) { 2222 requested_dc = enable_dc; 2223 } else if (enable_dc == -1) { 2224 requested_dc = max_dc; 2225 } else if (enable_dc > max_dc && enable_dc <= 2) { 2226 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", 2227 enable_dc, max_dc); 2228 requested_dc = max_dc; 2229 } else { 2230 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); 2231 requested_dc = max_dc; 2232 } 2233 2234 if (requested_dc > 1) 2235 mask |= DC_STATE_EN_UPTO_DC6; 2236 if (requested_dc > 0) 2237 mask |= DC_STATE_EN_UPTO_DC5; 2238 2239 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); 2240 2241 return mask; 2242 } 2243 2244 #define set_power_wells(power_domains, __power_wells) ({ \ 2245 (power_domains)->power_wells = (__power_wells); \ 2246 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 2247 }) 2248 2249 /** 2250 * intel_power_domains_init - initializes the power domain structures 2251 * @dev_priv: i915 device instance 2252 * 2253 * Initializes the power domain structures for @dev_priv depending upon the 2254 * supported platform. 2255 */ 2256 int intel_power_domains_init(struct drm_i915_private *dev_priv) 2257 { 2258 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2259 2260 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, 2261 i915.disable_power_well); 2262 dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv, 2263 i915.enable_dc); 2264 2265 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); 2266 2267 lockinit(&power_domains->lock, "i915pl", 0, LK_CANRECURSE); 2268 2269 /* 2270 * The enabling order will be from lower to higher indexed wells, 2271 * the disabling order is reversed. 2272 */ 2273 if (IS_HASWELL(dev_priv)) { 2274 set_power_wells(power_domains, hsw_power_wells); 2275 } else if (IS_BROADWELL(dev_priv)) { 2276 set_power_wells(power_domains, bdw_power_wells); 2277 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 2278 set_power_wells(power_domains, skl_power_wells); 2279 } else if (IS_BROXTON(dev_priv)) { 2280 set_power_wells(power_domains, bxt_power_wells); 2281 } else if (IS_CHERRYVIEW(dev_priv)) { 2282 set_power_wells(power_domains, chv_power_wells); 2283 } else if (IS_VALLEYVIEW(dev_priv)) { 2284 set_power_wells(power_domains, vlv_power_wells); 2285 } else { 2286 set_power_wells(power_domains, i9xx_always_on_power_well); 2287 } 2288 2289 return 0; 2290 } 2291 2292 /** 2293 * intel_power_domains_fini - finalizes the power domain structures 2294 * @dev_priv: i915 device instance 2295 * 2296 * Finalizes the power domain structures for @dev_priv depending upon the 2297 * supported platform. This function also disables runtime pm and ensures that 2298 * the device stays powered up so that the driver can be reloaded. 2299 */ 2300 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 2301 { 2302 #if 0 2303 struct device *device = &dev_priv->drm.pdev->dev; 2304 #endif 2305 2306 /* 2307 * The i915.ko module is still not prepared to be loaded when 2308 * the power well is not enabled, so just enable it in case 2309 * we're going to unload/reload. 2310 * The following also reacquires the RPM reference the core passed 2311 * to the driver during loading, which is dropped in 2312 * intel_runtime_pm_enable(). We have to hand back the control of the 2313 * device to the core with this reference held. 2314 */ 2315 intel_display_set_init_power(dev_priv, true); 2316 2317 /* Remove the refcount we took to keep power well support disabled. */ 2318 if (!i915.disable_power_well) 2319 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2320 2321 /* 2322 * Remove the refcount we took in intel_runtime_pm_enable() in case 2323 * the platform doesn't support runtime PM. 2324 */ 2325 #if 0 2326 if (!HAS_RUNTIME_PM(dev_priv)) 2327 pm_runtime_put(device); 2328 #endif 2329 } 2330 2331 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 2332 { 2333 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2334 struct i915_power_well *power_well; 2335 int i; 2336 2337 mutex_lock(&power_domains->lock); 2338 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 2339 power_well->ops->sync_hw(dev_priv, power_well); 2340 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 2341 power_well); 2342 } 2343 mutex_unlock(&power_domains->lock); 2344 } 2345 2346 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 2347 { 2348 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); 2349 POSTING_READ(DBUF_CTL); 2350 2351 udelay(10); 2352 2353 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) 2354 DRM_ERROR("DBuf power enable timeout\n"); 2355 } 2356 2357 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 2358 { 2359 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); 2360 POSTING_READ(DBUF_CTL); 2361 2362 udelay(10); 2363 2364 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) 2365 DRM_ERROR("DBuf power disable timeout!\n"); 2366 } 2367 2368 static void skl_display_core_init(struct drm_i915_private *dev_priv, 2369 bool resume) 2370 { 2371 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2372 struct i915_power_well *well; 2373 uint32_t val; 2374 2375 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2376 2377 /* enable PCH reset handshake */ 2378 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2379 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 2380 2381 /* enable PG1 and Misc I/O */ 2382 mutex_lock(&power_domains->lock); 2383 2384 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2385 intel_power_well_enable(dev_priv, well); 2386 2387 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 2388 intel_power_well_enable(dev_priv, well); 2389 2390 mutex_unlock(&power_domains->lock); 2391 2392 skl_init_cdclk(dev_priv); 2393 2394 gen9_dbuf_enable(dev_priv); 2395 2396 if (resume && dev_priv->csr.dmc_payload) 2397 intel_csr_load_program(dev_priv); 2398 } 2399 2400 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 2401 { 2402 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2403 struct i915_power_well *well; 2404 2405 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2406 2407 gen9_dbuf_disable(dev_priv); 2408 2409 skl_uninit_cdclk(dev_priv); 2410 2411 /* The spec doesn't call for removing the reset handshake flag */ 2412 /* disable PG1 and Misc I/O */ 2413 2414 mutex_lock(&power_domains->lock); 2415 2416 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 2417 intel_power_well_disable(dev_priv, well); 2418 2419 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2420 intel_power_well_disable(dev_priv, well); 2421 2422 mutex_unlock(&power_domains->lock); 2423 } 2424 2425 void bxt_display_core_init(struct drm_i915_private *dev_priv, 2426 bool resume) 2427 { 2428 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2429 struct i915_power_well *well; 2430 uint32_t val; 2431 2432 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2433 2434 /* 2435 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 2436 * or else the reset will hang because there is no PCH to respond. 2437 * Move the handshake programming to initialization sequence. 2438 * Previously was left up to BIOS. 2439 */ 2440 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2441 val &= ~RESET_PCH_HANDSHAKE_ENABLE; 2442 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2443 2444 /* Enable PG1 */ 2445 mutex_lock(&power_domains->lock); 2446 2447 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2448 intel_power_well_enable(dev_priv, well); 2449 2450 mutex_unlock(&power_domains->lock); 2451 2452 bxt_init_cdclk(dev_priv); 2453 2454 gen9_dbuf_enable(dev_priv); 2455 2456 if (resume && dev_priv->csr.dmc_payload) 2457 intel_csr_load_program(dev_priv); 2458 } 2459 2460 void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 2461 { 2462 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2463 struct i915_power_well *well; 2464 2465 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2466 2467 gen9_dbuf_disable(dev_priv); 2468 2469 bxt_uninit_cdclk(dev_priv); 2470 2471 /* The spec doesn't call for removing the reset handshake flag */ 2472 2473 /* Disable PG1 */ 2474 mutex_lock(&power_domains->lock); 2475 2476 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2477 intel_power_well_disable(dev_priv, well); 2478 2479 mutex_unlock(&power_domains->lock); 2480 } 2481 2482 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 2483 { 2484 struct i915_power_well *cmn_bc = 2485 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2486 struct i915_power_well *cmn_d = 2487 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 2488 2489 /* 2490 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 2491 * workaround never ever read DISPLAY_PHY_CONTROL, and 2492 * instead maintain a shadow copy ourselves. Use the actual 2493 * power well state and lane status to reconstruct the 2494 * expected initial value. 2495 */ 2496 dev_priv->chv_phy_control = 2497 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 2498 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 2499 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 2500 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 2501 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 2502 2503 /* 2504 * If all lanes are disabled we leave the override disabled 2505 * with all power down bits cleared to match the state we 2506 * would use after disabling the port. Otherwise enable the 2507 * override and set the lane powerdown bits accding to the 2508 * current lane status. 2509 */ 2510 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 2511 uint32_t status = I915_READ(DPLL(PIPE_A)); 2512 unsigned int mask; 2513 2514 mask = status & DPLL_PORTB_READY_MASK; 2515 if (mask == 0xf) 2516 mask = 0x0; 2517 else 2518 dev_priv->chv_phy_control |= 2519 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 2520 2521 dev_priv->chv_phy_control |= 2522 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 2523 2524 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 2525 if (mask == 0xf) 2526 mask = 0x0; 2527 else 2528 dev_priv->chv_phy_control |= 2529 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 2530 2531 dev_priv->chv_phy_control |= 2532 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 2533 2534 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 2535 2536 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 2537 } else { 2538 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 2539 } 2540 2541 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 2542 uint32_t status = I915_READ(DPIO_PHY_STATUS); 2543 unsigned int mask; 2544 2545 mask = status & DPLL_PORTD_READY_MASK; 2546 2547 if (mask == 0xf) 2548 mask = 0x0; 2549 else 2550 dev_priv->chv_phy_control |= 2551 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 2552 2553 dev_priv->chv_phy_control |= 2554 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 2555 2556 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 2557 2558 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 2559 } else { 2560 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 2561 } 2562 2563 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 2564 2565 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 2566 dev_priv->chv_phy_control); 2567 } 2568 2569 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 2570 { 2571 struct i915_power_well *cmn = 2572 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2573 struct i915_power_well *disp2d = 2574 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 2575 2576 /* If the display might be already active skip this */ 2577 if (cmn->ops->is_enabled(dev_priv, cmn) && 2578 disp2d->ops->is_enabled(dev_priv, disp2d) && 2579 I915_READ(DPIO_CTL) & DPIO_CMNRST) 2580 return; 2581 2582 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 2583 2584 /* cmnlane needs DPLL registers */ 2585 disp2d->ops->enable(dev_priv, disp2d); 2586 2587 /* 2588 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 2589 * Need to assert and de-assert PHY SB reset by gating the 2590 * common lane power, then un-gating it. 2591 * Simply ungating isn't enough to reset the PHY enough to get 2592 * ports and lanes running. 2593 */ 2594 cmn->ops->disable(dev_priv, cmn); 2595 } 2596 2597 /** 2598 * intel_power_domains_init_hw - initialize hardware power domain state 2599 * @dev_priv: i915 device instance 2600 * @resume: Called from resume code paths or not 2601 * 2602 * This function initializes the hardware power domain state and enables all 2603 * power domains using intel_display_set_init_power(). 2604 */ 2605 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 2606 { 2607 struct drm_device *dev = &dev_priv->drm; 2608 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2609 2610 power_domains->initializing = true; 2611 2612 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 2613 skl_display_core_init(dev_priv, resume); 2614 } else if (IS_BROXTON(dev)) { 2615 bxt_display_core_init(dev_priv, resume); 2616 } else if (IS_CHERRYVIEW(dev)) { 2617 mutex_lock(&power_domains->lock); 2618 chv_phy_control_init(dev_priv); 2619 mutex_unlock(&power_domains->lock); 2620 } else if (IS_VALLEYVIEW(dev)) { 2621 mutex_lock(&power_domains->lock); 2622 vlv_cmnlane_wa(dev_priv); 2623 mutex_unlock(&power_domains->lock); 2624 } 2625 2626 /* For now, we need the power well to be always enabled. */ 2627 intel_display_set_init_power(dev_priv, true); 2628 /* Disable power support if the user asked so. */ 2629 if (!i915.disable_power_well) 2630 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 2631 intel_power_domains_sync_hw(dev_priv); 2632 power_domains->initializing = false; 2633 } 2634 2635 /** 2636 * intel_power_domains_suspend - suspend power domain state 2637 * @dev_priv: i915 device instance 2638 * 2639 * This function prepares the hardware power domain state before entering 2640 * system suspend. It must be paired with intel_power_domains_init_hw(). 2641 */ 2642 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 2643 { 2644 /* 2645 * Even if power well support was disabled we still want to disable 2646 * power wells while we are system suspended. 2647 */ 2648 if (!i915.disable_power_well) 2649 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2650 2651 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 2652 skl_display_core_uninit(dev_priv); 2653 else if (IS_BROXTON(dev_priv)) 2654 bxt_display_core_uninit(dev_priv); 2655 } 2656 2657 /** 2658 * intel_runtime_pm_get - grab a runtime pm reference 2659 * @dev_priv: i915 device instance 2660 * 2661 * This function grabs a device-level runtime pm reference (mostly used for GEM 2662 * code to ensure the GTT or GT is on) and ensures that it is powered up. 2663 * 2664 * Any runtime pm reference obtained by this function must have a symmetric 2665 * call to intel_runtime_pm_put() to release the reference again. 2666 */ 2667 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 2668 { 2669 struct drm_device *dev = &dev_priv->drm; 2670 struct device *device = &dev->pdev->dev; 2671 2672 pm_runtime_get_sync(device); 2673 2674 atomic_inc(&dev_priv->pm.wakeref_count); 2675 assert_rpm_wakelock_held(dev_priv); 2676 } 2677 2678 /** 2679 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 2680 * @dev_priv: i915 device instance 2681 * 2682 * This function grabs a device-level runtime pm reference if the device is 2683 * already in use and ensures that it is powered up. 2684 * 2685 * Any runtime pm reference obtained by this function must have a symmetric 2686 * call to intel_runtime_pm_put() to release the reference again. 2687 */ 2688 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) 2689 { 2690 #ifndef __DragonFly__ 2691 struct drm_device *dev = &dev_priv->drm; 2692 struct device *device = &dev->pdev->dev; 2693 2694 if (IS_ENABLED(CONFIG_PM)) { 2695 int ret = pm_runtime_get_if_in_use(device); 2696 2697 /* 2698 * In cases runtime PM is disabled by the RPM core and we get 2699 * an -EINVAL return value we are not supposed to call this 2700 * function, since the power state is undefined. This applies 2701 * atm to the late/early system suspend/resume handlers. 2702 */ 2703 WARN_ON_ONCE(ret < 0); 2704 if (ret <= 0) 2705 return false; 2706 } 2707 2708 atomic_inc(&dev_priv->pm.wakeref_count); 2709 assert_rpm_wakelock_held(dev_priv); 2710 #endif 2711 2712 return true; 2713 } 2714 2715 /** 2716 * intel_runtime_pm_get_noresume - grab a runtime pm reference 2717 * @dev_priv: i915 device instance 2718 * 2719 * This function grabs a device-level runtime pm reference (mostly used for GEM 2720 * code to ensure the GTT or GT is on). 2721 * 2722 * It will _not_ power up the device but instead only check that it's powered 2723 * on. Therefore it is only valid to call this functions from contexts where 2724 * the device is known to be powered up and where trying to power it up would 2725 * result in hilarity and deadlocks. That pretty much means only the system 2726 * suspend/resume code where this is used to grab runtime pm references for 2727 * delayed setup down in work items. 2728 * 2729 * Any runtime pm reference obtained by this function must have a symmetric 2730 * call to intel_runtime_pm_put() to release the reference again. 2731 */ 2732 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 2733 { 2734 #if 0 2735 struct drm_device *dev = &dev_priv->drm; 2736 struct device *device = &dev->pdev->dev; 2737 #endif 2738 2739 assert_rpm_wakelock_held(dev_priv); 2740 #if 0 2741 pm_runtime_get_noresume(device); 2742 #endif 2743 2744 atomic_inc(&dev_priv->pm.wakeref_count); 2745 } 2746 2747 /** 2748 * intel_runtime_pm_put - release a runtime pm reference 2749 * @dev_priv: i915 device instance 2750 * 2751 * This function drops the device-level runtime pm reference obtained by 2752 * intel_runtime_pm_get() and might power down the corresponding 2753 * hardware block right away if this is the last reference. 2754 */ 2755 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 2756 { 2757 struct drm_device *dev = &dev_priv->drm; 2758 struct device *device = &dev->pdev->dev; 2759 2760 assert_rpm_wakelock_held(dev_priv); 2761 if (atomic_dec_and_test(&dev_priv->pm.wakeref_count)) 2762 atomic_inc(&dev_priv->pm.atomic_seq); 2763 2764 pm_runtime_mark_last_busy(device); 2765 pm_runtime_put_autosuspend(device); 2766 } 2767 2768 /** 2769 * intel_runtime_pm_enable - enable runtime pm 2770 * @dev_priv: i915 device instance 2771 * 2772 * This function enables runtime pm at the end of the driver load sequence. 2773 * 2774 * Note that this function does currently not enable runtime pm for the 2775 * subordinate display power domains. That is only done on the first modeset 2776 * using intel_display_set_init_power(). 2777 */ 2778 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 2779 { 2780 #if 0 2781 struct drm_device *dev = &dev_priv->drm; 2782 struct device *device = &dev->pdev->dev; 2783 2784 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 2785 pm_runtime_mark_last_busy(device); 2786 2787 /* 2788 * Take a permanent reference to disable the RPM functionality and drop 2789 * it only when unloading the driver. Use the low level get/put helpers, 2790 * so the driver's own RPM reference tracking asserts also work on 2791 * platforms without RPM support. 2792 */ 2793 if (!HAS_RUNTIME_PM(dev)) { 2794 pm_runtime_dont_use_autosuspend(device); 2795 pm_runtime_get_sync(device); 2796 } else { 2797 pm_runtime_use_autosuspend(device); 2798 } 2799 2800 /* 2801 * The core calls the driver load handler with an RPM reference held. 2802 * We drop that here and will reacquire it during unloading in 2803 * intel_power_domains_fini(). 2804 */ 2805 pm_runtime_put_autosuspend(device); 2806 #endif 2807 } 2808 2809