1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include "i915_drv.h" 30 #include "intel_drv.h" 31 32 /** 33 * DOC: runtime pm 34 * 35 * The i915 driver supports dynamic enabling and disabling of entire hardware 36 * blocks at runtime. This is especially important on the display side where 37 * software is supposed to control many power gates manually on recent hardware, 38 * since on the GT side a lot of the power management is done by the hardware. 39 * But even there some manual control at the device level is required. 40 * 41 * Since i915 supports a diverse set of platforms with a unified codebase and 42 * hardware engineers just love to shuffle functionality around between power 43 * domains there's a sizeable amount of indirection required. This file provides 44 * generic functions to the driver for grabbing and releasing references for 45 * abstract power domains. It then maps those to the actual power wells 46 * present for a given platform. 47 */ 48 49 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 50 for (i = 0; \ 51 i < (power_domains)->power_well_count && \ 52 ((power_well) = &(power_domains)->power_wells[i]); \ 53 i++) \ 54 for_each_if ((power_well)->domains & (domain_mask)) 55 56 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 57 for (i = (power_domains)->power_well_count - 1; \ 58 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 59 i--) \ 60 for_each_if ((power_well)->domains & (domain_mask)) 61 62 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 63 int power_well_id); 64 65 const char * 66 intel_display_power_domain_str(enum intel_display_power_domain domain) 67 { 68 switch (domain) { 69 case POWER_DOMAIN_PIPE_A: 70 return "PIPE_A"; 71 case POWER_DOMAIN_PIPE_B: 72 return "PIPE_B"; 73 case POWER_DOMAIN_PIPE_C: 74 return "PIPE_C"; 75 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 76 return "PIPE_A_PANEL_FITTER"; 77 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 78 return "PIPE_B_PANEL_FITTER"; 79 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 80 return "PIPE_C_PANEL_FITTER"; 81 case POWER_DOMAIN_TRANSCODER_A: 82 return "TRANSCODER_A"; 83 case POWER_DOMAIN_TRANSCODER_B: 84 return "TRANSCODER_B"; 85 case POWER_DOMAIN_TRANSCODER_C: 86 return "TRANSCODER_C"; 87 case POWER_DOMAIN_TRANSCODER_EDP: 88 return "TRANSCODER_EDP"; 89 case POWER_DOMAIN_PORT_DDI_A_LANES: 90 return "PORT_DDI_A_LANES"; 91 case POWER_DOMAIN_PORT_DDI_B_LANES: 92 return "PORT_DDI_B_LANES"; 93 case POWER_DOMAIN_PORT_DDI_C_LANES: 94 return "PORT_DDI_C_LANES"; 95 case POWER_DOMAIN_PORT_DDI_D_LANES: 96 return "PORT_DDI_D_LANES"; 97 case POWER_DOMAIN_PORT_DDI_E_LANES: 98 return "PORT_DDI_E_LANES"; 99 case POWER_DOMAIN_PORT_DSI: 100 return "PORT_DSI"; 101 case POWER_DOMAIN_PORT_CRT: 102 return "PORT_CRT"; 103 case POWER_DOMAIN_PORT_OTHER: 104 return "PORT_OTHER"; 105 case POWER_DOMAIN_VGA: 106 return "VGA"; 107 case POWER_DOMAIN_AUDIO: 108 return "AUDIO"; 109 case POWER_DOMAIN_PLLS: 110 return "PLLS"; 111 case POWER_DOMAIN_AUX_A: 112 return "AUX_A"; 113 case POWER_DOMAIN_AUX_B: 114 return "AUX_B"; 115 case POWER_DOMAIN_AUX_C: 116 return "AUX_C"; 117 case POWER_DOMAIN_AUX_D: 118 return "AUX_D"; 119 case POWER_DOMAIN_GMBUS: 120 return "GMBUS"; 121 case POWER_DOMAIN_INIT: 122 return "INIT"; 123 case POWER_DOMAIN_MODESET: 124 return "MODESET"; 125 default: 126 MISSING_CASE(domain); 127 return "?"; 128 } 129 } 130 131 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 132 struct i915_power_well *power_well) 133 { 134 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 135 power_well->ops->enable(dev_priv, power_well); 136 power_well->hw_enabled = true; 137 } 138 139 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 140 struct i915_power_well *power_well) 141 { 142 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 143 power_well->hw_enabled = false; 144 power_well->ops->disable(dev_priv, power_well); 145 } 146 147 /* 148 * We should only use the power well if we explicitly asked the hardware to 149 * enable it, so check if it's enabled and also check if we've requested it to 150 * be enabled. 151 */ 152 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 153 struct i915_power_well *power_well) 154 { 155 return I915_READ(HSW_PWR_WELL_DRIVER) == 156 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 157 } 158 159 /** 160 * __intel_display_power_is_enabled - unlocked check for a power domain 161 * @dev_priv: i915 device instance 162 * @domain: power domain to check 163 * 164 * This is the unlocked version of intel_display_power_is_enabled() and should 165 * only be used from error capture and recovery code where deadlocks are 166 * possible. 167 * 168 * Returns: 169 * True when the power domain is enabled, false otherwise. 170 */ 171 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 172 enum intel_display_power_domain domain) 173 { 174 struct i915_power_domains *power_domains; 175 struct i915_power_well *power_well; 176 bool is_enabled; 177 int i; 178 179 if (dev_priv->pm.suspended) 180 return false; 181 182 power_domains = &dev_priv->power_domains; 183 184 is_enabled = true; 185 186 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 187 if (power_well->always_on) 188 continue; 189 190 if (!power_well->hw_enabled) { 191 is_enabled = false; 192 break; 193 } 194 } 195 196 return is_enabled; 197 } 198 199 /** 200 * intel_display_power_is_enabled - check for a power domain 201 * @dev_priv: i915 device instance 202 * @domain: power domain to check 203 * 204 * This function can be used to check the hw power domain state. It is mostly 205 * used in hardware state readout functions. Everywhere else code should rely 206 * upon explicit power domain reference counting to ensure that the hardware 207 * block is powered up before accessing it. 208 * 209 * Callers must hold the relevant modesetting locks to ensure that concurrent 210 * threads can't disable the power well while the caller tries to read a few 211 * registers. 212 * 213 * Returns: 214 * True when the power domain is enabled, false otherwise. 215 */ 216 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 217 enum intel_display_power_domain domain) 218 { 219 struct i915_power_domains *power_domains; 220 bool ret; 221 222 power_domains = &dev_priv->power_domains; 223 224 mutex_lock(&power_domains->lock); 225 ret = __intel_display_power_is_enabled(dev_priv, domain); 226 mutex_unlock(&power_domains->lock); 227 228 return ret; 229 } 230 231 /** 232 * intel_display_set_init_power - set the initial power domain state 233 * @dev_priv: i915 device instance 234 * @enable: whether to enable or disable the initial power domain state 235 * 236 * For simplicity our driver load/unload and system suspend/resume code assumes 237 * that all power domains are always enabled. This functions controls the state 238 * of this little hack. While the initial power domain state is enabled runtime 239 * pm is effectively disabled. 240 */ 241 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 242 bool enable) 243 { 244 if (dev_priv->power_domains.init_power_on == enable) 245 return; 246 247 if (enable) 248 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 249 else 250 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 251 252 dev_priv->power_domains.init_power_on = enable; 253 } 254 255 /* 256 * Starting with Haswell, we have a "Power Down Well" that can be turned off 257 * when not needed anymore. We have 4 registers that can request the power well 258 * to be enabled, and it will only be disabled if none of the registers is 259 * requesting it to be enabled. 260 */ 261 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 262 { 263 struct drm_device *dev = dev_priv->dev; 264 265 /* 266 * After we re-enable the power well, if we touch VGA register 0x3d5 267 * we'll get unclaimed register interrupts. This stops after we write 268 * anything to the VGA MSR register. The vgacon module uses this 269 * register all the time, so if we unbind our driver and, as a 270 * consequence, bind vgacon, we'll get stuck in an infinite loop at 271 * console_unlock(). So make here we touch the VGA MSR register, making 272 * sure vgacon can keep working normally without triggering interrupts 273 * and error messages. 274 */ 275 #if 0 276 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 277 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 278 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 279 #endif 280 281 if (IS_BROADWELL(dev)) 282 gen8_irq_power_well_post_enable(dev_priv, 283 1 << PIPE_C | 1 << PIPE_B); 284 } 285 286 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, 287 struct i915_power_well *power_well) 288 { 289 #if 0 290 struct drm_device *dev = dev_priv->dev; 291 #endif 292 293 /* 294 * After we re-enable the power well, if we touch VGA register 0x3d5 295 * we'll get unclaimed register interrupts. This stops after we write 296 * anything to the VGA MSR register. The vgacon module uses this 297 * register all the time, so if we unbind our driver and, as a 298 * consequence, bind vgacon, we'll get stuck in an infinite loop at 299 * console_unlock(). So make here we touch the VGA MSR register, making 300 * sure vgacon can keep working normally without triggering interrupts 301 * and error messages. 302 */ 303 if (power_well->data == SKL_DISP_PW_2) { 304 #if 0 305 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 306 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 307 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 308 #endif 309 310 gen8_irq_power_well_post_enable(dev_priv, 311 1 << PIPE_C | 1 << PIPE_B); 312 } 313 } 314 315 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 316 struct i915_power_well *power_well, bool enable) 317 { 318 bool is_enabled, enable_requested; 319 uint32_t tmp; 320 321 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 322 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 323 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 324 325 if (enable) { 326 if (!enable_requested) 327 I915_WRITE(HSW_PWR_WELL_DRIVER, 328 HSW_PWR_WELL_ENABLE_REQUEST); 329 330 if (!is_enabled) { 331 DRM_DEBUG_KMS("Enabling power well\n"); 332 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 333 HSW_PWR_WELL_STATE_ENABLED), 20)) 334 DRM_ERROR("Timeout enabling power well\n"); 335 hsw_power_well_post_enable(dev_priv); 336 } 337 338 } else { 339 if (enable_requested) { 340 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 341 POSTING_READ(HSW_PWR_WELL_DRIVER); 342 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 343 } 344 } 345 } 346 347 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 348 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 349 BIT(POWER_DOMAIN_PIPE_B) | \ 350 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 351 BIT(POWER_DOMAIN_PIPE_C) | \ 352 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 353 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 354 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 355 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 356 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 357 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 358 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 359 BIT(POWER_DOMAIN_AUX_B) | \ 360 BIT(POWER_DOMAIN_AUX_C) | \ 361 BIT(POWER_DOMAIN_AUX_D) | \ 362 BIT(POWER_DOMAIN_AUDIO) | \ 363 BIT(POWER_DOMAIN_VGA) | \ 364 BIT(POWER_DOMAIN_INIT)) 365 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ 366 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 367 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 368 BIT(POWER_DOMAIN_INIT)) 369 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ 370 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 371 BIT(POWER_DOMAIN_INIT)) 372 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ 373 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 374 BIT(POWER_DOMAIN_INIT)) 375 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ 376 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 377 BIT(POWER_DOMAIN_INIT)) 378 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 379 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 380 BIT(POWER_DOMAIN_MODESET) | \ 381 BIT(POWER_DOMAIN_AUX_A) | \ 382 BIT(POWER_DOMAIN_INIT)) 383 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 384 (POWER_DOMAIN_MASK & ~( \ 385 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 386 SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \ 387 BIT(POWER_DOMAIN_INIT)) 388 389 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 390 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 391 BIT(POWER_DOMAIN_PIPE_B) | \ 392 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 393 BIT(POWER_DOMAIN_PIPE_C) | \ 394 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 395 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 396 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 397 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 398 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 399 BIT(POWER_DOMAIN_AUX_B) | \ 400 BIT(POWER_DOMAIN_AUX_C) | \ 401 BIT(POWER_DOMAIN_AUDIO) | \ 402 BIT(POWER_DOMAIN_VGA) | \ 403 BIT(POWER_DOMAIN_GMBUS) | \ 404 BIT(POWER_DOMAIN_INIT)) 405 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ 406 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 407 BIT(POWER_DOMAIN_PIPE_A) | \ 408 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 409 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 410 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 411 BIT(POWER_DOMAIN_AUX_A) | \ 412 BIT(POWER_DOMAIN_PLLS) | \ 413 BIT(POWER_DOMAIN_INIT)) 414 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 415 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 416 BIT(POWER_DOMAIN_MODESET) | \ 417 BIT(POWER_DOMAIN_AUX_A) | \ 418 BIT(POWER_DOMAIN_INIT)) 419 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 420 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 421 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ 422 BIT(POWER_DOMAIN_INIT)) 423 424 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 425 { 426 struct drm_device *dev = dev_priv->dev; 427 428 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); 429 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 430 "DC9 already programmed to be enabled.\n"); 431 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 432 "DC5 still not disabled to enable DC9.\n"); 433 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); 434 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 435 436 /* 437 * TODO: check for the following to verify the conditions to enter DC9 438 * state are satisfied: 439 * 1] Check relevant display engine registers to verify if mode set 440 * disable sequence was followed. 441 * 2] Check if display uninitialize sequence is initialized. 442 */ 443 } 444 445 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 446 { 447 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 448 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 449 "DC9 already programmed to be disabled.\n"); 450 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 451 "DC5 still not disabled.\n"); 452 453 /* 454 * TODO: check for the following to verify DC9 state was indeed 455 * entered before programming to disable it: 456 * 1] Check relevant display engine registers to verify if mode 457 * set disable sequence was followed. 458 * 2] Check if display uninitialize sequence is initialized. 459 */ 460 } 461 462 static void gen9_set_dc_state_debugmask_memory_up( 463 struct drm_i915_private *dev_priv) 464 { 465 uint32_t val; 466 467 /* The below bit doesn't need to be cleared ever afterwards */ 468 val = I915_READ(DC_STATE_DEBUG); 469 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { 470 val |= DC_STATE_DEBUG_MASK_MEMORY_UP; 471 I915_WRITE(DC_STATE_DEBUG, val); 472 POSTING_READ(DC_STATE_DEBUG); 473 } 474 } 475 476 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 477 u32 state) 478 { 479 int rewrites = 0; 480 int rereads = 0; 481 u32 v; 482 483 I915_WRITE(DC_STATE_EN, state); 484 485 /* It has been observed that disabling the dc6 state sometimes 486 * doesn't stick and dmc keeps returning old value. Make sure 487 * the write really sticks enough times and also force rewrite until 488 * we are confident that state is exactly what we want. 489 */ 490 do { 491 v = I915_READ(DC_STATE_EN); 492 493 if (v != state) { 494 I915_WRITE(DC_STATE_EN, state); 495 rewrites++; 496 rereads = 0; 497 } else if (rereads++ > 5) { 498 break; 499 } 500 501 } while (rewrites < 100); 502 503 if (v != state) 504 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", 505 state, v); 506 507 /* Most of the times we need one retry, avoid spam */ 508 if (rewrites > 1) 509 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", 510 state, rewrites); 511 } 512 513 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 514 { 515 uint32_t val; 516 uint32_t mask; 517 518 mask = DC_STATE_EN_UPTO_DC5; 519 if (IS_BROXTON(dev_priv)) 520 mask |= DC_STATE_EN_DC9; 521 else 522 mask |= DC_STATE_EN_UPTO_DC6; 523 524 WARN_ON_ONCE(state & ~mask); 525 526 if (i915.enable_dc == 0) 527 state = DC_STATE_DISABLE; 528 else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5) 529 state = DC_STATE_EN_UPTO_DC5; 530 531 if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK) 532 gen9_set_dc_state_debugmask_memory_up(dev_priv); 533 534 val = I915_READ(DC_STATE_EN); 535 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 536 val & mask, state); 537 538 /* Check if DMC is ignoring our DC state requests */ 539 if ((val & mask) != dev_priv->csr.dc_state) 540 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", 541 dev_priv->csr.dc_state, val & mask); 542 543 val &= ~mask; 544 val |= state; 545 546 gen9_write_dc_state(dev_priv, val); 547 548 dev_priv->csr.dc_state = val & mask; 549 } 550 551 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 552 { 553 assert_can_enable_dc9(dev_priv); 554 555 DRM_DEBUG_KMS("Enabling DC9\n"); 556 557 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 558 } 559 560 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 561 { 562 assert_can_disable_dc9(dev_priv); 563 564 DRM_DEBUG_KMS("Disabling DC9\n"); 565 566 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 567 } 568 569 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 570 { 571 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 572 "CSR program storage start is NULL\n"); 573 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 574 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 575 } 576 577 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 578 { 579 struct drm_device *dev = dev_priv->dev; 580 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 581 SKL_DISP_PW_2); 582 583 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); 584 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 585 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 586 587 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 588 "DC5 already programmed to be enabled.\n"); 589 assert_rpm_wakelock_held(dev_priv); 590 591 assert_csr_loaded(dev_priv); 592 } 593 594 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) 595 { 596 /* 597 * During initialization, the firmware may not be loaded yet. 598 * We still want to make sure that the DC enabling flag is cleared. 599 */ 600 if (dev_priv->power_domains.initializing) 601 return; 602 603 assert_rpm_wakelock_held(dev_priv); 604 } 605 606 static void gen9_enable_dc5(struct drm_i915_private *dev_priv) 607 { 608 assert_can_enable_dc5(dev_priv); 609 610 DRM_DEBUG_KMS("Enabling DC5\n"); 611 612 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 613 } 614 615 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 616 { 617 struct drm_device *dev = dev_priv->dev; 618 619 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); 620 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 621 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 622 "Backlight is not disabled.\n"); 623 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 624 "DC6 already programmed to be enabled.\n"); 625 626 assert_csr_loaded(dev_priv); 627 } 628 629 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) 630 { 631 /* 632 * During initialization, the firmware may not be loaded yet. 633 * We still want to make sure that the DC enabling flag is cleared. 634 */ 635 if (dev_priv->power_domains.initializing) 636 return; 637 638 WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 639 "DC6 already programmed to be disabled.\n"); 640 } 641 642 static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv) 643 { 644 assert_can_disable_dc5(dev_priv); 645 646 if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1) 647 assert_can_disable_dc6(dev_priv); 648 649 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 650 } 651 652 void skl_enable_dc6(struct drm_i915_private *dev_priv) 653 { 654 assert_can_enable_dc6(dev_priv); 655 656 DRM_DEBUG_KMS("Enabling DC6\n"); 657 658 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 659 660 } 661 662 void skl_disable_dc6(struct drm_i915_private *dev_priv) 663 { 664 assert_can_disable_dc6(dev_priv); 665 666 DRM_DEBUG_KMS("Disabling DC6\n"); 667 668 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 669 } 670 671 static void skl_set_power_well(struct drm_i915_private *dev_priv, 672 struct i915_power_well *power_well, bool enable) 673 { 674 struct drm_device *dev = dev_priv->dev; 675 uint32_t tmp, fuse_status; 676 uint32_t req_mask, state_mask; 677 bool is_enabled, enable_requested, check_fuse_status = false; 678 679 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 680 fuse_status = I915_READ(SKL_FUSE_STATUS); 681 682 switch (power_well->data) { 683 case SKL_DISP_PW_1: 684 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 685 SKL_FUSE_PG0_DIST_STATUS), 1)) { 686 DRM_ERROR("PG0 not enabled\n"); 687 return; 688 } 689 break; 690 case SKL_DISP_PW_2: 691 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { 692 DRM_ERROR("PG1 in disabled state\n"); 693 return; 694 } 695 break; 696 case SKL_DISP_PW_DDI_A_E: 697 case SKL_DISP_PW_DDI_B: 698 case SKL_DISP_PW_DDI_C: 699 case SKL_DISP_PW_DDI_D: 700 case SKL_DISP_PW_MISC_IO: 701 break; 702 default: 703 WARN(1, "Unknown power well %lu\n", power_well->data); 704 return; 705 } 706 707 req_mask = SKL_POWER_WELL_REQ(power_well->data); 708 enable_requested = tmp & req_mask; 709 state_mask = SKL_POWER_WELL_STATE(power_well->data); 710 is_enabled = tmp & state_mask; 711 712 if (enable) { 713 if (!enable_requested) { 714 WARN((tmp & state_mask) && 715 !I915_READ(HSW_PWR_WELL_BIOS), 716 "Invalid for power well status to be enabled, unless done by the BIOS, \ 717 when request is to disable!\n"); 718 if (power_well->data == SKL_DISP_PW_2) { 719 /* 720 * DDI buffer programming unnecessary during 721 * driver-load/resume as it's already done 722 * during modeset initialization then. It's 723 * also invalid here as encoder list is still 724 * uninitialized. 725 */ 726 if (!dev_priv->power_domains.initializing) 727 intel_prepare_ddi(dev); 728 } 729 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); 730 } 731 732 if (!is_enabled) { 733 DRM_DEBUG_KMS("Enabling %s\n", power_well->name); 734 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 735 state_mask), 1)) 736 DRM_ERROR("%s enable timeout\n", 737 power_well->name); 738 check_fuse_status = true; 739 } 740 } else { 741 if (enable_requested) { 742 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); 743 POSTING_READ(HSW_PWR_WELL_DRIVER); 744 DRM_DEBUG_KMS("Disabling %s\n", power_well->name); 745 } 746 } 747 748 if (check_fuse_status) { 749 if (power_well->data == SKL_DISP_PW_1) { 750 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 751 SKL_FUSE_PG1_DIST_STATUS), 1)) 752 DRM_ERROR("PG1 distributing status timeout\n"); 753 } else if (power_well->data == SKL_DISP_PW_2) { 754 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 755 SKL_FUSE_PG2_DIST_STATUS), 1)) 756 DRM_ERROR("PG2 distributing status timeout\n"); 757 } 758 } 759 760 if (enable && !is_enabled) 761 skl_power_well_post_enable(dev_priv, power_well); 762 } 763 764 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 765 struct i915_power_well *power_well) 766 { 767 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 768 769 /* 770 * We're taking over the BIOS, so clear any requests made by it since 771 * the driver is in charge now. 772 */ 773 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 774 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 775 } 776 777 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 778 struct i915_power_well *power_well) 779 { 780 hsw_set_power_well(dev_priv, power_well, true); 781 } 782 783 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 784 struct i915_power_well *power_well) 785 { 786 hsw_set_power_well(dev_priv, power_well, false); 787 } 788 789 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, 790 struct i915_power_well *power_well) 791 { 792 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | 793 SKL_POWER_WELL_STATE(power_well->data); 794 795 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; 796 } 797 798 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, 799 struct i915_power_well *power_well) 800 { 801 skl_set_power_well(dev_priv, power_well, power_well->count > 0); 802 803 /* Clear any request made by BIOS as driver is taking over */ 804 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 805 } 806 807 static void skl_power_well_enable(struct drm_i915_private *dev_priv, 808 struct i915_power_well *power_well) 809 { 810 skl_set_power_well(dev_priv, power_well, true); 811 } 812 813 static void skl_power_well_disable(struct drm_i915_private *dev_priv, 814 struct i915_power_well *power_well) 815 { 816 skl_set_power_well(dev_priv, power_well, false); 817 } 818 819 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 820 struct i915_power_well *power_well) 821 { 822 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 823 } 824 825 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 826 struct i915_power_well *power_well) 827 { 828 gen9_disable_dc5_dc6(dev_priv); 829 } 830 831 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 832 struct i915_power_well *power_well) 833 { 834 if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1) 835 skl_enable_dc6(dev_priv); 836 else 837 gen9_enable_dc5(dev_priv); 838 } 839 840 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv, 841 struct i915_power_well *power_well) 842 { 843 if (power_well->count > 0) { 844 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 845 } else { 846 if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && 847 i915.enable_dc != 1) 848 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 849 else 850 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 851 } 852 } 853 854 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 855 struct i915_power_well *power_well) 856 { 857 } 858 859 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 860 struct i915_power_well *power_well) 861 { 862 return true; 863 } 864 865 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 866 struct i915_power_well *power_well, bool enable) 867 { 868 enum punit_power_well power_well_id = power_well->data; 869 u32 mask; 870 u32 state; 871 u32 ctrl; 872 873 mask = PUNIT_PWRGT_MASK(power_well_id); 874 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 875 PUNIT_PWRGT_PWR_GATE(power_well_id); 876 877 mutex_lock(&dev_priv->rps.hw_lock); 878 879 #define COND \ 880 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 881 882 if (COND) 883 goto out; 884 885 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 886 ctrl &= ~mask; 887 ctrl |= state; 888 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 889 890 if (wait_for(COND, 100)) 891 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 892 state, 893 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 894 895 #undef COND 896 897 out: 898 mutex_unlock(&dev_priv->rps.hw_lock); 899 } 900 901 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 902 struct i915_power_well *power_well) 903 { 904 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 905 } 906 907 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 908 struct i915_power_well *power_well) 909 { 910 vlv_set_power_well(dev_priv, power_well, true); 911 } 912 913 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 914 struct i915_power_well *power_well) 915 { 916 vlv_set_power_well(dev_priv, power_well, false); 917 } 918 919 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 920 struct i915_power_well *power_well) 921 { 922 int power_well_id = power_well->data; 923 bool enabled = false; 924 u32 mask; 925 u32 state; 926 u32 ctrl; 927 928 mask = PUNIT_PWRGT_MASK(power_well_id); 929 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 930 931 mutex_lock(&dev_priv->rps.hw_lock); 932 933 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 934 /* 935 * We only ever set the power-on and power-gate states, anything 936 * else is unexpected. 937 */ 938 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 939 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 940 if (state == ctrl) 941 enabled = true; 942 943 /* 944 * A transient state at this point would mean some unexpected party 945 * is poking at the power controls too. 946 */ 947 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 948 WARN_ON(ctrl != state); 949 950 mutex_unlock(&dev_priv->rps.hw_lock); 951 952 return enabled; 953 } 954 955 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 956 { 957 enum i915_pipe pipe; 958 959 /* 960 * Enable the CRI clock source so we can get at the 961 * display and the reference clock for VGA 962 * hotplug / manual detection. Supposedly DSI also 963 * needs the ref clock up and running. 964 * 965 * CHV DPLL B/C have some issues if VGA mode is enabled. 966 */ 967 for_each_pipe(dev_priv->dev, pipe) { 968 u32 val = I915_READ(DPLL(pipe)); 969 970 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 971 if (pipe != PIPE_A) 972 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 973 974 I915_WRITE(DPLL(pipe), val); 975 } 976 977 spin_lock_irq(&dev_priv->irq_lock); 978 valleyview_enable_display_irqs(dev_priv); 979 spin_unlock_irq(&dev_priv->irq_lock); 980 981 /* 982 * During driver initialization/resume we can avoid restoring the 983 * part of the HW/SW state that will be inited anyway explicitly. 984 */ 985 if (dev_priv->power_domains.initializing) 986 return; 987 988 intel_hpd_init(dev_priv); 989 990 i915_redisable_vga_power_on(dev_priv->dev); 991 } 992 993 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 994 { 995 spin_lock_irq(&dev_priv->irq_lock); 996 valleyview_disable_display_irqs(dev_priv); 997 spin_unlock_irq(&dev_priv->irq_lock); 998 999 vlv_power_sequencer_reset(dev_priv); 1000 } 1001 1002 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 1003 struct i915_power_well *power_well) 1004 { 1005 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 1006 1007 vlv_set_power_well(dev_priv, power_well, true); 1008 1009 vlv_display_power_well_init(dev_priv); 1010 } 1011 1012 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1013 struct i915_power_well *power_well) 1014 { 1015 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 1016 1017 vlv_display_power_well_deinit(dev_priv); 1018 1019 vlv_set_power_well(dev_priv, power_well, false); 1020 } 1021 1022 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1023 struct i915_power_well *power_well) 1024 { 1025 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1026 1027 /* since ref/cri clock was enabled */ 1028 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1029 1030 vlv_set_power_well(dev_priv, power_well, true); 1031 1032 /* 1033 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1034 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1035 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1036 * b. The other bits such as sfr settings / modesel may all 1037 * be set to 0. 1038 * 1039 * This should only be done on init and resume from S3 with 1040 * both PLLs disabled, or we risk losing DPIO and PLL 1041 * synchronization. 1042 */ 1043 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 1044 } 1045 1046 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1047 struct i915_power_well *power_well) 1048 { 1049 enum i915_pipe pipe; 1050 1051 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1052 1053 for_each_pipe(dev_priv, pipe) 1054 assert_pll_disabled(dev_priv, pipe); 1055 1056 /* Assert common reset */ 1057 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1058 1059 vlv_set_power_well(dev_priv, power_well, false); 1060 } 1061 1062 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 1063 1064 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1065 int power_well_id) 1066 { 1067 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1068 int i; 1069 1070 for (i = 0; i < power_domains->power_well_count; i++) { 1071 struct i915_power_well *power_well; 1072 1073 power_well = &power_domains->power_wells[i]; 1074 if (power_well->data == power_well_id) 1075 return power_well; 1076 } 1077 1078 return NULL; 1079 } 1080 1081 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1082 1083 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1084 { 1085 struct i915_power_well *cmn_bc = 1086 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1087 struct i915_power_well *cmn_d = 1088 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1089 u32 phy_control = dev_priv->chv_phy_control; 1090 u32 phy_status = 0; 1091 u32 phy_status_mask = 0xffffffff; 1092 u32 tmp; 1093 1094 /* 1095 * The BIOS can leave the PHY is some weird state 1096 * where it doesn't fully power down some parts. 1097 * Disable the asserts until the PHY has been fully 1098 * reset (ie. the power well has been disabled at 1099 * least once). 1100 */ 1101 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1102 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1103 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1104 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1105 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1106 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1107 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1108 1109 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1110 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1111 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1112 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1113 1114 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1115 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1116 1117 /* this assumes override is only used to enable lanes */ 1118 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1119 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1120 1121 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1122 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1123 1124 /* CL1 is on whenever anything is on in either channel */ 1125 if (BITS_SET(phy_control, 1126 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1127 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1128 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1129 1130 /* 1131 * The DPLLB check accounts for the pipe B + port A usage 1132 * with CL2 powered up but all the lanes in the second channel 1133 * powered down. 1134 */ 1135 if (BITS_SET(phy_control, 1136 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1137 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1138 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1139 1140 if (BITS_SET(phy_control, 1141 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1142 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1143 if (BITS_SET(phy_control, 1144 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1145 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1146 1147 if (BITS_SET(phy_control, 1148 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1149 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1150 if (BITS_SET(phy_control, 1151 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1152 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1153 } 1154 1155 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1156 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1157 1158 /* this assumes override is only used to enable lanes */ 1159 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1160 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1161 1162 if (BITS_SET(phy_control, 1163 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1164 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1165 1166 if (BITS_SET(phy_control, 1167 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1168 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1169 if (BITS_SET(phy_control, 1170 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1171 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1172 } 1173 1174 phy_status &= phy_status_mask; 1175 1176 /* 1177 * The PHY may be busy with some initial calibration and whatnot, 1178 * so the power state can take a while to actually change. 1179 */ 1180 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) 1181 WARN(phy_status != tmp, 1182 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1183 tmp, phy_status, dev_priv->chv_phy_control); 1184 } 1185 1186 #undef BITS_SET 1187 1188 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1189 struct i915_power_well *power_well) 1190 { 1191 enum dpio_phy phy; 1192 enum i915_pipe pipe; 1193 uint32_t tmp; 1194 1195 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1196 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1197 1198 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1199 pipe = PIPE_A; 1200 phy = DPIO_PHY0; 1201 } else { 1202 pipe = PIPE_C; 1203 phy = DPIO_PHY1; 1204 } 1205 1206 /* since ref/cri clock was enabled */ 1207 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1208 vlv_set_power_well(dev_priv, power_well, true); 1209 1210 /* Poll for phypwrgood signal */ 1211 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) 1212 DRM_ERROR("Display PHY %d is not power up\n", phy); 1213 1214 mutex_lock(&dev_priv->sb_lock); 1215 1216 /* Enable dynamic power down */ 1217 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1218 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1219 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1220 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1221 1222 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1223 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1224 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1225 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1226 } else { 1227 /* 1228 * Force the non-existing CL2 off. BXT does this 1229 * too, so maybe it saves some power even though 1230 * CL2 doesn't exist? 1231 */ 1232 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1233 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1234 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1235 } 1236 1237 mutex_unlock(&dev_priv->sb_lock); 1238 1239 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1240 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1241 1242 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1243 phy, dev_priv->chv_phy_control); 1244 1245 assert_chv_phy_status(dev_priv); 1246 } 1247 1248 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1249 struct i915_power_well *power_well) 1250 { 1251 enum dpio_phy phy; 1252 1253 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1254 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1255 1256 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1257 phy = DPIO_PHY0; 1258 assert_pll_disabled(dev_priv, PIPE_A); 1259 assert_pll_disabled(dev_priv, PIPE_B); 1260 } else { 1261 phy = DPIO_PHY1; 1262 assert_pll_disabled(dev_priv, PIPE_C); 1263 } 1264 1265 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1266 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1267 1268 vlv_set_power_well(dev_priv, power_well, false); 1269 1270 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1271 phy, dev_priv->chv_phy_control); 1272 1273 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1274 dev_priv->chv_phy_assert[phy] = true; 1275 1276 assert_chv_phy_status(dev_priv); 1277 } 1278 1279 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1280 enum dpio_channel ch, bool override, unsigned int mask) 1281 { 1282 enum i915_pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1283 u32 reg, val, expected, actual; 1284 1285 /* 1286 * The BIOS can leave the PHY is some weird state 1287 * where it doesn't fully power down some parts. 1288 * Disable the asserts until the PHY has been fully 1289 * reset (ie. the power well has been disabled at 1290 * least once). 1291 */ 1292 if (!dev_priv->chv_phy_assert[phy]) 1293 return; 1294 1295 if (ch == DPIO_CH0) 1296 reg = _CHV_CMN_DW0_CH0; 1297 else 1298 reg = _CHV_CMN_DW6_CH1; 1299 1300 mutex_lock(&dev_priv->sb_lock); 1301 val = vlv_dpio_read(dev_priv, pipe, reg); 1302 mutex_unlock(&dev_priv->sb_lock); 1303 1304 /* 1305 * This assumes !override is only used when the port is disabled. 1306 * All lanes should power down even without the override when 1307 * the port is disabled. 1308 */ 1309 if (!override || mask == 0xf) { 1310 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1311 /* 1312 * If CH1 common lane is not active anymore 1313 * (eg. for pipe B DPLL) the entire channel will 1314 * shut down, which causes the common lane registers 1315 * to read as 0. That means we can't actually check 1316 * the lane power down status bits, but as the entire 1317 * register reads as 0 it's a good indication that the 1318 * channel is indeed entirely powered down. 1319 */ 1320 if (ch == DPIO_CH1 && val == 0) 1321 expected = 0; 1322 } else if (mask != 0x0) { 1323 expected = DPIO_ANYDL_POWERDOWN; 1324 } else { 1325 expected = 0; 1326 } 1327 1328 if (ch == DPIO_CH0) 1329 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1330 else 1331 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1332 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1333 1334 WARN(actual != expected, 1335 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1336 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1337 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1338 reg, val); 1339 } 1340 1341 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1342 enum dpio_channel ch, bool override) 1343 { 1344 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1345 bool was_override; 1346 1347 mutex_lock(&power_domains->lock); 1348 1349 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1350 1351 if (override == was_override) 1352 goto out; 1353 1354 if (override) 1355 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1356 else 1357 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1358 1359 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1360 1361 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1362 phy, ch, dev_priv->chv_phy_control); 1363 1364 assert_chv_phy_status(dev_priv); 1365 1366 out: 1367 mutex_unlock(&power_domains->lock); 1368 1369 return was_override; 1370 } 1371 1372 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1373 bool override, unsigned int mask) 1374 { 1375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1376 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1377 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1378 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1379 1380 mutex_lock(&power_domains->lock); 1381 1382 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1383 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1384 1385 if (override) 1386 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1387 else 1388 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1389 1390 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1391 1392 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1393 phy, ch, mask, dev_priv->chv_phy_control); 1394 1395 assert_chv_phy_status(dev_priv); 1396 1397 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1398 1399 mutex_unlock(&power_domains->lock); 1400 } 1401 1402 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1403 struct i915_power_well *power_well) 1404 { 1405 enum i915_pipe pipe = power_well->data; 1406 bool enabled; 1407 u32 state, ctrl; 1408 1409 mutex_lock(&dev_priv->rps.hw_lock); 1410 1411 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1412 /* 1413 * We only ever set the power-on and power-gate states, anything 1414 * else is unexpected. 1415 */ 1416 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1417 enabled = state == DP_SSS_PWR_ON(pipe); 1418 1419 /* 1420 * A transient state at this point would mean some unexpected party 1421 * is poking at the power controls too. 1422 */ 1423 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1424 WARN_ON(ctrl << 16 != state); 1425 1426 mutex_unlock(&dev_priv->rps.hw_lock); 1427 1428 return enabled; 1429 } 1430 1431 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1432 struct i915_power_well *power_well, 1433 bool enable) 1434 { 1435 enum i915_pipe pipe = power_well->data; 1436 u32 state; 1437 u32 ctrl; 1438 1439 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1440 1441 mutex_lock(&dev_priv->rps.hw_lock); 1442 1443 #define COND \ 1444 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1445 1446 if (COND) 1447 goto out; 1448 1449 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1450 ctrl &= ~DP_SSC_MASK(pipe); 1451 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1452 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1453 1454 if (wait_for(COND, 100)) 1455 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1456 state, 1457 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1458 1459 #undef COND 1460 1461 out: 1462 mutex_unlock(&dev_priv->rps.hw_lock); 1463 } 1464 1465 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1466 struct i915_power_well *power_well) 1467 { 1468 WARN_ON_ONCE(power_well->data != PIPE_A); 1469 1470 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 1471 } 1472 1473 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1474 struct i915_power_well *power_well) 1475 { 1476 WARN_ON_ONCE(power_well->data != PIPE_A); 1477 1478 chv_set_pipe_power_well(dev_priv, power_well, true); 1479 1480 vlv_display_power_well_init(dev_priv); 1481 } 1482 1483 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1484 struct i915_power_well *power_well) 1485 { 1486 WARN_ON_ONCE(power_well->data != PIPE_A); 1487 1488 vlv_display_power_well_deinit(dev_priv); 1489 1490 chv_set_pipe_power_well(dev_priv, power_well, false); 1491 } 1492 1493 static void 1494 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 1495 enum intel_display_power_domain domain) 1496 { 1497 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1498 struct i915_power_well *power_well; 1499 int i; 1500 1501 for_each_power_well(i, power_well, BIT(domain), power_domains) { 1502 if (!power_well->count++) 1503 intel_power_well_enable(dev_priv, power_well); 1504 } 1505 1506 power_domains->domain_use_count[domain]++; 1507 } 1508 1509 /** 1510 * intel_display_power_get - grab a power domain reference 1511 * @dev_priv: i915 device instance 1512 * @domain: power domain to reference 1513 * 1514 * This function grabs a power domain reference for @domain and ensures that the 1515 * power domain and all its parents are powered up. Therefore users should only 1516 * grab a reference to the innermost power domain they need. 1517 * 1518 * Any power domain reference obtained by this function must have a symmetric 1519 * call to intel_display_power_put() to release the reference again. 1520 */ 1521 void intel_display_power_get(struct drm_i915_private *dev_priv, 1522 enum intel_display_power_domain domain) 1523 { 1524 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1525 1526 intel_runtime_pm_get(dev_priv); 1527 1528 mutex_lock(&power_domains->lock); 1529 1530 __intel_display_power_get_domain(dev_priv, domain); 1531 1532 mutex_unlock(&power_domains->lock); 1533 } 1534 1535 /** 1536 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 1537 * @dev_priv: i915 device instance 1538 * @domain: power domain to reference 1539 * 1540 * This function grabs a power domain reference for @domain and ensures that the 1541 * power domain and all its parents are powered up. Therefore users should only 1542 * grab a reference to the innermost power domain they need. 1543 * 1544 * Any power domain reference obtained by this function must have a symmetric 1545 * call to intel_display_power_put() to release the reference again. 1546 */ 1547 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1548 enum intel_display_power_domain domain) 1549 { 1550 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1551 bool is_enabled; 1552 1553 if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1554 return false; 1555 1556 mutex_lock(&power_domains->lock); 1557 1558 if (__intel_display_power_is_enabled(dev_priv, domain)) { 1559 __intel_display_power_get_domain(dev_priv, domain); 1560 is_enabled = true; 1561 } else { 1562 is_enabled = false; 1563 } 1564 1565 mutex_unlock(&power_domains->lock); 1566 1567 if (!is_enabled) 1568 intel_runtime_pm_put(dev_priv); 1569 1570 return is_enabled; 1571 } 1572 1573 /** 1574 * intel_display_power_put - release a power domain reference 1575 * @dev_priv: i915 device instance 1576 * @domain: power domain to reference 1577 * 1578 * This function drops the power domain reference obtained by 1579 * intel_display_power_get() and might power down the corresponding hardware 1580 * block right away if this is the last reference. 1581 */ 1582 void intel_display_power_put(struct drm_i915_private *dev_priv, 1583 enum intel_display_power_domain domain) 1584 { 1585 struct i915_power_domains *power_domains; 1586 struct i915_power_well *power_well; 1587 int i; 1588 1589 power_domains = &dev_priv->power_domains; 1590 1591 mutex_lock(&power_domains->lock); 1592 1593 WARN(!power_domains->domain_use_count[domain], 1594 "Use count on domain %s is already zero\n", 1595 intel_display_power_domain_str(domain)); 1596 power_domains->domain_use_count[domain]--; 1597 1598 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 1599 WARN(!power_well->count, 1600 "Use count on power well %s is already zero", 1601 power_well->name); 1602 1603 if (!--power_well->count) 1604 intel_power_well_disable(dev_priv, power_well); 1605 } 1606 1607 mutex_unlock(&power_domains->lock); 1608 1609 intel_runtime_pm_put(dev_priv); 1610 } 1611 1612 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 1613 BIT(POWER_DOMAIN_PIPE_A) | \ 1614 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 1615 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1616 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1617 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1618 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1619 BIT(POWER_DOMAIN_PORT_CRT) | \ 1620 BIT(POWER_DOMAIN_PLLS) | \ 1621 BIT(POWER_DOMAIN_AUX_A) | \ 1622 BIT(POWER_DOMAIN_AUX_B) | \ 1623 BIT(POWER_DOMAIN_AUX_C) | \ 1624 BIT(POWER_DOMAIN_AUX_D) | \ 1625 BIT(POWER_DOMAIN_GMBUS) | \ 1626 BIT(POWER_DOMAIN_INIT)) 1627 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1628 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ 1629 BIT(POWER_DOMAIN_INIT)) 1630 1631 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 1632 HSW_ALWAYS_ON_POWER_DOMAINS | \ 1633 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 1634 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1635 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ 1636 BIT(POWER_DOMAIN_INIT)) 1637 1638 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) 1639 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK 1640 1641 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1642 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1643 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1644 BIT(POWER_DOMAIN_PORT_CRT) | \ 1645 BIT(POWER_DOMAIN_AUX_B) | \ 1646 BIT(POWER_DOMAIN_AUX_C) | \ 1647 BIT(POWER_DOMAIN_INIT)) 1648 1649 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1650 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1651 BIT(POWER_DOMAIN_AUX_B) | \ 1652 BIT(POWER_DOMAIN_INIT)) 1653 1654 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1655 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1656 BIT(POWER_DOMAIN_AUX_B) | \ 1657 BIT(POWER_DOMAIN_INIT)) 1658 1659 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1660 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1661 BIT(POWER_DOMAIN_AUX_C) | \ 1662 BIT(POWER_DOMAIN_INIT)) 1663 1664 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1665 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1666 BIT(POWER_DOMAIN_AUX_C) | \ 1667 BIT(POWER_DOMAIN_INIT)) 1668 1669 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1670 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1671 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1672 BIT(POWER_DOMAIN_AUX_B) | \ 1673 BIT(POWER_DOMAIN_AUX_C) | \ 1674 BIT(POWER_DOMAIN_INIT)) 1675 1676 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1677 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1678 BIT(POWER_DOMAIN_AUX_D) | \ 1679 BIT(POWER_DOMAIN_INIT)) 1680 1681 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1682 .sync_hw = i9xx_always_on_power_well_noop, 1683 .enable = i9xx_always_on_power_well_noop, 1684 .disable = i9xx_always_on_power_well_noop, 1685 .is_enabled = i9xx_always_on_power_well_enabled, 1686 }; 1687 1688 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1689 .sync_hw = chv_pipe_power_well_sync_hw, 1690 .enable = chv_pipe_power_well_enable, 1691 .disable = chv_pipe_power_well_disable, 1692 .is_enabled = chv_pipe_power_well_enabled, 1693 }; 1694 1695 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1696 .sync_hw = vlv_power_well_sync_hw, 1697 .enable = chv_dpio_cmn_power_well_enable, 1698 .disable = chv_dpio_cmn_power_well_disable, 1699 .is_enabled = vlv_power_well_enabled, 1700 }; 1701 1702 static struct i915_power_well i9xx_always_on_power_well[] = { 1703 { 1704 .name = "always-on", 1705 .always_on = 1, 1706 .domains = POWER_DOMAIN_MASK, 1707 .ops = &i9xx_always_on_power_well_ops, 1708 }, 1709 }; 1710 1711 static const struct i915_power_well_ops hsw_power_well_ops = { 1712 .sync_hw = hsw_power_well_sync_hw, 1713 .enable = hsw_power_well_enable, 1714 .disable = hsw_power_well_disable, 1715 .is_enabled = hsw_power_well_enabled, 1716 }; 1717 1718 static const struct i915_power_well_ops skl_power_well_ops = { 1719 .sync_hw = skl_power_well_sync_hw, 1720 .enable = skl_power_well_enable, 1721 .disable = skl_power_well_disable, 1722 .is_enabled = skl_power_well_enabled, 1723 }; 1724 1725 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1726 .sync_hw = gen9_dc_off_power_well_sync_hw, 1727 .enable = gen9_dc_off_power_well_enable, 1728 .disable = gen9_dc_off_power_well_disable, 1729 .is_enabled = gen9_dc_off_power_well_enabled, 1730 }; 1731 1732 static struct i915_power_well hsw_power_wells[] = { 1733 { 1734 .name = "always-on", 1735 .always_on = 1, 1736 .domains = HSW_ALWAYS_ON_POWER_DOMAINS, 1737 .ops = &i9xx_always_on_power_well_ops, 1738 }, 1739 { 1740 .name = "display", 1741 .domains = HSW_DISPLAY_POWER_DOMAINS, 1742 .ops = &hsw_power_well_ops, 1743 }, 1744 }; 1745 1746 static struct i915_power_well bdw_power_wells[] = { 1747 { 1748 .name = "always-on", 1749 .always_on = 1, 1750 .domains = BDW_ALWAYS_ON_POWER_DOMAINS, 1751 .ops = &i9xx_always_on_power_well_ops, 1752 }, 1753 { 1754 .name = "display", 1755 .domains = BDW_DISPLAY_POWER_DOMAINS, 1756 .ops = &hsw_power_well_ops, 1757 }, 1758 }; 1759 1760 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1761 .sync_hw = vlv_power_well_sync_hw, 1762 .enable = vlv_display_power_well_enable, 1763 .disable = vlv_display_power_well_disable, 1764 .is_enabled = vlv_power_well_enabled, 1765 }; 1766 1767 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1768 .sync_hw = vlv_power_well_sync_hw, 1769 .enable = vlv_dpio_cmn_power_well_enable, 1770 .disable = vlv_dpio_cmn_power_well_disable, 1771 .is_enabled = vlv_power_well_enabled, 1772 }; 1773 1774 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1775 .sync_hw = vlv_power_well_sync_hw, 1776 .enable = vlv_power_well_enable, 1777 .disable = vlv_power_well_disable, 1778 .is_enabled = vlv_power_well_enabled, 1779 }; 1780 1781 static struct i915_power_well vlv_power_wells[] = { 1782 { 1783 .name = "always-on", 1784 .always_on = 1, 1785 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1786 .ops = &i9xx_always_on_power_well_ops, 1787 .data = PUNIT_POWER_WELL_ALWAYS_ON, 1788 }, 1789 { 1790 .name = "display", 1791 .domains = VLV_DISPLAY_POWER_DOMAINS, 1792 .data = PUNIT_POWER_WELL_DISP2D, 1793 .ops = &vlv_display_power_well_ops, 1794 }, 1795 { 1796 .name = "dpio-tx-b-01", 1797 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1798 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1799 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1800 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1801 .ops = &vlv_dpio_power_well_ops, 1802 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 1803 }, 1804 { 1805 .name = "dpio-tx-b-23", 1806 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1807 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1808 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1809 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1810 .ops = &vlv_dpio_power_well_ops, 1811 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 1812 }, 1813 { 1814 .name = "dpio-tx-c-01", 1815 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1816 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1817 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1818 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1819 .ops = &vlv_dpio_power_well_ops, 1820 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 1821 }, 1822 { 1823 .name = "dpio-tx-c-23", 1824 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1825 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1826 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1827 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1828 .ops = &vlv_dpio_power_well_ops, 1829 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 1830 }, 1831 { 1832 .name = "dpio-common", 1833 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 1834 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1835 .ops = &vlv_dpio_cmn_power_well_ops, 1836 }, 1837 }; 1838 1839 static struct i915_power_well chv_power_wells[] = { 1840 { 1841 .name = "always-on", 1842 .always_on = 1, 1843 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1844 .ops = &i9xx_always_on_power_well_ops, 1845 }, 1846 { 1847 .name = "display", 1848 /* 1849 * Pipe A power well is the new disp2d well. Pipe B and C 1850 * power wells don't actually exist. Pipe A power well is 1851 * required for any pipe to work. 1852 */ 1853 .domains = VLV_DISPLAY_POWER_DOMAINS, 1854 .data = PIPE_A, 1855 .ops = &chv_pipe_power_well_ops, 1856 }, 1857 { 1858 .name = "dpio-common-bc", 1859 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 1860 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1861 .ops = &chv_dpio_cmn_power_well_ops, 1862 }, 1863 { 1864 .name = "dpio-common-d", 1865 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 1866 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 1867 .ops = &chv_dpio_cmn_power_well_ops, 1868 }, 1869 }; 1870 1871 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 1872 int power_well_id) 1873 { 1874 struct i915_power_well *power_well; 1875 bool ret; 1876 1877 power_well = lookup_power_well(dev_priv, power_well_id); 1878 ret = power_well->ops->is_enabled(dev_priv, power_well); 1879 1880 return ret; 1881 } 1882 1883 static struct i915_power_well skl_power_wells[] = { 1884 { 1885 .name = "always-on", 1886 .always_on = 1, 1887 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1888 .ops = &i9xx_always_on_power_well_ops, 1889 .data = SKL_DISP_PW_ALWAYS_ON, 1890 }, 1891 { 1892 .name = "power well 1", 1893 /* Handled by the DMC firmware */ 1894 .domains = 0, 1895 .ops = &skl_power_well_ops, 1896 .data = SKL_DISP_PW_1, 1897 }, 1898 { 1899 .name = "MISC IO power well", 1900 /* Handled by the DMC firmware */ 1901 .domains = 0, 1902 .ops = &skl_power_well_ops, 1903 .data = SKL_DISP_PW_MISC_IO, 1904 }, 1905 { 1906 .name = "DC off", 1907 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 1908 .ops = &gen9_dc_off_power_well_ops, 1909 .data = SKL_DISP_PW_DC_OFF, 1910 }, 1911 { 1912 .name = "power well 2", 1913 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1914 .ops = &skl_power_well_ops, 1915 .data = SKL_DISP_PW_2, 1916 }, 1917 { 1918 .name = "DDI A/E power well", 1919 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, 1920 .ops = &skl_power_well_ops, 1921 .data = SKL_DISP_PW_DDI_A_E, 1922 }, 1923 { 1924 .name = "DDI B power well", 1925 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, 1926 .ops = &skl_power_well_ops, 1927 .data = SKL_DISP_PW_DDI_B, 1928 }, 1929 { 1930 .name = "DDI C power well", 1931 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, 1932 .ops = &skl_power_well_ops, 1933 .data = SKL_DISP_PW_DDI_C, 1934 }, 1935 { 1936 .name = "DDI D power well", 1937 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, 1938 .ops = &skl_power_well_ops, 1939 .data = SKL_DISP_PW_DDI_D, 1940 }, 1941 }; 1942 1943 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv) 1944 { 1945 struct i915_power_well *well; 1946 1947 if (!IS_SKYLAKE(dev_priv)) 1948 return; 1949 1950 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1951 intel_power_well_enable(dev_priv, well); 1952 1953 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 1954 intel_power_well_enable(dev_priv, well); 1955 } 1956 1957 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv) 1958 { 1959 struct i915_power_well *well; 1960 1961 if (!IS_SKYLAKE(dev_priv)) 1962 return; 1963 1964 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1965 intel_power_well_disable(dev_priv, well); 1966 1967 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 1968 intel_power_well_disable(dev_priv, well); 1969 } 1970 1971 static struct i915_power_well bxt_power_wells[] = { 1972 { 1973 .name = "always-on", 1974 .always_on = 1, 1975 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1976 .ops = &i9xx_always_on_power_well_ops, 1977 }, 1978 { 1979 .name = "power well 1", 1980 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, 1981 .ops = &skl_power_well_ops, 1982 .data = SKL_DISP_PW_1, 1983 }, 1984 { 1985 .name = "DC off", 1986 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 1987 .ops = &gen9_dc_off_power_well_ops, 1988 .data = SKL_DISP_PW_DC_OFF, 1989 }, 1990 { 1991 .name = "power well 2", 1992 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1993 .ops = &skl_power_well_ops, 1994 .data = SKL_DISP_PW_2, 1995 }, 1996 }; 1997 1998 static int 1999 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 2000 int disable_power_well) 2001 { 2002 if (disable_power_well >= 0) 2003 return !!disable_power_well; 2004 2005 if (IS_BROXTON(dev_priv)) { 2006 DRM_DEBUG_KMS("Disabling display power well support\n"); 2007 return 0; 2008 } 2009 2010 return 1; 2011 } 2012 2013 #define set_power_wells(power_domains, __power_wells) ({ \ 2014 (power_domains)->power_wells = (__power_wells); \ 2015 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 2016 }) 2017 2018 /** 2019 * intel_power_domains_init - initializes the power domain structures 2020 * @dev_priv: i915 device instance 2021 * 2022 * Initializes the power domain structures for @dev_priv depending upon the 2023 * supported platform. 2024 */ 2025 int intel_power_domains_init(struct drm_i915_private *dev_priv) 2026 { 2027 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2028 2029 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, 2030 i915.disable_power_well); 2031 2032 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); 2033 2034 lockinit(&power_domains->lock, "i915pl", 0, LK_CANRECURSE); 2035 2036 /* 2037 * The enabling order will be from lower to higher indexed wells, 2038 * the disabling order is reversed. 2039 */ 2040 if (IS_HASWELL(dev_priv->dev)) { 2041 set_power_wells(power_domains, hsw_power_wells); 2042 } else if (IS_BROADWELL(dev_priv->dev)) { 2043 set_power_wells(power_domains, bdw_power_wells); 2044 } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) { 2045 set_power_wells(power_domains, skl_power_wells); 2046 } else if (IS_BROXTON(dev_priv->dev)) { 2047 set_power_wells(power_domains, bxt_power_wells); 2048 } else if (IS_CHERRYVIEW(dev_priv->dev)) { 2049 set_power_wells(power_domains, chv_power_wells); 2050 } else if (IS_VALLEYVIEW(dev_priv->dev)) { 2051 set_power_wells(power_domains, vlv_power_wells); 2052 } else { 2053 set_power_wells(power_domains, i9xx_always_on_power_well); 2054 } 2055 2056 return 0; 2057 } 2058 2059 /** 2060 * intel_power_domains_fini - finalizes the power domain structures 2061 * @dev_priv: i915 device instance 2062 * 2063 * Finalizes the power domain structures for @dev_priv depending upon the 2064 * supported platform. This function also disables runtime pm and ensures that 2065 * the device stays powered up so that the driver can be reloaded. 2066 */ 2067 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 2068 { 2069 #if 0 2070 struct device *device = &dev_priv->dev->pdev->dev; 2071 #endif 2072 2073 /* 2074 * The i915.ko module is still not prepared to be loaded when 2075 * the power well is not enabled, so just enable it in case 2076 * we're going to unload/reload. 2077 * The following also reacquires the RPM reference the core passed 2078 * to the driver during loading, which is dropped in 2079 * intel_runtime_pm_enable(). We have to hand back the control of the 2080 * device to the core with this reference held. 2081 */ 2082 intel_display_set_init_power(dev_priv, true); 2083 2084 /* Remove the refcount we took to keep power well support disabled. */ 2085 if (!i915.disable_power_well) 2086 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2087 2088 /* 2089 * Remove the refcount we took in intel_runtime_pm_enable() in case 2090 * the platform doesn't support runtime PM. 2091 */ 2092 #if 0 2093 if (!HAS_RUNTIME_PM(dev_priv)) 2094 pm_runtime_put(device); 2095 #endif 2096 } 2097 2098 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 2099 { 2100 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2101 struct i915_power_well *power_well; 2102 int i; 2103 2104 mutex_lock(&power_domains->lock); 2105 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 2106 power_well->ops->sync_hw(dev_priv, power_well); 2107 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 2108 power_well); 2109 } 2110 mutex_unlock(&power_domains->lock); 2111 } 2112 2113 static void skl_display_core_init(struct drm_i915_private *dev_priv, 2114 bool resume) 2115 { 2116 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2117 uint32_t val; 2118 2119 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2120 2121 /* enable PCH reset handshake */ 2122 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2123 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 2124 2125 /* enable PG1 and Misc I/O */ 2126 mutex_lock(&power_domains->lock); 2127 skl_pw1_misc_io_init(dev_priv); 2128 mutex_unlock(&power_domains->lock); 2129 2130 if (!resume) 2131 return; 2132 2133 skl_init_cdclk(dev_priv); 2134 2135 if (dev_priv->csr.dmc_payload) 2136 intel_csr_load_program(dev_priv); 2137 } 2138 2139 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 2140 { 2141 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2142 2143 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2144 2145 skl_uninit_cdclk(dev_priv); 2146 2147 /* The spec doesn't call for removing the reset handshake flag */ 2148 /* disable PG1 and Misc I/O */ 2149 mutex_lock(&power_domains->lock); 2150 skl_pw1_misc_io_fini(dev_priv); 2151 mutex_unlock(&power_domains->lock); 2152 } 2153 2154 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 2155 { 2156 struct i915_power_well *cmn_bc = 2157 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2158 struct i915_power_well *cmn_d = 2159 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 2160 2161 /* 2162 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 2163 * workaround never ever read DISPLAY_PHY_CONTROL, and 2164 * instead maintain a shadow copy ourselves. Use the actual 2165 * power well state and lane status to reconstruct the 2166 * expected initial value. 2167 */ 2168 dev_priv->chv_phy_control = 2169 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 2170 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 2171 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 2172 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 2173 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 2174 2175 /* 2176 * If all lanes are disabled we leave the override disabled 2177 * with all power down bits cleared to match the state we 2178 * would use after disabling the port. Otherwise enable the 2179 * override and set the lane powerdown bits accding to the 2180 * current lane status. 2181 */ 2182 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 2183 uint32_t status = I915_READ(DPLL(PIPE_A)); 2184 unsigned int mask; 2185 2186 mask = status & DPLL_PORTB_READY_MASK; 2187 if (mask == 0xf) 2188 mask = 0x0; 2189 else 2190 dev_priv->chv_phy_control |= 2191 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 2192 2193 dev_priv->chv_phy_control |= 2194 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 2195 2196 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 2197 if (mask == 0xf) 2198 mask = 0x0; 2199 else 2200 dev_priv->chv_phy_control |= 2201 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 2202 2203 dev_priv->chv_phy_control |= 2204 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 2205 2206 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 2207 2208 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 2209 } else { 2210 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 2211 } 2212 2213 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 2214 uint32_t status = I915_READ(DPIO_PHY_STATUS); 2215 unsigned int mask; 2216 2217 mask = status & DPLL_PORTD_READY_MASK; 2218 2219 if (mask == 0xf) 2220 mask = 0x0; 2221 else 2222 dev_priv->chv_phy_control |= 2223 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 2224 2225 dev_priv->chv_phy_control |= 2226 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 2227 2228 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 2229 2230 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 2231 } else { 2232 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 2233 } 2234 2235 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 2236 2237 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 2238 dev_priv->chv_phy_control); 2239 } 2240 2241 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 2242 { 2243 struct i915_power_well *cmn = 2244 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2245 struct i915_power_well *disp2d = 2246 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 2247 2248 /* If the display might be already active skip this */ 2249 if (cmn->ops->is_enabled(dev_priv, cmn) && 2250 disp2d->ops->is_enabled(dev_priv, disp2d) && 2251 I915_READ(DPIO_CTL) & DPIO_CMNRST) 2252 return; 2253 2254 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 2255 2256 /* cmnlane needs DPLL registers */ 2257 disp2d->ops->enable(dev_priv, disp2d); 2258 2259 /* 2260 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 2261 * Need to assert and de-assert PHY SB reset by gating the 2262 * common lane power, then un-gating it. 2263 * Simply ungating isn't enough to reset the PHY enough to get 2264 * ports and lanes running. 2265 */ 2266 cmn->ops->disable(dev_priv, cmn); 2267 } 2268 2269 /** 2270 * intel_power_domains_init_hw - initialize hardware power domain state 2271 * @dev_priv: i915 device instance 2272 * 2273 * This function initializes the hardware power domain state and enables all 2274 * power domains using intel_display_set_init_power(). 2275 */ 2276 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 2277 { 2278 struct drm_device *dev = dev_priv->dev; 2279 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2280 2281 power_domains->initializing = true; 2282 2283 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 2284 skl_display_core_init(dev_priv, resume); 2285 } else if (IS_CHERRYVIEW(dev)) { 2286 mutex_lock(&power_domains->lock); 2287 chv_phy_control_init(dev_priv); 2288 mutex_unlock(&power_domains->lock); 2289 } else if (IS_VALLEYVIEW(dev)) { 2290 mutex_lock(&power_domains->lock); 2291 vlv_cmnlane_wa(dev_priv); 2292 mutex_unlock(&power_domains->lock); 2293 } 2294 2295 /* For now, we need the power well to be always enabled. */ 2296 intel_display_set_init_power(dev_priv, true); 2297 /* Disable power support if the user asked so. */ 2298 if (!i915.disable_power_well) 2299 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 2300 intel_power_domains_sync_hw(dev_priv); 2301 power_domains->initializing = false; 2302 } 2303 2304 /** 2305 * intel_power_domains_suspend - suspend power domain state 2306 * @dev_priv: i915 device instance 2307 * 2308 * This function prepares the hardware power domain state before entering 2309 * system suspend. It must be paired with intel_power_domains_init_hw(). 2310 */ 2311 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 2312 { 2313 /* 2314 * Even if power well support was disabled we still want to disable 2315 * power wells while we are system suspended. 2316 */ 2317 if (!i915.disable_power_well) 2318 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2319 2320 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 2321 skl_display_core_uninit(dev_priv); 2322 } 2323 2324 /** 2325 * intel_runtime_pm_get - grab a runtime pm reference 2326 * @dev_priv: i915 device instance 2327 * 2328 * This function grabs a device-level runtime pm reference (mostly used for GEM 2329 * code to ensure the GTT or GT is on) and ensures that it is powered up. 2330 * 2331 * Any runtime pm reference obtained by this function must have a symmetric 2332 * call to intel_runtime_pm_put() to release the reference again. 2333 */ 2334 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 2335 { 2336 #if 0 2337 struct drm_device *dev = dev_priv->dev; 2338 struct device *device = &dev->pdev->dev; 2339 2340 pm_runtime_get_sync(device); 2341 #endif 2342 2343 atomic_inc(&dev_priv->pm.wakeref_count); 2344 assert_rpm_wakelock_held(dev_priv); 2345 } 2346 2347 /** 2348 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 2349 * @dev_priv: i915 device instance 2350 * 2351 * This function grabs a device-level runtime pm reference if the device is 2352 * already in use and ensures that it is powered up. 2353 * 2354 * Any runtime pm reference obtained by this function must have a symmetric 2355 * call to intel_runtime_pm_put() to release the reference again. 2356 */ 2357 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) 2358 { 2359 #ifndef __DragonFly__ 2360 struct drm_device *dev = dev_priv->dev; 2361 struct device *device = &dev->pdev->dev; 2362 2363 if (IS_ENABLED(CONFIG_PM)) { 2364 int ret = pm_runtime_get_if_in_use(device); 2365 2366 /* 2367 * In cases runtime PM is disabled by the RPM core and we get 2368 * an -EINVAL return value we are not supposed to call this 2369 * function, since the power state is undefined. This applies 2370 * atm to the late/early system suspend/resume handlers. 2371 */ 2372 WARN_ON_ONCE(ret < 0); 2373 if (ret <= 0) 2374 return false; 2375 } 2376 2377 atomic_inc(&dev_priv->pm.wakeref_count); 2378 assert_rpm_wakelock_held(dev_priv); 2379 #endif 2380 2381 return true; 2382 } 2383 2384 /** 2385 * intel_runtime_pm_get_noresume - grab a runtime pm reference 2386 * @dev_priv: i915 device instance 2387 * 2388 * This function grabs a device-level runtime pm reference (mostly used for GEM 2389 * code to ensure the GTT or GT is on). 2390 * 2391 * It will _not_ power up the device but instead only check that it's powered 2392 * on. Therefore it is only valid to call this functions from contexts where 2393 * the device is known to be powered up and where trying to power it up would 2394 * result in hilarity and deadlocks. That pretty much means only the system 2395 * suspend/resume code where this is used to grab runtime pm references for 2396 * delayed setup down in work items. 2397 * 2398 * Any runtime pm reference obtained by this function must have a symmetric 2399 * call to intel_runtime_pm_put() to release the reference again. 2400 */ 2401 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 2402 { 2403 #if 0 2404 struct drm_device *dev = dev_priv->dev; 2405 struct device *device = &dev->pdev->dev; 2406 #endif 2407 2408 assert_rpm_wakelock_held(dev_priv); 2409 #if 0 2410 pm_runtime_get_noresume(device); 2411 #endif 2412 2413 atomic_inc(&dev_priv->pm.wakeref_count); 2414 } 2415 2416 /** 2417 * intel_runtime_pm_put - release a runtime pm reference 2418 * @dev_priv: i915 device instance 2419 * 2420 * This function drops the device-level runtime pm reference obtained by 2421 * intel_runtime_pm_get() and might power down the corresponding 2422 * hardware block right away if this is the last reference. 2423 */ 2424 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 2425 { 2426 #if 0 2427 struct drm_device *dev = dev_priv->dev; 2428 struct device *device = &dev->pdev->dev; 2429 2430 assert_rpm_wakelock_held(dev_priv); 2431 if (atomic_dec_and_test(&dev_priv->pm.wakeref_count)) 2432 atomic_inc(&dev_priv->pm.atomic_seq); 2433 2434 pm_runtime_mark_last_busy(device); 2435 pm_runtime_put_autosuspend(device); 2436 #endif 2437 } 2438 2439 /** 2440 * intel_runtime_pm_enable - enable runtime pm 2441 * @dev_priv: i915 device instance 2442 * 2443 * This function enables runtime pm at the end of the driver load sequence. 2444 * 2445 * Note that this function does currently not enable runtime pm for the 2446 * subordinate display power domains. That is only done on the first modeset 2447 * using intel_display_set_init_power(). 2448 */ 2449 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 2450 { 2451 #if 0 2452 struct drm_device *dev = dev_priv->dev; 2453 struct device *device = &dev->pdev->dev; 2454 2455 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 2456 pm_runtime_mark_last_busy(device); 2457 2458 /* 2459 * Take a permanent reference to disable the RPM functionality and drop 2460 * it only when unloading the driver. Use the low level get/put helpers, 2461 * so the driver's own RPM reference tracking asserts also work on 2462 * platforms without RPM support. 2463 */ 2464 if (!HAS_RUNTIME_PM(dev)) { 2465 pm_runtime_dont_use_autosuspend(device); 2466 pm_runtime_get_sync(device); 2467 } else { 2468 pm_runtime_use_autosuspend(device); 2469 } 2470 2471 /* 2472 * The core calls the driver load handler with an RPM reference held. 2473 * We drop that here and will reacquire it during unloading in 2474 * intel_power_domains_fini(). 2475 */ 2476 pm_runtime_put_autosuspend(device); 2477 #endif 2478 } 2479 2480