1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include <linux/pm_runtime.h> 30 #include <linux/vgaarb.h> 31 32 #include "i915_drv.h" 33 #include "intel_drv.h" 34 35 /** 36 * DOC: runtime pm 37 * 38 * The i915 driver supports dynamic enabling and disabling of entire hardware 39 * blocks at runtime. This is especially important on the display side where 40 * software is supposed to control many power gates manually on recent hardware, 41 * since on the GT side a lot of the power management is done by the hardware. 42 * But even there some manual control at the device level is required. 43 * 44 * Since i915 supports a diverse set of platforms with a unified codebase and 45 * hardware engineers just love to shuffle functionality around between power 46 * domains there's a sizeable amount of indirection required. This file provides 47 * generic functions to the driver for grabbing and releasing references for 48 * abstract power domains. It then maps those to the actual power wells 49 * present for a given platform. 50 */ 51 52 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 53 for (i = 0; \ 54 i < (power_domains)->power_well_count && \ 55 ((power_well) = &(power_domains)->power_wells[i]); \ 56 i++) \ 57 for_each_if ((power_well)->domains & (domain_mask)) 58 59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 60 for (i = (power_domains)->power_well_count - 1; \ 61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 62 i--) \ 63 for_each_if ((power_well)->domains & (domain_mask)) 64 65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 66 int power_well_id); 67 68 static struct i915_power_well * 69 lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id); 70 71 const char * 72 intel_display_power_domain_str(enum intel_display_power_domain domain) 73 { 74 switch (domain) { 75 case POWER_DOMAIN_PIPE_A: 76 return "PIPE_A"; 77 case POWER_DOMAIN_PIPE_B: 78 return "PIPE_B"; 79 case POWER_DOMAIN_PIPE_C: 80 return "PIPE_C"; 81 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 82 return "PIPE_A_PANEL_FITTER"; 83 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 84 return "PIPE_B_PANEL_FITTER"; 85 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 86 return "PIPE_C_PANEL_FITTER"; 87 case POWER_DOMAIN_TRANSCODER_A: 88 return "TRANSCODER_A"; 89 case POWER_DOMAIN_TRANSCODER_B: 90 return "TRANSCODER_B"; 91 case POWER_DOMAIN_TRANSCODER_C: 92 return "TRANSCODER_C"; 93 case POWER_DOMAIN_TRANSCODER_EDP: 94 return "TRANSCODER_EDP"; 95 case POWER_DOMAIN_TRANSCODER_DSI_A: 96 return "TRANSCODER_DSI_A"; 97 case POWER_DOMAIN_TRANSCODER_DSI_C: 98 return "TRANSCODER_DSI_C"; 99 case POWER_DOMAIN_PORT_DDI_A_LANES: 100 return "PORT_DDI_A_LANES"; 101 case POWER_DOMAIN_PORT_DDI_B_LANES: 102 return "PORT_DDI_B_LANES"; 103 case POWER_DOMAIN_PORT_DDI_C_LANES: 104 return "PORT_DDI_C_LANES"; 105 case POWER_DOMAIN_PORT_DDI_D_LANES: 106 return "PORT_DDI_D_LANES"; 107 case POWER_DOMAIN_PORT_DDI_E_LANES: 108 return "PORT_DDI_E_LANES"; 109 case POWER_DOMAIN_PORT_DSI: 110 return "PORT_DSI"; 111 case POWER_DOMAIN_PORT_CRT: 112 return "PORT_CRT"; 113 case POWER_DOMAIN_PORT_OTHER: 114 return "PORT_OTHER"; 115 case POWER_DOMAIN_VGA: 116 return "VGA"; 117 case POWER_DOMAIN_AUDIO: 118 return "AUDIO"; 119 case POWER_DOMAIN_PLLS: 120 return "PLLS"; 121 case POWER_DOMAIN_AUX_A: 122 return "AUX_A"; 123 case POWER_DOMAIN_AUX_B: 124 return "AUX_B"; 125 case POWER_DOMAIN_AUX_C: 126 return "AUX_C"; 127 case POWER_DOMAIN_AUX_D: 128 return "AUX_D"; 129 case POWER_DOMAIN_GMBUS: 130 return "GMBUS"; 131 case POWER_DOMAIN_INIT: 132 return "INIT"; 133 case POWER_DOMAIN_MODESET: 134 return "MODESET"; 135 default: 136 MISSING_CASE(domain); 137 return "?"; 138 } 139 } 140 141 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 142 struct i915_power_well *power_well) 143 { 144 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 145 power_well->ops->enable(dev_priv, power_well); 146 power_well->hw_enabled = true; 147 } 148 149 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 150 struct i915_power_well *power_well) 151 { 152 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 153 power_well->hw_enabled = false; 154 power_well->ops->disable(dev_priv, power_well); 155 } 156 157 static void intel_power_well_get(struct drm_i915_private *dev_priv, 158 struct i915_power_well *power_well) 159 { 160 if (!power_well->count++) 161 intel_power_well_enable(dev_priv, power_well); 162 } 163 164 static void intel_power_well_put(struct drm_i915_private *dev_priv, 165 struct i915_power_well *power_well) 166 { 167 WARN(!power_well->count, "Use count on power well %s is already zero", 168 power_well->name); 169 170 if (!--power_well->count) 171 intel_power_well_disable(dev_priv, power_well); 172 } 173 174 /* 175 * We should only use the power well if we explicitly asked the hardware to 176 * enable it, so check if it's enabled and also check if we've requested it to 177 * be enabled. 178 */ 179 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 180 struct i915_power_well *power_well) 181 { 182 return I915_READ(HSW_PWR_WELL_DRIVER) == 183 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 184 } 185 186 /** 187 * __intel_display_power_is_enabled - unlocked check for a power domain 188 * @dev_priv: i915 device instance 189 * @domain: power domain to check 190 * 191 * This is the unlocked version of intel_display_power_is_enabled() and should 192 * only be used from error capture and recovery code where deadlocks are 193 * possible. 194 * 195 * Returns: 196 * True when the power domain is enabled, false otherwise. 197 */ 198 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 199 enum intel_display_power_domain domain) 200 { 201 struct i915_power_domains *power_domains; 202 struct i915_power_well *power_well; 203 bool is_enabled; 204 int i; 205 206 if (dev_priv->pm.suspended) 207 return false; 208 209 power_domains = &dev_priv->power_domains; 210 211 is_enabled = true; 212 213 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 214 if (power_well->always_on) 215 continue; 216 217 if (!power_well->hw_enabled) { 218 is_enabled = false; 219 break; 220 } 221 } 222 223 return is_enabled; 224 } 225 226 /** 227 * intel_display_power_is_enabled - check for a power domain 228 * @dev_priv: i915 device instance 229 * @domain: power domain to check 230 * 231 * This function can be used to check the hw power domain state. It is mostly 232 * used in hardware state readout functions. Everywhere else code should rely 233 * upon explicit power domain reference counting to ensure that the hardware 234 * block is powered up before accessing it. 235 * 236 * Callers must hold the relevant modesetting locks to ensure that concurrent 237 * threads can't disable the power well while the caller tries to read a few 238 * registers. 239 * 240 * Returns: 241 * True when the power domain is enabled, false otherwise. 242 */ 243 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 244 enum intel_display_power_domain domain) 245 { 246 struct i915_power_domains *power_domains; 247 bool ret; 248 249 power_domains = &dev_priv->power_domains; 250 251 mutex_lock(&power_domains->lock); 252 ret = __intel_display_power_is_enabled(dev_priv, domain); 253 mutex_unlock(&power_domains->lock); 254 255 return ret; 256 } 257 258 /** 259 * intel_display_set_init_power - set the initial power domain state 260 * @dev_priv: i915 device instance 261 * @enable: whether to enable or disable the initial power domain state 262 * 263 * For simplicity our driver load/unload and system suspend/resume code assumes 264 * that all power domains are always enabled. This functions controls the state 265 * of this little hack. While the initial power domain state is enabled runtime 266 * pm is effectively disabled. 267 */ 268 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 269 bool enable) 270 { 271 if (dev_priv->power_domains.init_power_on == enable) 272 return; 273 274 if (enable) 275 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 276 else 277 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 278 279 dev_priv->power_domains.init_power_on = enable; 280 } 281 282 /* 283 * Starting with Haswell, we have a "Power Down Well" that can be turned off 284 * when not needed anymore. We have 4 registers that can request the power well 285 * to be enabled, and it will only be disabled if none of the registers is 286 * requesting it to be enabled. 287 */ 288 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 289 { 290 struct drm_device *dev = &dev_priv->drm; 291 292 /* 293 * After we re-enable the power well, if we touch VGA register 0x3d5 294 * we'll get unclaimed register interrupts. This stops after we write 295 * anything to the VGA MSR register. The vgacon module uses this 296 * register all the time, so if we unbind our driver and, as a 297 * consequence, bind vgacon, we'll get stuck in an infinite loop at 298 * console_unlock(). So make here we touch the VGA MSR register, making 299 * sure vgacon can keep working normally without triggering interrupts 300 * and error messages. 301 */ 302 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 303 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 304 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 305 306 if (IS_BROADWELL(dev)) 307 gen8_irq_power_well_post_enable(dev_priv, 308 1 << PIPE_C | 1 << PIPE_B); 309 } 310 311 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv) 312 { 313 if (IS_BROADWELL(dev_priv)) 314 gen8_irq_power_well_pre_disable(dev_priv, 315 1 << PIPE_C | 1 << PIPE_B); 316 } 317 318 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, 319 struct i915_power_well *power_well) 320 { 321 struct drm_device *dev = &dev_priv->drm; 322 323 /* 324 * After we re-enable the power well, if we touch VGA register 0x3d5 325 * we'll get unclaimed register interrupts. This stops after we write 326 * anything to the VGA MSR register. The vgacon module uses this 327 * register all the time, so if we unbind our driver and, as a 328 * consequence, bind vgacon, we'll get stuck in an infinite loop at 329 * console_unlock(). So make here we touch the VGA MSR register, making 330 * sure vgacon can keep working normally without triggering interrupts 331 * and error messages. 332 */ 333 if (power_well->data == SKL_DISP_PW_2) { 334 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 335 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 336 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 337 338 gen8_irq_power_well_post_enable(dev_priv, 339 1 << PIPE_C | 1 << PIPE_B); 340 } 341 } 342 343 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, 344 struct i915_power_well *power_well) 345 { 346 if (power_well->data == SKL_DISP_PW_2) 347 gen8_irq_power_well_pre_disable(dev_priv, 348 1 << PIPE_C | 1 << PIPE_B); 349 } 350 351 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 352 struct i915_power_well *power_well, bool enable) 353 { 354 bool is_enabled, enable_requested; 355 uint32_t tmp; 356 357 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 358 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 359 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 360 361 if (enable) { 362 if (!enable_requested) 363 I915_WRITE(HSW_PWR_WELL_DRIVER, 364 HSW_PWR_WELL_ENABLE_REQUEST); 365 366 if (!is_enabled) { 367 DRM_DEBUG_KMS("Enabling power well\n"); 368 if (intel_wait_for_register(dev_priv, 369 HSW_PWR_WELL_DRIVER, 370 HSW_PWR_WELL_STATE_ENABLED, 371 HSW_PWR_WELL_STATE_ENABLED, 372 20)) 373 DRM_ERROR("Timeout enabling power well\n"); 374 hsw_power_well_post_enable(dev_priv); 375 } 376 377 } else { 378 if (enable_requested) { 379 hsw_power_well_pre_disable(dev_priv); 380 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 381 POSTING_READ(HSW_PWR_WELL_DRIVER); 382 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 383 } 384 } 385 } 386 387 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 388 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 389 BIT(POWER_DOMAIN_PIPE_B) | \ 390 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 391 BIT(POWER_DOMAIN_PIPE_C) | \ 392 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 393 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 394 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 395 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 396 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 397 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 398 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 399 BIT(POWER_DOMAIN_AUX_B) | \ 400 BIT(POWER_DOMAIN_AUX_C) | \ 401 BIT(POWER_DOMAIN_AUX_D) | \ 402 BIT(POWER_DOMAIN_AUDIO) | \ 403 BIT(POWER_DOMAIN_VGA) | \ 404 BIT(POWER_DOMAIN_INIT)) 405 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ 406 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 407 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 408 BIT(POWER_DOMAIN_INIT)) 409 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ 410 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 411 BIT(POWER_DOMAIN_INIT)) 412 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ 413 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 414 BIT(POWER_DOMAIN_INIT)) 415 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ 416 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 417 BIT(POWER_DOMAIN_INIT)) 418 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 419 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 420 BIT(POWER_DOMAIN_MODESET) | \ 421 BIT(POWER_DOMAIN_AUX_A) | \ 422 BIT(POWER_DOMAIN_INIT)) 423 424 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 425 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 426 BIT(POWER_DOMAIN_PIPE_B) | \ 427 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 428 BIT(POWER_DOMAIN_PIPE_C) | \ 429 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 430 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 431 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 432 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 433 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 434 BIT(POWER_DOMAIN_AUX_B) | \ 435 BIT(POWER_DOMAIN_AUX_C) | \ 436 BIT(POWER_DOMAIN_AUDIO) | \ 437 BIT(POWER_DOMAIN_VGA) | \ 438 BIT(POWER_DOMAIN_GMBUS) | \ 439 BIT(POWER_DOMAIN_INIT)) 440 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 441 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 442 BIT(POWER_DOMAIN_MODESET) | \ 443 BIT(POWER_DOMAIN_AUX_A) | \ 444 BIT(POWER_DOMAIN_INIT)) 445 #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \ 446 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 447 BIT(POWER_DOMAIN_AUX_A) | \ 448 BIT(POWER_DOMAIN_INIT)) 449 #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \ 450 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 451 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 452 BIT(POWER_DOMAIN_AUX_B) | \ 453 BIT(POWER_DOMAIN_AUX_C) | \ 454 BIT(POWER_DOMAIN_INIT)) 455 456 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 457 { 458 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 459 "DC9 already programmed to be enabled.\n"); 460 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 461 "DC5 still not disabled to enable DC9.\n"); 462 WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); 463 WARN_ONCE(intel_irqs_enabled(dev_priv), 464 "Interrupts not disabled yet.\n"); 465 466 /* 467 * TODO: check for the following to verify the conditions to enter DC9 468 * state are satisfied: 469 * 1] Check relevant display engine registers to verify if mode set 470 * disable sequence was followed. 471 * 2] Check if display uninitialize sequence is initialized. 472 */ 473 } 474 475 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 476 { 477 WARN_ONCE(intel_irqs_enabled(dev_priv), 478 "Interrupts not disabled yet.\n"); 479 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 480 "DC5 still not disabled.\n"); 481 482 /* 483 * TODO: check for the following to verify DC9 state was indeed 484 * entered before programming to disable it: 485 * 1] Check relevant display engine registers to verify if mode 486 * set disable sequence was followed. 487 * 2] Check if display uninitialize sequence is initialized. 488 */ 489 } 490 491 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 492 u32 state) 493 { 494 int rewrites = 0; 495 int rereads = 0; 496 u32 v; 497 498 I915_WRITE(DC_STATE_EN, state); 499 500 /* It has been observed that disabling the dc6 state sometimes 501 * doesn't stick and dmc keeps returning old value. Make sure 502 * the write really sticks enough times and also force rewrite until 503 * we are confident that state is exactly what we want. 504 */ 505 do { 506 v = I915_READ(DC_STATE_EN); 507 508 if (v != state) { 509 I915_WRITE(DC_STATE_EN, state); 510 rewrites++; 511 rereads = 0; 512 } else if (rereads++ > 5) { 513 break; 514 } 515 516 } while (rewrites < 100); 517 518 if (v != state) 519 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", 520 state, v); 521 522 /* Most of the times we need one retry, avoid spam */ 523 if (rewrites > 1) 524 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", 525 state, rewrites); 526 } 527 528 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) 529 { 530 u32 mask; 531 532 mask = DC_STATE_EN_UPTO_DC5; 533 if (IS_BROXTON(dev_priv)) 534 mask |= DC_STATE_EN_DC9; 535 else 536 mask |= DC_STATE_EN_UPTO_DC6; 537 538 return mask; 539 } 540 541 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) 542 { 543 u32 val; 544 545 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); 546 547 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", 548 dev_priv->csr.dc_state, val); 549 dev_priv->csr.dc_state = val; 550 } 551 552 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 553 { 554 uint32_t val; 555 uint32_t mask; 556 557 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) 558 state &= dev_priv->csr.allowed_dc_mask; 559 560 val = I915_READ(DC_STATE_EN); 561 mask = gen9_dc_mask(dev_priv); 562 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 563 val & mask, state); 564 565 /* Check if DMC is ignoring our DC state requests */ 566 if ((val & mask) != dev_priv->csr.dc_state) 567 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", 568 dev_priv->csr.dc_state, val & mask); 569 570 val &= ~mask; 571 val |= state; 572 573 gen9_write_dc_state(dev_priv, val); 574 575 dev_priv->csr.dc_state = val & mask; 576 } 577 578 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 579 { 580 assert_can_enable_dc9(dev_priv); 581 582 DRM_DEBUG_KMS("Enabling DC9\n"); 583 584 intel_power_sequencer_reset(dev_priv); 585 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 586 } 587 588 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 589 { 590 assert_can_disable_dc9(dev_priv); 591 592 DRM_DEBUG_KMS("Disabling DC9\n"); 593 594 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 595 } 596 597 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 598 { 599 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 600 "CSR program storage start is NULL\n"); 601 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 602 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 603 } 604 605 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 606 { 607 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 608 SKL_DISP_PW_2); 609 610 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 611 612 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 613 "DC5 already programmed to be enabled.\n"); 614 assert_rpm_wakelock_held(dev_priv); 615 616 assert_csr_loaded(dev_priv); 617 } 618 619 void gen9_enable_dc5(struct drm_i915_private *dev_priv) 620 { 621 assert_can_enable_dc5(dev_priv); 622 623 DRM_DEBUG_KMS("Enabling DC5\n"); 624 625 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 626 } 627 628 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 629 { 630 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 631 "Backlight is not disabled.\n"); 632 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 633 "DC6 already programmed to be enabled.\n"); 634 635 assert_csr_loaded(dev_priv); 636 } 637 638 void skl_enable_dc6(struct drm_i915_private *dev_priv) 639 { 640 assert_can_enable_dc6(dev_priv); 641 642 DRM_DEBUG_KMS("Enabling DC6\n"); 643 644 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 645 646 } 647 648 void skl_disable_dc6(struct drm_i915_private *dev_priv) 649 { 650 DRM_DEBUG_KMS("Disabling DC6\n"); 651 652 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 653 } 654 655 static void 656 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv, 657 struct i915_power_well *power_well) 658 { 659 enum skl_disp_power_wells power_well_id = power_well->data; 660 u32 val; 661 u32 mask; 662 663 mask = SKL_POWER_WELL_REQ(power_well_id); 664 665 val = I915_READ(HSW_PWR_WELL_KVMR); 666 if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n", 667 power_well->name)) 668 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask); 669 670 val = I915_READ(HSW_PWR_WELL_BIOS); 671 val |= I915_READ(HSW_PWR_WELL_DEBUG); 672 673 if (!(val & mask)) 674 return; 675 676 /* 677 * DMC is known to force on the request bits for power well 1 on SKL 678 * and BXT and the misc IO power well on SKL but we don't expect any 679 * other request bits to be set, so WARN for those. 680 */ 681 if (power_well_id == SKL_DISP_PW_1 || 682 ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && 683 power_well_id == SKL_DISP_PW_MISC_IO)) 684 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on " 685 "by DMC\n", power_well->name); 686 else 687 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n", 688 power_well->name); 689 690 I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask); 691 I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask); 692 } 693 694 static void skl_set_power_well(struct drm_i915_private *dev_priv, 695 struct i915_power_well *power_well, bool enable) 696 { 697 uint32_t tmp, fuse_status; 698 uint32_t req_mask, state_mask; 699 bool is_enabled, enable_requested, check_fuse_status = false; 700 701 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 702 fuse_status = I915_READ(SKL_FUSE_STATUS); 703 704 switch (power_well->data) { 705 case SKL_DISP_PW_1: 706 if (intel_wait_for_register(dev_priv, 707 SKL_FUSE_STATUS, 708 SKL_FUSE_PG0_DIST_STATUS, 709 SKL_FUSE_PG0_DIST_STATUS, 710 1)) { 711 DRM_ERROR("PG0 not enabled\n"); 712 return; 713 } 714 break; 715 case SKL_DISP_PW_2: 716 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { 717 DRM_ERROR("PG1 in disabled state\n"); 718 return; 719 } 720 break; 721 case SKL_DISP_PW_DDI_A_E: 722 case SKL_DISP_PW_DDI_B: 723 case SKL_DISP_PW_DDI_C: 724 case SKL_DISP_PW_DDI_D: 725 case SKL_DISP_PW_MISC_IO: 726 break; 727 default: 728 WARN(1, "Unknown power well %lu\n", power_well->data); 729 return; 730 } 731 732 req_mask = SKL_POWER_WELL_REQ(power_well->data); 733 enable_requested = tmp & req_mask; 734 state_mask = SKL_POWER_WELL_STATE(power_well->data); 735 is_enabled = tmp & state_mask; 736 737 if (!enable && enable_requested) 738 skl_power_well_pre_disable(dev_priv, power_well); 739 740 if (enable) { 741 if (!enable_requested) { 742 WARN((tmp & state_mask) && 743 !I915_READ(HSW_PWR_WELL_BIOS), 744 "Invalid for power well status to be enabled, unless done by the BIOS, \ 745 when request is to disable!\n"); 746 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); 747 } 748 749 if (!is_enabled) { 750 DRM_DEBUG_KMS("Enabling %s\n", power_well->name); 751 check_fuse_status = true; 752 } 753 } else { 754 if (enable_requested) { 755 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); 756 POSTING_READ(HSW_PWR_WELL_DRIVER); 757 DRM_DEBUG_KMS("Disabling %s\n", power_well->name); 758 } 759 760 if (IS_GEN9(dev_priv)) 761 gen9_sanitize_power_well_requests(dev_priv, power_well); 762 } 763 764 if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable, 765 1)) 766 DRM_ERROR("%s %s timeout\n", 767 power_well->name, enable ? "enable" : "disable"); 768 769 if (check_fuse_status) { 770 if (power_well->data == SKL_DISP_PW_1) { 771 if (intel_wait_for_register(dev_priv, 772 SKL_FUSE_STATUS, 773 SKL_FUSE_PG1_DIST_STATUS, 774 SKL_FUSE_PG1_DIST_STATUS, 775 1)) 776 DRM_ERROR("PG1 distributing status timeout\n"); 777 } else if (power_well->data == SKL_DISP_PW_2) { 778 if (intel_wait_for_register(dev_priv, 779 SKL_FUSE_STATUS, 780 SKL_FUSE_PG2_DIST_STATUS, 781 SKL_FUSE_PG2_DIST_STATUS, 782 1)) 783 DRM_ERROR("PG2 distributing status timeout\n"); 784 } 785 } 786 787 if (enable && !is_enabled) 788 skl_power_well_post_enable(dev_priv, power_well); 789 } 790 791 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 792 struct i915_power_well *power_well) 793 { 794 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 795 796 /* 797 * We're taking over the BIOS, so clear any requests made by it since 798 * the driver is in charge now. 799 */ 800 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 801 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 802 } 803 804 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 805 struct i915_power_well *power_well) 806 { 807 hsw_set_power_well(dev_priv, power_well, true); 808 } 809 810 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 811 struct i915_power_well *power_well) 812 { 813 hsw_set_power_well(dev_priv, power_well, false); 814 } 815 816 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, 817 struct i915_power_well *power_well) 818 { 819 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | 820 SKL_POWER_WELL_STATE(power_well->data); 821 822 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; 823 } 824 825 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, 826 struct i915_power_well *power_well) 827 { 828 skl_set_power_well(dev_priv, power_well, power_well->count > 0); 829 830 /* Clear any request made by BIOS as driver is taking over */ 831 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 832 } 833 834 static void skl_power_well_enable(struct drm_i915_private *dev_priv, 835 struct i915_power_well *power_well) 836 { 837 skl_set_power_well(dev_priv, power_well, true); 838 } 839 840 static void skl_power_well_disable(struct drm_i915_private *dev_priv, 841 struct i915_power_well *power_well) 842 { 843 skl_set_power_well(dev_priv, power_well, false); 844 } 845 846 static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well) 847 { 848 enum skl_disp_power_wells power_well_id = power_well->data; 849 850 return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0; 851 } 852 853 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 854 struct i915_power_well *power_well) 855 { 856 enum skl_disp_power_wells power_well_id = power_well->data; 857 struct i915_power_well *cmn_a_well; 858 859 if (power_well_id == BXT_DPIO_CMN_BC) { 860 /* 861 * We need to copy the GRC calibration value from the eDP PHY, 862 * so make sure it's powered up. 863 */ 864 cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); 865 intel_power_well_get(dev_priv, cmn_a_well); 866 } 867 868 bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well)); 869 870 if (power_well_id == BXT_DPIO_CMN_BC) 871 intel_power_well_put(dev_priv, cmn_a_well); 872 } 873 874 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 875 struct i915_power_well *power_well) 876 { 877 bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well)); 878 } 879 880 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, 881 struct i915_power_well *power_well) 882 { 883 return bxt_ddi_phy_is_enabled(dev_priv, 884 bxt_power_well_to_phy(power_well)); 885 } 886 887 static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv, 888 struct i915_power_well *power_well) 889 { 890 if (power_well->count > 0) 891 bxt_dpio_cmn_power_well_enable(dev_priv, power_well); 892 else 893 bxt_dpio_cmn_power_well_disable(dev_priv, power_well); 894 } 895 896 897 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) 898 { 899 struct i915_power_well *power_well; 900 901 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); 902 if (power_well->count > 0) 903 bxt_ddi_phy_verify_state(dev_priv, 904 bxt_power_well_to_phy(power_well)); 905 906 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); 907 if (power_well->count > 0) 908 bxt_ddi_phy_verify_state(dev_priv, 909 bxt_power_well_to_phy(power_well)); 910 } 911 912 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 913 struct i915_power_well *power_well) 914 { 915 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 916 } 917 918 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) 919 { 920 u32 tmp = I915_READ(DBUF_CTL); 921 922 WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) != 923 (DBUF_POWER_STATE | DBUF_POWER_REQUEST), 924 "Unexpected DBuf power power state (0x%08x)\n", tmp); 925 } 926 927 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 928 struct i915_power_well *power_well) 929 { 930 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 931 932 WARN_ON(dev_priv->cdclk_freq != 933 dev_priv->display.get_display_clock_speed(&dev_priv->drm)); 934 935 gen9_assert_dbuf_enabled(dev_priv); 936 937 if (IS_BROXTON(dev_priv)) 938 bxt_verify_ddi_phy_power_wells(dev_priv); 939 } 940 941 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 942 struct i915_power_well *power_well) 943 { 944 if (!dev_priv->csr.dmc_payload) 945 return; 946 947 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 948 skl_enable_dc6(dev_priv); 949 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 950 gen9_enable_dc5(dev_priv); 951 } 952 953 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv, 954 struct i915_power_well *power_well) 955 { 956 if (power_well->count > 0) 957 gen9_dc_off_power_well_enable(dev_priv, power_well); 958 else 959 gen9_dc_off_power_well_disable(dev_priv, power_well); 960 } 961 962 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 963 struct i915_power_well *power_well) 964 { 965 } 966 967 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 968 struct i915_power_well *power_well) 969 { 970 return true; 971 } 972 973 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 974 struct i915_power_well *power_well, bool enable) 975 { 976 enum punit_power_well power_well_id = power_well->data; 977 u32 mask; 978 u32 state; 979 u32 ctrl; 980 981 mask = PUNIT_PWRGT_MASK(power_well_id); 982 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 983 PUNIT_PWRGT_PWR_GATE(power_well_id); 984 985 mutex_lock(&dev_priv->rps.hw_lock); 986 987 #define COND \ 988 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 989 990 if (COND) 991 goto out; 992 993 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 994 ctrl &= ~mask; 995 ctrl |= state; 996 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 997 998 if (wait_for(COND, 100)) 999 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1000 state, 1001 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 1002 1003 #undef COND 1004 1005 out: 1006 mutex_unlock(&dev_priv->rps.hw_lock); 1007 } 1008 1009 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 1010 struct i915_power_well *power_well) 1011 { 1012 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 1013 } 1014 1015 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 1016 struct i915_power_well *power_well) 1017 { 1018 vlv_set_power_well(dev_priv, power_well, true); 1019 } 1020 1021 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 1022 struct i915_power_well *power_well) 1023 { 1024 vlv_set_power_well(dev_priv, power_well, false); 1025 } 1026 1027 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 1028 struct i915_power_well *power_well) 1029 { 1030 int power_well_id = power_well->data; 1031 bool enabled = false; 1032 u32 mask; 1033 u32 state; 1034 u32 ctrl; 1035 1036 mask = PUNIT_PWRGT_MASK(power_well_id); 1037 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 1038 1039 mutex_lock(&dev_priv->rps.hw_lock); 1040 1041 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 1042 /* 1043 * We only ever set the power-on and power-gate states, anything 1044 * else is unexpected. 1045 */ 1046 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 1047 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 1048 if (state == ctrl) 1049 enabled = true; 1050 1051 /* 1052 * A transient state at this point would mean some unexpected party 1053 * is poking at the power controls too. 1054 */ 1055 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 1056 WARN_ON(ctrl != state); 1057 1058 mutex_unlock(&dev_priv->rps.hw_lock); 1059 1060 return enabled; 1061 } 1062 1063 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 1064 { 1065 u32 val; 1066 1067 /* 1068 * On driver load, a pipe may be active and driving a DSI display. 1069 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck 1070 * (and never recovering) in this case. intel_dsi_post_disable() will 1071 * clear it when we turn off the display. 1072 */ 1073 val = I915_READ(DSPCLK_GATE_D); 1074 val &= DPOUNIT_CLOCK_GATE_DISABLE; 1075 val |= VRHUNIT_CLOCK_GATE_DISABLE; 1076 I915_WRITE(DSPCLK_GATE_D, val); 1077 1078 /* 1079 * Disable trickle feed and enable pnd deadline calculation 1080 */ 1081 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1082 I915_WRITE(CBR1_VLV, 0); 1083 1084 WARN_ON(dev_priv->rawclk_freq == 0); 1085 1086 I915_WRITE(RAWCLK_FREQ_VLV, 1087 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); 1088 } 1089 1090 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 1091 { 1092 struct intel_encoder *encoder; 1093 enum i915_pipe pipe; 1094 1095 /* 1096 * Enable the CRI clock source so we can get at the 1097 * display and the reference clock for VGA 1098 * hotplug / manual detection. Supposedly DSI also 1099 * needs the ref clock up and running. 1100 * 1101 * CHV DPLL B/C have some issues if VGA mode is enabled. 1102 */ 1103 for_each_pipe(&dev_priv->drm, pipe) { 1104 u32 val = I915_READ(DPLL(pipe)); 1105 1106 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1107 if (pipe != PIPE_A) 1108 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1109 1110 I915_WRITE(DPLL(pipe), val); 1111 } 1112 1113 vlv_init_display_clock_gating(dev_priv); 1114 1115 spin_lock_irq(&dev_priv->irq_lock); 1116 valleyview_enable_display_irqs(dev_priv); 1117 spin_unlock_irq(&dev_priv->irq_lock); 1118 1119 /* 1120 * During driver initialization/resume we can avoid restoring the 1121 * part of the HW/SW state that will be inited anyway explicitly. 1122 */ 1123 if (dev_priv->power_domains.initializing) 1124 return; 1125 1126 intel_hpd_init(dev_priv); 1127 1128 /* Re-enable the ADPA, if we have one */ 1129 for_each_intel_encoder(&dev_priv->drm, encoder) { 1130 if (encoder->type == INTEL_OUTPUT_ANALOG) 1131 intel_crt_reset(&encoder->base); 1132 } 1133 1134 i915_redisable_vga_power_on(&dev_priv->drm); 1135 } 1136 1137 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 1138 { 1139 spin_lock_irq(&dev_priv->irq_lock); 1140 valleyview_disable_display_irqs(dev_priv); 1141 spin_unlock_irq(&dev_priv->irq_lock); 1142 1143 /* make sure we're done processing display irqs */ 1144 synchronize_irq(dev_priv->drm.irq); 1145 1146 intel_power_sequencer_reset(dev_priv); 1147 1148 intel_hpd_poll_init(dev_priv); 1149 } 1150 1151 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 1152 struct i915_power_well *power_well) 1153 { 1154 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 1155 1156 vlv_set_power_well(dev_priv, power_well, true); 1157 1158 vlv_display_power_well_init(dev_priv); 1159 } 1160 1161 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1162 struct i915_power_well *power_well) 1163 { 1164 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 1165 1166 vlv_display_power_well_deinit(dev_priv); 1167 1168 vlv_set_power_well(dev_priv, power_well, false); 1169 } 1170 1171 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1172 struct i915_power_well *power_well) 1173 { 1174 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1175 1176 /* since ref/cri clock was enabled */ 1177 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1178 1179 vlv_set_power_well(dev_priv, power_well, true); 1180 1181 /* 1182 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1183 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1184 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1185 * b. The other bits such as sfr settings / modesel may all 1186 * be set to 0. 1187 * 1188 * This should only be done on init and resume from S3 with 1189 * both PLLs disabled, or we risk losing DPIO and PLL 1190 * synchronization. 1191 */ 1192 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 1193 } 1194 1195 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1196 struct i915_power_well *power_well) 1197 { 1198 enum i915_pipe pipe; 1199 1200 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1201 1202 for_each_pipe(dev_priv, pipe) 1203 assert_pll_disabled(dev_priv, pipe); 1204 1205 /* Assert common reset */ 1206 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1207 1208 vlv_set_power_well(dev_priv, power_well, false); 1209 } 1210 1211 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 1212 1213 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1214 int power_well_id) 1215 { 1216 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1217 int i; 1218 1219 for (i = 0; i < power_domains->power_well_count; i++) { 1220 struct i915_power_well *power_well; 1221 1222 power_well = &power_domains->power_wells[i]; 1223 if (power_well->data == power_well_id) 1224 return power_well; 1225 } 1226 1227 return NULL; 1228 } 1229 1230 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1231 1232 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1233 { 1234 struct i915_power_well *cmn_bc = 1235 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1236 struct i915_power_well *cmn_d = 1237 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1238 u32 phy_control = dev_priv->chv_phy_control; 1239 u32 phy_status = 0; 1240 u32 phy_status_mask = 0xffffffff; 1241 1242 /* 1243 * The BIOS can leave the PHY is some weird state 1244 * where it doesn't fully power down some parts. 1245 * Disable the asserts until the PHY has been fully 1246 * reset (ie. the power well has been disabled at 1247 * least once). 1248 */ 1249 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1250 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1251 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1252 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1253 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1254 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1255 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1256 1257 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1258 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1259 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1260 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1261 1262 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1263 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1264 1265 /* this assumes override is only used to enable lanes */ 1266 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1267 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1268 1269 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1270 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1271 1272 /* CL1 is on whenever anything is on in either channel */ 1273 if (BITS_SET(phy_control, 1274 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1275 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1276 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1277 1278 /* 1279 * The DPLLB check accounts for the pipe B + port A usage 1280 * with CL2 powered up but all the lanes in the second channel 1281 * powered down. 1282 */ 1283 if (BITS_SET(phy_control, 1284 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1285 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1286 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1287 1288 if (BITS_SET(phy_control, 1289 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1290 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1291 if (BITS_SET(phy_control, 1292 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1293 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1294 1295 if (BITS_SET(phy_control, 1296 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1297 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1298 if (BITS_SET(phy_control, 1299 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1300 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1301 } 1302 1303 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1304 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1305 1306 /* this assumes override is only used to enable lanes */ 1307 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1308 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1309 1310 if (BITS_SET(phy_control, 1311 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1312 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1313 1314 if (BITS_SET(phy_control, 1315 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1316 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1317 if (BITS_SET(phy_control, 1318 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1319 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1320 } 1321 1322 phy_status &= phy_status_mask; 1323 1324 /* 1325 * The PHY may be busy with some initial calibration and whatnot, 1326 * so the power state can take a while to actually change. 1327 */ 1328 if (intel_wait_for_register(dev_priv, 1329 DISPLAY_PHY_STATUS, 1330 phy_status_mask, 1331 phy_status, 1332 10)) 1333 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1334 I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, 1335 phy_status, dev_priv->chv_phy_control); 1336 } 1337 1338 #undef BITS_SET 1339 1340 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1341 struct i915_power_well *power_well) 1342 { 1343 enum dpio_phy phy; 1344 enum i915_pipe pipe; 1345 uint32_t tmp; 1346 1347 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1348 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1349 1350 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1351 pipe = PIPE_A; 1352 phy = DPIO_PHY0; 1353 } else { 1354 pipe = PIPE_C; 1355 phy = DPIO_PHY1; 1356 } 1357 1358 /* since ref/cri clock was enabled */ 1359 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1360 vlv_set_power_well(dev_priv, power_well, true); 1361 1362 /* Poll for phypwrgood signal */ 1363 if (intel_wait_for_register(dev_priv, 1364 DISPLAY_PHY_STATUS, 1365 PHY_POWERGOOD(phy), 1366 PHY_POWERGOOD(phy), 1367 1)) 1368 DRM_ERROR("Display PHY %d is not power up\n", phy); 1369 1370 mutex_lock(&dev_priv->sb_lock); 1371 1372 /* Enable dynamic power down */ 1373 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1374 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1375 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1376 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1377 1378 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1379 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1380 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1381 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1382 } else { 1383 /* 1384 * Force the non-existing CL2 off. BXT does this 1385 * too, so maybe it saves some power even though 1386 * CL2 doesn't exist? 1387 */ 1388 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1389 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1390 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1391 } 1392 1393 mutex_unlock(&dev_priv->sb_lock); 1394 1395 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1396 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1397 1398 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1399 phy, dev_priv->chv_phy_control); 1400 1401 assert_chv_phy_status(dev_priv); 1402 } 1403 1404 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1405 struct i915_power_well *power_well) 1406 { 1407 enum dpio_phy phy; 1408 1409 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1410 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1411 1412 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1413 phy = DPIO_PHY0; 1414 assert_pll_disabled(dev_priv, PIPE_A); 1415 assert_pll_disabled(dev_priv, PIPE_B); 1416 } else { 1417 phy = DPIO_PHY1; 1418 assert_pll_disabled(dev_priv, PIPE_C); 1419 } 1420 1421 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1422 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1423 1424 vlv_set_power_well(dev_priv, power_well, false); 1425 1426 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1427 phy, dev_priv->chv_phy_control); 1428 1429 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1430 dev_priv->chv_phy_assert[phy] = true; 1431 1432 assert_chv_phy_status(dev_priv); 1433 } 1434 1435 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1436 enum dpio_channel ch, bool override, unsigned int mask) 1437 { 1438 enum i915_pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1439 u32 reg, val, expected, actual; 1440 1441 /* 1442 * The BIOS can leave the PHY is some weird state 1443 * where it doesn't fully power down some parts. 1444 * Disable the asserts until the PHY has been fully 1445 * reset (ie. the power well has been disabled at 1446 * least once). 1447 */ 1448 if (!dev_priv->chv_phy_assert[phy]) 1449 return; 1450 1451 if (ch == DPIO_CH0) 1452 reg = _CHV_CMN_DW0_CH0; 1453 else 1454 reg = _CHV_CMN_DW6_CH1; 1455 1456 mutex_lock(&dev_priv->sb_lock); 1457 val = vlv_dpio_read(dev_priv, pipe, reg); 1458 mutex_unlock(&dev_priv->sb_lock); 1459 1460 /* 1461 * This assumes !override is only used when the port is disabled. 1462 * All lanes should power down even without the override when 1463 * the port is disabled. 1464 */ 1465 if (!override || mask == 0xf) { 1466 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1467 /* 1468 * If CH1 common lane is not active anymore 1469 * (eg. for pipe B DPLL) the entire channel will 1470 * shut down, which causes the common lane registers 1471 * to read as 0. That means we can't actually check 1472 * the lane power down status bits, but as the entire 1473 * register reads as 0 it's a good indication that the 1474 * channel is indeed entirely powered down. 1475 */ 1476 if (ch == DPIO_CH1 && val == 0) 1477 expected = 0; 1478 } else if (mask != 0x0) { 1479 expected = DPIO_ANYDL_POWERDOWN; 1480 } else { 1481 expected = 0; 1482 } 1483 1484 if (ch == DPIO_CH0) 1485 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1486 else 1487 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1488 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1489 1490 WARN(actual != expected, 1491 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1492 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1493 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1494 reg, val); 1495 } 1496 1497 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1498 enum dpio_channel ch, bool override) 1499 { 1500 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1501 bool was_override; 1502 1503 mutex_lock(&power_domains->lock); 1504 1505 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1506 1507 if (override == was_override) 1508 goto out; 1509 1510 if (override) 1511 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1512 else 1513 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1514 1515 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1516 1517 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1518 phy, ch, dev_priv->chv_phy_control); 1519 1520 assert_chv_phy_status(dev_priv); 1521 1522 out: 1523 mutex_unlock(&power_domains->lock); 1524 1525 return was_override; 1526 } 1527 1528 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1529 bool override, unsigned int mask) 1530 { 1531 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1532 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1533 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1534 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1535 1536 mutex_lock(&power_domains->lock); 1537 1538 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1539 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1540 1541 if (override) 1542 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1543 else 1544 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1545 1546 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1547 1548 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1549 phy, ch, mask, dev_priv->chv_phy_control); 1550 1551 assert_chv_phy_status(dev_priv); 1552 1553 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1554 1555 mutex_unlock(&power_domains->lock); 1556 } 1557 1558 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1559 struct i915_power_well *power_well) 1560 { 1561 enum i915_pipe pipe = power_well->data; 1562 bool enabled; 1563 u32 state, ctrl; 1564 1565 mutex_lock(&dev_priv->rps.hw_lock); 1566 1567 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1568 /* 1569 * We only ever set the power-on and power-gate states, anything 1570 * else is unexpected. 1571 */ 1572 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1573 enabled = state == DP_SSS_PWR_ON(pipe); 1574 1575 /* 1576 * A transient state at this point would mean some unexpected party 1577 * is poking at the power controls too. 1578 */ 1579 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1580 WARN_ON(ctrl << 16 != state); 1581 1582 mutex_unlock(&dev_priv->rps.hw_lock); 1583 1584 return enabled; 1585 } 1586 1587 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1588 struct i915_power_well *power_well, 1589 bool enable) 1590 { 1591 enum i915_pipe pipe = power_well->data; 1592 u32 state; 1593 u32 ctrl; 1594 1595 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1596 1597 mutex_lock(&dev_priv->rps.hw_lock); 1598 1599 #define COND \ 1600 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1601 1602 if (COND) 1603 goto out; 1604 1605 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1606 ctrl &= ~DP_SSC_MASK(pipe); 1607 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1608 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1609 1610 if (wait_for(COND, 100)) 1611 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1612 state, 1613 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1614 1615 #undef COND 1616 1617 out: 1618 mutex_unlock(&dev_priv->rps.hw_lock); 1619 } 1620 1621 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1622 struct i915_power_well *power_well) 1623 { 1624 WARN_ON_ONCE(power_well->data != PIPE_A); 1625 1626 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 1627 } 1628 1629 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1630 struct i915_power_well *power_well) 1631 { 1632 WARN_ON_ONCE(power_well->data != PIPE_A); 1633 1634 chv_set_pipe_power_well(dev_priv, power_well, true); 1635 1636 vlv_display_power_well_init(dev_priv); 1637 } 1638 1639 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1640 struct i915_power_well *power_well) 1641 { 1642 WARN_ON_ONCE(power_well->data != PIPE_A); 1643 1644 vlv_display_power_well_deinit(dev_priv); 1645 1646 chv_set_pipe_power_well(dev_priv, power_well, false); 1647 } 1648 1649 static void 1650 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 1651 enum intel_display_power_domain domain) 1652 { 1653 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1654 struct i915_power_well *power_well; 1655 int i; 1656 1657 for_each_power_well(i, power_well, BIT(domain), power_domains) 1658 intel_power_well_get(dev_priv, power_well); 1659 1660 power_domains->domain_use_count[domain]++; 1661 } 1662 1663 /** 1664 * intel_display_power_get - grab a power domain reference 1665 * @dev_priv: i915 device instance 1666 * @domain: power domain to reference 1667 * 1668 * This function grabs a power domain reference for @domain and ensures that the 1669 * power domain and all its parents are powered up. Therefore users should only 1670 * grab a reference to the innermost power domain they need. 1671 * 1672 * Any power domain reference obtained by this function must have a symmetric 1673 * call to intel_display_power_put() to release the reference again. 1674 */ 1675 void intel_display_power_get(struct drm_i915_private *dev_priv, 1676 enum intel_display_power_domain domain) 1677 { 1678 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1679 1680 intel_runtime_pm_get(dev_priv); 1681 1682 mutex_lock(&power_domains->lock); 1683 1684 __intel_display_power_get_domain(dev_priv, domain); 1685 1686 mutex_unlock(&power_domains->lock); 1687 } 1688 1689 /** 1690 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 1691 * @dev_priv: i915 device instance 1692 * @domain: power domain to reference 1693 * 1694 * This function grabs a power domain reference for @domain and ensures that the 1695 * power domain and all its parents are powered up. Therefore users should only 1696 * grab a reference to the innermost power domain they need. 1697 * 1698 * Any power domain reference obtained by this function must have a symmetric 1699 * call to intel_display_power_put() to release the reference again. 1700 */ 1701 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1702 enum intel_display_power_domain domain) 1703 { 1704 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1705 bool is_enabled; 1706 1707 if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1708 return false; 1709 1710 mutex_lock(&power_domains->lock); 1711 1712 if (__intel_display_power_is_enabled(dev_priv, domain)) { 1713 __intel_display_power_get_domain(dev_priv, domain); 1714 is_enabled = true; 1715 } else { 1716 is_enabled = false; 1717 } 1718 1719 mutex_unlock(&power_domains->lock); 1720 1721 if (!is_enabled) 1722 intel_runtime_pm_put(dev_priv); 1723 1724 return is_enabled; 1725 } 1726 1727 /** 1728 * intel_display_power_put - release a power domain reference 1729 * @dev_priv: i915 device instance 1730 * @domain: power domain to reference 1731 * 1732 * This function drops the power domain reference obtained by 1733 * intel_display_power_get() and might power down the corresponding hardware 1734 * block right away if this is the last reference. 1735 */ 1736 void intel_display_power_put(struct drm_i915_private *dev_priv, 1737 enum intel_display_power_domain domain) 1738 { 1739 struct i915_power_domains *power_domains; 1740 struct i915_power_well *power_well; 1741 int i; 1742 1743 power_domains = &dev_priv->power_domains; 1744 1745 mutex_lock(&power_domains->lock); 1746 1747 WARN(!power_domains->domain_use_count[domain], 1748 "Use count on domain %s is already zero\n", 1749 intel_display_power_domain_str(domain)); 1750 power_domains->domain_use_count[domain]--; 1751 1752 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) 1753 intel_power_well_put(dev_priv, power_well); 1754 1755 mutex_unlock(&power_domains->lock); 1756 1757 intel_runtime_pm_put(dev_priv); 1758 } 1759 1760 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1761 BIT(POWER_DOMAIN_PIPE_B) | \ 1762 BIT(POWER_DOMAIN_PIPE_C) | \ 1763 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1764 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1765 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1766 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1767 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1768 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 1769 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1770 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1771 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1772 BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1773 BIT(POWER_DOMAIN_VGA) | \ 1774 BIT(POWER_DOMAIN_AUDIO) | \ 1775 BIT(POWER_DOMAIN_INIT)) 1776 1777 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1778 BIT(POWER_DOMAIN_PIPE_B) | \ 1779 BIT(POWER_DOMAIN_PIPE_C) | \ 1780 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1781 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1782 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1783 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1784 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 1785 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1786 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1787 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1788 BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1789 BIT(POWER_DOMAIN_VGA) | \ 1790 BIT(POWER_DOMAIN_AUDIO) | \ 1791 BIT(POWER_DOMAIN_INIT)) 1792 1793 #define VLV_DISPLAY_POWER_DOMAINS ( \ 1794 BIT(POWER_DOMAIN_PIPE_A) | \ 1795 BIT(POWER_DOMAIN_PIPE_B) | \ 1796 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1797 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1798 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1799 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1800 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1801 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1802 BIT(POWER_DOMAIN_PORT_DSI) | \ 1803 BIT(POWER_DOMAIN_PORT_CRT) | \ 1804 BIT(POWER_DOMAIN_VGA) | \ 1805 BIT(POWER_DOMAIN_AUDIO) | \ 1806 BIT(POWER_DOMAIN_AUX_B) | \ 1807 BIT(POWER_DOMAIN_AUX_C) | \ 1808 BIT(POWER_DOMAIN_GMBUS) | \ 1809 BIT(POWER_DOMAIN_INIT)) 1810 1811 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1812 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1813 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1814 BIT(POWER_DOMAIN_PORT_CRT) | \ 1815 BIT(POWER_DOMAIN_AUX_B) | \ 1816 BIT(POWER_DOMAIN_AUX_C) | \ 1817 BIT(POWER_DOMAIN_INIT)) 1818 1819 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1820 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1821 BIT(POWER_DOMAIN_AUX_B) | \ 1822 BIT(POWER_DOMAIN_INIT)) 1823 1824 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1825 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1826 BIT(POWER_DOMAIN_AUX_B) | \ 1827 BIT(POWER_DOMAIN_INIT)) 1828 1829 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1830 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1831 BIT(POWER_DOMAIN_AUX_C) | \ 1832 BIT(POWER_DOMAIN_INIT)) 1833 1834 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1835 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1836 BIT(POWER_DOMAIN_AUX_C) | \ 1837 BIT(POWER_DOMAIN_INIT)) 1838 1839 #define CHV_DISPLAY_POWER_DOMAINS ( \ 1840 BIT(POWER_DOMAIN_PIPE_A) | \ 1841 BIT(POWER_DOMAIN_PIPE_B) | \ 1842 BIT(POWER_DOMAIN_PIPE_C) | \ 1843 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1844 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1845 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1846 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1847 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1848 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 1849 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1850 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1851 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1852 BIT(POWER_DOMAIN_PORT_DSI) | \ 1853 BIT(POWER_DOMAIN_VGA) | \ 1854 BIT(POWER_DOMAIN_AUDIO) | \ 1855 BIT(POWER_DOMAIN_AUX_B) | \ 1856 BIT(POWER_DOMAIN_AUX_C) | \ 1857 BIT(POWER_DOMAIN_AUX_D) | \ 1858 BIT(POWER_DOMAIN_GMBUS) | \ 1859 BIT(POWER_DOMAIN_INIT)) 1860 1861 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1862 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1863 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1864 BIT(POWER_DOMAIN_AUX_B) | \ 1865 BIT(POWER_DOMAIN_AUX_C) | \ 1866 BIT(POWER_DOMAIN_INIT)) 1867 1868 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1869 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1870 BIT(POWER_DOMAIN_AUX_D) | \ 1871 BIT(POWER_DOMAIN_INIT)) 1872 1873 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1874 .sync_hw = i9xx_always_on_power_well_noop, 1875 .enable = i9xx_always_on_power_well_noop, 1876 .disable = i9xx_always_on_power_well_noop, 1877 .is_enabled = i9xx_always_on_power_well_enabled, 1878 }; 1879 1880 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1881 .sync_hw = chv_pipe_power_well_sync_hw, 1882 .enable = chv_pipe_power_well_enable, 1883 .disable = chv_pipe_power_well_disable, 1884 .is_enabled = chv_pipe_power_well_enabled, 1885 }; 1886 1887 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1888 .sync_hw = vlv_power_well_sync_hw, 1889 .enable = chv_dpio_cmn_power_well_enable, 1890 .disable = chv_dpio_cmn_power_well_disable, 1891 .is_enabled = vlv_power_well_enabled, 1892 }; 1893 1894 static struct i915_power_well i9xx_always_on_power_well[] = { 1895 { 1896 .name = "always-on", 1897 .always_on = 1, 1898 .domains = POWER_DOMAIN_MASK, 1899 .ops = &i9xx_always_on_power_well_ops, 1900 }, 1901 }; 1902 1903 static const struct i915_power_well_ops hsw_power_well_ops = { 1904 .sync_hw = hsw_power_well_sync_hw, 1905 .enable = hsw_power_well_enable, 1906 .disable = hsw_power_well_disable, 1907 .is_enabled = hsw_power_well_enabled, 1908 }; 1909 1910 static const struct i915_power_well_ops skl_power_well_ops = { 1911 .sync_hw = skl_power_well_sync_hw, 1912 .enable = skl_power_well_enable, 1913 .disable = skl_power_well_disable, 1914 .is_enabled = skl_power_well_enabled, 1915 }; 1916 1917 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1918 .sync_hw = gen9_dc_off_power_well_sync_hw, 1919 .enable = gen9_dc_off_power_well_enable, 1920 .disable = gen9_dc_off_power_well_disable, 1921 .is_enabled = gen9_dc_off_power_well_enabled, 1922 }; 1923 1924 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = { 1925 .sync_hw = bxt_dpio_cmn_power_well_sync_hw, 1926 .enable = bxt_dpio_cmn_power_well_enable, 1927 .disable = bxt_dpio_cmn_power_well_disable, 1928 .is_enabled = bxt_dpio_cmn_power_well_enabled, 1929 }; 1930 1931 static struct i915_power_well hsw_power_wells[] = { 1932 { 1933 .name = "always-on", 1934 .always_on = 1, 1935 .domains = POWER_DOMAIN_MASK, 1936 .ops = &i9xx_always_on_power_well_ops, 1937 }, 1938 { 1939 .name = "display", 1940 .domains = HSW_DISPLAY_POWER_DOMAINS, 1941 .ops = &hsw_power_well_ops, 1942 }, 1943 }; 1944 1945 static struct i915_power_well bdw_power_wells[] = { 1946 { 1947 .name = "always-on", 1948 .always_on = 1, 1949 .domains = POWER_DOMAIN_MASK, 1950 .ops = &i9xx_always_on_power_well_ops, 1951 }, 1952 { 1953 .name = "display", 1954 .domains = BDW_DISPLAY_POWER_DOMAINS, 1955 .ops = &hsw_power_well_ops, 1956 }, 1957 }; 1958 1959 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1960 .sync_hw = vlv_power_well_sync_hw, 1961 .enable = vlv_display_power_well_enable, 1962 .disable = vlv_display_power_well_disable, 1963 .is_enabled = vlv_power_well_enabled, 1964 }; 1965 1966 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1967 .sync_hw = vlv_power_well_sync_hw, 1968 .enable = vlv_dpio_cmn_power_well_enable, 1969 .disable = vlv_dpio_cmn_power_well_disable, 1970 .is_enabled = vlv_power_well_enabled, 1971 }; 1972 1973 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1974 .sync_hw = vlv_power_well_sync_hw, 1975 .enable = vlv_power_well_enable, 1976 .disable = vlv_power_well_disable, 1977 .is_enabled = vlv_power_well_enabled, 1978 }; 1979 1980 static struct i915_power_well vlv_power_wells[] = { 1981 { 1982 .name = "always-on", 1983 .always_on = 1, 1984 .domains = POWER_DOMAIN_MASK, 1985 .ops = &i9xx_always_on_power_well_ops, 1986 .data = PUNIT_POWER_WELL_ALWAYS_ON, 1987 }, 1988 { 1989 .name = "display", 1990 .domains = VLV_DISPLAY_POWER_DOMAINS, 1991 .data = PUNIT_POWER_WELL_DISP2D, 1992 .ops = &vlv_display_power_well_ops, 1993 }, 1994 { 1995 .name = "dpio-tx-b-01", 1996 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1997 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1998 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1999 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2000 .ops = &vlv_dpio_power_well_ops, 2001 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 2002 }, 2003 { 2004 .name = "dpio-tx-b-23", 2005 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2006 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2007 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2008 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2009 .ops = &vlv_dpio_power_well_ops, 2010 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 2011 }, 2012 { 2013 .name = "dpio-tx-c-01", 2014 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2015 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2016 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2017 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2018 .ops = &vlv_dpio_power_well_ops, 2019 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 2020 }, 2021 { 2022 .name = "dpio-tx-c-23", 2023 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 2024 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 2025 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 2026 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 2027 .ops = &vlv_dpio_power_well_ops, 2028 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 2029 }, 2030 { 2031 .name = "dpio-common", 2032 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 2033 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 2034 .ops = &vlv_dpio_cmn_power_well_ops, 2035 }, 2036 }; 2037 2038 static struct i915_power_well chv_power_wells[] = { 2039 { 2040 .name = "always-on", 2041 .always_on = 1, 2042 .domains = POWER_DOMAIN_MASK, 2043 .ops = &i9xx_always_on_power_well_ops, 2044 }, 2045 { 2046 .name = "display", 2047 /* 2048 * Pipe A power well is the new disp2d well. Pipe B and C 2049 * power wells don't actually exist. Pipe A power well is 2050 * required for any pipe to work. 2051 */ 2052 .domains = CHV_DISPLAY_POWER_DOMAINS, 2053 .data = PIPE_A, 2054 .ops = &chv_pipe_power_well_ops, 2055 }, 2056 { 2057 .name = "dpio-common-bc", 2058 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 2059 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 2060 .ops = &chv_dpio_cmn_power_well_ops, 2061 }, 2062 { 2063 .name = "dpio-common-d", 2064 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 2065 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 2066 .ops = &chv_dpio_cmn_power_well_ops, 2067 }, 2068 }; 2069 2070 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 2071 int power_well_id) 2072 { 2073 struct i915_power_well *power_well; 2074 bool ret; 2075 2076 power_well = lookup_power_well(dev_priv, power_well_id); 2077 ret = power_well->ops->is_enabled(dev_priv, power_well); 2078 2079 return ret; 2080 } 2081 2082 static struct i915_power_well skl_power_wells[] = { 2083 { 2084 .name = "always-on", 2085 .always_on = 1, 2086 .domains = POWER_DOMAIN_MASK, 2087 .ops = &i9xx_always_on_power_well_ops, 2088 .data = SKL_DISP_PW_ALWAYS_ON, 2089 }, 2090 { 2091 .name = "power well 1", 2092 /* Handled by the DMC firmware */ 2093 .domains = 0, 2094 .ops = &skl_power_well_ops, 2095 .data = SKL_DISP_PW_1, 2096 }, 2097 { 2098 .name = "MISC IO power well", 2099 /* Handled by the DMC firmware */ 2100 .domains = 0, 2101 .ops = &skl_power_well_ops, 2102 .data = SKL_DISP_PW_MISC_IO, 2103 }, 2104 { 2105 .name = "DC off", 2106 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 2107 .ops = &gen9_dc_off_power_well_ops, 2108 .data = SKL_DISP_PW_DC_OFF, 2109 }, 2110 { 2111 .name = "power well 2", 2112 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2113 .ops = &skl_power_well_ops, 2114 .data = SKL_DISP_PW_2, 2115 }, 2116 { 2117 .name = "DDI A/E power well", 2118 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, 2119 .ops = &skl_power_well_ops, 2120 .data = SKL_DISP_PW_DDI_A_E, 2121 }, 2122 { 2123 .name = "DDI B power well", 2124 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, 2125 .ops = &skl_power_well_ops, 2126 .data = SKL_DISP_PW_DDI_B, 2127 }, 2128 { 2129 .name = "DDI C power well", 2130 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, 2131 .ops = &skl_power_well_ops, 2132 .data = SKL_DISP_PW_DDI_C, 2133 }, 2134 { 2135 .name = "DDI D power well", 2136 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, 2137 .ops = &skl_power_well_ops, 2138 .data = SKL_DISP_PW_DDI_D, 2139 }, 2140 }; 2141 2142 static struct i915_power_well bxt_power_wells[] = { 2143 { 2144 .name = "always-on", 2145 .always_on = 1, 2146 .domains = POWER_DOMAIN_MASK, 2147 .ops = &i9xx_always_on_power_well_ops, 2148 }, 2149 { 2150 .name = "power well 1", 2151 .domains = 0, 2152 .ops = &skl_power_well_ops, 2153 .data = SKL_DISP_PW_1, 2154 }, 2155 { 2156 .name = "DC off", 2157 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 2158 .ops = &gen9_dc_off_power_well_ops, 2159 .data = SKL_DISP_PW_DC_OFF, 2160 }, 2161 { 2162 .name = "power well 2", 2163 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2164 .ops = &skl_power_well_ops, 2165 .data = SKL_DISP_PW_2, 2166 }, 2167 { 2168 .name = "dpio-common-a", 2169 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS, 2170 .ops = &bxt_dpio_cmn_power_well_ops, 2171 .data = BXT_DPIO_CMN_A, 2172 }, 2173 { 2174 .name = "dpio-common-bc", 2175 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS, 2176 .ops = &bxt_dpio_cmn_power_well_ops, 2177 .data = BXT_DPIO_CMN_BC, 2178 }, 2179 }; 2180 2181 static int 2182 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 2183 int disable_power_well) 2184 { 2185 if (disable_power_well >= 0) 2186 return !!disable_power_well; 2187 2188 return 1; 2189 } 2190 2191 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 2192 int enable_dc) 2193 { 2194 uint32_t mask; 2195 int requested_dc; 2196 int max_dc; 2197 2198 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 2199 max_dc = 2; 2200 mask = 0; 2201 } else if (IS_BROXTON(dev_priv)) { 2202 max_dc = 1; 2203 /* 2204 * DC9 has a separate HW flow from the rest of the DC states, 2205 * not depending on the DMC firmware. It's needed by system 2206 * suspend/resume, so allow it unconditionally. 2207 */ 2208 mask = DC_STATE_EN_DC9; 2209 } else { 2210 max_dc = 0; 2211 mask = 0; 2212 } 2213 2214 if (!i915.disable_power_well) 2215 max_dc = 0; 2216 2217 if (enable_dc >= 0 && enable_dc <= max_dc) { 2218 requested_dc = enable_dc; 2219 } else if (enable_dc == -1) { 2220 requested_dc = max_dc; 2221 } else if (enable_dc > max_dc && enable_dc <= 2) { 2222 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", 2223 enable_dc, max_dc); 2224 requested_dc = max_dc; 2225 } else { 2226 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); 2227 requested_dc = max_dc; 2228 } 2229 2230 if (requested_dc > 1) 2231 mask |= DC_STATE_EN_UPTO_DC6; 2232 if (requested_dc > 0) 2233 mask |= DC_STATE_EN_UPTO_DC5; 2234 2235 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); 2236 2237 return mask; 2238 } 2239 2240 #define set_power_wells(power_domains, __power_wells) ({ \ 2241 (power_domains)->power_wells = (__power_wells); \ 2242 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 2243 }) 2244 2245 /** 2246 * intel_power_domains_init - initializes the power domain structures 2247 * @dev_priv: i915 device instance 2248 * 2249 * Initializes the power domain structures for @dev_priv depending upon the 2250 * supported platform. 2251 */ 2252 int intel_power_domains_init(struct drm_i915_private *dev_priv) 2253 { 2254 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2255 2256 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, 2257 i915.disable_power_well); 2258 dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv, 2259 i915.enable_dc); 2260 2261 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); 2262 2263 lockinit(&power_domains->lock, "i915pl", 0, LK_CANRECURSE); 2264 2265 /* 2266 * The enabling order will be from lower to higher indexed wells, 2267 * the disabling order is reversed. 2268 */ 2269 if (IS_HASWELL(dev_priv)) { 2270 set_power_wells(power_domains, hsw_power_wells); 2271 } else if (IS_BROADWELL(dev_priv)) { 2272 set_power_wells(power_domains, bdw_power_wells); 2273 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 2274 set_power_wells(power_domains, skl_power_wells); 2275 } else if (IS_BROXTON(dev_priv)) { 2276 set_power_wells(power_domains, bxt_power_wells); 2277 } else if (IS_CHERRYVIEW(dev_priv)) { 2278 set_power_wells(power_domains, chv_power_wells); 2279 } else if (IS_VALLEYVIEW(dev_priv)) { 2280 set_power_wells(power_domains, vlv_power_wells); 2281 } else { 2282 set_power_wells(power_domains, i9xx_always_on_power_well); 2283 } 2284 2285 return 0; 2286 } 2287 2288 /** 2289 * intel_power_domains_fini - finalizes the power domain structures 2290 * @dev_priv: i915 device instance 2291 * 2292 * Finalizes the power domain structures for @dev_priv depending upon the 2293 * supported platform. This function also disables runtime pm and ensures that 2294 * the device stays powered up so that the driver can be reloaded. 2295 */ 2296 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 2297 { 2298 #if 0 2299 struct device *device = &dev_priv->drm.pdev->dev; 2300 #endif 2301 2302 /* 2303 * The i915.ko module is still not prepared to be loaded when 2304 * the power well is not enabled, so just enable it in case 2305 * we're going to unload/reload. 2306 * The following also reacquires the RPM reference the core passed 2307 * to the driver during loading, which is dropped in 2308 * intel_runtime_pm_enable(). We have to hand back the control of the 2309 * device to the core with this reference held. 2310 */ 2311 intel_display_set_init_power(dev_priv, true); 2312 2313 /* Remove the refcount we took to keep power well support disabled. */ 2314 if (!i915.disable_power_well) 2315 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2316 2317 /* 2318 * Remove the refcount we took in intel_runtime_pm_enable() in case 2319 * the platform doesn't support runtime PM. 2320 */ 2321 #if 0 2322 if (!HAS_RUNTIME_PM(dev_priv)) 2323 pm_runtime_put(device); 2324 #endif 2325 } 2326 2327 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 2328 { 2329 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2330 struct i915_power_well *power_well; 2331 int i; 2332 2333 mutex_lock(&power_domains->lock); 2334 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 2335 power_well->ops->sync_hw(dev_priv, power_well); 2336 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 2337 power_well); 2338 } 2339 mutex_unlock(&power_domains->lock); 2340 } 2341 2342 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) 2343 { 2344 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); 2345 POSTING_READ(DBUF_CTL); 2346 2347 udelay(10); 2348 2349 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) 2350 DRM_ERROR("DBuf power enable timeout\n"); 2351 } 2352 2353 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) 2354 { 2355 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); 2356 POSTING_READ(DBUF_CTL); 2357 2358 udelay(10); 2359 2360 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) 2361 DRM_ERROR("DBuf power disable timeout!\n"); 2362 } 2363 2364 static void skl_display_core_init(struct drm_i915_private *dev_priv, 2365 bool resume) 2366 { 2367 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2368 struct i915_power_well *well; 2369 uint32_t val; 2370 2371 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2372 2373 /* enable PCH reset handshake */ 2374 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2375 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 2376 2377 /* enable PG1 and Misc I/O */ 2378 mutex_lock(&power_domains->lock); 2379 2380 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2381 intel_power_well_enable(dev_priv, well); 2382 2383 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 2384 intel_power_well_enable(dev_priv, well); 2385 2386 mutex_unlock(&power_domains->lock); 2387 2388 skl_init_cdclk(dev_priv); 2389 2390 gen9_dbuf_enable(dev_priv); 2391 2392 if (resume && dev_priv->csr.dmc_payload) 2393 intel_csr_load_program(dev_priv); 2394 } 2395 2396 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 2397 { 2398 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2399 struct i915_power_well *well; 2400 2401 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2402 2403 gen9_dbuf_disable(dev_priv); 2404 2405 skl_uninit_cdclk(dev_priv); 2406 2407 /* The spec doesn't call for removing the reset handshake flag */ 2408 /* disable PG1 and Misc I/O */ 2409 2410 mutex_lock(&power_domains->lock); 2411 2412 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 2413 intel_power_well_disable(dev_priv, well); 2414 2415 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2416 intel_power_well_disable(dev_priv, well); 2417 2418 mutex_unlock(&power_domains->lock); 2419 } 2420 2421 void bxt_display_core_init(struct drm_i915_private *dev_priv, 2422 bool resume) 2423 { 2424 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2425 struct i915_power_well *well; 2426 uint32_t val; 2427 2428 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2429 2430 /* 2431 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 2432 * or else the reset will hang because there is no PCH to respond. 2433 * Move the handshake programming to initialization sequence. 2434 * Previously was left up to BIOS. 2435 */ 2436 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2437 val &= ~RESET_PCH_HANDSHAKE_ENABLE; 2438 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2439 2440 /* Enable PG1 */ 2441 mutex_lock(&power_domains->lock); 2442 2443 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2444 intel_power_well_enable(dev_priv, well); 2445 2446 mutex_unlock(&power_domains->lock); 2447 2448 bxt_init_cdclk(dev_priv); 2449 2450 gen9_dbuf_enable(dev_priv); 2451 2452 if (resume && dev_priv->csr.dmc_payload) 2453 intel_csr_load_program(dev_priv); 2454 } 2455 2456 void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 2457 { 2458 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2459 struct i915_power_well *well; 2460 2461 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2462 2463 gen9_dbuf_disable(dev_priv); 2464 2465 bxt_uninit_cdclk(dev_priv); 2466 2467 /* The spec doesn't call for removing the reset handshake flag */ 2468 2469 /* Disable PG1 */ 2470 mutex_lock(&power_domains->lock); 2471 2472 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2473 intel_power_well_disable(dev_priv, well); 2474 2475 mutex_unlock(&power_domains->lock); 2476 } 2477 2478 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 2479 { 2480 struct i915_power_well *cmn_bc = 2481 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2482 struct i915_power_well *cmn_d = 2483 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 2484 2485 /* 2486 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 2487 * workaround never ever read DISPLAY_PHY_CONTROL, and 2488 * instead maintain a shadow copy ourselves. Use the actual 2489 * power well state and lane status to reconstruct the 2490 * expected initial value. 2491 */ 2492 dev_priv->chv_phy_control = 2493 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 2494 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 2495 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 2496 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 2497 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 2498 2499 /* 2500 * If all lanes are disabled we leave the override disabled 2501 * with all power down bits cleared to match the state we 2502 * would use after disabling the port. Otherwise enable the 2503 * override and set the lane powerdown bits accding to the 2504 * current lane status. 2505 */ 2506 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 2507 uint32_t status = I915_READ(DPLL(PIPE_A)); 2508 unsigned int mask; 2509 2510 mask = status & DPLL_PORTB_READY_MASK; 2511 if (mask == 0xf) 2512 mask = 0x0; 2513 else 2514 dev_priv->chv_phy_control |= 2515 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 2516 2517 dev_priv->chv_phy_control |= 2518 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 2519 2520 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 2521 if (mask == 0xf) 2522 mask = 0x0; 2523 else 2524 dev_priv->chv_phy_control |= 2525 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 2526 2527 dev_priv->chv_phy_control |= 2528 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 2529 2530 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 2531 2532 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 2533 } else { 2534 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 2535 } 2536 2537 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 2538 uint32_t status = I915_READ(DPIO_PHY_STATUS); 2539 unsigned int mask; 2540 2541 mask = status & DPLL_PORTD_READY_MASK; 2542 2543 if (mask == 0xf) 2544 mask = 0x0; 2545 else 2546 dev_priv->chv_phy_control |= 2547 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 2548 2549 dev_priv->chv_phy_control |= 2550 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 2551 2552 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 2553 2554 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 2555 } else { 2556 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 2557 } 2558 2559 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 2560 2561 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 2562 dev_priv->chv_phy_control); 2563 } 2564 2565 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 2566 { 2567 struct i915_power_well *cmn = 2568 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2569 struct i915_power_well *disp2d = 2570 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 2571 2572 /* If the display might be already active skip this */ 2573 if (cmn->ops->is_enabled(dev_priv, cmn) && 2574 disp2d->ops->is_enabled(dev_priv, disp2d) && 2575 I915_READ(DPIO_CTL) & DPIO_CMNRST) 2576 return; 2577 2578 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 2579 2580 /* cmnlane needs DPLL registers */ 2581 disp2d->ops->enable(dev_priv, disp2d); 2582 2583 /* 2584 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 2585 * Need to assert and de-assert PHY SB reset by gating the 2586 * common lane power, then un-gating it. 2587 * Simply ungating isn't enough to reset the PHY enough to get 2588 * ports and lanes running. 2589 */ 2590 cmn->ops->disable(dev_priv, cmn); 2591 } 2592 2593 /** 2594 * intel_power_domains_init_hw - initialize hardware power domain state 2595 * @dev_priv: i915 device instance 2596 * @resume: Called from resume code paths or not 2597 * 2598 * This function initializes the hardware power domain state and enables all 2599 * power domains using intel_display_set_init_power(). 2600 */ 2601 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 2602 { 2603 struct drm_device *dev = &dev_priv->drm; 2604 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2605 2606 power_domains->initializing = true; 2607 2608 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 2609 skl_display_core_init(dev_priv, resume); 2610 } else if (IS_BROXTON(dev)) { 2611 bxt_display_core_init(dev_priv, resume); 2612 } else if (IS_CHERRYVIEW(dev)) { 2613 mutex_lock(&power_domains->lock); 2614 chv_phy_control_init(dev_priv); 2615 mutex_unlock(&power_domains->lock); 2616 } else if (IS_VALLEYVIEW(dev)) { 2617 mutex_lock(&power_domains->lock); 2618 vlv_cmnlane_wa(dev_priv); 2619 mutex_unlock(&power_domains->lock); 2620 } 2621 2622 /* For now, we need the power well to be always enabled. */ 2623 intel_display_set_init_power(dev_priv, true); 2624 /* Disable power support if the user asked so. */ 2625 if (!i915.disable_power_well) 2626 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 2627 intel_power_domains_sync_hw(dev_priv); 2628 power_domains->initializing = false; 2629 } 2630 2631 /** 2632 * intel_power_domains_suspend - suspend power domain state 2633 * @dev_priv: i915 device instance 2634 * 2635 * This function prepares the hardware power domain state before entering 2636 * system suspend. It must be paired with intel_power_domains_init_hw(). 2637 */ 2638 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 2639 { 2640 /* 2641 * Even if power well support was disabled we still want to disable 2642 * power wells while we are system suspended. 2643 */ 2644 if (!i915.disable_power_well) 2645 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2646 2647 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 2648 skl_display_core_uninit(dev_priv); 2649 else if (IS_BROXTON(dev_priv)) 2650 bxt_display_core_uninit(dev_priv); 2651 } 2652 2653 /** 2654 * intel_runtime_pm_get - grab a runtime pm reference 2655 * @dev_priv: i915 device instance 2656 * 2657 * This function grabs a device-level runtime pm reference (mostly used for GEM 2658 * code to ensure the GTT or GT is on) and ensures that it is powered up. 2659 * 2660 * Any runtime pm reference obtained by this function must have a symmetric 2661 * call to intel_runtime_pm_put() to release the reference again. 2662 */ 2663 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 2664 { 2665 struct drm_device *dev = &dev_priv->drm; 2666 struct device *device = &dev->pdev->dev; 2667 2668 pm_runtime_get_sync(device); 2669 2670 atomic_inc(&dev_priv->pm.wakeref_count); 2671 assert_rpm_wakelock_held(dev_priv); 2672 } 2673 2674 /** 2675 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 2676 * @dev_priv: i915 device instance 2677 * 2678 * This function grabs a device-level runtime pm reference if the device is 2679 * already in use and ensures that it is powered up. 2680 * 2681 * Any runtime pm reference obtained by this function must have a symmetric 2682 * call to intel_runtime_pm_put() to release the reference again. 2683 */ 2684 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) 2685 { 2686 #ifndef __DragonFly__ 2687 struct drm_device *dev = &dev_priv->drm; 2688 struct device *device = &dev->pdev->dev; 2689 2690 if (IS_ENABLED(CONFIG_PM)) { 2691 int ret = pm_runtime_get_if_in_use(device); 2692 2693 /* 2694 * In cases runtime PM is disabled by the RPM core and we get 2695 * an -EINVAL return value we are not supposed to call this 2696 * function, since the power state is undefined. This applies 2697 * atm to the late/early system suspend/resume handlers. 2698 */ 2699 WARN_ON_ONCE(ret < 0); 2700 if (ret <= 0) 2701 return false; 2702 } 2703 2704 atomic_inc(&dev_priv->pm.wakeref_count); 2705 assert_rpm_wakelock_held(dev_priv); 2706 #endif 2707 2708 return true; 2709 } 2710 2711 /** 2712 * intel_runtime_pm_get_noresume - grab a runtime pm reference 2713 * @dev_priv: i915 device instance 2714 * 2715 * This function grabs a device-level runtime pm reference (mostly used for GEM 2716 * code to ensure the GTT or GT is on). 2717 * 2718 * It will _not_ power up the device but instead only check that it's powered 2719 * on. Therefore it is only valid to call this functions from contexts where 2720 * the device is known to be powered up and where trying to power it up would 2721 * result in hilarity and deadlocks. That pretty much means only the system 2722 * suspend/resume code where this is used to grab runtime pm references for 2723 * delayed setup down in work items. 2724 * 2725 * Any runtime pm reference obtained by this function must have a symmetric 2726 * call to intel_runtime_pm_put() to release the reference again. 2727 */ 2728 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 2729 { 2730 #if 0 2731 struct drm_device *dev = &dev_priv->drm; 2732 struct device *device = &dev->pdev->dev; 2733 #endif 2734 2735 assert_rpm_wakelock_held(dev_priv); 2736 #if 0 2737 pm_runtime_get_noresume(device); 2738 #endif 2739 2740 atomic_inc(&dev_priv->pm.wakeref_count); 2741 } 2742 2743 /** 2744 * intel_runtime_pm_put - release a runtime pm reference 2745 * @dev_priv: i915 device instance 2746 * 2747 * This function drops the device-level runtime pm reference obtained by 2748 * intel_runtime_pm_get() and might power down the corresponding 2749 * hardware block right away if this is the last reference. 2750 */ 2751 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 2752 { 2753 struct drm_device *dev = &dev_priv->drm; 2754 struct device *device = &dev->pdev->dev; 2755 2756 assert_rpm_wakelock_held(dev_priv); 2757 if (atomic_dec_and_test(&dev_priv->pm.wakeref_count)) 2758 atomic_inc(&dev_priv->pm.atomic_seq); 2759 2760 pm_runtime_mark_last_busy(device); 2761 pm_runtime_put_autosuspend(device); 2762 } 2763 2764 /** 2765 * intel_runtime_pm_enable - enable runtime pm 2766 * @dev_priv: i915 device instance 2767 * 2768 * This function enables runtime pm at the end of the driver load sequence. 2769 * 2770 * Note that this function does currently not enable runtime pm for the 2771 * subordinate display power domains. That is only done on the first modeset 2772 * using intel_display_set_init_power(). 2773 */ 2774 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 2775 { 2776 #if 0 2777 struct drm_device *dev = &dev_priv->drm; 2778 struct device *device = &dev->pdev->dev; 2779 2780 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 2781 pm_runtime_mark_last_busy(device); 2782 2783 /* 2784 * Take a permanent reference to disable the RPM functionality and drop 2785 * it only when unloading the driver. Use the low level get/put helpers, 2786 * so the driver's own RPM reference tracking asserts also work on 2787 * platforms without RPM support. 2788 */ 2789 if (!HAS_RUNTIME_PM(dev)) { 2790 pm_runtime_dont_use_autosuspend(device); 2791 pm_runtime_get_sync(device); 2792 } else { 2793 pm_runtime_use_autosuspend(device); 2794 } 2795 2796 /* 2797 * The core calls the driver load handler with an RPM reference held. 2798 * We drop that here and will reacquire it during unloading in 2799 * intel_power_domains_fini(). 2800 */ 2801 pm_runtime_put_autosuspend(device); 2802 #endif 2803 } 2804 2805