1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include "i915_drv.h" 30 #include "intel_drv.h" 31 32 /** 33 * DOC: runtime pm 34 * 35 * The i915 driver supports dynamic enabling and disabling of entire hardware 36 * blocks at runtime. This is especially important on the display side where 37 * software is supposed to control many power gates manually on recent hardware, 38 * since on the GT side a lot of the power management is done by the hardware. 39 * But even there some manual control at the device level is required. 40 * 41 * Since i915 supports a diverse set of platforms with a unified codebase and 42 * hardware engineers just love to shuffle functionality around between power 43 * domains there's a sizeable amount of indirection required. This file provides 44 * generic functions to the driver for grabbing and releasing references for 45 * abstract power domains. It then maps those to the actual power wells 46 * present for a given platform. 47 */ 48 49 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 50 for (i = 0; \ 51 i < (power_domains)->power_well_count && \ 52 ((power_well) = &(power_domains)->power_wells[i]); \ 53 i++) \ 54 for_each_if ((power_well)->domains & (domain_mask)) 55 56 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 57 for (i = (power_domains)->power_well_count - 1; \ 58 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 59 i--) \ 60 for_each_if ((power_well)->domains & (domain_mask)) 61 62 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 63 int power_well_id); 64 65 const char * 66 intel_display_power_domain_str(enum intel_display_power_domain domain) 67 { 68 switch (domain) { 69 case POWER_DOMAIN_PIPE_A: 70 return "PIPE_A"; 71 case POWER_DOMAIN_PIPE_B: 72 return "PIPE_B"; 73 case POWER_DOMAIN_PIPE_C: 74 return "PIPE_C"; 75 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 76 return "PIPE_A_PANEL_FITTER"; 77 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 78 return "PIPE_B_PANEL_FITTER"; 79 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 80 return "PIPE_C_PANEL_FITTER"; 81 case POWER_DOMAIN_TRANSCODER_A: 82 return "TRANSCODER_A"; 83 case POWER_DOMAIN_TRANSCODER_B: 84 return "TRANSCODER_B"; 85 case POWER_DOMAIN_TRANSCODER_C: 86 return "TRANSCODER_C"; 87 case POWER_DOMAIN_TRANSCODER_EDP: 88 return "TRANSCODER_EDP"; 89 case POWER_DOMAIN_TRANSCODER_DSI_A: 90 return "TRANSCODER_DSI_A"; 91 case POWER_DOMAIN_TRANSCODER_DSI_C: 92 return "TRANSCODER_DSI_C"; 93 case POWER_DOMAIN_PORT_DDI_A_LANES: 94 return "PORT_DDI_A_LANES"; 95 case POWER_DOMAIN_PORT_DDI_B_LANES: 96 return "PORT_DDI_B_LANES"; 97 case POWER_DOMAIN_PORT_DDI_C_LANES: 98 return "PORT_DDI_C_LANES"; 99 case POWER_DOMAIN_PORT_DDI_D_LANES: 100 return "PORT_DDI_D_LANES"; 101 case POWER_DOMAIN_PORT_DDI_E_LANES: 102 return "PORT_DDI_E_LANES"; 103 case POWER_DOMAIN_PORT_DSI: 104 return "PORT_DSI"; 105 case POWER_DOMAIN_PORT_CRT: 106 return "PORT_CRT"; 107 case POWER_DOMAIN_PORT_OTHER: 108 return "PORT_OTHER"; 109 case POWER_DOMAIN_VGA: 110 return "VGA"; 111 case POWER_DOMAIN_AUDIO: 112 return "AUDIO"; 113 case POWER_DOMAIN_PLLS: 114 return "PLLS"; 115 case POWER_DOMAIN_AUX_A: 116 return "AUX_A"; 117 case POWER_DOMAIN_AUX_B: 118 return "AUX_B"; 119 case POWER_DOMAIN_AUX_C: 120 return "AUX_C"; 121 case POWER_DOMAIN_AUX_D: 122 return "AUX_D"; 123 case POWER_DOMAIN_GMBUS: 124 return "GMBUS"; 125 case POWER_DOMAIN_INIT: 126 return "INIT"; 127 case POWER_DOMAIN_MODESET: 128 return "MODESET"; 129 default: 130 MISSING_CASE(domain); 131 return "?"; 132 } 133 } 134 135 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 136 struct i915_power_well *power_well) 137 { 138 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 139 power_well->ops->enable(dev_priv, power_well); 140 power_well->hw_enabled = true; 141 } 142 143 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 144 struct i915_power_well *power_well) 145 { 146 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 147 power_well->hw_enabled = false; 148 power_well->ops->disable(dev_priv, power_well); 149 } 150 151 /* 152 * We should only use the power well if we explicitly asked the hardware to 153 * enable it, so check if it's enabled and also check if we've requested it to 154 * be enabled. 155 */ 156 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 157 struct i915_power_well *power_well) 158 { 159 return I915_READ(HSW_PWR_WELL_DRIVER) == 160 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 161 } 162 163 /** 164 * __intel_display_power_is_enabled - unlocked check for a power domain 165 * @dev_priv: i915 device instance 166 * @domain: power domain to check 167 * 168 * This is the unlocked version of intel_display_power_is_enabled() and should 169 * only be used from error capture and recovery code where deadlocks are 170 * possible. 171 * 172 * Returns: 173 * True when the power domain is enabled, false otherwise. 174 */ 175 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 176 enum intel_display_power_domain domain) 177 { 178 struct i915_power_domains *power_domains; 179 struct i915_power_well *power_well; 180 bool is_enabled; 181 int i; 182 183 if (dev_priv->pm.suspended) 184 return false; 185 186 power_domains = &dev_priv->power_domains; 187 188 is_enabled = true; 189 190 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 191 if (power_well->always_on) 192 continue; 193 194 if (!power_well->hw_enabled) { 195 is_enabled = false; 196 break; 197 } 198 } 199 200 return is_enabled; 201 } 202 203 /** 204 * intel_display_power_is_enabled - check for a power domain 205 * @dev_priv: i915 device instance 206 * @domain: power domain to check 207 * 208 * This function can be used to check the hw power domain state. It is mostly 209 * used in hardware state readout functions. Everywhere else code should rely 210 * upon explicit power domain reference counting to ensure that the hardware 211 * block is powered up before accessing it. 212 * 213 * Callers must hold the relevant modesetting locks to ensure that concurrent 214 * threads can't disable the power well while the caller tries to read a few 215 * registers. 216 * 217 * Returns: 218 * True when the power domain is enabled, false otherwise. 219 */ 220 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 221 enum intel_display_power_domain domain) 222 { 223 struct i915_power_domains *power_domains; 224 bool ret; 225 226 power_domains = &dev_priv->power_domains; 227 228 mutex_lock(&power_domains->lock); 229 ret = __intel_display_power_is_enabled(dev_priv, domain); 230 mutex_unlock(&power_domains->lock); 231 232 return ret; 233 } 234 235 /** 236 * intel_display_set_init_power - set the initial power domain state 237 * @dev_priv: i915 device instance 238 * @enable: whether to enable or disable the initial power domain state 239 * 240 * For simplicity our driver load/unload and system suspend/resume code assumes 241 * that all power domains are always enabled. This functions controls the state 242 * of this little hack. While the initial power domain state is enabled runtime 243 * pm is effectively disabled. 244 */ 245 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 246 bool enable) 247 { 248 if (dev_priv->power_domains.init_power_on == enable) 249 return; 250 251 if (enable) 252 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 253 else 254 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 255 256 dev_priv->power_domains.init_power_on = enable; 257 } 258 259 /* 260 * Starting with Haswell, we have a "Power Down Well" that can be turned off 261 * when not needed anymore. We have 4 registers that can request the power well 262 * to be enabled, and it will only be disabled if none of the registers is 263 * requesting it to be enabled. 264 */ 265 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 266 { 267 struct drm_device *dev = dev_priv->dev; 268 269 /* 270 * After we re-enable the power well, if we touch VGA register 0x3d5 271 * we'll get unclaimed register interrupts. This stops after we write 272 * anything to the VGA MSR register. The vgacon module uses this 273 * register all the time, so if we unbind our driver and, as a 274 * consequence, bind vgacon, we'll get stuck in an infinite loop at 275 * console_unlock(). So make here we touch the VGA MSR register, making 276 * sure vgacon can keep working normally without triggering interrupts 277 * and error messages. 278 */ 279 #if 0 280 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 281 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 282 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 283 #endif 284 285 if (IS_BROADWELL(dev)) 286 gen8_irq_power_well_post_enable(dev_priv, 287 1 << PIPE_C | 1 << PIPE_B); 288 } 289 290 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv) 291 { 292 if (IS_BROADWELL(dev_priv)) 293 gen8_irq_power_well_pre_disable(dev_priv, 294 1 << PIPE_C | 1 << PIPE_B); 295 } 296 297 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, 298 struct i915_power_well *power_well) 299 { 300 #if 0 301 struct drm_device *dev = dev_priv->dev; 302 #endif 303 304 /* 305 * After we re-enable the power well, if we touch VGA register 0x3d5 306 * we'll get unclaimed register interrupts. This stops after we write 307 * anything to the VGA MSR register. The vgacon module uses this 308 * register all the time, so if we unbind our driver and, as a 309 * consequence, bind vgacon, we'll get stuck in an infinite loop at 310 * console_unlock(). So make here we touch the VGA MSR register, making 311 * sure vgacon can keep working normally without triggering interrupts 312 * and error messages. 313 */ 314 if (power_well->data == SKL_DISP_PW_2) { 315 #if 0 316 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 317 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 318 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 319 #endif 320 321 gen8_irq_power_well_post_enable(dev_priv, 322 1 << PIPE_C | 1 << PIPE_B); 323 } 324 } 325 326 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, 327 struct i915_power_well *power_well) 328 { 329 if (power_well->data == SKL_DISP_PW_2) 330 gen8_irq_power_well_pre_disable(dev_priv, 331 1 << PIPE_C | 1 << PIPE_B); 332 } 333 334 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 335 struct i915_power_well *power_well, bool enable) 336 { 337 bool is_enabled, enable_requested; 338 uint32_t tmp; 339 340 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 341 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 342 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 343 344 if (enable) { 345 if (!enable_requested) 346 I915_WRITE(HSW_PWR_WELL_DRIVER, 347 HSW_PWR_WELL_ENABLE_REQUEST); 348 349 if (!is_enabled) { 350 DRM_DEBUG_KMS("Enabling power well\n"); 351 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 352 HSW_PWR_WELL_STATE_ENABLED), 20)) 353 DRM_ERROR("Timeout enabling power well\n"); 354 hsw_power_well_post_enable(dev_priv); 355 } 356 357 } else { 358 if (enable_requested) { 359 hsw_power_well_pre_disable(dev_priv); 360 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 361 POSTING_READ(HSW_PWR_WELL_DRIVER); 362 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 363 } 364 } 365 } 366 367 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 368 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 369 BIT(POWER_DOMAIN_PIPE_B) | \ 370 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 371 BIT(POWER_DOMAIN_PIPE_C) | \ 372 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 373 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 374 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 375 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 376 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 377 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 378 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 379 BIT(POWER_DOMAIN_AUX_B) | \ 380 BIT(POWER_DOMAIN_AUX_C) | \ 381 BIT(POWER_DOMAIN_AUX_D) | \ 382 BIT(POWER_DOMAIN_AUDIO) | \ 383 BIT(POWER_DOMAIN_VGA) | \ 384 BIT(POWER_DOMAIN_INIT)) 385 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ 386 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 387 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 388 BIT(POWER_DOMAIN_INIT)) 389 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ 390 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 391 BIT(POWER_DOMAIN_INIT)) 392 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ 393 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 394 BIT(POWER_DOMAIN_INIT)) 395 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ 396 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 397 BIT(POWER_DOMAIN_INIT)) 398 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 399 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 400 BIT(POWER_DOMAIN_MODESET) | \ 401 BIT(POWER_DOMAIN_AUX_A) | \ 402 BIT(POWER_DOMAIN_INIT)) 403 404 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 405 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 406 BIT(POWER_DOMAIN_PIPE_B) | \ 407 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 408 BIT(POWER_DOMAIN_PIPE_C) | \ 409 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 410 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 411 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 412 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 413 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 414 BIT(POWER_DOMAIN_AUX_B) | \ 415 BIT(POWER_DOMAIN_AUX_C) | \ 416 BIT(POWER_DOMAIN_AUDIO) | \ 417 BIT(POWER_DOMAIN_VGA) | \ 418 BIT(POWER_DOMAIN_GMBUS) | \ 419 BIT(POWER_DOMAIN_INIT)) 420 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 421 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 422 BIT(POWER_DOMAIN_MODESET) | \ 423 BIT(POWER_DOMAIN_AUX_A) | \ 424 BIT(POWER_DOMAIN_INIT)) 425 426 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 427 { 428 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 429 "DC9 already programmed to be enabled.\n"); 430 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 431 "DC5 still not disabled to enable DC9.\n"); 432 WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); 433 WARN_ONCE(intel_irqs_enabled(dev_priv), 434 "Interrupts not disabled yet.\n"); 435 436 /* 437 * TODO: check for the following to verify the conditions to enter DC9 438 * state are satisfied: 439 * 1] Check relevant display engine registers to verify if mode set 440 * disable sequence was followed. 441 * 2] Check if display uninitialize sequence is initialized. 442 */ 443 } 444 445 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 446 { 447 WARN_ONCE(intel_irqs_enabled(dev_priv), 448 "Interrupts not disabled yet.\n"); 449 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 450 "DC5 still not disabled.\n"); 451 452 /* 453 * TODO: check for the following to verify DC9 state was indeed 454 * entered before programming to disable it: 455 * 1] Check relevant display engine registers to verify if mode 456 * set disable sequence was followed. 457 * 2] Check if display uninitialize sequence is initialized. 458 */ 459 } 460 461 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 462 u32 state) 463 { 464 int rewrites = 0; 465 int rereads = 0; 466 u32 v; 467 468 I915_WRITE(DC_STATE_EN, state); 469 470 /* It has been observed that disabling the dc6 state sometimes 471 * doesn't stick and dmc keeps returning old value. Make sure 472 * the write really sticks enough times and also force rewrite until 473 * we are confident that state is exactly what we want. 474 */ 475 do { 476 v = I915_READ(DC_STATE_EN); 477 478 if (v != state) { 479 I915_WRITE(DC_STATE_EN, state); 480 rewrites++; 481 rereads = 0; 482 } else if (rereads++ > 5) { 483 break; 484 } 485 486 } while (rewrites < 100); 487 488 if (v != state) 489 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", 490 state, v); 491 492 /* Most of the times we need one retry, avoid spam */ 493 if (rewrites > 1) 494 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", 495 state, rewrites); 496 } 497 498 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) 499 { 500 u32 mask; 501 502 mask = DC_STATE_EN_UPTO_DC5; 503 if (IS_BROXTON(dev_priv)) 504 mask |= DC_STATE_EN_DC9; 505 else 506 mask |= DC_STATE_EN_UPTO_DC6; 507 508 return mask; 509 } 510 511 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) 512 { 513 u32 val; 514 515 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); 516 517 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", 518 dev_priv->csr.dc_state, val); 519 dev_priv->csr.dc_state = val; 520 } 521 522 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 523 { 524 uint32_t val; 525 uint32_t mask; 526 527 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) 528 state &= dev_priv->csr.allowed_dc_mask; 529 530 val = I915_READ(DC_STATE_EN); 531 mask = gen9_dc_mask(dev_priv); 532 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 533 val & mask, state); 534 535 /* Check if DMC is ignoring our DC state requests */ 536 if ((val & mask) != dev_priv->csr.dc_state) 537 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", 538 dev_priv->csr.dc_state, val & mask); 539 540 val &= ~mask; 541 val |= state; 542 543 gen9_write_dc_state(dev_priv, val); 544 545 dev_priv->csr.dc_state = val & mask; 546 } 547 548 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 549 { 550 assert_can_enable_dc9(dev_priv); 551 552 DRM_DEBUG_KMS("Enabling DC9\n"); 553 554 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 555 } 556 557 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 558 { 559 assert_can_disable_dc9(dev_priv); 560 561 DRM_DEBUG_KMS("Disabling DC9\n"); 562 563 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 564 } 565 566 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 567 { 568 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 569 "CSR program storage start is NULL\n"); 570 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 571 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 572 } 573 574 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 575 { 576 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 577 SKL_DISP_PW_2); 578 579 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 580 581 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 582 "DC5 already programmed to be enabled.\n"); 583 assert_rpm_wakelock_held(dev_priv); 584 585 assert_csr_loaded(dev_priv); 586 } 587 588 void gen9_enable_dc5(struct drm_i915_private *dev_priv) 589 { 590 assert_can_enable_dc5(dev_priv); 591 592 DRM_DEBUG_KMS("Enabling DC5\n"); 593 594 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 595 } 596 597 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 598 { 599 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 600 "Backlight is not disabled.\n"); 601 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 602 "DC6 already programmed to be enabled.\n"); 603 604 assert_csr_loaded(dev_priv); 605 } 606 607 void skl_enable_dc6(struct drm_i915_private *dev_priv) 608 { 609 assert_can_enable_dc6(dev_priv); 610 611 DRM_DEBUG_KMS("Enabling DC6\n"); 612 613 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 614 615 } 616 617 void skl_disable_dc6(struct drm_i915_private *dev_priv) 618 { 619 DRM_DEBUG_KMS("Disabling DC6\n"); 620 621 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 622 } 623 624 static void 625 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv, 626 struct i915_power_well *power_well) 627 { 628 enum skl_disp_power_wells power_well_id = power_well->data; 629 u32 val; 630 u32 mask; 631 632 mask = SKL_POWER_WELL_REQ(power_well_id); 633 634 val = I915_READ(HSW_PWR_WELL_KVMR); 635 if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n", 636 power_well->name)) 637 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask); 638 639 val = I915_READ(HSW_PWR_WELL_BIOS); 640 val |= I915_READ(HSW_PWR_WELL_DEBUG); 641 642 if (!(val & mask)) 643 return; 644 645 /* 646 * DMC is known to force on the request bits for power well 1 on SKL 647 * and BXT and the misc IO power well on SKL but we don't expect any 648 * other request bits to be set, so WARN for those. 649 */ 650 if (power_well_id == SKL_DISP_PW_1 || 651 ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && 652 power_well_id == SKL_DISP_PW_MISC_IO)) 653 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on " 654 "by DMC\n", power_well->name); 655 else 656 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n", 657 power_well->name); 658 659 I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask); 660 I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask); 661 } 662 663 static void skl_set_power_well(struct drm_i915_private *dev_priv, 664 struct i915_power_well *power_well, bool enable) 665 { 666 uint32_t tmp, fuse_status; 667 uint32_t req_mask, state_mask; 668 bool is_enabled, enable_requested, check_fuse_status = false; 669 670 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 671 fuse_status = I915_READ(SKL_FUSE_STATUS); 672 673 switch (power_well->data) { 674 case SKL_DISP_PW_1: 675 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 676 SKL_FUSE_PG0_DIST_STATUS), 1)) { 677 DRM_ERROR("PG0 not enabled\n"); 678 return; 679 } 680 break; 681 case SKL_DISP_PW_2: 682 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { 683 DRM_ERROR("PG1 in disabled state\n"); 684 return; 685 } 686 break; 687 case SKL_DISP_PW_DDI_A_E: 688 case SKL_DISP_PW_DDI_B: 689 case SKL_DISP_PW_DDI_C: 690 case SKL_DISP_PW_DDI_D: 691 case SKL_DISP_PW_MISC_IO: 692 break; 693 default: 694 WARN(1, "Unknown power well %lu\n", power_well->data); 695 return; 696 } 697 698 req_mask = SKL_POWER_WELL_REQ(power_well->data); 699 enable_requested = tmp & req_mask; 700 state_mask = SKL_POWER_WELL_STATE(power_well->data); 701 is_enabled = tmp & state_mask; 702 703 if (!enable && enable_requested) 704 skl_power_well_pre_disable(dev_priv, power_well); 705 706 if (enable) { 707 if (!enable_requested) { 708 WARN((tmp & state_mask) && 709 !I915_READ(HSW_PWR_WELL_BIOS), 710 "Invalid for power well status to be enabled, unless done by the BIOS, \ 711 when request is to disable!\n"); 712 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); 713 } 714 715 if (!is_enabled) { 716 DRM_DEBUG_KMS("Enabling %s\n", power_well->name); 717 check_fuse_status = true; 718 } 719 } else { 720 if (enable_requested) { 721 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); 722 POSTING_READ(HSW_PWR_WELL_DRIVER); 723 DRM_DEBUG_KMS("Disabling %s\n", power_well->name); 724 } 725 726 if (IS_GEN9(dev_priv)) 727 gen9_sanitize_power_well_requests(dev_priv, power_well); 728 } 729 730 if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable, 731 1)) 732 DRM_ERROR("%s %s timeout\n", 733 power_well->name, enable ? "enable" : "disable"); 734 735 if (check_fuse_status) { 736 if (power_well->data == SKL_DISP_PW_1) { 737 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 738 SKL_FUSE_PG1_DIST_STATUS), 1)) 739 DRM_ERROR("PG1 distributing status timeout\n"); 740 } else if (power_well->data == SKL_DISP_PW_2) { 741 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 742 SKL_FUSE_PG2_DIST_STATUS), 1)) 743 DRM_ERROR("PG2 distributing status timeout\n"); 744 } 745 } 746 747 if (enable && !is_enabled) 748 skl_power_well_post_enable(dev_priv, power_well); 749 } 750 751 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 752 struct i915_power_well *power_well) 753 { 754 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 755 756 /* 757 * We're taking over the BIOS, so clear any requests made by it since 758 * the driver is in charge now. 759 */ 760 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 761 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 762 } 763 764 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 765 struct i915_power_well *power_well) 766 { 767 hsw_set_power_well(dev_priv, power_well, true); 768 } 769 770 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 771 struct i915_power_well *power_well) 772 { 773 hsw_set_power_well(dev_priv, power_well, false); 774 } 775 776 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, 777 struct i915_power_well *power_well) 778 { 779 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | 780 SKL_POWER_WELL_STATE(power_well->data); 781 782 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; 783 } 784 785 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, 786 struct i915_power_well *power_well) 787 { 788 skl_set_power_well(dev_priv, power_well, power_well->count > 0); 789 790 /* Clear any request made by BIOS as driver is taking over */ 791 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 792 } 793 794 static void skl_power_well_enable(struct drm_i915_private *dev_priv, 795 struct i915_power_well *power_well) 796 { 797 skl_set_power_well(dev_priv, power_well, true); 798 } 799 800 static void skl_power_well_disable(struct drm_i915_private *dev_priv, 801 struct i915_power_well *power_well) 802 { 803 skl_set_power_well(dev_priv, power_well, false); 804 } 805 806 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 807 struct i915_power_well *power_well) 808 { 809 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 810 } 811 812 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 813 struct i915_power_well *power_well) 814 { 815 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 816 817 if (IS_BROXTON(dev_priv)) { 818 broxton_cdclk_verify_state(dev_priv); 819 broxton_ddi_phy_verify_state(dev_priv); 820 } 821 } 822 823 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 824 struct i915_power_well *power_well) 825 { 826 if (!dev_priv->csr.dmc_payload) 827 return; 828 829 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) 830 skl_enable_dc6(dev_priv); 831 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) 832 gen9_enable_dc5(dev_priv); 833 } 834 835 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv, 836 struct i915_power_well *power_well) 837 { 838 if (power_well->count > 0) 839 gen9_dc_off_power_well_enable(dev_priv, power_well); 840 else 841 gen9_dc_off_power_well_disable(dev_priv, power_well); 842 } 843 844 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 845 struct i915_power_well *power_well) 846 { 847 } 848 849 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 850 struct i915_power_well *power_well) 851 { 852 return true; 853 } 854 855 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 856 struct i915_power_well *power_well, bool enable) 857 { 858 enum punit_power_well power_well_id = power_well->data; 859 u32 mask; 860 u32 state; 861 u32 ctrl; 862 863 mask = PUNIT_PWRGT_MASK(power_well_id); 864 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 865 PUNIT_PWRGT_PWR_GATE(power_well_id); 866 867 mutex_lock(&dev_priv->rps.hw_lock); 868 869 #define COND \ 870 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 871 872 if (COND) 873 goto out; 874 875 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 876 ctrl &= ~mask; 877 ctrl |= state; 878 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 879 880 if (wait_for(COND, 100)) 881 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 882 state, 883 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 884 885 #undef COND 886 887 out: 888 mutex_unlock(&dev_priv->rps.hw_lock); 889 } 890 891 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 892 struct i915_power_well *power_well) 893 { 894 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 895 } 896 897 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 898 struct i915_power_well *power_well) 899 { 900 vlv_set_power_well(dev_priv, power_well, true); 901 } 902 903 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 904 struct i915_power_well *power_well) 905 { 906 vlv_set_power_well(dev_priv, power_well, false); 907 } 908 909 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 910 struct i915_power_well *power_well) 911 { 912 int power_well_id = power_well->data; 913 bool enabled = false; 914 u32 mask; 915 u32 state; 916 u32 ctrl; 917 918 mask = PUNIT_PWRGT_MASK(power_well_id); 919 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 920 921 mutex_lock(&dev_priv->rps.hw_lock); 922 923 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 924 /* 925 * We only ever set the power-on and power-gate states, anything 926 * else is unexpected. 927 */ 928 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 929 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 930 if (state == ctrl) 931 enabled = true; 932 933 /* 934 * A transient state at this point would mean some unexpected party 935 * is poking at the power controls too. 936 */ 937 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 938 WARN_ON(ctrl != state); 939 940 mutex_unlock(&dev_priv->rps.hw_lock); 941 942 return enabled; 943 } 944 945 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 946 { 947 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); 948 949 /* 950 * Disable trickle feed and enable pnd deadline calculation 951 */ 952 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 953 I915_WRITE(CBR1_VLV, 0); 954 } 955 956 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 957 { 958 struct intel_encoder *encoder; 959 enum i915_pipe pipe; 960 961 /* 962 * Enable the CRI clock source so we can get at the 963 * display and the reference clock for VGA 964 * hotplug / manual detection. Supposedly DSI also 965 * needs the ref clock up and running. 966 * 967 * CHV DPLL B/C have some issues if VGA mode is enabled. 968 */ 969 for_each_pipe(dev_priv->dev, pipe) { 970 u32 val = I915_READ(DPLL(pipe)); 971 972 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 973 if (pipe != PIPE_A) 974 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 975 976 I915_WRITE(DPLL(pipe), val); 977 } 978 979 vlv_init_display_clock_gating(dev_priv); 980 981 spin_lock_irq(&dev_priv->irq_lock); 982 valleyview_enable_display_irqs(dev_priv); 983 spin_unlock_irq(&dev_priv->irq_lock); 984 985 /* 986 * During driver initialization/resume we can avoid restoring the 987 * part of the HW/SW state that will be inited anyway explicitly. 988 */ 989 if (dev_priv->power_domains.initializing) 990 return; 991 992 intel_hpd_init(dev_priv); 993 994 /* Re-enable the ADPA, if we have one */ 995 for_each_intel_encoder(dev_priv->dev, encoder) { 996 if (encoder->type == INTEL_OUTPUT_ANALOG) 997 intel_crt_reset(&encoder->base); 998 } 999 1000 i915_redisable_vga_power_on(dev_priv->dev); 1001 } 1002 1003 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 1004 { 1005 spin_lock_irq(&dev_priv->irq_lock); 1006 valleyview_disable_display_irqs(dev_priv); 1007 spin_unlock_irq(&dev_priv->irq_lock); 1008 1009 /* make sure we're done processing display irqs */ 1010 #if 0 1011 synchronize_irq(dev_priv->dev->irq); 1012 #endif 1013 1014 vlv_power_sequencer_reset(dev_priv); 1015 1016 intel_hpd_poll_init(dev_priv); 1017 } 1018 1019 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 1020 struct i915_power_well *power_well) 1021 { 1022 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 1023 1024 vlv_set_power_well(dev_priv, power_well, true); 1025 1026 vlv_display_power_well_init(dev_priv); 1027 } 1028 1029 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1030 struct i915_power_well *power_well) 1031 { 1032 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 1033 1034 vlv_display_power_well_deinit(dev_priv); 1035 1036 vlv_set_power_well(dev_priv, power_well, false); 1037 } 1038 1039 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1040 struct i915_power_well *power_well) 1041 { 1042 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1043 1044 /* since ref/cri clock was enabled */ 1045 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1046 1047 vlv_set_power_well(dev_priv, power_well, true); 1048 1049 /* 1050 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1051 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1052 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1053 * b. The other bits such as sfr settings / modesel may all 1054 * be set to 0. 1055 * 1056 * This should only be done on init and resume from S3 with 1057 * both PLLs disabled, or we risk losing DPIO and PLL 1058 * synchronization. 1059 */ 1060 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 1061 } 1062 1063 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1064 struct i915_power_well *power_well) 1065 { 1066 enum i915_pipe pipe; 1067 1068 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1069 1070 for_each_pipe(dev_priv, pipe) 1071 assert_pll_disabled(dev_priv, pipe); 1072 1073 /* Assert common reset */ 1074 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1075 1076 vlv_set_power_well(dev_priv, power_well, false); 1077 } 1078 1079 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 1080 1081 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1082 int power_well_id) 1083 { 1084 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1085 int i; 1086 1087 for (i = 0; i < power_domains->power_well_count; i++) { 1088 struct i915_power_well *power_well; 1089 1090 power_well = &power_domains->power_wells[i]; 1091 if (power_well->data == power_well_id) 1092 return power_well; 1093 } 1094 1095 return NULL; 1096 } 1097 1098 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1099 1100 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1101 { 1102 struct i915_power_well *cmn_bc = 1103 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1104 struct i915_power_well *cmn_d = 1105 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1106 u32 phy_control = dev_priv->chv_phy_control; 1107 u32 phy_status = 0; 1108 u32 phy_status_mask = 0xffffffff; 1109 u32 tmp; 1110 1111 /* 1112 * The BIOS can leave the PHY is some weird state 1113 * where it doesn't fully power down some parts. 1114 * Disable the asserts until the PHY has been fully 1115 * reset (ie. the power well has been disabled at 1116 * least once). 1117 */ 1118 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1119 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1120 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1121 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1122 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1123 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1124 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1125 1126 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1127 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1128 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1129 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1130 1131 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1132 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1133 1134 /* this assumes override is only used to enable lanes */ 1135 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1136 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1137 1138 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1139 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1140 1141 /* CL1 is on whenever anything is on in either channel */ 1142 if (BITS_SET(phy_control, 1143 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1144 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1145 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1146 1147 /* 1148 * The DPLLB check accounts for the pipe B + port A usage 1149 * with CL2 powered up but all the lanes in the second channel 1150 * powered down. 1151 */ 1152 if (BITS_SET(phy_control, 1153 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1154 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1155 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1156 1157 if (BITS_SET(phy_control, 1158 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1159 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1160 if (BITS_SET(phy_control, 1161 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1162 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1163 1164 if (BITS_SET(phy_control, 1165 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1166 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1167 if (BITS_SET(phy_control, 1168 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1169 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1170 } 1171 1172 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1173 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1174 1175 /* this assumes override is only used to enable lanes */ 1176 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1177 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1178 1179 if (BITS_SET(phy_control, 1180 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1181 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1182 1183 if (BITS_SET(phy_control, 1184 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1185 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1186 if (BITS_SET(phy_control, 1187 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1188 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1189 } 1190 1191 phy_status &= phy_status_mask; 1192 1193 /* 1194 * The PHY may be busy with some initial calibration and whatnot, 1195 * so the power state can take a while to actually change. 1196 */ 1197 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) 1198 WARN(phy_status != tmp, 1199 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1200 tmp, phy_status, dev_priv->chv_phy_control); 1201 } 1202 1203 #undef BITS_SET 1204 1205 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1206 struct i915_power_well *power_well) 1207 { 1208 enum dpio_phy phy; 1209 enum i915_pipe pipe; 1210 uint32_t tmp; 1211 1212 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1213 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1214 1215 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1216 pipe = PIPE_A; 1217 phy = DPIO_PHY0; 1218 } else { 1219 pipe = PIPE_C; 1220 phy = DPIO_PHY1; 1221 } 1222 1223 /* since ref/cri clock was enabled */ 1224 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1225 vlv_set_power_well(dev_priv, power_well, true); 1226 1227 /* Poll for phypwrgood signal */ 1228 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) 1229 DRM_ERROR("Display PHY %d is not power up\n", phy); 1230 1231 mutex_lock(&dev_priv->sb_lock); 1232 1233 /* Enable dynamic power down */ 1234 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1235 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1236 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1237 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1238 1239 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1240 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1241 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1242 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1243 } else { 1244 /* 1245 * Force the non-existing CL2 off. BXT does this 1246 * too, so maybe it saves some power even though 1247 * CL2 doesn't exist? 1248 */ 1249 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1250 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1251 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1252 } 1253 1254 mutex_unlock(&dev_priv->sb_lock); 1255 1256 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1257 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1258 1259 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1260 phy, dev_priv->chv_phy_control); 1261 1262 assert_chv_phy_status(dev_priv); 1263 } 1264 1265 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1266 struct i915_power_well *power_well) 1267 { 1268 enum dpio_phy phy; 1269 1270 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1271 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1272 1273 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1274 phy = DPIO_PHY0; 1275 assert_pll_disabled(dev_priv, PIPE_A); 1276 assert_pll_disabled(dev_priv, PIPE_B); 1277 } else { 1278 phy = DPIO_PHY1; 1279 assert_pll_disabled(dev_priv, PIPE_C); 1280 } 1281 1282 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1283 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1284 1285 vlv_set_power_well(dev_priv, power_well, false); 1286 1287 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1288 phy, dev_priv->chv_phy_control); 1289 1290 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1291 dev_priv->chv_phy_assert[phy] = true; 1292 1293 assert_chv_phy_status(dev_priv); 1294 } 1295 1296 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1297 enum dpio_channel ch, bool override, unsigned int mask) 1298 { 1299 enum i915_pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1300 u32 reg, val, expected, actual; 1301 1302 /* 1303 * The BIOS can leave the PHY is some weird state 1304 * where it doesn't fully power down some parts. 1305 * Disable the asserts until the PHY has been fully 1306 * reset (ie. the power well has been disabled at 1307 * least once). 1308 */ 1309 if (!dev_priv->chv_phy_assert[phy]) 1310 return; 1311 1312 if (ch == DPIO_CH0) 1313 reg = _CHV_CMN_DW0_CH0; 1314 else 1315 reg = _CHV_CMN_DW6_CH1; 1316 1317 mutex_lock(&dev_priv->sb_lock); 1318 val = vlv_dpio_read(dev_priv, pipe, reg); 1319 mutex_unlock(&dev_priv->sb_lock); 1320 1321 /* 1322 * This assumes !override is only used when the port is disabled. 1323 * All lanes should power down even without the override when 1324 * the port is disabled. 1325 */ 1326 if (!override || mask == 0xf) { 1327 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1328 /* 1329 * If CH1 common lane is not active anymore 1330 * (eg. for pipe B DPLL) the entire channel will 1331 * shut down, which causes the common lane registers 1332 * to read as 0. That means we can't actually check 1333 * the lane power down status bits, but as the entire 1334 * register reads as 0 it's a good indication that the 1335 * channel is indeed entirely powered down. 1336 */ 1337 if (ch == DPIO_CH1 && val == 0) 1338 expected = 0; 1339 } else if (mask != 0x0) { 1340 expected = DPIO_ANYDL_POWERDOWN; 1341 } else { 1342 expected = 0; 1343 } 1344 1345 if (ch == DPIO_CH0) 1346 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1347 else 1348 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1349 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1350 1351 WARN(actual != expected, 1352 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1353 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1354 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1355 reg, val); 1356 } 1357 1358 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1359 enum dpio_channel ch, bool override) 1360 { 1361 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1362 bool was_override; 1363 1364 mutex_lock(&power_domains->lock); 1365 1366 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1367 1368 if (override == was_override) 1369 goto out; 1370 1371 if (override) 1372 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1373 else 1374 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1375 1376 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1377 1378 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1379 phy, ch, dev_priv->chv_phy_control); 1380 1381 assert_chv_phy_status(dev_priv); 1382 1383 out: 1384 mutex_unlock(&power_domains->lock); 1385 1386 return was_override; 1387 } 1388 1389 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1390 bool override, unsigned int mask) 1391 { 1392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1393 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1394 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1395 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1396 1397 mutex_lock(&power_domains->lock); 1398 1399 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1400 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1401 1402 if (override) 1403 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1404 else 1405 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1406 1407 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1408 1409 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1410 phy, ch, mask, dev_priv->chv_phy_control); 1411 1412 assert_chv_phy_status(dev_priv); 1413 1414 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1415 1416 mutex_unlock(&power_domains->lock); 1417 } 1418 1419 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1420 struct i915_power_well *power_well) 1421 { 1422 enum i915_pipe pipe = power_well->data; 1423 bool enabled; 1424 u32 state, ctrl; 1425 1426 mutex_lock(&dev_priv->rps.hw_lock); 1427 1428 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1429 /* 1430 * We only ever set the power-on and power-gate states, anything 1431 * else is unexpected. 1432 */ 1433 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1434 enabled = state == DP_SSS_PWR_ON(pipe); 1435 1436 /* 1437 * A transient state at this point would mean some unexpected party 1438 * is poking at the power controls too. 1439 */ 1440 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1441 WARN_ON(ctrl << 16 != state); 1442 1443 mutex_unlock(&dev_priv->rps.hw_lock); 1444 1445 return enabled; 1446 } 1447 1448 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1449 struct i915_power_well *power_well, 1450 bool enable) 1451 { 1452 enum i915_pipe pipe = power_well->data; 1453 u32 state; 1454 u32 ctrl; 1455 1456 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1457 1458 mutex_lock(&dev_priv->rps.hw_lock); 1459 1460 #define COND \ 1461 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1462 1463 if (COND) 1464 goto out; 1465 1466 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1467 ctrl &= ~DP_SSC_MASK(pipe); 1468 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1469 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1470 1471 if (wait_for(COND, 100)) 1472 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1473 state, 1474 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1475 1476 #undef COND 1477 1478 out: 1479 mutex_unlock(&dev_priv->rps.hw_lock); 1480 } 1481 1482 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1483 struct i915_power_well *power_well) 1484 { 1485 WARN_ON_ONCE(power_well->data != PIPE_A); 1486 1487 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 1488 } 1489 1490 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1491 struct i915_power_well *power_well) 1492 { 1493 WARN_ON_ONCE(power_well->data != PIPE_A); 1494 1495 chv_set_pipe_power_well(dev_priv, power_well, true); 1496 1497 vlv_display_power_well_init(dev_priv); 1498 } 1499 1500 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1501 struct i915_power_well *power_well) 1502 { 1503 WARN_ON_ONCE(power_well->data != PIPE_A); 1504 1505 vlv_display_power_well_deinit(dev_priv); 1506 1507 chv_set_pipe_power_well(dev_priv, power_well, false); 1508 } 1509 1510 static void 1511 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 1512 enum intel_display_power_domain domain) 1513 { 1514 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1515 struct i915_power_well *power_well; 1516 int i; 1517 1518 for_each_power_well(i, power_well, BIT(domain), power_domains) { 1519 if (!power_well->count++) 1520 intel_power_well_enable(dev_priv, power_well); 1521 } 1522 1523 power_domains->domain_use_count[domain]++; 1524 } 1525 1526 /** 1527 * intel_display_power_get - grab a power domain reference 1528 * @dev_priv: i915 device instance 1529 * @domain: power domain to reference 1530 * 1531 * This function grabs a power domain reference for @domain and ensures that the 1532 * power domain and all its parents are powered up. Therefore users should only 1533 * grab a reference to the innermost power domain they need. 1534 * 1535 * Any power domain reference obtained by this function must have a symmetric 1536 * call to intel_display_power_put() to release the reference again. 1537 */ 1538 void intel_display_power_get(struct drm_i915_private *dev_priv, 1539 enum intel_display_power_domain domain) 1540 { 1541 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1542 1543 intel_runtime_pm_get(dev_priv); 1544 1545 mutex_lock(&power_domains->lock); 1546 1547 __intel_display_power_get_domain(dev_priv, domain); 1548 1549 mutex_unlock(&power_domains->lock); 1550 } 1551 1552 /** 1553 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 1554 * @dev_priv: i915 device instance 1555 * @domain: power domain to reference 1556 * 1557 * This function grabs a power domain reference for @domain and ensures that the 1558 * power domain and all its parents are powered up. Therefore users should only 1559 * grab a reference to the innermost power domain they need. 1560 * 1561 * Any power domain reference obtained by this function must have a symmetric 1562 * call to intel_display_power_put() to release the reference again. 1563 */ 1564 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1565 enum intel_display_power_domain domain) 1566 { 1567 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1568 bool is_enabled; 1569 1570 if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1571 return false; 1572 1573 mutex_lock(&power_domains->lock); 1574 1575 if (__intel_display_power_is_enabled(dev_priv, domain)) { 1576 __intel_display_power_get_domain(dev_priv, domain); 1577 is_enabled = true; 1578 } else { 1579 is_enabled = false; 1580 } 1581 1582 mutex_unlock(&power_domains->lock); 1583 1584 if (!is_enabled) 1585 intel_runtime_pm_put(dev_priv); 1586 1587 return is_enabled; 1588 } 1589 1590 /** 1591 * intel_display_power_put - release a power domain reference 1592 * @dev_priv: i915 device instance 1593 * @domain: power domain to reference 1594 * 1595 * This function drops the power domain reference obtained by 1596 * intel_display_power_get() and might power down the corresponding hardware 1597 * block right away if this is the last reference. 1598 */ 1599 void intel_display_power_put(struct drm_i915_private *dev_priv, 1600 enum intel_display_power_domain domain) 1601 { 1602 struct i915_power_domains *power_domains; 1603 struct i915_power_well *power_well; 1604 int i; 1605 1606 power_domains = &dev_priv->power_domains; 1607 1608 mutex_lock(&power_domains->lock); 1609 1610 WARN(!power_domains->domain_use_count[domain], 1611 "Use count on domain %s is already zero\n", 1612 intel_display_power_domain_str(domain)); 1613 power_domains->domain_use_count[domain]--; 1614 1615 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 1616 WARN(!power_well->count, 1617 "Use count on power well %s is already zero", 1618 power_well->name); 1619 1620 if (!--power_well->count) 1621 intel_power_well_disable(dev_priv, power_well); 1622 } 1623 1624 mutex_unlock(&power_domains->lock); 1625 1626 intel_runtime_pm_put(dev_priv); 1627 } 1628 1629 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1630 BIT(POWER_DOMAIN_PIPE_B) | \ 1631 BIT(POWER_DOMAIN_PIPE_C) | \ 1632 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1633 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1634 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1635 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1636 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1637 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 1638 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1639 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1640 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1641 BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1642 BIT(POWER_DOMAIN_VGA) | \ 1643 BIT(POWER_DOMAIN_AUDIO) | \ 1644 BIT(POWER_DOMAIN_INIT)) 1645 1646 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1647 BIT(POWER_DOMAIN_PIPE_B) | \ 1648 BIT(POWER_DOMAIN_PIPE_C) | \ 1649 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1650 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1651 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1652 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1653 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 1654 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1655 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1656 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1657 BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ 1658 BIT(POWER_DOMAIN_VGA) | \ 1659 BIT(POWER_DOMAIN_AUDIO) | \ 1660 BIT(POWER_DOMAIN_INIT)) 1661 1662 #define VLV_DISPLAY_POWER_DOMAINS ( \ 1663 BIT(POWER_DOMAIN_PIPE_A) | \ 1664 BIT(POWER_DOMAIN_PIPE_B) | \ 1665 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1666 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1667 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1668 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1669 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1670 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1671 BIT(POWER_DOMAIN_PORT_DSI) | \ 1672 BIT(POWER_DOMAIN_PORT_CRT) | \ 1673 BIT(POWER_DOMAIN_VGA) | \ 1674 BIT(POWER_DOMAIN_AUDIO) | \ 1675 BIT(POWER_DOMAIN_AUX_B) | \ 1676 BIT(POWER_DOMAIN_AUX_C) | \ 1677 BIT(POWER_DOMAIN_GMBUS) | \ 1678 BIT(POWER_DOMAIN_INIT)) 1679 1680 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1681 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1682 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1683 BIT(POWER_DOMAIN_PORT_CRT) | \ 1684 BIT(POWER_DOMAIN_AUX_B) | \ 1685 BIT(POWER_DOMAIN_AUX_C) | \ 1686 BIT(POWER_DOMAIN_INIT)) 1687 1688 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1689 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1690 BIT(POWER_DOMAIN_AUX_B) | \ 1691 BIT(POWER_DOMAIN_INIT)) 1692 1693 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1694 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1695 BIT(POWER_DOMAIN_AUX_B) | \ 1696 BIT(POWER_DOMAIN_INIT)) 1697 1698 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1699 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1700 BIT(POWER_DOMAIN_AUX_C) | \ 1701 BIT(POWER_DOMAIN_INIT)) 1702 1703 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1704 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1705 BIT(POWER_DOMAIN_AUX_C) | \ 1706 BIT(POWER_DOMAIN_INIT)) 1707 1708 #define CHV_DISPLAY_POWER_DOMAINS ( \ 1709 BIT(POWER_DOMAIN_PIPE_A) | \ 1710 BIT(POWER_DOMAIN_PIPE_B) | \ 1711 BIT(POWER_DOMAIN_PIPE_C) | \ 1712 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 1713 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 1714 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 1715 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 1716 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 1717 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 1718 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1719 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1720 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1721 BIT(POWER_DOMAIN_PORT_DSI) | \ 1722 BIT(POWER_DOMAIN_VGA) | \ 1723 BIT(POWER_DOMAIN_AUDIO) | \ 1724 BIT(POWER_DOMAIN_AUX_B) | \ 1725 BIT(POWER_DOMAIN_AUX_C) | \ 1726 BIT(POWER_DOMAIN_AUX_D) | \ 1727 BIT(POWER_DOMAIN_GMBUS) | \ 1728 BIT(POWER_DOMAIN_INIT)) 1729 1730 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1731 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1732 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1733 BIT(POWER_DOMAIN_AUX_B) | \ 1734 BIT(POWER_DOMAIN_AUX_C) | \ 1735 BIT(POWER_DOMAIN_INIT)) 1736 1737 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1738 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1739 BIT(POWER_DOMAIN_AUX_D) | \ 1740 BIT(POWER_DOMAIN_INIT)) 1741 1742 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1743 .sync_hw = i9xx_always_on_power_well_noop, 1744 .enable = i9xx_always_on_power_well_noop, 1745 .disable = i9xx_always_on_power_well_noop, 1746 .is_enabled = i9xx_always_on_power_well_enabled, 1747 }; 1748 1749 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1750 .sync_hw = chv_pipe_power_well_sync_hw, 1751 .enable = chv_pipe_power_well_enable, 1752 .disable = chv_pipe_power_well_disable, 1753 .is_enabled = chv_pipe_power_well_enabled, 1754 }; 1755 1756 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1757 .sync_hw = vlv_power_well_sync_hw, 1758 .enable = chv_dpio_cmn_power_well_enable, 1759 .disable = chv_dpio_cmn_power_well_disable, 1760 .is_enabled = vlv_power_well_enabled, 1761 }; 1762 1763 static struct i915_power_well i9xx_always_on_power_well[] = { 1764 { 1765 .name = "always-on", 1766 .always_on = 1, 1767 .domains = POWER_DOMAIN_MASK, 1768 .ops = &i9xx_always_on_power_well_ops, 1769 }, 1770 }; 1771 1772 static const struct i915_power_well_ops hsw_power_well_ops = { 1773 .sync_hw = hsw_power_well_sync_hw, 1774 .enable = hsw_power_well_enable, 1775 .disable = hsw_power_well_disable, 1776 .is_enabled = hsw_power_well_enabled, 1777 }; 1778 1779 static const struct i915_power_well_ops skl_power_well_ops = { 1780 .sync_hw = skl_power_well_sync_hw, 1781 .enable = skl_power_well_enable, 1782 .disable = skl_power_well_disable, 1783 .is_enabled = skl_power_well_enabled, 1784 }; 1785 1786 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1787 .sync_hw = gen9_dc_off_power_well_sync_hw, 1788 .enable = gen9_dc_off_power_well_enable, 1789 .disable = gen9_dc_off_power_well_disable, 1790 .is_enabled = gen9_dc_off_power_well_enabled, 1791 }; 1792 1793 static struct i915_power_well hsw_power_wells[] = { 1794 { 1795 .name = "always-on", 1796 .always_on = 1, 1797 .domains = POWER_DOMAIN_MASK, 1798 .ops = &i9xx_always_on_power_well_ops, 1799 }, 1800 { 1801 .name = "display", 1802 .domains = HSW_DISPLAY_POWER_DOMAINS, 1803 .ops = &hsw_power_well_ops, 1804 }, 1805 }; 1806 1807 static struct i915_power_well bdw_power_wells[] = { 1808 { 1809 .name = "always-on", 1810 .always_on = 1, 1811 .domains = POWER_DOMAIN_MASK, 1812 .ops = &i9xx_always_on_power_well_ops, 1813 }, 1814 { 1815 .name = "display", 1816 .domains = BDW_DISPLAY_POWER_DOMAINS, 1817 .ops = &hsw_power_well_ops, 1818 }, 1819 }; 1820 1821 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1822 .sync_hw = vlv_power_well_sync_hw, 1823 .enable = vlv_display_power_well_enable, 1824 .disable = vlv_display_power_well_disable, 1825 .is_enabled = vlv_power_well_enabled, 1826 }; 1827 1828 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1829 .sync_hw = vlv_power_well_sync_hw, 1830 .enable = vlv_dpio_cmn_power_well_enable, 1831 .disable = vlv_dpio_cmn_power_well_disable, 1832 .is_enabled = vlv_power_well_enabled, 1833 }; 1834 1835 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1836 .sync_hw = vlv_power_well_sync_hw, 1837 .enable = vlv_power_well_enable, 1838 .disable = vlv_power_well_disable, 1839 .is_enabled = vlv_power_well_enabled, 1840 }; 1841 1842 static struct i915_power_well vlv_power_wells[] = { 1843 { 1844 .name = "always-on", 1845 .always_on = 1, 1846 .domains = POWER_DOMAIN_MASK, 1847 .ops = &i9xx_always_on_power_well_ops, 1848 .data = PUNIT_POWER_WELL_ALWAYS_ON, 1849 }, 1850 { 1851 .name = "display", 1852 .domains = VLV_DISPLAY_POWER_DOMAINS, 1853 .data = PUNIT_POWER_WELL_DISP2D, 1854 .ops = &vlv_display_power_well_ops, 1855 }, 1856 { 1857 .name = "dpio-tx-b-01", 1858 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1859 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1860 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1861 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1862 .ops = &vlv_dpio_power_well_ops, 1863 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 1864 }, 1865 { 1866 .name = "dpio-tx-b-23", 1867 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1868 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1869 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1870 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1871 .ops = &vlv_dpio_power_well_ops, 1872 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 1873 }, 1874 { 1875 .name = "dpio-tx-c-01", 1876 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1877 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1878 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1879 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1880 .ops = &vlv_dpio_power_well_ops, 1881 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 1882 }, 1883 { 1884 .name = "dpio-tx-c-23", 1885 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1886 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1887 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1888 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1889 .ops = &vlv_dpio_power_well_ops, 1890 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 1891 }, 1892 { 1893 .name = "dpio-common", 1894 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 1895 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1896 .ops = &vlv_dpio_cmn_power_well_ops, 1897 }, 1898 }; 1899 1900 static struct i915_power_well chv_power_wells[] = { 1901 { 1902 .name = "always-on", 1903 .always_on = 1, 1904 .domains = POWER_DOMAIN_MASK, 1905 .ops = &i9xx_always_on_power_well_ops, 1906 }, 1907 { 1908 .name = "display", 1909 /* 1910 * Pipe A power well is the new disp2d well. Pipe B and C 1911 * power wells don't actually exist. Pipe A power well is 1912 * required for any pipe to work. 1913 */ 1914 .domains = CHV_DISPLAY_POWER_DOMAINS, 1915 .data = PIPE_A, 1916 .ops = &chv_pipe_power_well_ops, 1917 }, 1918 { 1919 .name = "dpio-common-bc", 1920 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 1921 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1922 .ops = &chv_dpio_cmn_power_well_ops, 1923 }, 1924 { 1925 .name = "dpio-common-d", 1926 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 1927 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 1928 .ops = &chv_dpio_cmn_power_well_ops, 1929 }, 1930 }; 1931 1932 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 1933 int power_well_id) 1934 { 1935 struct i915_power_well *power_well; 1936 bool ret; 1937 1938 power_well = lookup_power_well(dev_priv, power_well_id); 1939 ret = power_well->ops->is_enabled(dev_priv, power_well); 1940 1941 return ret; 1942 } 1943 1944 static struct i915_power_well skl_power_wells[] = { 1945 { 1946 .name = "always-on", 1947 .always_on = 1, 1948 .domains = POWER_DOMAIN_MASK, 1949 .ops = &i9xx_always_on_power_well_ops, 1950 .data = SKL_DISP_PW_ALWAYS_ON, 1951 }, 1952 { 1953 .name = "power well 1", 1954 /* Handled by the DMC firmware */ 1955 .domains = 0, 1956 .ops = &skl_power_well_ops, 1957 .data = SKL_DISP_PW_1, 1958 }, 1959 { 1960 .name = "MISC IO power well", 1961 /* Handled by the DMC firmware */ 1962 .domains = 0, 1963 .ops = &skl_power_well_ops, 1964 .data = SKL_DISP_PW_MISC_IO, 1965 }, 1966 { 1967 .name = "DC off", 1968 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 1969 .ops = &gen9_dc_off_power_well_ops, 1970 .data = SKL_DISP_PW_DC_OFF, 1971 }, 1972 { 1973 .name = "power well 2", 1974 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1975 .ops = &skl_power_well_ops, 1976 .data = SKL_DISP_PW_2, 1977 }, 1978 { 1979 .name = "DDI A/E power well", 1980 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, 1981 .ops = &skl_power_well_ops, 1982 .data = SKL_DISP_PW_DDI_A_E, 1983 }, 1984 { 1985 .name = "DDI B power well", 1986 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, 1987 .ops = &skl_power_well_ops, 1988 .data = SKL_DISP_PW_DDI_B, 1989 }, 1990 { 1991 .name = "DDI C power well", 1992 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, 1993 .ops = &skl_power_well_ops, 1994 .data = SKL_DISP_PW_DDI_C, 1995 }, 1996 { 1997 .name = "DDI D power well", 1998 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, 1999 .ops = &skl_power_well_ops, 2000 .data = SKL_DISP_PW_DDI_D, 2001 }, 2002 }; 2003 2004 static struct i915_power_well bxt_power_wells[] = { 2005 { 2006 .name = "always-on", 2007 .always_on = 1, 2008 .domains = POWER_DOMAIN_MASK, 2009 .ops = &i9xx_always_on_power_well_ops, 2010 }, 2011 { 2012 .name = "power well 1", 2013 .domains = 0, 2014 .ops = &skl_power_well_ops, 2015 .data = SKL_DISP_PW_1, 2016 }, 2017 { 2018 .name = "DC off", 2019 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 2020 .ops = &gen9_dc_off_power_well_ops, 2021 .data = SKL_DISP_PW_DC_OFF, 2022 }, 2023 { 2024 .name = "power well 2", 2025 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2026 .ops = &skl_power_well_ops, 2027 .data = SKL_DISP_PW_2, 2028 }, 2029 }; 2030 2031 static int 2032 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 2033 int disable_power_well) 2034 { 2035 if (disable_power_well >= 0) 2036 return !!disable_power_well; 2037 2038 return 1; 2039 } 2040 2041 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, 2042 int enable_dc) 2043 { 2044 uint32_t mask; 2045 int requested_dc; 2046 int max_dc; 2047 2048 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 2049 max_dc = 2; 2050 mask = 0; 2051 } else if (IS_BROXTON(dev_priv)) { 2052 max_dc = 1; 2053 /* 2054 * DC9 has a separate HW flow from the rest of the DC states, 2055 * not depending on the DMC firmware. It's needed by system 2056 * suspend/resume, so allow it unconditionally. 2057 */ 2058 mask = DC_STATE_EN_DC9; 2059 } else { 2060 max_dc = 0; 2061 mask = 0; 2062 } 2063 2064 if (!i915.disable_power_well) 2065 max_dc = 0; 2066 2067 if (enable_dc >= 0 && enable_dc <= max_dc) { 2068 requested_dc = enable_dc; 2069 } else if (enable_dc == -1) { 2070 requested_dc = max_dc; 2071 } else if (enable_dc > max_dc && enable_dc <= 2) { 2072 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", 2073 enable_dc, max_dc); 2074 requested_dc = max_dc; 2075 } else { 2076 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); 2077 requested_dc = max_dc; 2078 } 2079 2080 if (requested_dc > 1) 2081 mask |= DC_STATE_EN_UPTO_DC6; 2082 if (requested_dc > 0) 2083 mask |= DC_STATE_EN_UPTO_DC5; 2084 2085 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); 2086 2087 return mask; 2088 } 2089 2090 #define set_power_wells(power_domains, __power_wells) ({ \ 2091 (power_domains)->power_wells = (__power_wells); \ 2092 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 2093 }) 2094 2095 /** 2096 * intel_power_domains_init - initializes the power domain structures 2097 * @dev_priv: i915 device instance 2098 * 2099 * Initializes the power domain structures for @dev_priv depending upon the 2100 * supported platform. 2101 */ 2102 int intel_power_domains_init(struct drm_i915_private *dev_priv) 2103 { 2104 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2105 2106 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, 2107 i915.disable_power_well); 2108 dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv, 2109 i915.enable_dc); 2110 2111 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); 2112 2113 lockinit(&power_domains->lock, "i915pl", 0, LK_CANRECURSE); 2114 2115 /* 2116 * The enabling order will be from lower to higher indexed wells, 2117 * the disabling order is reversed. 2118 */ 2119 if (IS_HASWELL(dev_priv)) { 2120 set_power_wells(power_domains, hsw_power_wells); 2121 } else if (IS_BROADWELL(dev_priv)) { 2122 set_power_wells(power_domains, bdw_power_wells); 2123 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { 2124 set_power_wells(power_domains, skl_power_wells); 2125 } else if (IS_BROXTON(dev_priv)) { 2126 set_power_wells(power_domains, bxt_power_wells); 2127 } else if (IS_CHERRYVIEW(dev_priv)) { 2128 set_power_wells(power_domains, chv_power_wells); 2129 } else if (IS_VALLEYVIEW(dev_priv)) { 2130 set_power_wells(power_domains, vlv_power_wells); 2131 } else { 2132 set_power_wells(power_domains, i9xx_always_on_power_well); 2133 } 2134 2135 return 0; 2136 } 2137 2138 /** 2139 * intel_power_domains_fini - finalizes the power domain structures 2140 * @dev_priv: i915 device instance 2141 * 2142 * Finalizes the power domain structures for @dev_priv depending upon the 2143 * supported platform. This function also disables runtime pm and ensures that 2144 * the device stays powered up so that the driver can be reloaded. 2145 */ 2146 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 2147 { 2148 #if 0 2149 struct device *device = &dev_priv->dev->pdev->dev; 2150 #endif 2151 2152 /* 2153 * The i915.ko module is still not prepared to be loaded when 2154 * the power well is not enabled, so just enable it in case 2155 * we're going to unload/reload. 2156 * The following also reacquires the RPM reference the core passed 2157 * to the driver during loading, which is dropped in 2158 * intel_runtime_pm_enable(). We have to hand back the control of the 2159 * device to the core with this reference held. 2160 */ 2161 intel_display_set_init_power(dev_priv, true); 2162 2163 /* Remove the refcount we took to keep power well support disabled. */ 2164 if (!i915.disable_power_well) 2165 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2166 2167 /* 2168 * Remove the refcount we took in intel_runtime_pm_enable() in case 2169 * the platform doesn't support runtime PM. 2170 */ 2171 #if 0 2172 if (!HAS_RUNTIME_PM(dev_priv)) 2173 pm_runtime_put(device); 2174 #endif 2175 } 2176 2177 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 2178 { 2179 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2180 struct i915_power_well *power_well; 2181 int i; 2182 2183 mutex_lock(&power_domains->lock); 2184 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 2185 power_well->ops->sync_hw(dev_priv, power_well); 2186 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 2187 power_well); 2188 } 2189 mutex_unlock(&power_domains->lock); 2190 } 2191 2192 static void skl_display_core_init(struct drm_i915_private *dev_priv, 2193 bool resume) 2194 { 2195 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2196 struct i915_power_well *well; 2197 uint32_t val; 2198 2199 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2200 2201 /* enable PCH reset handshake */ 2202 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2203 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 2204 2205 /* enable PG1 and Misc I/O */ 2206 mutex_lock(&power_domains->lock); 2207 2208 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2209 intel_power_well_enable(dev_priv, well); 2210 2211 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 2212 intel_power_well_enable(dev_priv, well); 2213 2214 mutex_unlock(&power_domains->lock); 2215 2216 if (!resume) 2217 return; 2218 2219 skl_init_cdclk(dev_priv); 2220 2221 if (dev_priv->csr.dmc_payload) 2222 intel_csr_load_program(dev_priv); 2223 } 2224 2225 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 2226 { 2227 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2228 struct i915_power_well *well; 2229 2230 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2231 2232 skl_uninit_cdclk(dev_priv); 2233 2234 /* The spec doesn't call for removing the reset handshake flag */ 2235 /* disable PG1 and Misc I/O */ 2236 2237 mutex_lock(&power_domains->lock); 2238 2239 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 2240 intel_power_well_disable(dev_priv, well); 2241 2242 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2243 intel_power_well_disable(dev_priv, well); 2244 2245 mutex_unlock(&power_domains->lock); 2246 } 2247 2248 void bxt_display_core_init(struct drm_i915_private *dev_priv, 2249 bool resume) 2250 { 2251 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2252 struct i915_power_well *well; 2253 uint32_t val; 2254 2255 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2256 2257 /* 2258 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT 2259 * or else the reset will hang because there is no PCH to respond. 2260 * Move the handshake programming to initialization sequence. 2261 * Previously was left up to BIOS. 2262 */ 2263 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2264 val &= ~RESET_PCH_HANDSHAKE_ENABLE; 2265 I915_WRITE(HSW_NDE_RSTWRN_OPT, val); 2266 2267 /* Enable PG1 */ 2268 mutex_lock(&power_domains->lock); 2269 2270 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2271 intel_power_well_enable(dev_priv, well); 2272 2273 mutex_unlock(&power_domains->lock); 2274 2275 broxton_init_cdclk(dev_priv); 2276 broxton_ddi_phy_init(dev_priv); 2277 2278 broxton_cdclk_verify_state(dev_priv); 2279 broxton_ddi_phy_verify_state(dev_priv); 2280 2281 if (resume && dev_priv->csr.dmc_payload) 2282 intel_csr_load_program(dev_priv); 2283 } 2284 2285 void bxt_display_core_uninit(struct drm_i915_private *dev_priv) 2286 { 2287 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2288 struct i915_power_well *well; 2289 2290 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2291 2292 broxton_ddi_phy_uninit(dev_priv); 2293 broxton_uninit_cdclk(dev_priv); 2294 2295 /* The spec doesn't call for removing the reset handshake flag */ 2296 2297 /* Disable PG1 */ 2298 mutex_lock(&power_domains->lock); 2299 2300 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 2301 intel_power_well_disable(dev_priv, well); 2302 2303 mutex_unlock(&power_domains->lock); 2304 } 2305 2306 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 2307 { 2308 struct i915_power_well *cmn_bc = 2309 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2310 struct i915_power_well *cmn_d = 2311 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 2312 2313 /* 2314 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 2315 * workaround never ever read DISPLAY_PHY_CONTROL, and 2316 * instead maintain a shadow copy ourselves. Use the actual 2317 * power well state and lane status to reconstruct the 2318 * expected initial value. 2319 */ 2320 dev_priv->chv_phy_control = 2321 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 2322 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 2323 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 2324 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 2325 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 2326 2327 /* 2328 * If all lanes are disabled we leave the override disabled 2329 * with all power down bits cleared to match the state we 2330 * would use after disabling the port. Otherwise enable the 2331 * override and set the lane powerdown bits accding to the 2332 * current lane status. 2333 */ 2334 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 2335 uint32_t status = I915_READ(DPLL(PIPE_A)); 2336 unsigned int mask; 2337 2338 mask = status & DPLL_PORTB_READY_MASK; 2339 if (mask == 0xf) 2340 mask = 0x0; 2341 else 2342 dev_priv->chv_phy_control |= 2343 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 2344 2345 dev_priv->chv_phy_control |= 2346 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 2347 2348 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 2349 if (mask == 0xf) 2350 mask = 0x0; 2351 else 2352 dev_priv->chv_phy_control |= 2353 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 2354 2355 dev_priv->chv_phy_control |= 2356 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 2357 2358 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 2359 2360 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 2361 } else { 2362 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 2363 } 2364 2365 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 2366 uint32_t status = I915_READ(DPIO_PHY_STATUS); 2367 unsigned int mask; 2368 2369 mask = status & DPLL_PORTD_READY_MASK; 2370 2371 if (mask == 0xf) 2372 mask = 0x0; 2373 else 2374 dev_priv->chv_phy_control |= 2375 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 2376 2377 dev_priv->chv_phy_control |= 2378 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 2379 2380 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 2381 2382 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 2383 } else { 2384 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 2385 } 2386 2387 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 2388 2389 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 2390 dev_priv->chv_phy_control); 2391 } 2392 2393 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 2394 { 2395 struct i915_power_well *cmn = 2396 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2397 struct i915_power_well *disp2d = 2398 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 2399 2400 /* If the display might be already active skip this */ 2401 if (cmn->ops->is_enabled(dev_priv, cmn) && 2402 disp2d->ops->is_enabled(dev_priv, disp2d) && 2403 I915_READ(DPIO_CTL) & DPIO_CMNRST) 2404 return; 2405 2406 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 2407 2408 /* cmnlane needs DPLL registers */ 2409 disp2d->ops->enable(dev_priv, disp2d); 2410 2411 /* 2412 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 2413 * Need to assert and de-assert PHY SB reset by gating the 2414 * common lane power, then un-gating it. 2415 * Simply ungating isn't enough to reset the PHY enough to get 2416 * ports and lanes running. 2417 */ 2418 cmn->ops->disable(dev_priv, cmn); 2419 } 2420 2421 /** 2422 * intel_power_domains_init_hw - initialize hardware power domain state 2423 * @dev_priv: i915 device instance 2424 * 2425 * This function initializes the hardware power domain state and enables all 2426 * power domains using intel_display_set_init_power(). 2427 */ 2428 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 2429 { 2430 struct drm_device *dev = dev_priv->dev; 2431 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2432 2433 power_domains->initializing = true; 2434 2435 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 2436 skl_display_core_init(dev_priv, resume); 2437 } else if (IS_BROXTON(dev)) { 2438 bxt_display_core_init(dev_priv, resume); 2439 } else if (IS_CHERRYVIEW(dev)) { 2440 mutex_lock(&power_domains->lock); 2441 chv_phy_control_init(dev_priv); 2442 mutex_unlock(&power_domains->lock); 2443 } else if (IS_VALLEYVIEW(dev)) { 2444 mutex_lock(&power_domains->lock); 2445 vlv_cmnlane_wa(dev_priv); 2446 mutex_unlock(&power_domains->lock); 2447 } 2448 2449 /* For now, we need the power well to be always enabled. */ 2450 intel_display_set_init_power(dev_priv, true); 2451 /* Disable power support if the user asked so. */ 2452 if (!i915.disable_power_well) 2453 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 2454 intel_power_domains_sync_hw(dev_priv); 2455 power_domains->initializing = false; 2456 } 2457 2458 /** 2459 * intel_power_domains_suspend - suspend power domain state 2460 * @dev_priv: i915 device instance 2461 * 2462 * This function prepares the hardware power domain state before entering 2463 * system suspend. It must be paired with intel_power_domains_init_hw(). 2464 */ 2465 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 2466 { 2467 /* 2468 * Even if power well support was disabled we still want to disable 2469 * power wells while we are system suspended. 2470 */ 2471 if (!i915.disable_power_well) 2472 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2473 2474 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 2475 skl_display_core_uninit(dev_priv); 2476 else if (IS_BROXTON(dev_priv)) 2477 bxt_display_core_uninit(dev_priv); 2478 } 2479 2480 /** 2481 * intel_runtime_pm_get - grab a runtime pm reference 2482 * @dev_priv: i915 device instance 2483 * 2484 * This function grabs a device-level runtime pm reference (mostly used for GEM 2485 * code to ensure the GTT or GT is on) and ensures that it is powered up. 2486 * 2487 * Any runtime pm reference obtained by this function must have a symmetric 2488 * call to intel_runtime_pm_put() to release the reference again. 2489 */ 2490 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 2491 { 2492 #if 0 2493 struct drm_device *dev = dev_priv->dev; 2494 struct device *device = &dev->pdev->dev; 2495 2496 pm_runtime_get_sync(device); 2497 #endif 2498 2499 atomic_inc(&dev_priv->pm.wakeref_count); 2500 assert_rpm_wakelock_held(dev_priv); 2501 } 2502 2503 /** 2504 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 2505 * @dev_priv: i915 device instance 2506 * 2507 * This function grabs a device-level runtime pm reference if the device is 2508 * already in use and ensures that it is powered up. 2509 * 2510 * Any runtime pm reference obtained by this function must have a symmetric 2511 * call to intel_runtime_pm_put() to release the reference again. 2512 */ 2513 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) 2514 { 2515 #ifndef __DragonFly__ 2516 struct drm_device *dev = dev_priv->dev; 2517 struct device *device = &dev->pdev->dev; 2518 2519 if (IS_ENABLED(CONFIG_PM)) { 2520 int ret = pm_runtime_get_if_in_use(device); 2521 2522 /* 2523 * In cases runtime PM is disabled by the RPM core and we get 2524 * an -EINVAL return value we are not supposed to call this 2525 * function, since the power state is undefined. This applies 2526 * atm to the late/early system suspend/resume handlers. 2527 */ 2528 WARN_ON_ONCE(ret < 0); 2529 if (ret <= 0) 2530 return false; 2531 } 2532 2533 atomic_inc(&dev_priv->pm.wakeref_count); 2534 assert_rpm_wakelock_held(dev_priv); 2535 #endif 2536 2537 return true; 2538 } 2539 2540 /** 2541 * intel_runtime_pm_get_noresume - grab a runtime pm reference 2542 * @dev_priv: i915 device instance 2543 * 2544 * This function grabs a device-level runtime pm reference (mostly used for GEM 2545 * code to ensure the GTT or GT is on). 2546 * 2547 * It will _not_ power up the device but instead only check that it's powered 2548 * on. Therefore it is only valid to call this functions from contexts where 2549 * the device is known to be powered up and where trying to power it up would 2550 * result in hilarity and deadlocks. That pretty much means only the system 2551 * suspend/resume code where this is used to grab runtime pm references for 2552 * delayed setup down in work items. 2553 * 2554 * Any runtime pm reference obtained by this function must have a symmetric 2555 * call to intel_runtime_pm_put() to release the reference again. 2556 */ 2557 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 2558 { 2559 #if 0 2560 struct drm_device *dev = dev_priv->dev; 2561 struct device *device = &dev->pdev->dev; 2562 #endif 2563 2564 assert_rpm_wakelock_held(dev_priv); 2565 #if 0 2566 pm_runtime_get_noresume(device); 2567 #endif 2568 2569 atomic_inc(&dev_priv->pm.wakeref_count); 2570 } 2571 2572 /** 2573 * intel_runtime_pm_put - release a runtime pm reference 2574 * @dev_priv: i915 device instance 2575 * 2576 * This function drops the device-level runtime pm reference obtained by 2577 * intel_runtime_pm_get() and might power down the corresponding 2578 * hardware block right away if this is the last reference. 2579 */ 2580 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 2581 { 2582 #if 0 2583 struct drm_device *dev = dev_priv->dev; 2584 struct device *device = &dev->pdev->dev; 2585 2586 assert_rpm_wakelock_held(dev_priv); 2587 if (atomic_dec_and_test(&dev_priv->pm.wakeref_count)) 2588 atomic_inc(&dev_priv->pm.atomic_seq); 2589 2590 pm_runtime_mark_last_busy(device); 2591 pm_runtime_put_autosuspend(device); 2592 #endif 2593 } 2594 2595 /** 2596 * intel_runtime_pm_enable - enable runtime pm 2597 * @dev_priv: i915 device instance 2598 * 2599 * This function enables runtime pm at the end of the driver load sequence. 2600 * 2601 * Note that this function does currently not enable runtime pm for the 2602 * subordinate display power domains. That is only done on the first modeset 2603 * using intel_display_set_init_power(). 2604 */ 2605 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 2606 { 2607 #if 0 2608 struct drm_device *dev = dev_priv->dev; 2609 struct device *device = &dev->pdev->dev; 2610 2611 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 2612 pm_runtime_mark_last_busy(device); 2613 2614 /* 2615 * Take a permanent reference to disable the RPM functionality and drop 2616 * it only when unloading the driver. Use the low level get/put helpers, 2617 * so the driver's own RPM reference tracking asserts also work on 2618 * platforms without RPM support. 2619 */ 2620 if (!HAS_RUNTIME_PM(dev)) { 2621 pm_runtime_dont_use_autosuspend(device); 2622 pm_runtime_get_sync(device); 2623 } else { 2624 pm_runtime_use_autosuspend(device); 2625 } 2626 2627 /* 2628 * The core calls the driver load handler with an RPM reference held. 2629 * We drop that here and will reacquire it during unloading in 2630 * intel_power_domains_fini(). 2631 */ 2632 pm_runtime_put_autosuspend(device); 2633 #endif 2634 } 2635 2636