1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 #include <linux/i2c.h> 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_atomic_helper.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 #include "intel_sdvo_regs.h" 39 40 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 41 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 42 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 43 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 44 45 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 46 SDVO_TV_MASK) 47 48 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 49 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 50 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 51 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 52 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 53 54 55 static const char * const tv_format_names[] = { 56 "NTSC_M" , "NTSC_J" , "NTSC_443", 57 "PAL_B" , "PAL_D" , "PAL_G" , 58 "PAL_H" , "PAL_I" , "PAL_M" , 59 "PAL_N" , "PAL_NC" , "PAL_60" , 60 "SECAM_B" , "SECAM_D" , "SECAM_G" , 61 "SECAM_K" , "SECAM_K1", "SECAM_L" , 62 "SECAM_60" 63 }; 64 65 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 66 67 struct intel_sdvo { 68 struct intel_encoder base; 69 70 struct i2c_adapter *i2c; 71 u8 slave_addr; 72 73 struct i2c_adapter ddc; 74 75 /* Register for the SDVO device: SDVOB or SDVOC */ 76 i915_reg_t sdvo_reg; 77 78 /* Active outputs controlled by this SDVO output */ 79 uint16_t controlled_output; 80 81 /* 82 * Capabilities of the SDVO device returned by 83 * intel_sdvo_get_capabilities() 84 */ 85 struct intel_sdvo_caps caps; 86 87 /* Pixel clock limitations reported by the SDVO device, in kHz */ 88 int pixel_clock_min, pixel_clock_max; 89 90 /* 91 * For multiple function SDVO device, 92 * this is for current attached outputs. 93 */ 94 uint16_t attached_output; 95 96 /* 97 * Hotplug activation bits for this device 98 */ 99 uint16_t hotplug_active; 100 101 /** 102 * This is used to select the color range of RBG outputs in HDMI mode. 103 * It is only valid when using TMDS encoding and 8 bit per color mode. 104 */ 105 uint32_t color_range; 106 bool color_range_auto; 107 108 /** 109 * HDMI user specified aspect ratio 110 */ 111 enum hdmi_picture_aspect aspect_ratio; 112 113 /** 114 * This is set if we're going to treat the device as TV-out. 115 * 116 * While we have these nice friendly flags for output types that ought 117 * to decide this for us, the S-Video output on our HDMI+S-Video card 118 * shows up as RGB1 (VGA). 119 */ 120 bool is_tv; 121 122 enum port port; 123 124 /* This is for current tv format name */ 125 int tv_format_index; 126 127 /** 128 * This is set if we treat the device as HDMI, instead of DVI. 129 */ 130 bool is_hdmi; 131 bool has_hdmi_monitor; 132 bool has_hdmi_audio; 133 bool rgb_quant_range_selectable; 134 135 /** 136 * This is set if we detect output of sdvo device as LVDS and 137 * have a valid fixed mode to use with the panel. 138 */ 139 bool is_lvds; 140 141 /** 142 * This is sdvo fixed pannel mode pointer 143 */ 144 struct drm_display_mode *sdvo_lvds_fixed_mode; 145 146 /* DDC bus used by this SDVO encoder */ 147 uint8_t ddc_bus; 148 149 /* 150 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 151 */ 152 uint8_t dtd_sdvo_flags; 153 }; 154 155 struct intel_sdvo_connector { 156 struct intel_connector base; 157 158 /* Mark the type of connector */ 159 uint16_t output_flag; 160 161 enum hdmi_force_audio force_audio; 162 163 /* This contains all current supported TV format */ 164 u8 tv_format_supported[TV_FORMAT_NUM]; 165 int format_supported_num; 166 struct drm_property *tv_format; 167 168 /* add the property for the SDVO-TV */ 169 struct drm_property *left; 170 struct drm_property *right; 171 struct drm_property *top; 172 struct drm_property *bottom; 173 struct drm_property *hpos; 174 struct drm_property *vpos; 175 struct drm_property *contrast; 176 struct drm_property *saturation; 177 struct drm_property *hue; 178 struct drm_property *sharpness; 179 struct drm_property *flicker_filter; 180 struct drm_property *flicker_filter_adaptive; 181 struct drm_property *flicker_filter_2d; 182 struct drm_property *tv_chroma_filter; 183 struct drm_property *tv_luma_filter; 184 struct drm_property *dot_crawl; 185 186 /* add the property for the SDVO-TV/LVDS */ 187 struct drm_property *brightness; 188 189 /* Add variable to record current setting for the above property */ 190 u32 left_margin, right_margin, top_margin, bottom_margin; 191 192 /* this is to get the range of margin.*/ 193 u32 max_hscan, max_vscan; 194 u32 max_hpos, cur_hpos; 195 u32 max_vpos, cur_vpos; 196 u32 cur_brightness, max_brightness; 197 u32 cur_contrast, max_contrast; 198 u32 cur_saturation, max_saturation; 199 u32 cur_hue, max_hue; 200 u32 cur_sharpness, max_sharpness; 201 u32 cur_flicker_filter, max_flicker_filter; 202 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 203 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 204 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 205 u32 cur_tv_luma_filter, max_tv_luma_filter; 206 u32 cur_dot_crawl, max_dot_crawl; 207 }; 208 209 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 210 { 211 return container_of(encoder, struct intel_sdvo, base); 212 } 213 214 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 215 { 216 return to_sdvo(intel_attached_encoder(connector)); 217 } 218 219 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 220 { 221 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 222 } 223 224 static bool 225 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 226 static bool 227 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 228 struct intel_sdvo_connector *intel_sdvo_connector, 229 int type); 230 static bool 231 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 232 struct intel_sdvo_connector *intel_sdvo_connector); 233 234 /** 235 * Writes the SDVOB or SDVOC with the given value, but always writes both 236 * SDVOB and SDVOC to work around apparent hardware issues (according to 237 * comments in the BIOS). 238 */ 239 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 240 { 241 struct drm_device *dev = intel_sdvo->base.base.dev; 242 struct drm_i915_private *dev_priv = dev->dev_private; 243 u32 bval = val, cval = val; 244 int i; 245 246 if (HAS_PCH_SPLIT(dev_priv)) { 247 I915_WRITE(intel_sdvo->sdvo_reg, val); 248 POSTING_READ(intel_sdvo->sdvo_reg); 249 /* 250 * HW workaround, need to write this twice for issue 251 * that may result in first write getting masked. 252 */ 253 if (HAS_PCH_IBX(dev)) { 254 I915_WRITE(intel_sdvo->sdvo_reg, val); 255 POSTING_READ(intel_sdvo->sdvo_reg); 256 } 257 return; 258 } 259 260 if (intel_sdvo->port == PORT_B) 261 cval = I915_READ(GEN3_SDVOC); 262 else 263 bval = I915_READ(GEN3_SDVOB); 264 265 /* 266 * Write the registers twice for luck. Sometimes, 267 * writing them only once doesn't appear to 'stick'. 268 * The BIOS does this too. Yay, magic 269 */ 270 for (i = 0; i < 2; i++) 271 { 272 I915_WRITE(GEN3_SDVOB, bval); 273 POSTING_READ(GEN3_SDVOB); 274 I915_WRITE(GEN3_SDVOC, cval); 275 POSTING_READ(GEN3_SDVOC); 276 } 277 } 278 279 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 280 { 281 struct i2c_msg msgs[] = { 282 { 283 .addr = intel_sdvo->slave_addr, 284 .flags = 0, 285 .len = 1, 286 .buf = &addr, 287 }, 288 { 289 .addr = intel_sdvo->slave_addr, 290 .flags = I2C_M_RD, 291 .len = 1, 292 .buf = ch, 293 } 294 }; 295 int ret; 296 297 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 298 return true; 299 300 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 301 return false; 302 } 303 304 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 305 /** Mapping of command numbers to names, for debug output */ 306 static const struct _sdvo_cmd_name { 307 u8 cmd; 308 const char *name; 309 } sdvo_cmd_names[] = { 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 353 354 /* Add the op code for SDVO enhancements */ 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 399 400 /* HDMI op code */ 401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 412 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 413 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 414 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 415 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 416 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 417 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 418 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 419 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 420 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 421 }; 422 423 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") 424 425 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 426 const void *args, int args_len) 427 { 428 int i, pos = 0; 429 #define BUF_LEN 256 430 char buffer[BUF_LEN]; 431 432 #define BUF_PRINT(args...) \ 433 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 434 435 436 for (i = 0; i < args_len; i++) { 437 BUF_PRINT("%02X ", ((const u8 *)args)[i]); 438 } 439 for (; i < 8; i++) { 440 BUF_PRINT(" "); 441 } 442 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 443 if (cmd == sdvo_cmd_names[i].cmd) { 444 BUF_PRINT("(%s)", sdvo_cmd_names[i].name); 445 break; 446 } 447 } 448 if (i == ARRAY_SIZE(sdvo_cmd_names)) { 449 BUF_PRINT("(%02X)", cmd); 450 } 451 BUG_ON(pos >= BUF_LEN - 1); 452 #undef BUF_PRINT 453 #undef BUF_LEN 454 455 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 456 } 457 458 static const char * const cmd_status_names[] = { 459 "Power on", 460 "Success", 461 "Not supported", 462 "Invalid arg", 463 "Pending", 464 "Target not specified", 465 "Scaling not supported" 466 }; 467 468 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 469 const void *args, int args_len) 470 { 471 u8 *buf, status; 472 struct i2c_msg *msgs; 473 int i, ret = true; 474 475 /* Would be simpler to allocate both in one go ? */ 476 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 477 if (!buf) 478 return false; 479 480 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 481 if (!msgs) { 482 kfree(buf); 483 return false; 484 } 485 486 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 487 488 for (i = 0; i < args_len; i++) { 489 msgs[i].addr = intel_sdvo->slave_addr; 490 msgs[i].flags = 0; 491 msgs[i].len = 2; 492 msgs[i].buf = buf + 2 *i; 493 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 494 buf[2*i + 1] = ((const u8*)args)[i]; 495 } 496 msgs[i].addr = intel_sdvo->slave_addr; 497 msgs[i].flags = 0; 498 msgs[i].len = 2; 499 msgs[i].buf = buf + 2*i; 500 buf[2*i + 0] = SDVO_I2C_OPCODE; 501 buf[2*i + 1] = cmd; 502 503 /* the following two are to read the response */ 504 status = SDVO_I2C_CMD_STATUS; 505 msgs[i+1].addr = intel_sdvo->slave_addr; 506 msgs[i+1].flags = 0; 507 msgs[i+1].len = 1; 508 msgs[i+1].buf = &status; 509 510 msgs[i+2].addr = intel_sdvo->slave_addr; 511 msgs[i+2].flags = I2C_M_RD; 512 msgs[i+2].len = 1; 513 msgs[i+2].buf = &status; 514 515 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 516 if (ret < 0) { 517 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 518 ret = false; 519 goto out; 520 } 521 if (ret != i+3) { 522 /* failure in I2C transfer */ 523 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 524 ret = false; 525 } 526 527 out: 528 kfree(msgs); 529 kfree(buf); 530 return ret; 531 } 532 533 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 534 void *response, int response_len) 535 { 536 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 537 u8 status; 538 int i, pos = 0; 539 #define BUF_LEN 256 540 char buffer[BUF_LEN]; 541 542 543 /* 544 * The documentation states that all commands will be 545 * processed within 15µs, and that we need only poll 546 * the status byte a maximum of 3 times in order for the 547 * command to be complete. 548 * 549 * Check 5 times in case the hardware failed to read the docs. 550 * 551 * Also beware that the first response by many devices is to 552 * reply PENDING and stall for time. TVs are notorious for 553 * requiring longer than specified to complete their replies. 554 * Originally (in the DDX long ago), the delay was only ever 15ms 555 * with an additional delay of 30ms applied for TVs added later after 556 * many experiments. To accommodate both sets of delays, we do a 557 * sequence of slow checks if the device is falling behind and fails 558 * to reply within 5*15µs. 559 */ 560 if (!intel_sdvo_read_byte(intel_sdvo, 561 SDVO_I2C_CMD_STATUS, 562 &status)) 563 goto log_fail; 564 565 while ((status == SDVO_CMD_STATUS_PENDING || 566 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 567 if (retry < 10) 568 msleep(15); 569 else 570 udelay(15); 571 572 if (!intel_sdvo_read_byte(intel_sdvo, 573 SDVO_I2C_CMD_STATUS, 574 &status)) 575 goto log_fail; 576 } 577 578 #define BUF_PRINT(args...) \ 579 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 580 581 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 582 BUF_PRINT("(%s)", cmd_status_names[status]); 583 else 584 BUF_PRINT("(??? %d)", status); 585 586 if (status != SDVO_CMD_STATUS_SUCCESS) 587 goto log_fail; 588 589 /* Read the command response */ 590 for (i = 0; i < response_len; i++) { 591 if (!intel_sdvo_read_byte(intel_sdvo, 592 SDVO_I2C_RETURN_0 + i, 593 &((u8 *)response)[i])) 594 goto log_fail; 595 BUF_PRINT(" %02X", ((u8 *)response)[i]); 596 } 597 BUG_ON(pos >= BUF_LEN - 1); 598 #undef BUF_PRINT 599 #undef BUF_LEN 600 601 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 602 return true; 603 604 log_fail: 605 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); 606 return false; 607 } 608 609 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 610 { 611 if (adjusted_mode->crtc_clock >= 100000) 612 return 1; 613 else if (adjusted_mode->crtc_clock >= 50000) 614 return 2; 615 else 616 return 4; 617 } 618 619 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 620 u8 ddc_bus) 621 { 622 /* This must be the immediately preceding write before the i2c xfer */ 623 return intel_sdvo_write_cmd(intel_sdvo, 624 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 625 &ddc_bus, 1); 626 } 627 628 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 629 { 630 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 631 return false; 632 633 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 634 } 635 636 static bool 637 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 638 { 639 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 640 return false; 641 642 return intel_sdvo_read_response(intel_sdvo, value, len); 643 } 644 645 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 646 { 647 struct intel_sdvo_set_target_input_args targets = {0}; 648 return intel_sdvo_set_value(intel_sdvo, 649 SDVO_CMD_SET_TARGET_INPUT, 650 &targets, sizeof(targets)); 651 } 652 653 /** 654 * Return whether each input is trained. 655 * 656 * This function is making an assumption about the layout of the response, 657 * which should be checked against the docs. 658 */ 659 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 660 { 661 struct intel_sdvo_get_trained_inputs_response response; 662 663 BUILD_BUG_ON(sizeof(response) != 1); 664 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 665 &response, sizeof(response))) 666 return false; 667 668 *input_1 = response.input0_trained; 669 *input_2 = response.input1_trained; 670 return true; 671 } 672 673 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 674 u16 outputs) 675 { 676 return intel_sdvo_set_value(intel_sdvo, 677 SDVO_CMD_SET_ACTIVE_OUTPUTS, 678 &outputs, sizeof(outputs)); 679 } 680 681 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 682 u16 *outputs) 683 { 684 return intel_sdvo_get_value(intel_sdvo, 685 SDVO_CMD_GET_ACTIVE_OUTPUTS, 686 outputs, sizeof(*outputs)); 687 } 688 689 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 690 int mode) 691 { 692 u8 state = SDVO_ENCODER_STATE_ON; 693 694 switch (mode) { 695 case DRM_MODE_DPMS_ON: 696 state = SDVO_ENCODER_STATE_ON; 697 break; 698 case DRM_MODE_DPMS_STANDBY: 699 state = SDVO_ENCODER_STATE_STANDBY; 700 break; 701 case DRM_MODE_DPMS_SUSPEND: 702 state = SDVO_ENCODER_STATE_SUSPEND; 703 break; 704 case DRM_MODE_DPMS_OFF: 705 state = SDVO_ENCODER_STATE_OFF; 706 break; 707 } 708 709 return intel_sdvo_set_value(intel_sdvo, 710 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 711 } 712 713 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 714 int *clock_min, 715 int *clock_max) 716 { 717 struct intel_sdvo_pixel_clock_range clocks; 718 719 BUILD_BUG_ON(sizeof(clocks) != 4); 720 if (!intel_sdvo_get_value(intel_sdvo, 721 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 722 &clocks, sizeof(clocks))) 723 return false; 724 725 /* Convert the values from units of 10 kHz to kHz. */ 726 *clock_min = clocks.min * 10; 727 *clock_max = clocks.max * 10; 728 return true; 729 } 730 731 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 732 u16 outputs) 733 { 734 return intel_sdvo_set_value(intel_sdvo, 735 SDVO_CMD_SET_TARGET_OUTPUT, 736 &outputs, sizeof(outputs)); 737 } 738 739 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 740 struct intel_sdvo_dtd *dtd) 741 { 742 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 743 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 744 } 745 746 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 747 struct intel_sdvo_dtd *dtd) 748 { 749 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 750 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 751 } 752 753 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 754 struct intel_sdvo_dtd *dtd) 755 { 756 return intel_sdvo_set_timing(intel_sdvo, 757 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 758 } 759 760 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 761 struct intel_sdvo_dtd *dtd) 762 { 763 return intel_sdvo_set_timing(intel_sdvo, 764 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 765 } 766 767 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 768 struct intel_sdvo_dtd *dtd) 769 { 770 return intel_sdvo_get_timing(intel_sdvo, 771 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 772 } 773 774 static bool 775 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 776 uint16_t clock, 777 uint16_t width, 778 uint16_t height) 779 { 780 struct intel_sdvo_preferred_input_timing_args args; 781 782 memset(&args, 0, sizeof(args)); 783 args.clock = clock; 784 args.width = width; 785 args.height = height; 786 args.interlace = 0; 787 788 if (intel_sdvo->is_lvds && 789 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 790 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 791 args.scaled = 1; 792 793 return intel_sdvo_set_value(intel_sdvo, 794 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 795 &args, sizeof(args)); 796 } 797 798 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 799 struct intel_sdvo_dtd *dtd) 800 { 801 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 802 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 803 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 804 &dtd->part1, sizeof(dtd->part1)) && 805 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 806 &dtd->part2, sizeof(dtd->part2)); 807 } 808 809 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 810 { 811 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 812 } 813 814 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 815 const struct drm_display_mode *mode) 816 { 817 uint16_t width, height; 818 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 819 uint16_t h_sync_offset, v_sync_offset; 820 int mode_clock; 821 822 memset(dtd, 0, sizeof(*dtd)); 823 824 width = mode->hdisplay; 825 height = mode->vdisplay; 826 827 /* do some mode translations */ 828 h_blank_len = mode->htotal - mode->hdisplay; 829 h_sync_len = mode->hsync_end - mode->hsync_start; 830 831 v_blank_len = mode->vtotal - mode->vdisplay; 832 v_sync_len = mode->vsync_end - mode->vsync_start; 833 834 h_sync_offset = mode->hsync_start - mode->hdisplay; 835 v_sync_offset = mode->vsync_start - mode->vdisplay; 836 837 mode_clock = mode->clock; 838 mode_clock /= 10; 839 dtd->part1.clock = mode_clock; 840 841 dtd->part1.h_active = width & 0xff; 842 dtd->part1.h_blank = h_blank_len & 0xff; 843 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 844 ((h_blank_len >> 8) & 0xf); 845 dtd->part1.v_active = height & 0xff; 846 dtd->part1.v_blank = v_blank_len & 0xff; 847 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 848 ((v_blank_len >> 8) & 0xf); 849 850 dtd->part2.h_sync_off = h_sync_offset & 0xff; 851 dtd->part2.h_sync_width = h_sync_len & 0xff; 852 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 853 (v_sync_len & 0xf); 854 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 855 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 856 ((v_sync_len & 0x30) >> 4); 857 858 dtd->part2.dtd_flags = 0x18; 859 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 860 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 861 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 862 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 863 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 864 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 865 866 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 867 } 868 869 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 870 const struct intel_sdvo_dtd *dtd) 871 { 872 struct drm_display_mode mode = {}; 873 874 mode.hdisplay = dtd->part1.h_active; 875 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 876 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 877 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 878 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 879 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 880 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 881 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 882 883 mode.vdisplay = dtd->part1.v_active; 884 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 885 mode.vsync_start = mode.vdisplay; 886 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 887 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 888 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 889 mode.vsync_end = mode.vsync_start + 890 (dtd->part2.v_sync_off_width & 0xf); 891 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 892 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 893 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 894 895 mode.clock = dtd->part1.clock * 10; 896 897 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 898 mode.flags |= DRM_MODE_FLAG_INTERLACE; 899 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 900 mode.flags |= DRM_MODE_FLAG_PHSYNC; 901 else 902 mode.flags |= DRM_MODE_FLAG_NHSYNC; 903 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 904 mode.flags |= DRM_MODE_FLAG_PVSYNC; 905 else 906 mode.flags |= DRM_MODE_FLAG_NVSYNC; 907 908 drm_mode_set_crtcinfo(&mode, 0); 909 910 drm_mode_copy(pmode, &mode); 911 } 912 913 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 914 { 915 struct intel_sdvo_encode encode; 916 917 BUILD_BUG_ON(sizeof(encode) != 2); 918 return intel_sdvo_get_value(intel_sdvo, 919 SDVO_CMD_GET_SUPP_ENCODE, 920 &encode, sizeof(encode)); 921 } 922 923 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 924 uint8_t mode) 925 { 926 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 927 } 928 929 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 930 uint8_t mode) 931 { 932 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 933 } 934 935 #if 0 936 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 937 { 938 int i, j; 939 uint8_t set_buf_index[2]; 940 uint8_t av_split; 941 uint8_t buf_size; 942 uint8_t buf[48]; 943 uint8_t *pos; 944 945 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 946 947 for (i = 0; i <= av_split; i++) { 948 set_buf_index[0] = i; set_buf_index[1] = 0; 949 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 950 set_buf_index, 2); 951 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 952 intel_sdvo_read_response(encoder, &buf_size, 1); 953 954 pos = buf; 955 for (j = 0; j <= buf_size; j += 8) { 956 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 957 NULL, 0); 958 intel_sdvo_read_response(encoder, pos, 8); 959 pos += 8; 960 } 961 } 962 } 963 #endif 964 965 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 966 unsigned if_index, uint8_t tx_rate, 967 const uint8_t *data, unsigned length) 968 { 969 uint8_t set_buf_index[2] = { if_index, 0 }; 970 uint8_t hbuf_size, tmp[8]; 971 int i; 972 973 if (!intel_sdvo_set_value(intel_sdvo, 974 SDVO_CMD_SET_HBUF_INDEX, 975 set_buf_index, 2)) 976 return false; 977 978 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 979 &hbuf_size, 1)) 980 return false; 981 982 /* Buffer size is 0 based, hooray! */ 983 hbuf_size++; 984 985 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", 986 if_index, length, hbuf_size); 987 988 for (i = 0; i < hbuf_size; i += 8) { 989 memset(tmp, 0, 8); 990 if (i < length) 991 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 992 993 if (!intel_sdvo_set_value(intel_sdvo, 994 SDVO_CMD_SET_HBUF_DATA, 995 tmp, 8)) 996 return false; 997 } 998 999 return intel_sdvo_set_value(intel_sdvo, 1000 SDVO_CMD_SET_HBUF_TXRATE, 1001 &tx_rate, 1); 1002 } 1003 1004 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1005 const struct drm_display_mode *adjusted_mode) 1006 { 1007 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1008 struct drm_crtc *crtc = intel_sdvo->base.base.crtc; 1009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1010 union hdmi_infoframe frame; 1011 int ret; 1012 ssize_t len; 1013 1014 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 1015 adjusted_mode); 1016 if (ret < 0) { 1017 DRM_ERROR("couldn't fill AVI infoframe\n"); 1018 return false; 1019 } 1020 1021 if (intel_sdvo->rgb_quant_range_selectable) { 1022 if (intel_crtc->config->limited_color_range) 1023 frame.avi.quantization_range = 1024 HDMI_QUANTIZATION_RANGE_LIMITED; 1025 else 1026 frame.avi.quantization_range = 1027 HDMI_QUANTIZATION_RANGE_FULL; 1028 } 1029 1030 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); 1031 if (len < 0) 1032 return false; 1033 1034 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1035 SDVO_HBUF_TX_VSYNC, 1036 sdvo_data, sizeof(sdvo_data)); 1037 } 1038 1039 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 1040 { 1041 struct intel_sdvo_tv_format format; 1042 uint32_t format_map; 1043 1044 format_map = 1 << intel_sdvo->tv_format_index; 1045 memset(&format, 0, sizeof(format)); 1046 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1047 1048 BUILD_BUG_ON(sizeof(format) != 6); 1049 return intel_sdvo_set_value(intel_sdvo, 1050 SDVO_CMD_SET_TV_FORMAT, 1051 &format, sizeof(format)); 1052 } 1053 1054 static bool 1055 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1056 const struct drm_display_mode *mode) 1057 { 1058 struct intel_sdvo_dtd output_dtd; 1059 1060 if (!intel_sdvo_set_target_output(intel_sdvo, 1061 intel_sdvo->attached_output)) 1062 return false; 1063 1064 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1065 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1066 return false; 1067 1068 return true; 1069 } 1070 1071 /* Asks the sdvo controller for the preferred input mode given the output mode. 1072 * Unfortunately we have to set up the full output mode to do that. */ 1073 static bool 1074 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1075 const struct drm_display_mode *mode, 1076 struct drm_display_mode *adjusted_mode) 1077 { 1078 struct intel_sdvo_dtd input_dtd; 1079 1080 /* Reset the input timing to the screen. Assume always input 0. */ 1081 if (!intel_sdvo_set_target_input(intel_sdvo)) 1082 return false; 1083 1084 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1085 mode->clock / 10, 1086 mode->hdisplay, 1087 mode->vdisplay)) 1088 return false; 1089 1090 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1091 &input_dtd)) 1092 return false; 1093 1094 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1095 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1096 1097 return true; 1098 } 1099 1100 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1101 { 1102 unsigned dotclock = pipe_config->port_clock; 1103 struct dpll *clock = &pipe_config->dpll; 1104 1105 /* SDVO TV has fixed PLL values depend on its clock range, 1106 this mirrors vbios setting. */ 1107 if (dotclock >= 100000 && dotclock < 140500) { 1108 clock->p1 = 2; 1109 clock->p2 = 10; 1110 clock->n = 3; 1111 clock->m1 = 16; 1112 clock->m2 = 8; 1113 } else if (dotclock >= 140500 && dotclock <= 200000) { 1114 clock->p1 = 1; 1115 clock->p2 = 10; 1116 clock->n = 6; 1117 clock->m1 = 12; 1118 clock->m2 = 8; 1119 } else { 1120 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1121 } 1122 1123 pipe_config->clock_set = true; 1124 } 1125 1126 static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 1127 struct intel_crtc_state *pipe_config) 1128 { 1129 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1130 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1131 struct drm_display_mode *mode = &pipe_config->base.mode; 1132 1133 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1134 pipe_config->pipe_bpp = 8*3; 1135 1136 if (HAS_PCH_SPLIT(encoder->base.dev)) 1137 pipe_config->has_pch_encoder = true; 1138 1139 /* We need to construct preferred input timings based on our 1140 * output timings. To do that, we have to set the output 1141 * timings, even though this isn't really the right place in 1142 * the sequence to do it. Oh well. 1143 */ 1144 if (intel_sdvo->is_tv) { 1145 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1146 return false; 1147 1148 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1149 mode, 1150 adjusted_mode); 1151 pipe_config->sdvo_tv_clock = true; 1152 } else if (intel_sdvo->is_lvds) { 1153 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1154 intel_sdvo->sdvo_lvds_fixed_mode)) 1155 return false; 1156 1157 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1158 mode, 1159 adjusted_mode); 1160 } 1161 1162 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1163 * SDVO device will factor out the multiplier during mode_set. 1164 */ 1165 pipe_config->pixel_multiplier = 1166 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1167 1168 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; 1169 1170 if (intel_sdvo->color_range_auto) { 1171 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1172 /* FIXME: This bit is only valid when using TMDS encoding and 8 1173 * bit per color mode. */ 1174 if (pipe_config->has_hdmi_sink && 1175 drm_match_cea_mode(adjusted_mode) > 1) 1176 pipe_config->limited_color_range = true; 1177 } else { 1178 if (pipe_config->has_hdmi_sink && 1179 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) 1180 pipe_config->limited_color_range = true; 1181 } 1182 1183 /* Clock computation needs to happen after pixel multiplier. */ 1184 if (intel_sdvo->is_tv) 1185 i9xx_adjust_sdvo_tv_clock(pipe_config); 1186 1187 /* Set user selected PAR to incoming mode's member */ 1188 if (intel_sdvo->is_hdmi) 1189 adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio; 1190 1191 return true; 1192 } 1193 1194 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) 1195 { 1196 struct drm_device *dev = intel_encoder->base.dev; 1197 struct drm_i915_private *dev_priv = dev->dev_private; 1198 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); 1199 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 1200 struct drm_display_mode *mode = &crtc->config->base.mode; 1201 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1202 u32 sdvox; 1203 struct intel_sdvo_in_out_map in_out; 1204 struct intel_sdvo_dtd input_dtd, output_dtd; 1205 int rate; 1206 1207 if (!mode) 1208 return; 1209 1210 /* First, set the input mapping for the first input to our controlled 1211 * output. This is only correct if we're a single-input device, in 1212 * which case the first input is the output from the appropriate SDVO 1213 * channel on the motherboard. In a two-input device, the first input 1214 * will be SDVOB and the second SDVOC. 1215 */ 1216 in_out.in0 = intel_sdvo->attached_output; 1217 in_out.in1 = 0; 1218 1219 intel_sdvo_set_value(intel_sdvo, 1220 SDVO_CMD_SET_IN_OUT_MAP, 1221 &in_out, sizeof(in_out)); 1222 1223 /* Set the output timings to the screen */ 1224 if (!intel_sdvo_set_target_output(intel_sdvo, 1225 intel_sdvo->attached_output)) 1226 return; 1227 1228 /* lvds has a special fixed output timing. */ 1229 if (intel_sdvo->is_lvds) 1230 intel_sdvo_get_dtd_from_mode(&output_dtd, 1231 intel_sdvo->sdvo_lvds_fixed_mode); 1232 else 1233 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1234 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1235 DRM_INFO("Setting output timings on %s failed\n", 1236 SDVO_NAME(intel_sdvo)); 1237 1238 /* Set the input timing to the screen. Assume always input 0. */ 1239 if (!intel_sdvo_set_target_input(intel_sdvo)) 1240 return; 1241 1242 if (crtc->config->has_hdmi_sink) { 1243 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1244 intel_sdvo_set_colorimetry(intel_sdvo, 1245 SDVO_COLORIMETRY_RGB256); 1246 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); 1247 } else 1248 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1249 1250 if (intel_sdvo->is_tv && 1251 !intel_sdvo_set_tv_format(intel_sdvo)) 1252 return; 1253 1254 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1255 1256 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) 1257 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1258 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1259 DRM_INFO("Setting input timings on %s failed\n", 1260 SDVO_NAME(intel_sdvo)); 1261 1262 switch (crtc->config->pixel_multiplier) { 1263 default: 1264 WARN(1, "unknown pixel multiplier specified\n"); 1265 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1266 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1267 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1268 } 1269 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1270 return; 1271 1272 /* Set the SDVO control regs. */ 1273 if (INTEL_INFO(dev)->gen >= 4) { 1274 /* The real mode polarity is set by the SDVO commands, using 1275 * struct intel_sdvo_dtd. */ 1276 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1277 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) 1278 sdvox |= HDMI_COLOR_RANGE_16_235; 1279 if (INTEL_INFO(dev)->gen < 5) 1280 sdvox |= SDVO_BORDER_ENABLE; 1281 } else { 1282 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1283 if (intel_sdvo->port == PORT_B) 1284 sdvox &= SDVOB_PRESERVE_MASK; 1285 else 1286 sdvox &= SDVOC_PRESERVE_MASK; 1287 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1288 } 1289 1290 if (INTEL_PCH_TYPE(dev) >= PCH_CPT) 1291 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1292 else 1293 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1294 1295 if (intel_sdvo->has_hdmi_audio) 1296 sdvox |= SDVO_AUDIO_ENABLE; 1297 1298 if (INTEL_INFO(dev)->gen >= 4) { 1299 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1300 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1301 /* done in crtc_mode_set as it lives inside the dpll register */ 1302 } else { 1303 sdvox |= (crtc->config->pixel_multiplier - 1) 1304 << SDVO_PORT_MULTIPLY_SHIFT; 1305 } 1306 1307 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1308 INTEL_INFO(dev)->gen < 5) 1309 sdvox |= SDVO_STALL_SELECT; 1310 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1311 } 1312 1313 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1314 { 1315 struct intel_sdvo_connector *intel_sdvo_connector = 1316 to_intel_sdvo_connector(&connector->base); 1317 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1318 u16 active_outputs = 0; 1319 1320 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1321 1322 if (active_outputs & intel_sdvo_connector->output_flag) 1323 return true; 1324 else 1325 return false; 1326 } 1327 1328 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1329 enum i915_pipe *pipe) 1330 { 1331 struct drm_device *dev = encoder->base.dev; 1332 struct drm_i915_private *dev_priv = dev->dev_private; 1333 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1334 u16 active_outputs = 0; 1335 u32 tmp; 1336 1337 tmp = I915_READ(intel_sdvo->sdvo_reg); 1338 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1339 1340 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) 1341 return false; 1342 1343 if (HAS_PCH_CPT(dev)) 1344 *pipe = PORT_TO_PIPE_CPT(tmp); 1345 else 1346 *pipe = PORT_TO_PIPE(tmp); 1347 1348 return true; 1349 } 1350 1351 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1352 struct intel_crtc_state *pipe_config) 1353 { 1354 struct drm_device *dev = encoder->base.dev; 1355 struct drm_i915_private *dev_priv = dev->dev_private; 1356 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1357 struct intel_sdvo_dtd dtd; 1358 int encoder_pixel_multiplier = 0; 1359 int dotclock; 1360 u32 flags = 0, sdvox; 1361 u8 val; 1362 bool ret; 1363 1364 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1365 1366 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1367 if (!ret) { 1368 /* Some sdvo encoders are not spec compliant and don't 1369 * implement the mandatory get_timings function. */ 1370 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1371 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1372 } else { 1373 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1374 flags |= DRM_MODE_FLAG_PHSYNC; 1375 else 1376 flags |= DRM_MODE_FLAG_NHSYNC; 1377 1378 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1379 flags |= DRM_MODE_FLAG_PVSYNC; 1380 else 1381 flags |= DRM_MODE_FLAG_NVSYNC; 1382 } 1383 1384 pipe_config->base.adjusted_mode.flags |= flags; 1385 1386 /* 1387 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1388 * the sdvo port register, on all other platforms it is part of the dpll 1389 * state. Since the general pipe state readout happens before the 1390 * encoder->get_config we so already have a valid pixel multplier on all 1391 * other platfroms. 1392 */ 1393 if (IS_I915G(dev) || IS_I915GM(dev)) { 1394 pipe_config->pixel_multiplier = 1395 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1396 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1397 } 1398 1399 dotclock = pipe_config->port_clock; 1400 1401 if (pipe_config->pixel_multiplier) 1402 dotclock /= pipe_config->pixel_multiplier; 1403 1404 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1405 1406 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1407 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1408 &val, 1)) { 1409 switch (val) { 1410 case SDVO_CLOCK_RATE_MULT_1X: 1411 encoder_pixel_multiplier = 1; 1412 break; 1413 case SDVO_CLOCK_RATE_MULT_2X: 1414 encoder_pixel_multiplier = 2; 1415 break; 1416 case SDVO_CLOCK_RATE_MULT_4X: 1417 encoder_pixel_multiplier = 4; 1418 break; 1419 } 1420 } 1421 1422 if (sdvox & HDMI_COLOR_RANGE_16_235) 1423 pipe_config->limited_color_range = true; 1424 1425 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1426 &val, 1)) { 1427 if (val == SDVO_ENCODE_HDMI) 1428 pipe_config->has_hdmi_sink = true; 1429 } 1430 1431 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1432 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1433 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1434 } 1435 1436 static void intel_disable_sdvo(struct intel_encoder *encoder) 1437 { 1438 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1439 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1440 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1441 u32 temp; 1442 1443 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1444 if (0) 1445 intel_sdvo_set_encoder_power_state(intel_sdvo, 1446 DRM_MODE_DPMS_OFF); 1447 1448 temp = I915_READ(intel_sdvo->sdvo_reg); 1449 1450 temp &= ~SDVO_ENABLE; 1451 intel_sdvo_write_sdvox(intel_sdvo, temp); 1452 1453 /* 1454 * HW workaround for IBX, we need to move the port 1455 * to transcoder A after disabling it to allow the 1456 * matching DP port to be enabled on transcoder A. 1457 */ 1458 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1459 /* 1460 * We get CPU/PCH FIFO underruns on the other pipe when 1461 * doing the workaround. Sweep them under the rug. 1462 */ 1463 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1464 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1465 1466 temp &= ~SDVO_PIPE_B_SELECT; 1467 temp |= SDVO_ENABLE; 1468 intel_sdvo_write_sdvox(intel_sdvo, temp); 1469 1470 temp &= ~SDVO_ENABLE; 1471 intel_sdvo_write_sdvox(intel_sdvo, temp); 1472 1473 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); 1474 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1475 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1476 } 1477 } 1478 1479 static void pch_disable_sdvo(struct intel_encoder *encoder) 1480 { 1481 } 1482 1483 static void pch_post_disable_sdvo(struct intel_encoder *encoder) 1484 { 1485 intel_disable_sdvo(encoder); 1486 } 1487 1488 static void intel_enable_sdvo(struct intel_encoder *encoder) 1489 { 1490 struct drm_device *dev = encoder->base.dev; 1491 struct drm_i915_private *dev_priv = dev->dev_private; 1492 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1493 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1494 u32 temp; 1495 bool input1, input2; 1496 int i; 1497 bool success; 1498 1499 temp = I915_READ(intel_sdvo->sdvo_reg); 1500 temp |= SDVO_ENABLE; 1501 intel_sdvo_write_sdvox(intel_sdvo, temp); 1502 1503 for (i = 0; i < 2; i++) 1504 intel_wait_for_vblank(dev, intel_crtc->pipe); 1505 1506 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1507 /* Warn if the device reported failure to sync. 1508 * A lot of SDVO devices fail to notify of sync, but it's 1509 * a given it the status is a success, we succeeded. 1510 */ 1511 if (success && !input1) { 1512 DRM_DEBUG_KMS("First %s output reported failure to " 1513 "sync\n", SDVO_NAME(intel_sdvo)); 1514 } 1515 1516 if (0) 1517 intel_sdvo_set_encoder_power_state(intel_sdvo, 1518 DRM_MODE_DPMS_ON); 1519 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1520 } 1521 1522 static enum drm_mode_status 1523 intel_sdvo_mode_valid(struct drm_connector *connector, 1524 struct drm_display_mode *mode) 1525 { 1526 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1527 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1528 1529 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1530 return MODE_NO_DBLESCAN; 1531 1532 if (intel_sdvo->pixel_clock_min > mode->clock) 1533 return MODE_CLOCK_LOW; 1534 1535 if (intel_sdvo->pixel_clock_max < mode->clock) 1536 return MODE_CLOCK_HIGH; 1537 1538 if (mode->clock > max_dotclk) 1539 return MODE_CLOCK_HIGH; 1540 1541 if (intel_sdvo->is_lvds) { 1542 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1543 return MODE_PANEL; 1544 1545 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1546 return MODE_PANEL; 1547 } 1548 1549 return MODE_OK; 1550 } 1551 1552 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1553 { 1554 BUILD_BUG_ON(sizeof(*caps) != 8); 1555 if (!intel_sdvo_get_value(intel_sdvo, 1556 SDVO_CMD_GET_DEVICE_CAPS, 1557 caps, sizeof(*caps))) 1558 return false; 1559 1560 DRM_DEBUG_KMS("SDVO capabilities:\n" 1561 " vendor_id: %d\n" 1562 " device_id: %d\n" 1563 " device_rev_id: %d\n" 1564 " sdvo_version_major: %d\n" 1565 " sdvo_version_minor: %d\n" 1566 " sdvo_inputs_mask: %d\n" 1567 " smooth_scaling: %d\n" 1568 " sharp_scaling: %d\n" 1569 " up_scaling: %d\n" 1570 " down_scaling: %d\n" 1571 " stall_support: %d\n" 1572 " output_flags: %d\n", 1573 caps->vendor_id, 1574 caps->device_id, 1575 caps->device_rev_id, 1576 caps->sdvo_version_major, 1577 caps->sdvo_version_minor, 1578 caps->sdvo_inputs_mask, 1579 caps->smooth_scaling, 1580 caps->sharp_scaling, 1581 caps->up_scaling, 1582 caps->down_scaling, 1583 caps->stall_support, 1584 caps->output_flags); 1585 1586 return true; 1587 } 1588 1589 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1590 { 1591 struct drm_device *dev = intel_sdvo->base.base.dev; 1592 uint16_t hotplug; 1593 1594 if (!I915_HAS_HOTPLUG(dev)) 1595 return 0; 1596 1597 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1598 * on the line. */ 1599 if (IS_I945G(dev) || IS_I945GM(dev)) 1600 return 0; 1601 1602 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1603 &hotplug, sizeof(hotplug))) 1604 return 0; 1605 1606 return hotplug; 1607 } 1608 1609 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1610 { 1611 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1612 1613 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1614 &intel_sdvo->hotplug_active, 2); 1615 } 1616 1617 static bool 1618 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1619 { 1620 /* Is there more than one type of output? */ 1621 return hweight16(intel_sdvo->caps.output_flags) > 1; 1622 } 1623 1624 static struct edid * 1625 intel_sdvo_get_edid(struct drm_connector *connector) 1626 { 1627 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 1628 return drm_get_edid(connector, &sdvo->ddc); 1629 } 1630 1631 /* Mac mini hack -- use the same DDC as the analog connector */ 1632 static struct edid * 1633 intel_sdvo_get_analog_edid(struct drm_connector *connector) 1634 { 1635 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1636 1637 return drm_get_edid(connector, 1638 intel_gmbus_get_adapter(dev_priv, 1639 dev_priv->vbt.crt_ddc_pin)); 1640 } 1641 1642 static enum drm_connector_status 1643 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1644 { 1645 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1646 enum drm_connector_status status; 1647 struct edid *edid; 1648 1649 edid = intel_sdvo_get_edid(connector); 1650 1651 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1652 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1653 1654 /* 1655 * Don't use the 1 as the argument of DDC bus switch to get 1656 * the EDID. It is used for SDVO SPD ROM. 1657 */ 1658 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1659 intel_sdvo->ddc_bus = ddc; 1660 edid = intel_sdvo_get_edid(connector); 1661 if (edid) 1662 break; 1663 } 1664 /* 1665 * If we found the EDID on the other bus, 1666 * assume that is the correct DDC bus. 1667 */ 1668 if (edid == NULL) 1669 intel_sdvo->ddc_bus = saved_ddc; 1670 } 1671 1672 /* 1673 * When there is no edid and no monitor is connected with VGA 1674 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1675 */ 1676 if (edid == NULL) 1677 edid = intel_sdvo_get_analog_edid(connector); 1678 1679 status = connector_status_unknown; 1680 if (edid != NULL) { 1681 /* DDC bus is shared, match EDID to connector type */ 1682 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1683 status = connector_status_connected; 1684 if (intel_sdvo->is_hdmi) { 1685 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1686 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1687 intel_sdvo->rgb_quant_range_selectable = 1688 drm_rgb_quant_range_selectable(edid); 1689 } 1690 } else 1691 status = connector_status_disconnected; 1692 kfree(edid); 1693 } 1694 1695 if (status == connector_status_connected) { 1696 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1697 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) 1698 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); 1699 } 1700 1701 return status; 1702 } 1703 1704 static bool 1705 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 1706 struct edid *edid) 1707 { 1708 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1709 bool connector_is_digital = !!IS_DIGITAL(sdvo); 1710 1711 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 1712 connector_is_digital, monitor_is_digital); 1713 return connector_is_digital == monitor_is_digital; 1714 } 1715 1716 static enum drm_connector_status 1717 intel_sdvo_detect(struct drm_connector *connector, bool force) 1718 { 1719 uint16_t response; 1720 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1721 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1722 enum drm_connector_status ret; 1723 1724 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1725 connector->base.id, connector->name); 1726 1727 if (!intel_sdvo_get_value(intel_sdvo, 1728 SDVO_CMD_GET_ATTACHED_DISPLAYS, 1729 &response, 2)) 1730 return connector_status_unknown; 1731 1732 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1733 response & 0xff, response >> 8, 1734 intel_sdvo_connector->output_flag); 1735 1736 if (response == 0) 1737 return connector_status_disconnected; 1738 1739 intel_sdvo->attached_output = response; 1740 1741 intel_sdvo->has_hdmi_monitor = false; 1742 intel_sdvo->has_hdmi_audio = false; 1743 intel_sdvo->rgb_quant_range_selectable = false; 1744 1745 if ((intel_sdvo_connector->output_flag & response) == 0) 1746 ret = connector_status_disconnected; 1747 else if (IS_TMDS(intel_sdvo_connector)) 1748 ret = intel_sdvo_tmds_sink_detect(connector); 1749 else { 1750 struct edid *edid; 1751 1752 /* if we have an edid check it matches the connection */ 1753 edid = intel_sdvo_get_edid(connector); 1754 if (edid == NULL) 1755 edid = intel_sdvo_get_analog_edid(connector); 1756 if (edid != NULL) { 1757 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 1758 edid)) 1759 ret = connector_status_connected; 1760 else 1761 ret = connector_status_disconnected; 1762 1763 kfree(edid); 1764 } else 1765 ret = connector_status_connected; 1766 } 1767 1768 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1769 if (ret == connector_status_connected) { 1770 intel_sdvo->is_tv = false; 1771 intel_sdvo->is_lvds = false; 1772 1773 if (response & SDVO_TV_MASK) 1774 intel_sdvo->is_tv = true; 1775 if (response & SDVO_LVDS_MASK) 1776 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1777 } 1778 1779 return ret; 1780 } 1781 1782 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1783 { 1784 struct edid *edid; 1785 1786 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1787 connector->base.id, connector->name); 1788 1789 /* set the bus switch and get the modes */ 1790 edid = intel_sdvo_get_edid(connector); 1791 1792 /* 1793 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1794 * link between analog and digital outputs. So, if the regular SDVO 1795 * DDC fails, check to see if the analog output is disconnected, in 1796 * which case we'll look there for the digital DDC data. 1797 */ 1798 if (edid == NULL) 1799 edid = intel_sdvo_get_analog_edid(connector); 1800 1801 if (edid != NULL) { 1802 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 1803 edid)) { 1804 drm_mode_connector_update_edid_property(connector, edid); 1805 drm_add_edid_modes(connector, edid); 1806 } 1807 1808 kfree(edid); 1809 } 1810 } 1811 1812 /* 1813 * Set of SDVO TV modes. 1814 * Note! This is in reply order (see loop in get_tv_modes). 1815 * XXX: all 60Hz refresh? 1816 */ 1817 static const struct drm_display_mode sdvo_tv_modes[] = { 1818 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1819 416, 0, 200, 201, 232, 233, 0, 1820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1821 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1822 416, 0, 240, 241, 272, 273, 0, 1823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1824 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1825 496, 0, 300, 301, 332, 333, 0, 1826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1827 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1828 736, 0, 350, 351, 382, 383, 0, 1829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1830 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1831 736, 0, 400, 401, 432, 433, 0, 1832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1833 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1834 736, 0, 480, 481, 512, 513, 0, 1835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1836 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1837 800, 0, 480, 481, 512, 513, 0, 1838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1839 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1840 800, 0, 576, 577, 608, 609, 0, 1841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1842 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1843 816, 0, 350, 351, 382, 383, 0, 1844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1845 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1846 816, 0, 400, 401, 432, 433, 0, 1847 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1848 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1849 816, 0, 480, 481, 512, 513, 0, 1850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1851 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1852 816, 0, 540, 541, 572, 573, 0, 1853 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1854 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1855 816, 0, 576, 577, 608, 609, 0, 1856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1857 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1858 864, 0, 576, 577, 608, 609, 0, 1859 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1860 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1861 896, 0, 600, 601, 632, 633, 0, 1862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1863 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1864 928, 0, 624, 625, 656, 657, 0, 1865 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1866 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1867 1016, 0, 766, 767, 798, 799, 0, 1868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1869 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1870 1120, 0, 768, 769, 800, 801, 0, 1871 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1872 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1873 1376, 0, 1024, 1025, 1056, 1057, 0, 1874 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1875 }; 1876 1877 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1878 { 1879 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1880 struct intel_sdvo_sdtv_resolution_request tv_res; 1881 uint32_t reply = 0, format_map = 0; 1882 int i; 1883 1884 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1885 connector->base.id, connector->name); 1886 1887 /* Read the list of supported input resolutions for the selected TV 1888 * format. 1889 */ 1890 format_map = 1 << intel_sdvo->tv_format_index; 1891 memcpy(&tv_res, &format_map, 1892 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1893 1894 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1895 return; 1896 1897 BUILD_BUG_ON(sizeof(tv_res) != 3); 1898 if (!intel_sdvo_write_cmd(intel_sdvo, 1899 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1900 &tv_res, sizeof(tv_res))) 1901 return; 1902 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1903 return; 1904 1905 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1906 if (reply & (1 << i)) { 1907 struct drm_display_mode *nmode; 1908 nmode = drm_mode_duplicate(connector->dev, 1909 &sdvo_tv_modes[i]); 1910 if (nmode) 1911 drm_mode_probed_add(connector, nmode); 1912 } 1913 } 1914 1915 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1916 { 1917 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1918 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1919 struct drm_display_mode *newmode; 1920 1921 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1922 connector->base.id, connector->name); 1923 1924 /* 1925 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 1926 * SDVO->LVDS transcoders can't cope with the EDID mode. 1927 */ 1928 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 1929 newmode = drm_mode_duplicate(connector->dev, 1930 dev_priv->vbt.sdvo_lvds_vbt_mode); 1931 if (newmode != NULL) { 1932 /* Guarantee the mode is preferred */ 1933 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1934 DRM_MODE_TYPE_DRIVER); 1935 drm_mode_probed_add(connector, newmode); 1936 } 1937 } 1938 1939 /* 1940 * Attempt to get the mode list from DDC. 1941 * Assume that the preferred modes are 1942 * arranged in priority order. 1943 */ 1944 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 1945 1946 list_for_each_entry(newmode, &connector->probed_modes, head) { 1947 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1948 intel_sdvo->sdvo_lvds_fixed_mode = 1949 drm_mode_duplicate(connector->dev, newmode); 1950 1951 intel_sdvo->is_lvds = true; 1952 break; 1953 } 1954 } 1955 } 1956 1957 static int intel_sdvo_get_modes(struct drm_connector *connector) 1958 { 1959 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1960 1961 if (IS_TV(intel_sdvo_connector)) 1962 intel_sdvo_get_tv_modes(connector); 1963 else if (IS_LVDS(intel_sdvo_connector)) 1964 intel_sdvo_get_lvds_modes(connector); 1965 else 1966 intel_sdvo_get_ddc_modes(connector); 1967 1968 return !list_empty(&connector->probed_modes); 1969 } 1970 1971 static void intel_sdvo_destroy(struct drm_connector *connector) 1972 { 1973 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1974 1975 drm_connector_cleanup(connector); 1976 kfree(intel_sdvo_connector); 1977 } 1978 1979 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 1980 { 1981 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1982 struct edid *edid; 1983 bool has_audio = false; 1984 1985 if (!intel_sdvo->is_hdmi) 1986 return false; 1987 1988 edid = intel_sdvo_get_edid(connector); 1989 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 1990 has_audio = drm_detect_monitor_audio(edid); 1991 kfree(edid); 1992 1993 return has_audio; 1994 } 1995 1996 static int 1997 intel_sdvo_set_property(struct drm_connector *connector, 1998 struct drm_property *property, 1999 uint64_t val) 2000 { 2001 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2002 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2003 struct drm_i915_private *dev_priv = connector->dev->dev_private; 2004 uint16_t temp_value; 2005 uint8_t cmd; 2006 int ret; 2007 2008 ret = drm_object_property_set_value(&connector->base, property, val); 2009 if (ret) 2010 return ret; 2011 2012 if (property == dev_priv->force_audio_property) { 2013 int i = val; 2014 bool has_audio; 2015 2016 if (i == intel_sdvo_connector->force_audio) 2017 return 0; 2018 2019 intel_sdvo_connector->force_audio = i; 2020 2021 if (i == HDMI_AUDIO_AUTO) 2022 has_audio = intel_sdvo_detect_hdmi_audio(connector); 2023 else 2024 has_audio = (i == HDMI_AUDIO_ON); 2025 2026 if (has_audio == intel_sdvo->has_hdmi_audio) 2027 return 0; 2028 2029 intel_sdvo->has_hdmi_audio = has_audio; 2030 goto done; 2031 } 2032 2033 if (property == dev_priv->broadcast_rgb_property) { 2034 bool old_auto = intel_sdvo->color_range_auto; 2035 uint32_t old_range = intel_sdvo->color_range; 2036 2037 switch (val) { 2038 case INTEL_BROADCAST_RGB_AUTO: 2039 intel_sdvo->color_range_auto = true; 2040 break; 2041 case INTEL_BROADCAST_RGB_FULL: 2042 intel_sdvo->color_range_auto = false; 2043 intel_sdvo->color_range = 0; 2044 break; 2045 case INTEL_BROADCAST_RGB_LIMITED: 2046 intel_sdvo->color_range_auto = false; 2047 /* FIXME: this bit is only valid when using TMDS 2048 * encoding and 8 bit per color mode. */ 2049 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; 2050 break; 2051 default: 2052 return -EINVAL; 2053 } 2054 2055 if (old_auto == intel_sdvo->color_range_auto && 2056 old_range == intel_sdvo->color_range) 2057 return 0; 2058 2059 goto done; 2060 } 2061 2062 if (property == connector->dev->mode_config.aspect_ratio_property) { 2063 switch (val) { 2064 case DRM_MODE_PICTURE_ASPECT_NONE: 2065 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2066 break; 2067 case DRM_MODE_PICTURE_ASPECT_4_3: 2068 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 2069 break; 2070 case DRM_MODE_PICTURE_ASPECT_16_9: 2071 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 2072 break; 2073 default: 2074 return -EINVAL; 2075 } 2076 goto done; 2077 } 2078 2079 #define CHECK_PROPERTY(name, NAME) \ 2080 if (intel_sdvo_connector->name == property) { \ 2081 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 2082 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 2083 cmd = SDVO_CMD_SET_##NAME; \ 2084 intel_sdvo_connector->cur_##name = temp_value; \ 2085 goto set_value; \ 2086 } 2087 2088 if (property == intel_sdvo_connector->tv_format) { 2089 if (val >= TV_FORMAT_NUM) 2090 return -EINVAL; 2091 2092 if (intel_sdvo->tv_format_index == 2093 intel_sdvo_connector->tv_format_supported[val]) 2094 return 0; 2095 2096 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 2097 goto done; 2098 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 2099 temp_value = val; 2100 if (intel_sdvo_connector->left == property) { 2101 drm_object_property_set_value(&connector->base, 2102 intel_sdvo_connector->right, val); 2103 if (intel_sdvo_connector->left_margin == temp_value) 2104 return 0; 2105 2106 intel_sdvo_connector->left_margin = temp_value; 2107 intel_sdvo_connector->right_margin = temp_value; 2108 temp_value = intel_sdvo_connector->max_hscan - 2109 intel_sdvo_connector->left_margin; 2110 cmd = SDVO_CMD_SET_OVERSCAN_H; 2111 goto set_value; 2112 } else if (intel_sdvo_connector->right == property) { 2113 drm_object_property_set_value(&connector->base, 2114 intel_sdvo_connector->left, val); 2115 if (intel_sdvo_connector->right_margin == temp_value) 2116 return 0; 2117 2118 intel_sdvo_connector->left_margin = temp_value; 2119 intel_sdvo_connector->right_margin = temp_value; 2120 temp_value = intel_sdvo_connector->max_hscan - 2121 intel_sdvo_connector->left_margin; 2122 cmd = SDVO_CMD_SET_OVERSCAN_H; 2123 goto set_value; 2124 } else if (intel_sdvo_connector->top == property) { 2125 drm_object_property_set_value(&connector->base, 2126 intel_sdvo_connector->bottom, val); 2127 if (intel_sdvo_connector->top_margin == temp_value) 2128 return 0; 2129 2130 intel_sdvo_connector->top_margin = temp_value; 2131 intel_sdvo_connector->bottom_margin = temp_value; 2132 temp_value = intel_sdvo_connector->max_vscan - 2133 intel_sdvo_connector->top_margin; 2134 cmd = SDVO_CMD_SET_OVERSCAN_V; 2135 goto set_value; 2136 } else if (intel_sdvo_connector->bottom == property) { 2137 drm_object_property_set_value(&connector->base, 2138 intel_sdvo_connector->top, val); 2139 if (intel_sdvo_connector->bottom_margin == temp_value) 2140 return 0; 2141 2142 intel_sdvo_connector->top_margin = temp_value; 2143 intel_sdvo_connector->bottom_margin = temp_value; 2144 temp_value = intel_sdvo_connector->max_vscan - 2145 intel_sdvo_connector->top_margin; 2146 cmd = SDVO_CMD_SET_OVERSCAN_V; 2147 goto set_value; 2148 } 2149 CHECK_PROPERTY(hpos, HPOS) 2150 CHECK_PROPERTY(vpos, VPOS) 2151 CHECK_PROPERTY(saturation, SATURATION) 2152 CHECK_PROPERTY(contrast, CONTRAST) 2153 CHECK_PROPERTY(hue, HUE) 2154 CHECK_PROPERTY(brightness, BRIGHTNESS) 2155 CHECK_PROPERTY(sharpness, SHARPNESS) 2156 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 2157 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 2158 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 2159 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 2160 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 2161 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 2162 } 2163 2164 return -EINVAL; /* unknown property */ 2165 2166 set_value: 2167 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 2168 return -EIO; 2169 2170 2171 done: 2172 if (intel_sdvo->base.base.crtc) 2173 intel_crtc_restore_mode(intel_sdvo->base.base.crtc); 2174 2175 return 0; 2176 #undef CHECK_PROPERTY 2177 } 2178 2179 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2180 .dpms = drm_atomic_helper_connector_dpms, 2181 .detect = intel_sdvo_detect, 2182 .fill_modes = drm_helper_probe_single_connector_modes, 2183 .set_property = intel_sdvo_set_property, 2184 .atomic_get_property = intel_connector_atomic_get_property, 2185 .destroy = intel_sdvo_destroy, 2186 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2187 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2188 }; 2189 2190 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2191 .get_modes = intel_sdvo_get_modes, 2192 .mode_valid = intel_sdvo_mode_valid, 2193 .best_encoder = intel_best_encoder, 2194 }; 2195 2196 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2197 { 2198 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2199 2200 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 2201 drm_mode_destroy(encoder->dev, 2202 intel_sdvo->sdvo_lvds_fixed_mode); 2203 2204 i2c_del_adapter(&intel_sdvo->ddc); 2205 intel_encoder_destroy(encoder); 2206 } 2207 2208 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2209 .destroy = intel_sdvo_enc_destroy, 2210 }; 2211 2212 static void 2213 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2214 { 2215 uint16_t mask = 0; 2216 unsigned int num_bits; 2217 2218 /* Make a mask of outputs less than or equal to our own priority in the 2219 * list. 2220 */ 2221 switch (sdvo->controlled_output) { 2222 case SDVO_OUTPUT_LVDS1: 2223 mask |= SDVO_OUTPUT_LVDS1; 2224 case SDVO_OUTPUT_LVDS0: 2225 mask |= SDVO_OUTPUT_LVDS0; 2226 case SDVO_OUTPUT_TMDS1: 2227 mask |= SDVO_OUTPUT_TMDS1; 2228 case SDVO_OUTPUT_TMDS0: 2229 mask |= SDVO_OUTPUT_TMDS0; 2230 case SDVO_OUTPUT_RGB1: 2231 mask |= SDVO_OUTPUT_RGB1; 2232 case SDVO_OUTPUT_RGB0: 2233 mask |= SDVO_OUTPUT_RGB0; 2234 break; 2235 } 2236 2237 /* Count bits to find what number we are in the priority list. */ 2238 mask &= sdvo->caps.output_flags; 2239 num_bits = hweight16(mask); 2240 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2241 if (num_bits > 3) 2242 num_bits = 3; 2243 2244 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2245 sdvo->ddc_bus = 1 << num_bits; 2246 } 2247 2248 /** 2249 * Choose the appropriate DDC bus for control bus switch command for this 2250 * SDVO output based on the controlled output. 2251 * 2252 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2253 * outputs, then LVDS outputs. 2254 */ 2255 static void 2256 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2257 struct intel_sdvo *sdvo) 2258 { 2259 struct sdvo_device_mapping *mapping; 2260 2261 if (sdvo->port == PORT_B) 2262 mapping = &dev_priv->vbt.sdvo_mappings[0]; 2263 else 2264 mapping = &dev_priv->vbt.sdvo_mappings[1]; 2265 2266 if (mapping->initialized) 2267 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2268 else 2269 intel_sdvo_guess_ddc_bus(sdvo); 2270 } 2271 2272 static void 2273 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2274 struct intel_sdvo *sdvo) 2275 { 2276 struct sdvo_device_mapping *mapping; 2277 u8 pin; 2278 2279 if (sdvo->port == PORT_B) 2280 mapping = &dev_priv->vbt.sdvo_mappings[0]; 2281 else 2282 mapping = &dev_priv->vbt.sdvo_mappings[1]; 2283 2284 if (mapping->initialized && 2285 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2286 pin = mapping->i2c_pin; 2287 else 2288 pin = GMBUS_PIN_DPB; 2289 2290 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2291 2292 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2293 * our code totally fails once we start using gmbus. Hence fall back to 2294 * bit banging for now. */ 2295 intel_gmbus_force_bit(sdvo->i2c, true); 2296 } 2297 2298 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2299 static void 2300 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2301 { 2302 intel_gmbus_force_bit(sdvo->i2c, false); 2303 } 2304 2305 static bool 2306 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2307 { 2308 return intel_sdvo_check_supp_encode(intel_sdvo); 2309 } 2310 2311 static u8 2312 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) 2313 { 2314 struct drm_i915_private *dev_priv = dev->dev_private; 2315 struct sdvo_device_mapping *my_mapping, *other_mapping; 2316 2317 if (sdvo->port == PORT_B) { 2318 my_mapping = &dev_priv->vbt.sdvo_mappings[0]; 2319 other_mapping = &dev_priv->vbt.sdvo_mappings[1]; 2320 } else { 2321 my_mapping = &dev_priv->vbt.sdvo_mappings[1]; 2322 other_mapping = &dev_priv->vbt.sdvo_mappings[0]; 2323 } 2324 2325 /* If the BIOS described our SDVO device, take advantage of it. */ 2326 if (my_mapping->slave_addr) 2327 return my_mapping->slave_addr; 2328 2329 /* If the BIOS only described a different SDVO device, use the 2330 * address that it isn't using. 2331 */ 2332 if (other_mapping->slave_addr) { 2333 if (other_mapping->slave_addr == 0x70) 2334 return 0x72; 2335 else 2336 return 0x70; 2337 } 2338 2339 /* No SDVO device info is found for another DVO port, 2340 * so use mapping assumption we had before BIOS parsing. 2341 */ 2342 if (sdvo->port == PORT_B) 2343 return 0x70; 2344 else 2345 return 0x72; 2346 } 2347 2348 static void 2349 intel_sdvo_connector_unregister(struct intel_connector *intel_connector) 2350 { 2351 struct drm_connector *drm_connector; 2352 struct intel_sdvo *sdvo_encoder; 2353 2354 drm_connector = &intel_connector->base; 2355 sdvo_encoder = intel_attached_sdvo(&intel_connector->base); 2356 2357 #if 0 2358 sysfs_remove_link(&drm_connector->kdev->kobj, 2359 sdvo_encoder->ddc.dev.kobj.name); 2360 #endif 2361 intel_connector_unregister(intel_connector); 2362 } 2363 2364 static int 2365 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2366 struct intel_sdvo *encoder) 2367 { 2368 struct drm_connector *drm_connector; 2369 int ret; 2370 2371 drm_connector = &connector->base.base; 2372 ret = drm_connector_init(encoder->base.base.dev, 2373 drm_connector, 2374 &intel_sdvo_connector_funcs, 2375 connector->base.base.connector_type); 2376 if (ret < 0) 2377 return ret; 2378 2379 drm_connector_helper_add(drm_connector, 2380 &intel_sdvo_connector_helper_funcs); 2381 2382 connector->base.base.interlace_allowed = 1; 2383 connector->base.base.doublescan_allowed = 0; 2384 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2385 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2386 connector->base.unregister = intel_sdvo_connector_unregister; 2387 2388 intel_connector_attach_encoder(&connector->base, &encoder->base); 2389 ret = drm_connector_register(drm_connector); 2390 if (ret < 0) 2391 goto err1; 2392 2393 #if 0 2394 ret = sysfs_create_link(&drm_connector->kdev->kobj, 2395 &encoder->ddc.dev.kobj, 2396 encoder->ddc.dev.kobj.name); 2397 if (ret < 0) 2398 goto err2; 2399 2400 return 0; 2401 2402 err2: 2403 #endif 2404 drm_connector_unregister(drm_connector); 2405 err1: 2406 drm_connector_cleanup(drm_connector); 2407 2408 return ret; 2409 } 2410 2411 static void 2412 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2413 struct intel_sdvo_connector *connector) 2414 { 2415 struct drm_device *dev = connector->base.base.dev; 2416 2417 intel_attach_force_audio_property(&connector->base.base); 2418 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { 2419 intel_attach_broadcast_rgb_property(&connector->base.base); 2420 intel_sdvo->color_range_auto = true; 2421 } 2422 intel_attach_aspect_ratio_property(&connector->base.base); 2423 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2424 } 2425 2426 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2427 { 2428 struct intel_sdvo_connector *sdvo_connector; 2429 2430 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2431 if (!sdvo_connector) 2432 return NULL; 2433 2434 if (intel_connector_init(&sdvo_connector->base) < 0) { 2435 kfree(sdvo_connector); 2436 return NULL; 2437 } 2438 2439 return sdvo_connector; 2440 } 2441 2442 static bool 2443 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2444 { 2445 struct drm_encoder *encoder = &intel_sdvo->base.base; 2446 struct drm_connector *connector; 2447 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2448 struct intel_connector *intel_connector; 2449 struct intel_sdvo_connector *intel_sdvo_connector; 2450 2451 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2452 2453 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2454 if (!intel_sdvo_connector) 2455 return false; 2456 2457 if (device == 0) { 2458 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2459 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2460 } else if (device == 1) { 2461 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2462 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2463 } 2464 2465 intel_connector = &intel_sdvo_connector->base; 2466 connector = &intel_connector->base; 2467 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2468 intel_sdvo_connector->output_flag) { 2469 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2470 /* Some SDVO devices have one-shot hotplug interrupts. 2471 * Ensure that they get re-enabled when an interrupt happens. 2472 */ 2473 intel_encoder->hot_plug = intel_sdvo_enable_hotplug; 2474 intel_sdvo_enable_hotplug(intel_encoder); 2475 } else { 2476 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2477 } 2478 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2479 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2480 2481 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2482 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2483 intel_sdvo->is_hdmi = true; 2484 } 2485 2486 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2487 kfree(intel_sdvo_connector); 2488 return false; 2489 } 2490 2491 if (intel_sdvo->is_hdmi) 2492 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2493 2494 return true; 2495 } 2496 2497 static bool 2498 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2499 { 2500 struct drm_encoder *encoder = &intel_sdvo->base.base; 2501 struct drm_connector *connector; 2502 struct intel_connector *intel_connector; 2503 struct intel_sdvo_connector *intel_sdvo_connector; 2504 2505 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2506 2507 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2508 if (!intel_sdvo_connector) 2509 return false; 2510 2511 intel_connector = &intel_sdvo_connector->base; 2512 connector = &intel_connector->base; 2513 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2514 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2515 2516 intel_sdvo->controlled_output |= type; 2517 intel_sdvo_connector->output_flag = type; 2518 2519 intel_sdvo->is_tv = true; 2520 2521 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2522 kfree(intel_sdvo_connector); 2523 return false; 2524 } 2525 2526 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2527 goto err; 2528 2529 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2530 goto err; 2531 2532 return true; 2533 2534 err: 2535 drm_connector_unregister(connector); 2536 intel_sdvo_destroy(connector); 2537 return false; 2538 } 2539 2540 static bool 2541 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2542 { 2543 struct drm_encoder *encoder = &intel_sdvo->base.base; 2544 struct drm_connector *connector; 2545 struct intel_connector *intel_connector; 2546 struct intel_sdvo_connector *intel_sdvo_connector; 2547 2548 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2549 2550 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2551 if (!intel_sdvo_connector) 2552 return false; 2553 2554 intel_connector = &intel_sdvo_connector->base; 2555 connector = &intel_connector->base; 2556 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2557 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2558 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2559 2560 if (device == 0) { 2561 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2562 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2563 } else if (device == 1) { 2564 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2565 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2566 } 2567 2568 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2569 kfree(intel_sdvo_connector); 2570 return false; 2571 } 2572 2573 return true; 2574 } 2575 2576 static bool 2577 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2578 { 2579 struct drm_encoder *encoder = &intel_sdvo->base.base; 2580 struct drm_connector *connector; 2581 struct intel_connector *intel_connector; 2582 struct intel_sdvo_connector *intel_sdvo_connector; 2583 2584 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2585 2586 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2587 if (!intel_sdvo_connector) 2588 return false; 2589 2590 intel_connector = &intel_sdvo_connector->base; 2591 connector = &intel_connector->base; 2592 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2593 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2594 2595 if (device == 0) { 2596 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2597 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2598 } else if (device == 1) { 2599 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2600 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2601 } 2602 2603 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2604 kfree(intel_sdvo_connector); 2605 return false; 2606 } 2607 2608 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2609 goto err; 2610 2611 return true; 2612 2613 err: 2614 drm_connector_unregister(connector); 2615 intel_sdvo_destroy(connector); 2616 return false; 2617 } 2618 2619 static bool 2620 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2621 { 2622 intel_sdvo->is_tv = false; 2623 intel_sdvo->is_lvds = false; 2624 2625 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2626 2627 if (flags & SDVO_OUTPUT_TMDS0) 2628 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2629 return false; 2630 2631 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2632 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2633 return false; 2634 2635 /* TV has no XXX1 function block */ 2636 if (flags & SDVO_OUTPUT_SVID0) 2637 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2638 return false; 2639 2640 if (flags & SDVO_OUTPUT_CVBS0) 2641 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2642 return false; 2643 2644 if (flags & SDVO_OUTPUT_YPRPB0) 2645 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2646 return false; 2647 2648 if (flags & SDVO_OUTPUT_RGB0) 2649 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2650 return false; 2651 2652 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2653 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2654 return false; 2655 2656 if (flags & SDVO_OUTPUT_LVDS0) 2657 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2658 return false; 2659 2660 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2661 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2662 return false; 2663 2664 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2665 unsigned char bytes[2]; 2666 2667 intel_sdvo->controlled_output = 0; 2668 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2669 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2670 SDVO_NAME(intel_sdvo), 2671 bytes[0], bytes[1]); 2672 return false; 2673 } 2674 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2675 2676 return true; 2677 } 2678 2679 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2680 { 2681 struct drm_device *dev = intel_sdvo->base.base.dev; 2682 struct drm_connector *connector, *tmp; 2683 2684 list_for_each_entry_safe(connector, tmp, 2685 &dev->mode_config.connector_list, head) { 2686 if (intel_attached_encoder(connector) == &intel_sdvo->base) { 2687 drm_connector_unregister(connector); 2688 intel_sdvo_destroy(connector); 2689 } 2690 } 2691 } 2692 2693 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2694 struct intel_sdvo_connector *intel_sdvo_connector, 2695 int type) 2696 { 2697 struct drm_device *dev = intel_sdvo->base.base.dev; 2698 struct intel_sdvo_tv_format format; 2699 uint32_t format_map, i; 2700 2701 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2702 return false; 2703 2704 BUILD_BUG_ON(sizeof(format) != 6); 2705 if (!intel_sdvo_get_value(intel_sdvo, 2706 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2707 &format, sizeof(format))) 2708 return false; 2709 2710 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2711 2712 if (format_map == 0) 2713 return false; 2714 2715 intel_sdvo_connector->format_supported_num = 0; 2716 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2717 if (format_map & (1 << i)) 2718 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2719 2720 2721 intel_sdvo_connector->tv_format = 2722 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2723 "mode", intel_sdvo_connector->format_supported_num); 2724 if (!intel_sdvo_connector->tv_format) 2725 return false; 2726 2727 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2728 drm_property_add_enum( 2729 intel_sdvo_connector->tv_format, i, 2730 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2731 2732 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2733 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2734 intel_sdvo_connector->tv_format, 0); 2735 return true; 2736 2737 } 2738 2739 #define ENHANCEMENT(name, NAME) do { \ 2740 if (enhancements.name) { \ 2741 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2742 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2743 return false; \ 2744 intel_sdvo_connector->max_##name = data_value[0]; \ 2745 intel_sdvo_connector->cur_##name = response; \ 2746 intel_sdvo_connector->name = \ 2747 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2748 if (!intel_sdvo_connector->name) return false; \ 2749 drm_object_attach_property(&connector->base, \ 2750 intel_sdvo_connector->name, \ 2751 intel_sdvo_connector->cur_##name); \ 2752 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2753 data_value[0], data_value[1], response); \ 2754 } \ 2755 } while (0) 2756 2757 static bool 2758 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2759 struct intel_sdvo_connector *intel_sdvo_connector, 2760 struct intel_sdvo_enhancements_reply enhancements) 2761 { 2762 struct drm_device *dev = intel_sdvo->base.base.dev; 2763 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2764 uint16_t response, data_value[2]; 2765 2766 /* when horizontal overscan is supported, Add the left/right property */ 2767 if (enhancements.overscan_h) { 2768 if (!intel_sdvo_get_value(intel_sdvo, 2769 SDVO_CMD_GET_MAX_OVERSCAN_H, 2770 &data_value, 4)) 2771 return false; 2772 2773 if (!intel_sdvo_get_value(intel_sdvo, 2774 SDVO_CMD_GET_OVERSCAN_H, 2775 &response, 2)) 2776 return false; 2777 2778 intel_sdvo_connector->max_hscan = data_value[0]; 2779 intel_sdvo_connector->left_margin = data_value[0] - response; 2780 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2781 intel_sdvo_connector->left = 2782 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2783 if (!intel_sdvo_connector->left) 2784 return false; 2785 2786 drm_object_attach_property(&connector->base, 2787 intel_sdvo_connector->left, 2788 intel_sdvo_connector->left_margin); 2789 2790 intel_sdvo_connector->right = 2791 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2792 if (!intel_sdvo_connector->right) 2793 return false; 2794 2795 drm_object_attach_property(&connector->base, 2796 intel_sdvo_connector->right, 2797 intel_sdvo_connector->right_margin); 2798 DRM_DEBUG_KMS("h_overscan: max %d, " 2799 "default %d, current %d\n", 2800 data_value[0], data_value[1], response); 2801 } 2802 2803 if (enhancements.overscan_v) { 2804 if (!intel_sdvo_get_value(intel_sdvo, 2805 SDVO_CMD_GET_MAX_OVERSCAN_V, 2806 &data_value, 4)) 2807 return false; 2808 2809 if (!intel_sdvo_get_value(intel_sdvo, 2810 SDVO_CMD_GET_OVERSCAN_V, 2811 &response, 2)) 2812 return false; 2813 2814 intel_sdvo_connector->max_vscan = data_value[0]; 2815 intel_sdvo_connector->top_margin = data_value[0] - response; 2816 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2817 intel_sdvo_connector->top = 2818 drm_property_create_range(dev, 0, 2819 "top_margin", 0, data_value[0]); 2820 if (!intel_sdvo_connector->top) 2821 return false; 2822 2823 drm_object_attach_property(&connector->base, 2824 intel_sdvo_connector->top, 2825 intel_sdvo_connector->top_margin); 2826 2827 intel_sdvo_connector->bottom = 2828 drm_property_create_range(dev, 0, 2829 "bottom_margin", 0, data_value[0]); 2830 if (!intel_sdvo_connector->bottom) 2831 return false; 2832 2833 drm_object_attach_property(&connector->base, 2834 intel_sdvo_connector->bottom, 2835 intel_sdvo_connector->bottom_margin); 2836 DRM_DEBUG_KMS("v_overscan: max %d, " 2837 "default %d, current %d\n", 2838 data_value[0], data_value[1], response); 2839 } 2840 2841 ENHANCEMENT(hpos, HPOS); 2842 ENHANCEMENT(vpos, VPOS); 2843 ENHANCEMENT(saturation, SATURATION); 2844 ENHANCEMENT(contrast, CONTRAST); 2845 ENHANCEMENT(hue, HUE); 2846 ENHANCEMENT(sharpness, SHARPNESS); 2847 ENHANCEMENT(brightness, BRIGHTNESS); 2848 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2849 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2850 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2851 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2852 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2853 2854 if (enhancements.dot_crawl) { 2855 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2856 return false; 2857 2858 intel_sdvo_connector->max_dot_crawl = 1; 2859 intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2860 intel_sdvo_connector->dot_crawl = 2861 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2862 if (!intel_sdvo_connector->dot_crawl) 2863 return false; 2864 2865 drm_object_attach_property(&connector->base, 2866 intel_sdvo_connector->dot_crawl, 2867 intel_sdvo_connector->cur_dot_crawl); 2868 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2869 } 2870 2871 return true; 2872 } 2873 2874 static bool 2875 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2876 struct intel_sdvo_connector *intel_sdvo_connector, 2877 struct intel_sdvo_enhancements_reply enhancements) 2878 { 2879 struct drm_device *dev = intel_sdvo->base.base.dev; 2880 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2881 uint16_t response, data_value[2]; 2882 2883 ENHANCEMENT(brightness, BRIGHTNESS); 2884 2885 return true; 2886 } 2887 #undef ENHANCEMENT 2888 2889 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2890 struct intel_sdvo_connector *intel_sdvo_connector) 2891 { 2892 union { 2893 struct intel_sdvo_enhancements_reply reply; 2894 uint16_t response; 2895 } enhancements; 2896 2897 BUILD_BUG_ON(sizeof(enhancements) != 2); 2898 2899 enhancements.response = 0; 2900 intel_sdvo_get_value(intel_sdvo, 2901 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2902 &enhancements, sizeof(enhancements)); 2903 if (enhancements.response == 0) { 2904 DRM_DEBUG_KMS("No enhancement is supported\n"); 2905 return true; 2906 } 2907 2908 if (IS_TV(intel_sdvo_connector)) 2909 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2910 else if (IS_LVDS(intel_sdvo_connector)) 2911 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2912 else 2913 return true; 2914 } 2915 2916 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 2917 struct i2c_msg *msgs, 2918 int num) 2919 { 2920 struct intel_sdvo *sdvo = adapter->algo_data; 2921 2922 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2923 return -EIO; 2924 2925 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 2926 } 2927 2928 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 2929 { 2930 struct intel_sdvo *sdvo = adapter->algo_data; 2931 return sdvo->i2c->algo->functionality(sdvo->i2c); 2932 } 2933 2934 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 2935 .master_xfer = intel_sdvo_ddc_proxy_xfer, 2936 .functionality = intel_sdvo_ddc_proxy_func 2937 }; 2938 2939 static bool 2940 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 2941 struct drm_device *dev) 2942 { 2943 #if 0 2944 sdvo->ddc.owner = THIS_MODULE; 2945 sdvo->ddc.class = I2C_CLASS_DDC; 2946 #endif 2947 ksnprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 2948 sdvo->ddc.dev.parent = &dev->pdev->dev; 2949 sdvo->ddc.algo_data = sdvo; 2950 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 2951 2952 return i2c_add_adapter(&sdvo->ddc) == 0; 2953 } 2954 2955 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, 2956 enum port port) 2957 { 2958 if (HAS_PCH_SPLIT(dev_priv)) 2959 WARN_ON(port != PORT_B); 2960 else 2961 WARN_ON(port != PORT_B && port != PORT_C); 2962 } 2963 2964 bool intel_sdvo_init(struct drm_device *dev, 2965 i915_reg_t sdvo_reg, enum port port) 2966 { 2967 struct drm_i915_private *dev_priv = dev->dev_private; 2968 struct intel_encoder *intel_encoder; 2969 struct intel_sdvo *intel_sdvo; 2970 int i; 2971 2972 assert_sdvo_port_valid(dev_priv, port); 2973 2974 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 2975 if (!intel_sdvo) 2976 return false; 2977 2978 intel_sdvo->sdvo_reg = sdvo_reg; 2979 intel_sdvo->port = port; 2980 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; 2981 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); 2982 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) 2983 goto err_i2c_bus; 2984 2985 /* encoder type will be decided later */ 2986 intel_encoder = &intel_sdvo->base; 2987 intel_encoder->type = INTEL_OUTPUT_SDVO; 2988 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0, 2989 NULL); 2990 2991 /* Read the regs to test if we can talk to the device */ 2992 for (i = 0; i < 0x40; i++) { 2993 u8 byte; 2994 2995 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 2996 DRM_DEBUG_KMS("No SDVO device found on %s\n", 2997 SDVO_NAME(intel_sdvo)); 2998 goto err; 2999 } 3000 } 3001 3002 intel_encoder->compute_config = intel_sdvo_compute_config; 3003 if (HAS_PCH_SPLIT(dev)) { 3004 intel_encoder->disable = pch_disable_sdvo; 3005 intel_encoder->post_disable = pch_post_disable_sdvo; 3006 } else { 3007 intel_encoder->disable = intel_disable_sdvo; 3008 } 3009 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3010 intel_encoder->enable = intel_enable_sdvo; 3011 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3012 intel_encoder->get_config = intel_sdvo_get_config; 3013 3014 /* In default case sdvo lvds is false */ 3015 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3016 goto err; 3017 3018 if (intel_sdvo_output_setup(intel_sdvo, 3019 intel_sdvo->caps.output_flags) != true) { 3020 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 3021 SDVO_NAME(intel_sdvo)); 3022 /* Output_setup can leave behind connectors! */ 3023 goto err_output; 3024 } 3025 3026 /* Only enable the hotplug irq if we need it, to work around noisy 3027 * hotplug lines. 3028 */ 3029 if (intel_sdvo->hotplug_active) { 3030 if (intel_sdvo->port == PORT_B) 3031 intel_encoder->hpd_pin = HPD_SDVO_B; 3032 else 3033 intel_encoder->hpd_pin = HPD_SDVO_C; 3034 } 3035 3036 /* 3037 * Cloning SDVO with anything is often impossible, since the SDVO 3038 * encoder can request a special input timing mode. And even if that's 3039 * not the case we have evidence that cloning a plain unscaled mode with 3040 * VGA doesn't really work. Furthermore the cloning flags are way too 3041 * simplistic anyway to express such constraints, so just give up on 3042 * cloning for SDVO encoders. 3043 */ 3044 intel_sdvo->base.cloneable = 0; 3045 3046 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); 3047 3048 /* Set the input timing to the screen. Assume always input 0. */ 3049 if (!intel_sdvo_set_target_input(intel_sdvo)) 3050 goto err_output; 3051 3052 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3053 &intel_sdvo->pixel_clock_min, 3054 &intel_sdvo->pixel_clock_max)) 3055 goto err_output; 3056 3057 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 3058 "clock range %dMHz - %dMHz, " 3059 "input 1: %c, input 2: %c, " 3060 "output 1: %c, output 2: %c\n", 3061 SDVO_NAME(intel_sdvo), 3062 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3063 intel_sdvo->caps.device_rev_id, 3064 intel_sdvo->pixel_clock_min / 1000, 3065 intel_sdvo->pixel_clock_max / 1000, 3066 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3067 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3068 /* check currently supported outputs */ 3069 intel_sdvo->caps.output_flags & 3070 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3071 intel_sdvo->caps.output_flags & 3072 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3073 return true; 3074 3075 err_output: 3076 intel_sdvo_output_cleanup(intel_sdvo); 3077 3078 err: 3079 drm_encoder_cleanup(&intel_encoder->base); 3080 i2c_del_adapter(&intel_sdvo->ddc); 3081 err_i2c_bus: 3082 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3083 kfree(intel_sdvo); 3084 3085 return false; 3086 } 3087