1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 #include <linux/i2c.h> 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_atomic_helper.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 #include "intel_sdvo_regs.h" 39 40 #include <bus/iicbus/iic.h> 41 #include <bus/iicbus/iiconf.h> 42 #include "iicbus_if.h" 43 44 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 45 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 46 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 47 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 48 49 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 50 SDVO_TV_MASK) 51 52 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 53 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 54 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 55 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 56 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 57 58 59 static const char * const tv_format_names[] = { 60 "NTSC_M" , "NTSC_J" , "NTSC_443", 61 "PAL_B" , "PAL_D" , "PAL_G" , 62 "PAL_H" , "PAL_I" , "PAL_M" , 63 "PAL_N" , "PAL_NC" , "PAL_60" , 64 "SECAM_B" , "SECAM_D" , "SECAM_G" , 65 "SECAM_K" , "SECAM_K1", "SECAM_L" , 66 "SECAM_60" 67 }; 68 69 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 70 71 struct intel_sdvo { 72 struct intel_encoder base; 73 74 struct device *i2c; 75 u8 slave_addr; 76 77 device_t ddc_iic_bus, ddc; 78 79 /* Register for the SDVO device: SDVOB or SDVOC */ 80 uint32_t sdvo_reg; 81 82 /* Active outputs controlled by this SDVO output */ 83 uint16_t controlled_output; 84 85 /* 86 * Capabilities of the SDVO device returned by 87 * intel_sdvo_get_capabilities() 88 */ 89 struct intel_sdvo_caps caps; 90 91 /* Pixel clock limitations reported by the SDVO device, in kHz */ 92 int pixel_clock_min, pixel_clock_max; 93 94 /* 95 * For multiple function SDVO device, 96 * this is for current attached outputs. 97 */ 98 uint16_t attached_output; 99 100 /* 101 * Hotplug activation bits for this device 102 */ 103 uint16_t hotplug_active; 104 105 /** 106 * This is used to select the color range of RBG outputs in HDMI mode. 107 * It is only valid when using TMDS encoding and 8 bit per color mode. 108 */ 109 uint32_t color_range; 110 bool color_range_auto; 111 112 /** 113 * HDMI user specified aspect ratio 114 */ 115 enum hdmi_picture_aspect aspect_ratio; 116 117 /** 118 * This is set if we're going to treat the device as TV-out. 119 * 120 * While we have these nice friendly flags for output types that ought 121 * to decide this for us, the S-Video output on our HDMI+S-Video card 122 * shows up as RGB1 (VGA). 123 */ 124 bool is_tv; 125 126 /* On different gens SDVOB is at different places. */ 127 bool is_sdvob; 128 129 /* This is for current tv format name */ 130 int tv_format_index; 131 132 /** 133 * This is set if we treat the device as HDMI, instead of DVI. 134 */ 135 bool is_hdmi; 136 bool has_hdmi_monitor; 137 bool has_hdmi_audio; 138 bool rgb_quant_range_selectable; 139 140 /** 141 * This is set if we detect output of sdvo device as LVDS and 142 * have a valid fixed mode to use with the panel. 143 */ 144 bool is_lvds; 145 146 /** 147 * This is sdvo fixed pannel mode pointer 148 */ 149 struct drm_display_mode *sdvo_lvds_fixed_mode; 150 151 /* DDC bus used by this SDVO encoder */ 152 uint8_t ddc_bus; 153 154 /* 155 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 156 */ 157 uint8_t dtd_sdvo_flags; 158 }; 159 160 struct intel_sdvo_connector { 161 struct intel_connector base; 162 163 /* Mark the type of connector */ 164 uint16_t output_flag; 165 166 enum hdmi_force_audio force_audio; 167 168 /* This contains all current supported TV format */ 169 u8 tv_format_supported[TV_FORMAT_NUM]; 170 int format_supported_num; 171 struct drm_property *tv_format; 172 173 /* add the property for the SDVO-TV */ 174 struct drm_property *left; 175 struct drm_property *right; 176 struct drm_property *top; 177 struct drm_property *bottom; 178 struct drm_property *hpos; 179 struct drm_property *vpos; 180 struct drm_property *contrast; 181 struct drm_property *saturation; 182 struct drm_property *hue; 183 struct drm_property *sharpness; 184 struct drm_property *flicker_filter; 185 struct drm_property *flicker_filter_adaptive; 186 struct drm_property *flicker_filter_2d; 187 struct drm_property *tv_chroma_filter; 188 struct drm_property *tv_luma_filter; 189 struct drm_property *dot_crawl; 190 191 /* add the property for the SDVO-TV/LVDS */ 192 struct drm_property *brightness; 193 194 /* Add variable to record current setting for the above property */ 195 u32 left_margin, right_margin, top_margin, bottom_margin; 196 197 /* this is to get the range of margin.*/ 198 u32 max_hscan, max_vscan; 199 u32 max_hpos, cur_hpos; 200 u32 max_vpos, cur_vpos; 201 u32 cur_brightness, max_brightness; 202 u32 cur_contrast, max_contrast; 203 u32 cur_saturation, max_saturation; 204 u32 cur_hue, max_hue; 205 u32 cur_sharpness, max_sharpness; 206 u32 cur_flicker_filter, max_flicker_filter; 207 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 208 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 209 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 210 u32 cur_tv_luma_filter, max_tv_luma_filter; 211 u32 cur_dot_crawl, max_dot_crawl; 212 }; 213 214 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 215 { 216 return container_of(encoder, struct intel_sdvo, base); 217 } 218 219 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 220 { 221 return to_sdvo(intel_attached_encoder(connector)); 222 } 223 224 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 225 { 226 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 227 } 228 229 static bool 230 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 231 static bool 232 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 233 struct intel_sdvo_connector *intel_sdvo_connector, 234 int type); 235 static bool 236 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 237 struct intel_sdvo_connector *intel_sdvo_connector); 238 239 /** 240 * Writes the SDVOB or SDVOC with the given value, but always writes both 241 * SDVOB and SDVOC to work around apparent hardware issues (according to 242 * comments in the BIOS). 243 */ 244 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 245 { 246 struct drm_device *dev = intel_sdvo->base.base.dev; 247 struct drm_i915_private *dev_priv = dev->dev_private; 248 u32 bval = val, cval = val; 249 int i; 250 251 if (intel_sdvo->sdvo_reg == PCH_SDVOB) { 252 I915_WRITE(intel_sdvo->sdvo_reg, val); 253 POSTING_READ(intel_sdvo->sdvo_reg); 254 /* 255 * HW workaround, need to write this twice for issue 256 * that may result in first write getting masked. 257 */ 258 if (HAS_PCH_IBX(dev)) { 259 I915_WRITE(intel_sdvo->sdvo_reg, val); 260 POSTING_READ(intel_sdvo->sdvo_reg); 261 } 262 return; 263 } 264 265 if (intel_sdvo->sdvo_reg == GEN3_SDVOB) 266 cval = I915_READ(GEN3_SDVOC); 267 else 268 bval = I915_READ(GEN3_SDVOB); 269 270 /* 271 * Write the registers twice for luck. Sometimes, 272 * writing them only once doesn't appear to 'stick'. 273 * The BIOS does this too. Yay, magic 274 */ 275 for (i = 0; i < 2; i++) 276 { 277 I915_WRITE(GEN3_SDVOB, bval); 278 POSTING_READ(GEN3_SDVOB); 279 I915_WRITE(GEN3_SDVOC, cval); 280 POSTING_READ(GEN3_SDVOC); 281 } 282 } 283 284 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 285 { 286 struct i2c_msg msgs[] = { 287 { 288 .slave = intel_sdvo->slave_addr << 1, 289 .flags = 0, 290 .len = 1, 291 .buf = &addr, 292 }, 293 { 294 .slave = intel_sdvo->slave_addr << 1, 295 .flags = I2C_M_RD, 296 .len = 1, 297 .buf = ch, 298 } 299 }; 300 int ret; 301 302 if ((ret = iicbus_transfer(intel_sdvo->i2c, msgs, 2)) == 0) 303 return true; 304 305 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 306 return false; 307 } 308 309 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 310 /** Mapping of command numbers to names, for debug output */ 311 static const struct _sdvo_cmd_name { 312 u8 cmd; 313 const char *name; 314 } sdvo_cmd_names[] = { 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 358 359 /* Add the op code for SDVO enhancements */ 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 404 405 /* HDMI op code */ 406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 412 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 413 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 414 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 415 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 416 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 417 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 418 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 419 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 420 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 421 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 422 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 423 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 424 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 425 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 426 }; 427 428 #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") 429 430 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 431 const void *args, int args_len) 432 { 433 int i, pos = 0; 434 #define BUF_LEN 256 435 char buffer[BUF_LEN]; 436 437 #define BUF_PRINT(args...) \ 438 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 439 440 441 for (i = 0; i < args_len; i++) { 442 BUF_PRINT("%02X ", ((const u8 *)args)[i]); 443 } 444 for (; i < 8; i++) { 445 BUF_PRINT(" "); 446 } 447 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 448 if (cmd == sdvo_cmd_names[i].cmd) { 449 BUF_PRINT("(%s)", sdvo_cmd_names[i].name); 450 break; 451 } 452 } 453 if (i == ARRAY_SIZE(sdvo_cmd_names)) { 454 BUF_PRINT("(%02X)", cmd); 455 } 456 BUG_ON(pos >= BUF_LEN - 1); 457 #undef BUF_PRINT 458 #undef BUF_LEN 459 460 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 461 } 462 463 static const char * const cmd_status_names[] = { 464 "Power on", 465 "Success", 466 "Not supported", 467 "Invalid arg", 468 "Pending", 469 "Target not specified", 470 "Scaling not supported" 471 }; 472 473 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 474 const void *args, int args_len) 475 { 476 u8 *buf, status; 477 struct i2c_msg *msgs; 478 int i, ret = true; 479 480 /* Would be simpler to allocate both in one go ? */ 481 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 482 if (!buf) 483 return false; 484 485 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 486 if (!msgs) { 487 kfree(buf); 488 return false; 489 } 490 491 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 492 493 for (i = 0; i < args_len; i++) { 494 msgs[i].slave = intel_sdvo->slave_addr << 1; 495 msgs[i].flags = 0; 496 msgs[i].len = 2; 497 msgs[i].buf = buf + 2 *i; 498 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 499 buf[2*i + 1] = ((const u8*)args)[i]; 500 } 501 msgs[i].slave = intel_sdvo->slave_addr << 1; 502 msgs[i].flags = 0; 503 msgs[i].len = 2; 504 msgs[i].buf = buf + 2*i; 505 buf[2*i + 0] = SDVO_I2C_OPCODE; 506 buf[2*i + 1] = cmd; 507 508 /* the following two are to read the response */ 509 status = SDVO_I2C_CMD_STATUS; 510 msgs[i+1].slave = intel_sdvo->slave_addr << 1; 511 msgs[i+1].flags = 0; 512 msgs[i+1].len = 1; 513 msgs[i+1].buf = &status; 514 515 msgs[i+2].slave = intel_sdvo->slave_addr << 1; 516 msgs[i+2].flags = I2C_M_RD; 517 msgs[i+2].len = 1; 518 msgs[i+2].buf = &status; 519 520 ret = iicbus_transfer(intel_sdvo->i2c, msgs, i+3); 521 if (ret != 0) { 522 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 523 ret = false; 524 goto out; 525 } 526 #if 0 527 if (ret != i+3) { 528 /* failure in I2C transfer */ 529 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 530 ret = false; 531 } 532 #endif 533 534 out: 535 kfree(msgs); 536 kfree(buf); 537 return ret; 538 } 539 540 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 541 void *response, int response_len) 542 { 543 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 544 u8 status; 545 int i, pos = 0; 546 #define BUF_LEN 256 547 char buffer[BUF_LEN]; 548 549 550 /* 551 * The documentation states that all commands will be 552 * processed within 15µs, and that we need only poll 553 * the status byte a maximum of 3 times in order for the 554 * command to be complete. 555 * 556 * Check 5 times in case the hardware failed to read the docs. 557 * 558 * Also beware that the first response by many devices is to 559 * reply PENDING and stall for time. TVs are notorious for 560 * requiring longer than specified to complete their replies. 561 * Originally (in the DDX long ago), the delay was only ever 15ms 562 * with an additional delay of 30ms applied for TVs added later after 563 * many experiments. To accommodate both sets of delays, we do a 564 * sequence of slow checks if the device is falling behind and fails 565 * to reply within 5*15µs. 566 */ 567 if (!intel_sdvo_read_byte(intel_sdvo, 568 SDVO_I2C_CMD_STATUS, 569 &status)) 570 goto log_fail; 571 572 while ((status == SDVO_CMD_STATUS_PENDING || 573 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 574 if (retry < 10) 575 msleep(15); 576 else 577 udelay(15); 578 579 if (!intel_sdvo_read_byte(intel_sdvo, 580 SDVO_I2C_CMD_STATUS, 581 &status)) 582 goto log_fail; 583 } 584 585 #define BUF_PRINT(args...) \ 586 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 587 588 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 589 BUF_PRINT("(%s)", cmd_status_names[status]); 590 else 591 BUF_PRINT("(??? %d)", status); 592 593 if (status != SDVO_CMD_STATUS_SUCCESS) 594 goto log_fail; 595 596 /* Read the command response */ 597 for (i = 0; i < response_len; i++) { 598 if (!intel_sdvo_read_byte(intel_sdvo, 599 SDVO_I2C_RETURN_0 + i, 600 &((u8 *)response)[i])) 601 goto log_fail; 602 BUF_PRINT(" %02X", ((u8 *)response)[i]); 603 } 604 BUG_ON(pos >= BUF_LEN - 1); 605 #undef BUF_PRINT 606 #undef BUF_LEN 607 608 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 609 return true; 610 611 log_fail: 612 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); 613 return false; 614 } 615 616 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 617 { 618 if (adjusted_mode->crtc_clock >= 100000) 619 return 1; 620 else if (adjusted_mode->crtc_clock >= 50000) 621 return 2; 622 else 623 return 4; 624 } 625 626 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 627 u8 ddc_bus) 628 { 629 /* This must be the immediately preceding write before the i2c xfer */ 630 return intel_sdvo_write_cmd(intel_sdvo, 631 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 632 &ddc_bus, 1); 633 } 634 635 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 636 { 637 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 638 return false; 639 640 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 641 } 642 643 static bool 644 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 645 { 646 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 647 return false; 648 649 return intel_sdvo_read_response(intel_sdvo, value, len); 650 } 651 652 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 653 { 654 struct intel_sdvo_set_target_input_args targets = {0}; 655 return intel_sdvo_set_value(intel_sdvo, 656 SDVO_CMD_SET_TARGET_INPUT, 657 &targets, sizeof(targets)); 658 } 659 660 /** 661 * Return whether each input is trained. 662 * 663 * This function is making an assumption about the layout of the response, 664 * which should be checked against the docs. 665 */ 666 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 667 { 668 struct intel_sdvo_get_trained_inputs_response response; 669 670 BUILD_BUG_ON(sizeof(response) != 1); 671 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 672 &response, sizeof(response))) 673 return false; 674 675 *input_1 = response.input0_trained; 676 *input_2 = response.input1_trained; 677 return true; 678 } 679 680 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 681 u16 outputs) 682 { 683 return intel_sdvo_set_value(intel_sdvo, 684 SDVO_CMD_SET_ACTIVE_OUTPUTS, 685 &outputs, sizeof(outputs)); 686 } 687 688 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 689 u16 *outputs) 690 { 691 return intel_sdvo_get_value(intel_sdvo, 692 SDVO_CMD_GET_ACTIVE_OUTPUTS, 693 outputs, sizeof(*outputs)); 694 } 695 696 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 697 int mode) 698 { 699 u8 state = SDVO_ENCODER_STATE_ON; 700 701 switch (mode) { 702 case DRM_MODE_DPMS_ON: 703 state = SDVO_ENCODER_STATE_ON; 704 break; 705 case DRM_MODE_DPMS_STANDBY: 706 state = SDVO_ENCODER_STATE_STANDBY; 707 break; 708 case DRM_MODE_DPMS_SUSPEND: 709 state = SDVO_ENCODER_STATE_SUSPEND; 710 break; 711 case DRM_MODE_DPMS_OFF: 712 state = SDVO_ENCODER_STATE_OFF; 713 break; 714 } 715 716 return intel_sdvo_set_value(intel_sdvo, 717 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 718 } 719 720 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 721 int *clock_min, 722 int *clock_max) 723 { 724 struct intel_sdvo_pixel_clock_range clocks; 725 726 BUILD_BUG_ON(sizeof(clocks) != 4); 727 if (!intel_sdvo_get_value(intel_sdvo, 728 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 729 &clocks, sizeof(clocks))) 730 return false; 731 732 /* Convert the values from units of 10 kHz to kHz. */ 733 *clock_min = clocks.min * 10; 734 *clock_max = clocks.max * 10; 735 return true; 736 } 737 738 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 739 u16 outputs) 740 { 741 return intel_sdvo_set_value(intel_sdvo, 742 SDVO_CMD_SET_TARGET_OUTPUT, 743 &outputs, sizeof(outputs)); 744 } 745 746 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 747 struct intel_sdvo_dtd *dtd) 748 { 749 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 750 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 751 } 752 753 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 754 struct intel_sdvo_dtd *dtd) 755 { 756 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 757 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 758 } 759 760 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 761 struct intel_sdvo_dtd *dtd) 762 { 763 return intel_sdvo_set_timing(intel_sdvo, 764 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 765 } 766 767 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 768 struct intel_sdvo_dtd *dtd) 769 { 770 return intel_sdvo_set_timing(intel_sdvo, 771 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 772 } 773 774 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 775 struct intel_sdvo_dtd *dtd) 776 { 777 return intel_sdvo_get_timing(intel_sdvo, 778 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 779 } 780 781 static bool 782 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 783 uint16_t clock, 784 uint16_t width, 785 uint16_t height) 786 { 787 struct intel_sdvo_preferred_input_timing_args args; 788 789 memset(&args, 0, sizeof(args)); 790 args.clock = clock; 791 args.width = width; 792 args.height = height; 793 args.interlace = 0; 794 795 if (intel_sdvo->is_lvds && 796 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 797 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 798 args.scaled = 1; 799 800 return intel_sdvo_set_value(intel_sdvo, 801 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 802 &args, sizeof(args)); 803 } 804 805 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 806 struct intel_sdvo_dtd *dtd) 807 { 808 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 809 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 810 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 811 &dtd->part1, sizeof(dtd->part1)) && 812 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 813 &dtd->part2, sizeof(dtd->part2)); 814 } 815 816 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 817 { 818 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 819 } 820 821 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 822 const struct drm_display_mode *mode) 823 { 824 uint16_t width, height; 825 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 826 uint16_t h_sync_offset, v_sync_offset; 827 int mode_clock; 828 829 memset(dtd, 0, sizeof(*dtd)); 830 831 width = mode->hdisplay; 832 height = mode->vdisplay; 833 834 /* do some mode translations */ 835 h_blank_len = mode->htotal - mode->hdisplay; 836 h_sync_len = mode->hsync_end - mode->hsync_start; 837 838 v_blank_len = mode->vtotal - mode->vdisplay; 839 v_sync_len = mode->vsync_end - mode->vsync_start; 840 841 h_sync_offset = mode->hsync_start - mode->hdisplay; 842 v_sync_offset = mode->vsync_start - mode->vdisplay; 843 844 mode_clock = mode->clock; 845 mode_clock /= 10; 846 dtd->part1.clock = mode_clock; 847 848 dtd->part1.h_active = width & 0xff; 849 dtd->part1.h_blank = h_blank_len & 0xff; 850 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 851 ((h_blank_len >> 8) & 0xf); 852 dtd->part1.v_active = height & 0xff; 853 dtd->part1.v_blank = v_blank_len & 0xff; 854 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 855 ((v_blank_len >> 8) & 0xf); 856 857 dtd->part2.h_sync_off = h_sync_offset & 0xff; 858 dtd->part2.h_sync_width = h_sync_len & 0xff; 859 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 860 (v_sync_len & 0xf); 861 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 862 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 863 ((v_sync_len & 0x30) >> 4); 864 865 dtd->part2.dtd_flags = 0x18; 866 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 867 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 868 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 869 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 870 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 871 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 872 873 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 874 } 875 876 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 877 const struct intel_sdvo_dtd *dtd) 878 { 879 struct drm_display_mode mode = {}; 880 881 mode.hdisplay = dtd->part1.h_active; 882 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 883 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 884 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 885 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 886 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 887 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 888 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 889 890 mode.vdisplay = dtd->part1.v_active; 891 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 892 mode.vsync_start = mode.vdisplay; 893 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 894 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 895 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 896 mode.vsync_end = mode.vsync_start + 897 (dtd->part2.v_sync_off_width & 0xf); 898 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 899 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 900 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 901 902 mode.clock = dtd->part1.clock * 10; 903 904 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 905 mode.flags |= DRM_MODE_FLAG_INTERLACE; 906 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 907 mode.flags |= DRM_MODE_FLAG_PHSYNC; 908 else 909 mode.flags |= DRM_MODE_FLAG_NHSYNC; 910 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 911 mode.flags |= DRM_MODE_FLAG_PVSYNC; 912 else 913 mode.flags |= DRM_MODE_FLAG_NVSYNC; 914 915 drm_mode_set_crtcinfo(&mode, 0); 916 917 drm_mode_copy(pmode, &mode); 918 } 919 920 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 921 { 922 struct intel_sdvo_encode encode; 923 924 BUILD_BUG_ON(sizeof(encode) != 2); 925 return intel_sdvo_get_value(intel_sdvo, 926 SDVO_CMD_GET_SUPP_ENCODE, 927 &encode, sizeof(encode)); 928 } 929 930 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 931 uint8_t mode) 932 { 933 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 934 } 935 936 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 937 uint8_t mode) 938 { 939 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 940 } 941 942 #if 0 943 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 944 { 945 int i, j; 946 uint8_t set_buf_index[2]; 947 uint8_t av_split; 948 uint8_t buf_size; 949 uint8_t buf[48]; 950 uint8_t *pos; 951 952 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 953 954 for (i = 0; i <= av_split; i++) { 955 set_buf_index[0] = i; set_buf_index[1] = 0; 956 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 957 set_buf_index, 2); 958 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 959 intel_sdvo_read_response(encoder, &buf_size, 1); 960 961 pos = buf; 962 for (j = 0; j <= buf_size; j += 8) { 963 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 964 NULL, 0); 965 intel_sdvo_read_response(encoder, pos, 8); 966 pos += 8; 967 } 968 } 969 } 970 #endif 971 972 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 973 unsigned if_index, uint8_t tx_rate, 974 const uint8_t *data, unsigned length) 975 { 976 uint8_t set_buf_index[2] = { if_index, 0 }; 977 uint8_t hbuf_size, tmp[8]; 978 int i; 979 980 if (!intel_sdvo_set_value(intel_sdvo, 981 SDVO_CMD_SET_HBUF_INDEX, 982 set_buf_index, 2)) 983 return false; 984 985 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 986 &hbuf_size, 1)) 987 return false; 988 989 /* Buffer size is 0 based, hooray! */ 990 hbuf_size++; 991 992 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", 993 if_index, length, hbuf_size); 994 995 for (i = 0; i < hbuf_size; i += 8) { 996 memset(tmp, 0, 8); 997 if (i < length) 998 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 999 1000 if (!intel_sdvo_set_value(intel_sdvo, 1001 SDVO_CMD_SET_HBUF_DATA, 1002 tmp, 8)) 1003 return false; 1004 } 1005 1006 return intel_sdvo_set_value(intel_sdvo, 1007 SDVO_CMD_SET_HBUF_TXRATE, 1008 &tx_rate, 1); 1009 } 1010 1011 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1012 const struct drm_display_mode *adjusted_mode) 1013 { 1014 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1015 struct drm_crtc *crtc = intel_sdvo->base.base.crtc; 1016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1017 union hdmi_infoframe frame; 1018 int ret; 1019 ssize_t len; 1020 1021 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 1022 adjusted_mode); 1023 if (ret < 0) { 1024 DRM_ERROR("couldn't fill AVI infoframe\n"); 1025 return false; 1026 } 1027 1028 if (intel_sdvo->rgb_quant_range_selectable) { 1029 if (intel_crtc->config->limited_color_range) 1030 frame.avi.quantization_range = 1031 HDMI_QUANTIZATION_RANGE_LIMITED; 1032 else 1033 frame.avi.quantization_range = 1034 HDMI_QUANTIZATION_RANGE_FULL; 1035 } 1036 1037 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); 1038 if (len < 0) 1039 return false; 1040 1041 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1042 SDVO_HBUF_TX_VSYNC, 1043 sdvo_data, sizeof(sdvo_data)); 1044 } 1045 1046 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 1047 { 1048 struct intel_sdvo_tv_format format; 1049 uint32_t format_map; 1050 1051 format_map = 1 << intel_sdvo->tv_format_index; 1052 memset(&format, 0, sizeof(format)); 1053 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1054 1055 BUILD_BUG_ON(sizeof(format) != 6); 1056 return intel_sdvo_set_value(intel_sdvo, 1057 SDVO_CMD_SET_TV_FORMAT, 1058 &format, sizeof(format)); 1059 } 1060 1061 static bool 1062 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1063 const struct drm_display_mode *mode) 1064 { 1065 struct intel_sdvo_dtd output_dtd; 1066 1067 if (!intel_sdvo_set_target_output(intel_sdvo, 1068 intel_sdvo->attached_output)) 1069 return false; 1070 1071 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1072 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1073 return false; 1074 1075 return true; 1076 } 1077 1078 /* Asks the sdvo controller for the preferred input mode given the output mode. 1079 * Unfortunately we have to set up the full output mode to do that. */ 1080 static bool 1081 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1082 const struct drm_display_mode *mode, 1083 struct drm_display_mode *adjusted_mode) 1084 { 1085 struct intel_sdvo_dtd input_dtd; 1086 1087 /* Reset the input timing to the screen. Assume always input 0. */ 1088 if (!intel_sdvo_set_target_input(intel_sdvo)) 1089 return false; 1090 1091 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1092 mode->clock / 10, 1093 mode->hdisplay, 1094 mode->vdisplay)) 1095 return false; 1096 1097 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1098 &input_dtd)) 1099 return false; 1100 1101 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1102 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1103 1104 return true; 1105 } 1106 1107 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1108 { 1109 unsigned dotclock = pipe_config->port_clock; 1110 struct dpll *clock = &pipe_config->dpll; 1111 1112 /* SDVO TV has fixed PLL values depend on its clock range, 1113 this mirrors vbios setting. */ 1114 if (dotclock >= 100000 && dotclock < 140500) { 1115 clock->p1 = 2; 1116 clock->p2 = 10; 1117 clock->n = 3; 1118 clock->m1 = 16; 1119 clock->m2 = 8; 1120 } else if (dotclock >= 140500 && dotclock <= 200000) { 1121 clock->p1 = 1; 1122 clock->p2 = 10; 1123 clock->n = 6; 1124 clock->m1 = 12; 1125 clock->m2 = 8; 1126 } else { 1127 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1128 } 1129 1130 pipe_config->clock_set = true; 1131 } 1132 1133 static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 1134 struct intel_crtc_state *pipe_config) 1135 { 1136 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1137 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1138 struct drm_display_mode *mode = &pipe_config->base.mode; 1139 1140 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1141 pipe_config->pipe_bpp = 8*3; 1142 1143 if (HAS_PCH_SPLIT(encoder->base.dev)) 1144 pipe_config->has_pch_encoder = true; 1145 1146 /* We need to construct preferred input timings based on our 1147 * output timings. To do that, we have to set the output 1148 * timings, even though this isn't really the right place in 1149 * the sequence to do it. Oh well. 1150 */ 1151 if (intel_sdvo->is_tv) { 1152 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1153 return false; 1154 1155 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1156 mode, 1157 adjusted_mode); 1158 pipe_config->sdvo_tv_clock = true; 1159 } else if (intel_sdvo->is_lvds) { 1160 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1161 intel_sdvo->sdvo_lvds_fixed_mode)) 1162 return false; 1163 1164 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1165 mode, 1166 adjusted_mode); 1167 } 1168 1169 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1170 * SDVO device will factor out the multiplier during mode_set. 1171 */ 1172 pipe_config->pixel_multiplier = 1173 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1174 1175 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; 1176 1177 if (intel_sdvo->color_range_auto) { 1178 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1179 /* FIXME: This bit is only valid when using TMDS encoding and 8 1180 * bit per color mode. */ 1181 if (pipe_config->has_hdmi_sink && 1182 drm_match_cea_mode(adjusted_mode) > 1) 1183 pipe_config->limited_color_range = true; 1184 } else { 1185 if (pipe_config->has_hdmi_sink && 1186 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) 1187 pipe_config->limited_color_range = true; 1188 } 1189 1190 /* Clock computation needs to happen after pixel multiplier. */ 1191 if (intel_sdvo->is_tv) 1192 i9xx_adjust_sdvo_tv_clock(pipe_config); 1193 1194 /* Set user selected PAR to incoming mode's member */ 1195 if (intel_sdvo->is_hdmi) 1196 adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio; 1197 1198 return true; 1199 } 1200 1201 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) 1202 { 1203 struct drm_device *dev = intel_encoder->base.dev; 1204 struct drm_i915_private *dev_priv = dev->dev_private; 1205 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); 1206 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 1207 struct drm_display_mode *mode = &crtc->config->base.mode; 1208 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1209 u32 sdvox; 1210 struct intel_sdvo_in_out_map in_out; 1211 struct intel_sdvo_dtd input_dtd, output_dtd; 1212 int rate; 1213 1214 if (!mode) 1215 return; 1216 1217 /* First, set the input mapping for the first input to our controlled 1218 * output. This is only correct if we're a single-input device, in 1219 * which case the first input is the output from the appropriate SDVO 1220 * channel on the motherboard. In a two-input device, the first input 1221 * will be SDVOB and the second SDVOC. 1222 */ 1223 in_out.in0 = intel_sdvo->attached_output; 1224 in_out.in1 = 0; 1225 1226 intel_sdvo_set_value(intel_sdvo, 1227 SDVO_CMD_SET_IN_OUT_MAP, 1228 &in_out, sizeof(in_out)); 1229 1230 /* Set the output timings to the screen */ 1231 if (!intel_sdvo_set_target_output(intel_sdvo, 1232 intel_sdvo->attached_output)) 1233 return; 1234 1235 /* lvds has a special fixed output timing. */ 1236 if (intel_sdvo->is_lvds) 1237 intel_sdvo_get_dtd_from_mode(&output_dtd, 1238 intel_sdvo->sdvo_lvds_fixed_mode); 1239 else 1240 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1241 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1242 DRM_INFO("Setting output timings on %s failed\n", 1243 SDVO_NAME(intel_sdvo)); 1244 1245 /* Set the input timing to the screen. Assume always input 0. */ 1246 if (!intel_sdvo_set_target_input(intel_sdvo)) 1247 return; 1248 1249 if (crtc->config->has_hdmi_sink) { 1250 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1251 intel_sdvo_set_colorimetry(intel_sdvo, 1252 SDVO_COLORIMETRY_RGB256); 1253 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); 1254 } else 1255 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1256 1257 if (intel_sdvo->is_tv && 1258 !intel_sdvo_set_tv_format(intel_sdvo)) 1259 return; 1260 1261 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1262 1263 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) 1264 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1265 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1266 DRM_INFO("Setting input timings on %s failed\n", 1267 SDVO_NAME(intel_sdvo)); 1268 1269 switch (crtc->config->pixel_multiplier) { 1270 default: 1271 WARN(1, "unknown pixel multiplier specified\n"); 1272 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1273 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1274 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1275 } 1276 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1277 return; 1278 1279 /* Set the SDVO control regs. */ 1280 if (INTEL_INFO(dev)->gen >= 4) { 1281 /* The real mode polarity is set by the SDVO commands, using 1282 * struct intel_sdvo_dtd. */ 1283 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1284 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) 1285 sdvox |= HDMI_COLOR_RANGE_16_235; 1286 if (INTEL_INFO(dev)->gen < 5) 1287 sdvox |= SDVO_BORDER_ENABLE; 1288 } else { 1289 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1290 switch (intel_sdvo->sdvo_reg) { 1291 case GEN3_SDVOB: 1292 sdvox &= SDVOB_PRESERVE_MASK; 1293 break; 1294 case GEN3_SDVOC: 1295 sdvox &= SDVOC_PRESERVE_MASK; 1296 break; 1297 } 1298 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1299 } 1300 1301 if (INTEL_PCH_TYPE(dev) >= PCH_CPT) 1302 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1303 else 1304 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1305 1306 if (intel_sdvo->has_hdmi_audio) 1307 sdvox |= SDVO_AUDIO_ENABLE; 1308 1309 if (INTEL_INFO(dev)->gen >= 4) { 1310 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1311 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1312 /* done in crtc_mode_set as it lives inside the dpll register */ 1313 } else { 1314 sdvox |= (crtc->config->pixel_multiplier - 1) 1315 << SDVO_PORT_MULTIPLY_SHIFT; 1316 } 1317 1318 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1319 INTEL_INFO(dev)->gen < 5) 1320 sdvox |= SDVO_STALL_SELECT; 1321 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1322 } 1323 1324 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1325 { 1326 struct intel_sdvo_connector *intel_sdvo_connector = 1327 to_intel_sdvo_connector(&connector->base); 1328 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1329 u16 active_outputs = 0; 1330 1331 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1332 1333 if (active_outputs & intel_sdvo_connector->output_flag) 1334 return true; 1335 else 1336 return false; 1337 } 1338 1339 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1340 enum i915_pipe *pipe) 1341 { 1342 struct drm_device *dev = encoder->base.dev; 1343 struct drm_i915_private *dev_priv = dev->dev_private; 1344 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1345 u16 active_outputs = 0; 1346 u32 tmp; 1347 1348 tmp = I915_READ(intel_sdvo->sdvo_reg); 1349 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1350 1351 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) 1352 return false; 1353 1354 if (HAS_PCH_CPT(dev)) 1355 *pipe = PORT_TO_PIPE_CPT(tmp); 1356 else 1357 *pipe = PORT_TO_PIPE(tmp); 1358 1359 return true; 1360 } 1361 1362 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1363 struct intel_crtc_state *pipe_config) 1364 { 1365 struct drm_device *dev = encoder->base.dev; 1366 struct drm_i915_private *dev_priv = dev->dev_private; 1367 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1368 struct intel_sdvo_dtd dtd; 1369 int encoder_pixel_multiplier = 0; 1370 int dotclock; 1371 u32 flags = 0, sdvox; 1372 u8 val; 1373 bool ret; 1374 1375 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1376 1377 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1378 if (!ret) { 1379 /* Some sdvo encoders are not spec compliant and don't 1380 * implement the mandatory get_timings function. */ 1381 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1382 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1383 } else { 1384 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1385 flags |= DRM_MODE_FLAG_PHSYNC; 1386 else 1387 flags |= DRM_MODE_FLAG_NHSYNC; 1388 1389 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1390 flags |= DRM_MODE_FLAG_PVSYNC; 1391 else 1392 flags |= DRM_MODE_FLAG_NVSYNC; 1393 } 1394 1395 pipe_config->base.adjusted_mode.flags |= flags; 1396 1397 /* 1398 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1399 * the sdvo port register, on all other platforms it is part of the dpll 1400 * state. Since the general pipe state readout happens before the 1401 * encoder->get_config we so already have a valid pixel multplier on all 1402 * other platfroms. 1403 */ 1404 if (IS_I915G(dev) || IS_I915GM(dev)) { 1405 pipe_config->pixel_multiplier = 1406 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1407 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1408 } 1409 1410 dotclock = pipe_config->port_clock; 1411 if (pipe_config->pixel_multiplier) 1412 dotclock /= pipe_config->pixel_multiplier; 1413 1414 if (HAS_PCH_SPLIT(dev)) 1415 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1416 1417 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1418 1419 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1420 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1421 &val, 1)) { 1422 switch (val) { 1423 case SDVO_CLOCK_RATE_MULT_1X: 1424 encoder_pixel_multiplier = 1; 1425 break; 1426 case SDVO_CLOCK_RATE_MULT_2X: 1427 encoder_pixel_multiplier = 2; 1428 break; 1429 case SDVO_CLOCK_RATE_MULT_4X: 1430 encoder_pixel_multiplier = 4; 1431 break; 1432 } 1433 } 1434 1435 if (sdvox & HDMI_COLOR_RANGE_16_235) 1436 pipe_config->limited_color_range = true; 1437 1438 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1439 &val, 1)) { 1440 if (val == SDVO_ENCODE_HDMI) 1441 pipe_config->has_hdmi_sink = true; 1442 } 1443 1444 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1445 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1446 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1447 } 1448 1449 static void intel_disable_sdvo(struct intel_encoder *encoder) 1450 { 1451 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1452 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1453 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1454 u32 temp; 1455 1456 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1457 if (0) 1458 intel_sdvo_set_encoder_power_state(intel_sdvo, 1459 DRM_MODE_DPMS_OFF); 1460 1461 temp = I915_READ(intel_sdvo->sdvo_reg); 1462 1463 temp &= ~SDVO_ENABLE; 1464 intel_sdvo_write_sdvox(intel_sdvo, temp); 1465 1466 /* 1467 * HW workaround for IBX, we need to move the port 1468 * to transcoder A after disabling it to allow the 1469 * matching DP port to be enabled on transcoder A. 1470 */ 1471 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1472 temp &= ~SDVO_PIPE_B_SELECT; 1473 temp |= SDVO_ENABLE; 1474 intel_sdvo_write_sdvox(intel_sdvo, temp); 1475 1476 temp &= ~SDVO_ENABLE; 1477 intel_sdvo_write_sdvox(intel_sdvo, temp); 1478 } 1479 } 1480 1481 static void pch_disable_sdvo(struct intel_encoder *encoder) 1482 { 1483 } 1484 1485 static void pch_post_disable_sdvo(struct intel_encoder *encoder) 1486 { 1487 intel_disable_sdvo(encoder); 1488 } 1489 1490 static void intel_enable_sdvo(struct intel_encoder *encoder) 1491 { 1492 struct drm_device *dev = encoder->base.dev; 1493 struct drm_i915_private *dev_priv = dev->dev_private; 1494 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1495 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1496 u32 temp; 1497 bool input1, input2; 1498 int i; 1499 bool success; 1500 1501 temp = I915_READ(intel_sdvo->sdvo_reg); 1502 temp |= SDVO_ENABLE; 1503 intel_sdvo_write_sdvox(intel_sdvo, temp); 1504 1505 for (i = 0; i < 2; i++) 1506 intel_wait_for_vblank(dev, intel_crtc->pipe); 1507 1508 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1509 /* Warn if the device reported failure to sync. 1510 * A lot of SDVO devices fail to notify of sync, but it's 1511 * a given it the status is a success, we succeeded. 1512 */ 1513 if (success && !input1) { 1514 DRM_DEBUG_KMS("First %s output reported failure to " 1515 "sync\n", SDVO_NAME(intel_sdvo)); 1516 } 1517 1518 if (0) 1519 intel_sdvo_set_encoder_power_state(intel_sdvo, 1520 DRM_MODE_DPMS_ON); 1521 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1522 } 1523 1524 static enum drm_mode_status 1525 intel_sdvo_mode_valid(struct drm_connector *connector, 1526 struct drm_display_mode *mode) 1527 { 1528 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1529 1530 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1531 return MODE_NO_DBLESCAN; 1532 1533 if (intel_sdvo->pixel_clock_min > mode->clock) 1534 return MODE_CLOCK_LOW; 1535 1536 if (intel_sdvo->pixel_clock_max < mode->clock) 1537 return MODE_CLOCK_HIGH; 1538 1539 if (intel_sdvo->is_lvds) { 1540 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1541 return MODE_PANEL; 1542 1543 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1544 return MODE_PANEL; 1545 } 1546 1547 return MODE_OK; 1548 } 1549 1550 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1551 { 1552 BUILD_BUG_ON(sizeof(*caps) != 8); 1553 if (!intel_sdvo_get_value(intel_sdvo, 1554 SDVO_CMD_GET_DEVICE_CAPS, 1555 caps, sizeof(*caps))) 1556 return false; 1557 1558 DRM_DEBUG_KMS("SDVO capabilities:\n" 1559 " vendor_id: %d\n" 1560 " device_id: %d\n" 1561 " device_rev_id: %d\n" 1562 " sdvo_version_major: %d\n" 1563 " sdvo_version_minor: %d\n" 1564 " sdvo_inputs_mask: %d\n" 1565 " smooth_scaling: %d\n" 1566 " sharp_scaling: %d\n" 1567 " up_scaling: %d\n" 1568 " down_scaling: %d\n" 1569 " stall_support: %d\n" 1570 " output_flags: %d\n", 1571 caps->vendor_id, 1572 caps->device_id, 1573 caps->device_rev_id, 1574 caps->sdvo_version_major, 1575 caps->sdvo_version_minor, 1576 caps->sdvo_inputs_mask, 1577 caps->smooth_scaling, 1578 caps->sharp_scaling, 1579 caps->up_scaling, 1580 caps->down_scaling, 1581 caps->stall_support, 1582 caps->output_flags); 1583 1584 return true; 1585 } 1586 1587 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1588 { 1589 struct drm_device *dev = intel_sdvo->base.base.dev; 1590 uint16_t hotplug; 1591 1592 if (!I915_HAS_HOTPLUG(dev)) 1593 return 0; 1594 1595 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1596 * on the line. */ 1597 if (IS_I945G(dev) || IS_I945GM(dev)) 1598 return 0; 1599 1600 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1601 &hotplug, sizeof(hotplug))) 1602 return 0; 1603 1604 return hotplug; 1605 } 1606 1607 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1608 { 1609 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1610 1611 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1612 &intel_sdvo->hotplug_active, 2); 1613 } 1614 1615 static bool 1616 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1617 { 1618 /* Is there more than one type of output? */ 1619 return hweight16(intel_sdvo->caps.output_flags) > 1; 1620 } 1621 1622 static struct edid * 1623 intel_sdvo_get_edid(struct drm_connector *connector) 1624 { 1625 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 1626 return drm_get_edid(connector, sdvo->ddc); 1627 } 1628 1629 /* Mac mini hack -- use the same DDC as the analog connector */ 1630 static struct edid * 1631 intel_sdvo_get_analog_edid(struct drm_connector *connector) 1632 { 1633 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1634 1635 return drm_get_edid(connector, 1636 intel_gmbus_get_adapter(dev_priv, 1637 dev_priv->vbt.crt_ddc_pin)); 1638 } 1639 1640 static enum drm_connector_status 1641 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1642 { 1643 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1644 enum drm_connector_status status; 1645 struct edid *edid; 1646 1647 edid = intel_sdvo_get_edid(connector); 1648 1649 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1650 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1651 1652 /* 1653 * Don't use the 1 as the argument of DDC bus switch to get 1654 * the EDID. It is used for SDVO SPD ROM. 1655 */ 1656 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1657 intel_sdvo->ddc_bus = ddc; 1658 edid = intel_sdvo_get_edid(connector); 1659 if (edid) 1660 break; 1661 } 1662 /* 1663 * If we found the EDID on the other bus, 1664 * assume that is the correct DDC bus. 1665 */ 1666 if (edid == NULL) 1667 intel_sdvo->ddc_bus = saved_ddc; 1668 } 1669 1670 /* 1671 * When there is no edid and no monitor is connected with VGA 1672 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1673 */ 1674 if (edid == NULL) 1675 edid = intel_sdvo_get_analog_edid(connector); 1676 1677 status = connector_status_unknown; 1678 if (edid != NULL) { 1679 /* DDC bus is shared, match EDID to connector type */ 1680 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1681 status = connector_status_connected; 1682 if (intel_sdvo->is_hdmi) { 1683 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1684 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1685 intel_sdvo->rgb_quant_range_selectable = 1686 drm_rgb_quant_range_selectable(edid); 1687 } 1688 } else 1689 status = connector_status_disconnected; 1690 kfree(edid); 1691 } 1692 1693 if (status == connector_status_connected) { 1694 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1695 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) 1696 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); 1697 } 1698 1699 return status; 1700 } 1701 1702 static bool 1703 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 1704 struct edid *edid) 1705 { 1706 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1707 bool connector_is_digital = !!IS_DIGITAL(sdvo); 1708 1709 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 1710 connector_is_digital, monitor_is_digital); 1711 return connector_is_digital == monitor_is_digital; 1712 } 1713 1714 static enum drm_connector_status 1715 intel_sdvo_detect(struct drm_connector *connector, bool force) 1716 { 1717 uint16_t response; 1718 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1719 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1720 enum drm_connector_status ret; 1721 1722 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1723 connector->base.id, connector->name); 1724 1725 if (!intel_sdvo_get_value(intel_sdvo, 1726 SDVO_CMD_GET_ATTACHED_DISPLAYS, 1727 &response, 2)) 1728 return connector_status_unknown; 1729 1730 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1731 response & 0xff, response >> 8, 1732 intel_sdvo_connector->output_flag); 1733 1734 if (response == 0) 1735 return connector_status_disconnected; 1736 1737 intel_sdvo->attached_output = response; 1738 1739 intel_sdvo->has_hdmi_monitor = false; 1740 intel_sdvo->has_hdmi_audio = false; 1741 intel_sdvo->rgb_quant_range_selectable = false; 1742 1743 if ((intel_sdvo_connector->output_flag & response) == 0) 1744 ret = connector_status_disconnected; 1745 else if (IS_TMDS(intel_sdvo_connector)) 1746 ret = intel_sdvo_tmds_sink_detect(connector); 1747 else { 1748 struct edid *edid; 1749 1750 /* if we have an edid check it matches the connection */ 1751 edid = intel_sdvo_get_edid(connector); 1752 if (edid == NULL) 1753 edid = intel_sdvo_get_analog_edid(connector); 1754 if (edid != NULL) { 1755 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 1756 edid)) 1757 ret = connector_status_connected; 1758 else 1759 ret = connector_status_disconnected; 1760 1761 kfree(edid); 1762 } else 1763 ret = connector_status_connected; 1764 } 1765 1766 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1767 if (ret == connector_status_connected) { 1768 intel_sdvo->is_tv = false; 1769 intel_sdvo->is_lvds = false; 1770 1771 if (response & SDVO_TV_MASK) 1772 intel_sdvo->is_tv = true; 1773 if (response & SDVO_LVDS_MASK) 1774 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1775 } 1776 1777 return ret; 1778 } 1779 1780 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1781 { 1782 struct edid *edid; 1783 1784 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1785 connector->base.id, connector->name); 1786 1787 /* set the bus switch and get the modes */ 1788 edid = intel_sdvo_get_edid(connector); 1789 1790 /* 1791 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1792 * link between analog and digital outputs. So, if the regular SDVO 1793 * DDC fails, check to see if the analog output is disconnected, in 1794 * which case we'll look there for the digital DDC data. 1795 */ 1796 if (edid == NULL) 1797 edid = intel_sdvo_get_analog_edid(connector); 1798 1799 if (edid != NULL) { 1800 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 1801 edid)) { 1802 drm_mode_connector_update_edid_property(connector, edid); 1803 drm_add_edid_modes(connector, edid); 1804 } 1805 1806 kfree(edid); 1807 } 1808 } 1809 1810 /* 1811 * Set of SDVO TV modes. 1812 * Note! This is in reply order (see loop in get_tv_modes). 1813 * XXX: all 60Hz refresh? 1814 */ 1815 static const struct drm_display_mode sdvo_tv_modes[] = { 1816 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1817 416, 0, 200, 201, 232, 233, 0, 1818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1819 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1820 416, 0, 240, 241, 272, 273, 0, 1821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1822 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1823 496, 0, 300, 301, 332, 333, 0, 1824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1825 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1826 736, 0, 350, 351, 382, 383, 0, 1827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1828 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1829 736, 0, 400, 401, 432, 433, 0, 1830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1831 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1832 736, 0, 480, 481, 512, 513, 0, 1833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1834 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1835 800, 0, 480, 481, 512, 513, 0, 1836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1837 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1838 800, 0, 576, 577, 608, 609, 0, 1839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1840 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1841 816, 0, 350, 351, 382, 383, 0, 1842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1843 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1844 816, 0, 400, 401, 432, 433, 0, 1845 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1846 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1847 816, 0, 480, 481, 512, 513, 0, 1848 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1849 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1850 816, 0, 540, 541, 572, 573, 0, 1851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1852 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1853 816, 0, 576, 577, 608, 609, 0, 1854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1855 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1856 864, 0, 576, 577, 608, 609, 0, 1857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1858 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1859 896, 0, 600, 601, 632, 633, 0, 1860 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1861 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1862 928, 0, 624, 625, 656, 657, 0, 1863 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1864 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1865 1016, 0, 766, 767, 798, 799, 0, 1866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1867 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1868 1120, 0, 768, 769, 800, 801, 0, 1869 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1870 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1871 1376, 0, 1024, 1025, 1056, 1057, 0, 1872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1873 }; 1874 1875 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1876 { 1877 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1878 struct intel_sdvo_sdtv_resolution_request tv_res; 1879 uint32_t reply = 0, format_map = 0; 1880 int i; 1881 1882 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1883 connector->base.id, connector->name); 1884 1885 /* Read the list of supported input resolutions for the selected TV 1886 * format. 1887 */ 1888 format_map = 1 << intel_sdvo->tv_format_index; 1889 memcpy(&tv_res, &format_map, 1890 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1891 1892 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1893 return; 1894 1895 BUILD_BUG_ON(sizeof(tv_res) != 3); 1896 if (!intel_sdvo_write_cmd(intel_sdvo, 1897 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1898 &tv_res, sizeof(tv_res))) 1899 return; 1900 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1901 return; 1902 1903 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1904 if (reply & (1 << i)) { 1905 struct drm_display_mode *nmode; 1906 nmode = drm_mode_duplicate(connector->dev, 1907 &sdvo_tv_modes[i]); 1908 if (nmode) 1909 drm_mode_probed_add(connector, nmode); 1910 } 1911 } 1912 1913 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1914 { 1915 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1916 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1917 struct drm_display_mode *newmode; 1918 1919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1920 connector->base.id, connector->name); 1921 1922 /* 1923 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 1924 * SDVO->LVDS transcoders can't cope with the EDID mode. 1925 */ 1926 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 1927 newmode = drm_mode_duplicate(connector->dev, 1928 dev_priv->vbt.sdvo_lvds_vbt_mode); 1929 if (newmode != NULL) { 1930 /* Guarantee the mode is preferred */ 1931 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1932 DRM_MODE_TYPE_DRIVER); 1933 drm_mode_probed_add(connector, newmode); 1934 } 1935 } 1936 1937 /* 1938 * Attempt to get the mode list from DDC. 1939 * Assume that the preferred modes are 1940 * arranged in priority order. 1941 */ 1942 intel_ddc_get_modes(connector, intel_sdvo->ddc); 1943 1944 list_for_each_entry(newmode, &connector->probed_modes, head) { 1945 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1946 intel_sdvo->sdvo_lvds_fixed_mode = 1947 drm_mode_duplicate(connector->dev, newmode); 1948 1949 intel_sdvo->is_lvds = true; 1950 break; 1951 } 1952 } 1953 } 1954 1955 static int intel_sdvo_get_modes(struct drm_connector *connector) 1956 { 1957 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1958 1959 if (IS_TV(intel_sdvo_connector)) 1960 intel_sdvo_get_tv_modes(connector); 1961 else if (IS_LVDS(intel_sdvo_connector)) 1962 intel_sdvo_get_lvds_modes(connector); 1963 else 1964 intel_sdvo_get_ddc_modes(connector); 1965 1966 return !list_empty(&connector->probed_modes); 1967 } 1968 1969 static void intel_sdvo_destroy(struct drm_connector *connector) 1970 { 1971 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1972 1973 drm_connector_cleanup(connector); 1974 kfree(intel_sdvo_connector); 1975 } 1976 1977 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 1978 { 1979 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1980 struct edid *edid; 1981 bool has_audio = false; 1982 1983 if (!intel_sdvo->is_hdmi) 1984 return false; 1985 1986 edid = intel_sdvo_get_edid(connector); 1987 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 1988 has_audio = drm_detect_monitor_audio(edid); 1989 kfree(edid); 1990 1991 return has_audio; 1992 } 1993 1994 static int 1995 intel_sdvo_set_property(struct drm_connector *connector, 1996 struct drm_property *property, 1997 uint64_t val) 1998 { 1999 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2000 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2001 struct drm_i915_private *dev_priv = connector->dev->dev_private; 2002 uint16_t temp_value; 2003 uint8_t cmd; 2004 int ret; 2005 2006 ret = drm_object_property_set_value(&connector->base, property, val); 2007 if (ret) 2008 return ret; 2009 2010 if (property == dev_priv->force_audio_property) { 2011 int i = val; 2012 bool has_audio; 2013 2014 if (i == intel_sdvo_connector->force_audio) 2015 return 0; 2016 2017 intel_sdvo_connector->force_audio = i; 2018 2019 if (i == HDMI_AUDIO_AUTO) 2020 has_audio = intel_sdvo_detect_hdmi_audio(connector); 2021 else 2022 has_audio = (i == HDMI_AUDIO_ON); 2023 2024 if (has_audio == intel_sdvo->has_hdmi_audio) 2025 return 0; 2026 2027 intel_sdvo->has_hdmi_audio = has_audio; 2028 goto done; 2029 } 2030 2031 if (property == dev_priv->broadcast_rgb_property) { 2032 bool old_auto = intel_sdvo->color_range_auto; 2033 uint32_t old_range = intel_sdvo->color_range; 2034 2035 switch (val) { 2036 case INTEL_BROADCAST_RGB_AUTO: 2037 intel_sdvo->color_range_auto = true; 2038 break; 2039 case INTEL_BROADCAST_RGB_FULL: 2040 intel_sdvo->color_range_auto = false; 2041 intel_sdvo->color_range = 0; 2042 break; 2043 case INTEL_BROADCAST_RGB_LIMITED: 2044 intel_sdvo->color_range_auto = false; 2045 /* FIXME: this bit is only valid when using TMDS 2046 * encoding and 8 bit per color mode. */ 2047 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; 2048 break; 2049 default: 2050 return -EINVAL; 2051 } 2052 2053 if (old_auto == intel_sdvo->color_range_auto && 2054 old_range == intel_sdvo->color_range) 2055 return 0; 2056 2057 goto done; 2058 } 2059 2060 if (property == connector->dev->mode_config.aspect_ratio_property) { 2061 switch (val) { 2062 case DRM_MODE_PICTURE_ASPECT_NONE: 2063 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2064 break; 2065 case DRM_MODE_PICTURE_ASPECT_4_3: 2066 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 2067 break; 2068 case DRM_MODE_PICTURE_ASPECT_16_9: 2069 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 2070 break; 2071 default: 2072 return -EINVAL; 2073 } 2074 goto done; 2075 } 2076 2077 #define CHECK_PROPERTY(name, NAME) \ 2078 if (intel_sdvo_connector->name == property) { \ 2079 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 2080 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 2081 cmd = SDVO_CMD_SET_##NAME; \ 2082 intel_sdvo_connector->cur_##name = temp_value; \ 2083 goto set_value; \ 2084 } 2085 2086 if (property == intel_sdvo_connector->tv_format) { 2087 if (val >= TV_FORMAT_NUM) 2088 return -EINVAL; 2089 2090 if (intel_sdvo->tv_format_index == 2091 intel_sdvo_connector->tv_format_supported[val]) 2092 return 0; 2093 2094 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 2095 goto done; 2096 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 2097 temp_value = val; 2098 if (intel_sdvo_connector->left == property) { 2099 drm_object_property_set_value(&connector->base, 2100 intel_sdvo_connector->right, val); 2101 if (intel_sdvo_connector->left_margin == temp_value) 2102 return 0; 2103 2104 intel_sdvo_connector->left_margin = temp_value; 2105 intel_sdvo_connector->right_margin = temp_value; 2106 temp_value = intel_sdvo_connector->max_hscan - 2107 intel_sdvo_connector->left_margin; 2108 cmd = SDVO_CMD_SET_OVERSCAN_H; 2109 goto set_value; 2110 } else if (intel_sdvo_connector->right == property) { 2111 drm_object_property_set_value(&connector->base, 2112 intel_sdvo_connector->left, val); 2113 if (intel_sdvo_connector->right_margin == temp_value) 2114 return 0; 2115 2116 intel_sdvo_connector->left_margin = temp_value; 2117 intel_sdvo_connector->right_margin = temp_value; 2118 temp_value = intel_sdvo_connector->max_hscan - 2119 intel_sdvo_connector->left_margin; 2120 cmd = SDVO_CMD_SET_OVERSCAN_H; 2121 goto set_value; 2122 } else if (intel_sdvo_connector->top == property) { 2123 drm_object_property_set_value(&connector->base, 2124 intel_sdvo_connector->bottom, val); 2125 if (intel_sdvo_connector->top_margin == temp_value) 2126 return 0; 2127 2128 intel_sdvo_connector->top_margin = temp_value; 2129 intel_sdvo_connector->bottom_margin = temp_value; 2130 temp_value = intel_sdvo_connector->max_vscan - 2131 intel_sdvo_connector->top_margin; 2132 cmd = SDVO_CMD_SET_OVERSCAN_V; 2133 goto set_value; 2134 } else if (intel_sdvo_connector->bottom == property) { 2135 drm_object_property_set_value(&connector->base, 2136 intel_sdvo_connector->top, val); 2137 if (intel_sdvo_connector->bottom_margin == temp_value) 2138 return 0; 2139 2140 intel_sdvo_connector->top_margin = temp_value; 2141 intel_sdvo_connector->bottom_margin = temp_value; 2142 temp_value = intel_sdvo_connector->max_vscan - 2143 intel_sdvo_connector->top_margin; 2144 cmd = SDVO_CMD_SET_OVERSCAN_V; 2145 goto set_value; 2146 } 2147 CHECK_PROPERTY(hpos, HPOS) 2148 CHECK_PROPERTY(vpos, VPOS) 2149 CHECK_PROPERTY(saturation, SATURATION) 2150 CHECK_PROPERTY(contrast, CONTRAST) 2151 CHECK_PROPERTY(hue, HUE) 2152 CHECK_PROPERTY(brightness, BRIGHTNESS) 2153 CHECK_PROPERTY(sharpness, SHARPNESS) 2154 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 2155 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 2156 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 2157 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 2158 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 2159 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 2160 } 2161 2162 return -EINVAL; /* unknown property */ 2163 2164 set_value: 2165 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 2166 return -EIO; 2167 2168 2169 done: 2170 if (intel_sdvo->base.base.crtc) 2171 intel_crtc_restore_mode(intel_sdvo->base.base.crtc); 2172 2173 return 0; 2174 #undef CHECK_PROPERTY 2175 } 2176 2177 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2178 .dpms = drm_atomic_helper_connector_dpms, 2179 .detect = intel_sdvo_detect, 2180 .fill_modes = drm_helper_probe_single_connector_modes, 2181 .set_property = intel_sdvo_set_property, 2182 .atomic_get_property = intel_connector_atomic_get_property, 2183 .destroy = intel_sdvo_destroy, 2184 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2185 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2186 }; 2187 2188 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2189 .get_modes = intel_sdvo_get_modes, 2190 .mode_valid = intel_sdvo_mode_valid, 2191 .best_encoder = intel_best_encoder, 2192 }; 2193 2194 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2195 { 2196 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2197 2198 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 2199 drm_mode_destroy(encoder->dev, 2200 intel_sdvo->sdvo_lvds_fixed_mode); 2201 2202 device_delete_child(intel_sdvo->base.base.dev->dev, 2203 intel_sdvo->ddc_iic_bus); 2204 intel_encoder_destroy(encoder); 2205 } 2206 2207 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2208 .destroy = intel_sdvo_enc_destroy, 2209 }; 2210 2211 static void 2212 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2213 { 2214 uint16_t mask = 0; 2215 unsigned int num_bits; 2216 2217 /* Make a mask of outputs less than or equal to our own priority in the 2218 * list. 2219 */ 2220 switch (sdvo->controlled_output) { 2221 case SDVO_OUTPUT_LVDS1: 2222 mask |= SDVO_OUTPUT_LVDS1; 2223 case SDVO_OUTPUT_LVDS0: 2224 mask |= SDVO_OUTPUT_LVDS0; 2225 case SDVO_OUTPUT_TMDS1: 2226 mask |= SDVO_OUTPUT_TMDS1; 2227 case SDVO_OUTPUT_TMDS0: 2228 mask |= SDVO_OUTPUT_TMDS0; 2229 case SDVO_OUTPUT_RGB1: 2230 mask |= SDVO_OUTPUT_RGB1; 2231 case SDVO_OUTPUT_RGB0: 2232 mask |= SDVO_OUTPUT_RGB0; 2233 break; 2234 } 2235 2236 /* Count bits to find what number we are in the priority list. */ 2237 mask &= sdvo->caps.output_flags; 2238 num_bits = hweight16(mask); 2239 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2240 if (num_bits > 3) 2241 num_bits = 3; 2242 2243 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2244 sdvo->ddc_bus = 1 << num_bits; 2245 } 2246 2247 /** 2248 * Choose the appropriate DDC bus for control bus switch command for this 2249 * SDVO output based on the controlled output. 2250 * 2251 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2252 * outputs, then LVDS outputs. 2253 */ 2254 static void 2255 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2256 struct intel_sdvo *sdvo) 2257 { 2258 struct sdvo_device_mapping *mapping; 2259 2260 if (sdvo->is_sdvob) 2261 mapping = &(dev_priv->sdvo_mappings[0]); 2262 else 2263 mapping = &(dev_priv->sdvo_mappings[1]); 2264 2265 if (mapping->initialized) 2266 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2267 else 2268 intel_sdvo_guess_ddc_bus(sdvo); 2269 } 2270 2271 static void 2272 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2273 struct intel_sdvo *sdvo) 2274 { 2275 struct sdvo_device_mapping *mapping; 2276 u8 pin; 2277 2278 if (sdvo->is_sdvob) 2279 mapping = &dev_priv->sdvo_mappings[0]; 2280 else 2281 mapping = &dev_priv->sdvo_mappings[1]; 2282 2283 if (mapping->initialized && 2284 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2285 pin = mapping->i2c_pin; 2286 else 2287 pin = GMBUS_PIN_DPB; 2288 2289 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2290 2291 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2292 * our code totally fails once we start using gmbus. Hence fall back to 2293 * bit banging for now. */ 2294 intel_gmbus_force_bit(sdvo->i2c, true); 2295 } 2296 2297 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2298 static void 2299 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2300 { 2301 intel_gmbus_force_bit(sdvo->i2c, false); 2302 } 2303 2304 static bool 2305 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2306 { 2307 return intel_sdvo_check_supp_encode(intel_sdvo); 2308 } 2309 2310 static u8 2311 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) 2312 { 2313 struct drm_i915_private *dev_priv = dev->dev_private; 2314 struct sdvo_device_mapping *my_mapping, *other_mapping; 2315 2316 if (sdvo->is_sdvob) { 2317 my_mapping = &dev_priv->sdvo_mappings[0]; 2318 other_mapping = &dev_priv->sdvo_mappings[1]; 2319 } else { 2320 my_mapping = &dev_priv->sdvo_mappings[1]; 2321 other_mapping = &dev_priv->sdvo_mappings[0]; 2322 } 2323 2324 /* If the BIOS described our SDVO device, take advantage of it. */ 2325 if (my_mapping->slave_addr) 2326 return my_mapping->slave_addr; 2327 2328 /* If the BIOS only described a different SDVO device, use the 2329 * address that it isn't using. 2330 */ 2331 if (other_mapping->slave_addr) { 2332 if (other_mapping->slave_addr == 0x70) 2333 return 0x72; 2334 else 2335 return 0x70; 2336 } 2337 2338 /* No SDVO device info is found for another DVO port, 2339 * so use mapping assumption we had before BIOS parsing. 2340 */ 2341 if (sdvo->is_sdvob) 2342 return 0x70; 2343 else 2344 return 0x72; 2345 } 2346 2347 static void 2348 intel_sdvo_connector_unregister(struct intel_connector *intel_connector) 2349 { 2350 struct drm_connector *drm_connector; 2351 struct intel_sdvo *sdvo_encoder; 2352 2353 drm_connector = &intel_connector->base; 2354 sdvo_encoder = intel_attached_sdvo(&intel_connector->base); 2355 2356 #if 0 2357 sysfs_remove_link(&drm_connector->kdev->kobj, 2358 sdvo_encoder->ddc.dev.kobj.name); 2359 #endif 2360 intel_connector_unregister(intel_connector); 2361 } 2362 2363 static int 2364 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2365 struct intel_sdvo *encoder) 2366 { 2367 struct drm_connector *drm_connector; 2368 int ret; 2369 2370 drm_connector = &connector->base.base; 2371 ret = drm_connector_init(encoder->base.base.dev, 2372 drm_connector, 2373 &intel_sdvo_connector_funcs, 2374 connector->base.base.connector_type); 2375 if (ret < 0) 2376 return ret; 2377 2378 drm_connector_helper_add(drm_connector, 2379 &intel_sdvo_connector_helper_funcs); 2380 2381 connector->base.base.interlace_allowed = 1; 2382 connector->base.base.doublescan_allowed = 0; 2383 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2384 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2385 connector->base.unregister = intel_sdvo_connector_unregister; 2386 2387 intel_connector_attach_encoder(&connector->base, &encoder->base); 2388 ret = drm_connector_register(drm_connector); 2389 if (ret < 0) 2390 goto err1; 2391 2392 #if 0 2393 ret = sysfs_create_link(&drm_connector->kdev->kobj, 2394 &encoder->ddc.dev.kobj, 2395 encoder->ddc.dev.kobj.name); 2396 if (ret < 0) 2397 goto err2; 2398 2399 return 0; 2400 2401 err2: 2402 #endif 2403 drm_connector_unregister(drm_connector); 2404 err1: 2405 drm_connector_cleanup(drm_connector); 2406 2407 return ret; 2408 } 2409 2410 static void 2411 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2412 struct intel_sdvo_connector *connector) 2413 { 2414 struct drm_device *dev = connector->base.base.dev; 2415 2416 intel_attach_force_audio_property(&connector->base.base); 2417 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { 2418 intel_attach_broadcast_rgb_property(&connector->base.base); 2419 intel_sdvo->color_range_auto = true; 2420 } 2421 intel_attach_aspect_ratio_property(&connector->base.base); 2422 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2423 } 2424 2425 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2426 { 2427 struct intel_sdvo_connector *sdvo_connector; 2428 2429 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2430 if (!sdvo_connector) 2431 return NULL; 2432 2433 if (intel_connector_init(&sdvo_connector->base) < 0) { 2434 kfree(sdvo_connector); 2435 return NULL; 2436 } 2437 2438 return sdvo_connector; 2439 } 2440 2441 static bool 2442 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2443 { 2444 struct drm_encoder *encoder = &intel_sdvo->base.base; 2445 struct drm_connector *connector; 2446 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2447 struct intel_connector *intel_connector; 2448 struct intel_sdvo_connector *intel_sdvo_connector; 2449 2450 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2451 2452 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2453 if (!intel_sdvo_connector) 2454 return false; 2455 2456 if (device == 0) { 2457 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2458 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2459 } else if (device == 1) { 2460 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2461 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2462 } 2463 2464 intel_connector = &intel_sdvo_connector->base; 2465 connector = &intel_connector->base; 2466 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2467 intel_sdvo_connector->output_flag) { 2468 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2469 /* Some SDVO devices have one-shot hotplug interrupts. 2470 * Ensure that they get re-enabled when an interrupt happens. 2471 */ 2472 intel_encoder->hot_plug = intel_sdvo_enable_hotplug; 2473 intel_sdvo_enable_hotplug(intel_encoder); 2474 } else { 2475 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2476 } 2477 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2478 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2479 2480 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2481 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2482 intel_sdvo->is_hdmi = true; 2483 } 2484 2485 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2486 kfree(intel_sdvo_connector); 2487 return false; 2488 } 2489 2490 if (intel_sdvo->is_hdmi) 2491 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2492 2493 return true; 2494 } 2495 2496 static bool 2497 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2498 { 2499 struct drm_encoder *encoder = &intel_sdvo->base.base; 2500 struct drm_connector *connector; 2501 struct intel_connector *intel_connector; 2502 struct intel_sdvo_connector *intel_sdvo_connector; 2503 2504 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2505 2506 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2507 if (!intel_sdvo_connector) 2508 return false; 2509 2510 intel_connector = &intel_sdvo_connector->base; 2511 connector = &intel_connector->base; 2512 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2513 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2514 2515 intel_sdvo->controlled_output |= type; 2516 intel_sdvo_connector->output_flag = type; 2517 2518 intel_sdvo->is_tv = true; 2519 2520 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2521 kfree(intel_sdvo_connector); 2522 return false; 2523 } 2524 2525 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2526 goto err; 2527 2528 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2529 goto err; 2530 2531 return true; 2532 2533 err: 2534 drm_connector_unregister(connector); 2535 intel_sdvo_destroy(connector); 2536 return false; 2537 } 2538 2539 static bool 2540 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2541 { 2542 struct drm_encoder *encoder = &intel_sdvo->base.base; 2543 struct drm_connector *connector; 2544 struct intel_connector *intel_connector; 2545 struct intel_sdvo_connector *intel_sdvo_connector; 2546 2547 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2548 2549 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2550 if (!intel_sdvo_connector) 2551 return false; 2552 2553 intel_connector = &intel_sdvo_connector->base; 2554 connector = &intel_connector->base; 2555 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2556 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2557 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2558 2559 if (device == 0) { 2560 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2561 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2562 } else if (device == 1) { 2563 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2564 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2565 } 2566 2567 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2568 kfree(intel_sdvo_connector); 2569 return false; 2570 } 2571 2572 return true; 2573 } 2574 2575 static bool 2576 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2577 { 2578 struct drm_encoder *encoder = &intel_sdvo->base.base; 2579 struct drm_connector *connector; 2580 struct intel_connector *intel_connector; 2581 struct intel_sdvo_connector *intel_sdvo_connector; 2582 2583 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2584 2585 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2586 if (!intel_sdvo_connector) 2587 return false; 2588 2589 intel_connector = &intel_sdvo_connector->base; 2590 connector = &intel_connector->base; 2591 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2592 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2593 2594 if (device == 0) { 2595 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2596 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2597 } else if (device == 1) { 2598 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2599 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2600 } 2601 2602 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2603 kfree(intel_sdvo_connector); 2604 return false; 2605 } 2606 2607 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2608 goto err; 2609 2610 return true; 2611 2612 err: 2613 drm_connector_unregister(connector); 2614 intel_sdvo_destroy(connector); 2615 return false; 2616 } 2617 2618 static bool 2619 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2620 { 2621 intel_sdvo->is_tv = false; 2622 intel_sdvo->is_lvds = false; 2623 2624 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2625 2626 if (flags & SDVO_OUTPUT_TMDS0) 2627 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2628 return false; 2629 2630 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2631 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2632 return false; 2633 2634 /* TV has no XXX1 function block */ 2635 if (flags & SDVO_OUTPUT_SVID0) 2636 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2637 return false; 2638 2639 if (flags & SDVO_OUTPUT_CVBS0) 2640 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2641 return false; 2642 2643 if (flags & SDVO_OUTPUT_YPRPB0) 2644 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2645 return false; 2646 2647 if (flags & SDVO_OUTPUT_RGB0) 2648 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2649 return false; 2650 2651 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2652 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2653 return false; 2654 2655 if (flags & SDVO_OUTPUT_LVDS0) 2656 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2657 return false; 2658 2659 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2660 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2661 return false; 2662 2663 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2664 unsigned char bytes[2]; 2665 2666 intel_sdvo->controlled_output = 0; 2667 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2668 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2669 SDVO_NAME(intel_sdvo), 2670 bytes[0], bytes[1]); 2671 return false; 2672 } 2673 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2674 2675 return true; 2676 } 2677 2678 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2679 { 2680 struct drm_device *dev = intel_sdvo->base.base.dev; 2681 struct drm_connector *connector, *tmp; 2682 2683 list_for_each_entry_safe(connector, tmp, 2684 &dev->mode_config.connector_list, head) { 2685 if (intel_attached_encoder(connector) == &intel_sdvo->base) { 2686 drm_connector_unregister(connector); 2687 intel_sdvo_destroy(connector); 2688 } 2689 } 2690 } 2691 2692 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2693 struct intel_sdvo_connector *intel_sdvo_connector, 2694 int type) 2695 { 2696 struct drm_device *dev = intel_sdvo->base.base.dev; 2697 struct intel_sdvo_tv_format format; 2698 uint32_t format_map, i; 2699 2700 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2701 return false; 2702 2703 BUILD_BUG_ON(sizeof(format) != 6); 2704 if (!intel_sdvo_get_value(intel_sdvo, 2705 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2706 &format, sizeof(format))) 2707 return false; 2708 2709 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2710 2711 if (format_map == 0) 2712 return false; 2713 2714 intel_sdvo_connector->format_supported_num = 0; 2715 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2716 if (format_map & (1 << i)) 2717 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2718 2719 2720 intel_sdvo_connector->tv_format = 2721 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2722 "mode", intel_sdvo_connector->format_supported_num); 2723 if (!intel_sdvo_connector->tv_format) 2724 return false; 2725 2726 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2727 drm_property_add_enum( 2728 intel_sdvo_connector->tv_format, i, 2729 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2730 2731 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2732 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2733 intel_sdvo_connector->tv_format, 0); 2734 return true; 2735 2736 } 2737 2738 #define ENHANCEMENT(name, NAME) do { \ 2739 if (enhancements.name) { \ 2740 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2741 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2742 return false; \ 2743 intel_sdvo_connector->max_##name = data_value[0]; \ 2744 intel_sdvo_connector->cur_##name = response; \ 2745 intel_sdvo_connector->name = \ 2746 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2747 if (!intel_sdvo_connector->name) return false; \ 2748 drm_object_attach_property(&connector->base, \ 2749 intel_sdvo_connector->name, \ 2750 intel_sdvo_connector->cur_##name); \ 2751 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2752 data_value[0], data_value[1], response); \ 2753 } \ 2754 } while (0) 2755 2756 static bool 2757 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2758 struct intel_sdvo_connector *intel_sdvo_connector, 2759 struct intel_sdvo_enhancements_reply enhancements) 2760 { 2761 struct drm_device *dev = intel_sdvo->base.base.dev; 2762 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2763 uint16_t response, data_value[2]; 2764 2765 /* when horizontal overscan is supported, Add the left/right property */ 2766 if (enhancements.overscan_h) { 2767 if (!intel_sdvo_get_value(intel_sdvo, 2768 SDVO_CMD_GET_MAX_OVERSCAN_H, 2769 &data_value, 4)) 2770 return false; 2771 2772 if (!intel_sdvo_get_value(intel_sdvo, 2773 SDVO_CMD_GET_OVERSCAN_H, 2774 &response, 2)) 2775 return false; 2776 2777 intel_sdvo_connector->max_hscan = data_value[0]; 2778 intel_sdvo_connector->left_margin = data_value[0] - response; 2779 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2780 intel_sdvo_connector->left = 2781 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2782 if (!intel_sdvo_connector->left) 2783 return false; 2784 2785 drm_object_attach_property(&connector->base, 2786 intel_sdvo_connector->left, 2787 intel_sdvo_connector->left_margin); 2788 2789 intel_sdvo_connector->right = 2790 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2791 if (!intel_sdvo_connector->right) 2792 return false; 2793 2794 drm_object_attach_property(&connector->base, 2795 intel_sdvo_connector->right, 2796 intel_sdvo_connector->right_margin); 2797 DRM_DEBUG_KMS("h_overscan: max %d, " 2798 "default %d, current %d\n", 2799 data_value[0], data_value[1], response); 2800 } 2801 2802 if (enhancements.overscan_v) { 2803 if (!intel_sdvo_get_value(intel_sdvo, 2804 SDVO_CMD_GET_MAX_OVERSCAN_V, 2805 &data_value, 4)) 2806 return false; 2807 2808 if (!intel_sdvo_get_value(intel_sdvo, 2809 SDVO_CMD_GET_OVERSCAN_V, 2810 &response, 2)) 2811 return false; 2812 2813 intel_sdvo_connector->max_vscan = data_value[0]; 2814 intel_sdvo_connector->top_margin = data_value[0] - response; 2815 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2816 intel_sdvo_connector->top = 2817 drm_property_create_range(dev, 0, 2818 "top_margin", 0, data_value[0]); 2819 if (!intel_sdvo_connector->top) 2820 return false; 2821 2822 drm_object_attach_property(&connector->base, 2823 intel_sdvo_connector->top, 2824 intel_sdvo_connector->top_margin); 2825 2826 intel_sdvo_connector->bottom = 2827 drm_property_create_range(dev, 0, 2828 "bottom_margin", 0, data_value[0]); 2829 if (!intel_sdvo_connector->bottom) 2830 return false; 2831 2832 drm_object_attach_property(&connector->base, 2833 intel_sdvo_connector->bottom, 2834 intel_sdvo_connector->bottom_margin); 2835 DRM_DEBUG_KMS("v_overscan: max %d, " 2836 "default %d, current %d\n", 2837 data_value[0], data_value[1], response); 2838 } 2839 2840 ENHANCEMENT(hpos, HPOS); 2841 ENHANCEMENT(vpos, VPOS); 2842 ENHANCEMENT(saturation, SATURATION); 2843 ENHANCEMENT(contrast, CONTRAST); 2844 ENHANCEMENT(hue, HUE); 2845 ENHANCEMENT(sharpness, SHARPNESS); 2846 ENHANCEMENT(brightness, BRIGHTNESS); 2847 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2848 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2849 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2850 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2851 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2852 2853 if (enhancements.dot_crawl) { 2854 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2855 return false; 2856 2857 intel_sdvo_connector->max_dot_crawl = 1; 2858 intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2859 intel_sdvo_connector->dot_crawl = 2860 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2861 if (!intel_sdvo_connector->dot_crawl) 2862 return false; 2863 2864 drm_object_attach_property(&connector->base, 2865 intel_sdvo_connector->dot_crawl, 2866 intel_sdvo_connector->cur_dot_crawl); 2867 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2868 } 2869 2870 return true; 2871 } 2872 2873 static bool 2874 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2875 struct intel_sdvo_connector *intel_sdvo_connector, 2876 struct intel_sdvo_enhancements_reply enhancements) 2877 { 2878 struct drm_device *dev = intel_sdvo->base.base.dev; 2879 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2880 uint16_t response, data_value[2]; 2881 2882 ENHANCEMENT(brightness, BRIGHTNESS); 2883 2884 return true; 2885 } 2886 #undef ENHANCEMENT 2887 2888 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2889 struct intel_sdvo_connector *intel_sdvo_connector) 2890 { 2891 union { 2892 struct intel_sdvo_enhancements_reply reply; 2893 uint16_t response; 2894 } enhancements; 2895 2896 BUILD_BUG_ON(sizeof(enhancements) != 2); 2897 2898 enhancements.response = 0; 2899 intel_sdvo_get_value(intel_sdvo, 2900 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2901 &enhancements, sizeof(enhancements)); 2902 if (enhancements.response == 0) { 2903 DRM_DEBUG_KMS("No enhancement is supported\n"); 2904 return true; 2905 } 2906 2907 if (IS_TV(intel_sdvo_connector)) 2908 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2909 else if (IS_LVDS(intel_sdvo_connector)) 2910 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2911 else 2912 return true; 2913 } 2914 2915 struct intel_sdvo_ddc_proxy_sc { 2916 struct intel_sdvo *intel_sdvo; 2917 device_t port; 2918 }; 2919 2920 static int 2921 intel_sdvo_ddc_proxy_probe(device_t idev) 2922 { 2923 return (BUS_PROBE_DEFAULT); 2924 } 2925 2926 static int 2927 intel_sdvo_ddc_proxy_attach(device_t idev) 2928 { 2929 struct intel_sdvo_ddc_proxy_sc *sc; 2930 2931 sc = device_get_softc(idev); 2932 sc->port = device_add_child(idev, "iicbus", -1); 2933 if (sc->port == NULL) 2934 return (ENXIO); 2935 device_quiet(sc->port); 2936 bus_generic_attach(idev); 2937 return (0); 2938 } 2939 2940 static int 2941 intel_sdvo_ddc_proxy_detach(device_t idev) 2942 { 2943 struct intel_sdvo_ddc_proxy_sc *sc; 2944 device_t port; 2945 2946 sc = device_get_softc(idev); 2947 port = sc->port; 2948 bus_generic_detach(idev); 2949 if (port != NULL) 2950 device_delete_child(idev, port); 2951 return (0); 2952 } 2953 2954 static int 2955 intel_sdvo_ddc_proxy_reset(device_t idev, u_char speed, u_char addr, 2956 u_char *oldaddr) 2957 { 2958 struct intel_sdvo_ddc_proxy_sc *sc; 2959 struct intel_sdvo *sdvo; 2960 2961 sc = device_get_softc(idev); 2962 sdvo = sc->intel_sdvo; 2963 2964 return (IICBUS_RESET(device_get_parent(sdvo->i2c), speed, addr, 2965 oldaddr)); 2966 } 2967 2968 static int intel_sdvo_ddc_proxy_xfer(struct device *adapter, 2969 struct i2c_msg *msgs, 2970 int num) 2971 { 2972 struct intel_sdvo_ddc_proxy_sc *sc = device_get_softc(adapter); 2973 struct intel_sdvo *sdvo = sc->intel_sdvo; 2974 2975 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2976 return -EIO; 2977 2978 return (iicbus_transfer(sdvo->i2c, msgs, num)); 2979 } 2980 2981 static bool 2982 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, struct drm_device *dev, 2983 int sdvo_reg) 2984 { 2985 struct intel_sdvo_ddc_proxy_sc *sc; 2986 int ret; 2987 2988 sdvo->ddc_iic_bus = device_add_child(dev->dev, 2989 "intel_sdvo_ddc_proxy", sdvo_reg); 2990 if (sdvo->ddc_iic_bus == NULL) { 2991 DRM_ERROR("cannot create ddc proxy bus %d\n", sdvo_reg); 2992 return (false); 2993 } 2994 device_quiet(sdvo->ddc_iic_bus); 2995 ret = device_probe_and_attach(sdvo->ddc_iic_bus); 2996 if (ret != 0) { 2997 DRM_ERROR("cannot attach proxy bus %d error %d\n", 2998 sdvo_reg, ret); 2999 device_delete_child(dev->dev, sdvo->ddc_iic_bus); 3000 return (false); 3001 } 3002 sc = device_get_softc(sdvo->ddc_iic_bus); 3003 sc->intel_sdvo = sdvo; 3004 3005 sdvo->ddc = sc->port; 3006 return (true); 3007 } 3008 3009 static device_method_t intel_sdvo_ddc_proxy_methods[] = { 3010 DEVMETHOD(device_probe, intel_sdvo_ddc_proxy_probe), 3011 DEVMETHOD(device_attach, intel_sdvo_ddc_proxy_attach), 3012 DEVMETHOD(device_detach, intel_sdvo_ddc_proxy_detach), 3013 DEVMETHOD(iicbus_reset, intel_sdvo_ddc_proxy_reset), 3014 DEVMETHOD(iicbus_transfer, intel_sdvo_ddc_proxy_xfer), 3015 DEVMETHOD_END 3016 }; 3017 static driver_t intel_sdvo_ddc_proxy_driver = { 3018 "intel_sdvo_ddc_proxy", 3019 intel_sdvo_ddc_proxy_methods, 3020 sizeof(struct intel_sdvo_ddc_proxy_sc) 3021 }; 3022 3023 static devclass_t intel_sdvo_devclass; 3024 DRIVER_MODULE_ORDERED(intel_sdvo_ddc_proxy, drm, intel_sdvo_ddc_proxy_driver, 3025 intel_sdvo_devclass, NULL, NULL, SI_ORDER_FIRST); 3026 3027 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) 3028 { 3029 struct drm_i915_private *dev_priv = dev->dev_private; 3030 struct intel_encoder *intel_encoder; 3031 struct intel_sdvo *intel_sdvo; 3032 int i; 3033 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3034 if (!intel_sdvo) 3035 return false; 3036 3037 intel_sdvo->sdvo_reg = sdvo_reg; 3038 intel_sdvo->is_sdvob = is_sdvob; 3039 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; 3040 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); 3041 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev, sdvo_reg)) 3042 goto err_i2c_bus; 3043 3044 /* encoder type will be decided later */ 3045 intel_encoder = &intel_sdvo->base; 3046 intel_encoder->type = INTEL_OUTPUT_SDVO; 3047 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); 3048 3049 /* Read the regs to test if we can talk to the device */ 3050 for (i = 0; i < 0x40; i++) { 3051 u8 byte; 3052 3053 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3054 DRM_DEBUG_KMS("No SDVO device found on %s\n", 3055 SDVO_NAME(intel_sdvo)); 3056 goto err; 3057 } 3058 } 3059 3060 intel_encoder->compute_config = intel_sdvo_compute_config; 3061 if (HAS_PCH_SPLIT(dev)) { 3062 intel_encoder->disable = pch_disable_sdvo; 3063 intel_encoder->post_disable = pch_post_disable_sdvo; 3064 } else { 3065 intel_encoder->disable = intel_disable_sdvo; 3066 } 3067 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3068 intel_encoder->enable = intel_enable_sdvo; 3069 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3070 intel_encoder->get_config = intel_sdvo_get_config; 3071 3072 /* In default case sdvo lvds is false */ 3073 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3074 goto err; 3075 3076 if (intel_sdvo_output_setup(intel_sdvo, 3077 intel_sdvo->caps.output_flags) != true) { 3078 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 3079 SDVO_NAME(intel_sdvo)); 3080 /* Output_setup can leave behind connectors! */ 3081 goto err_output; 3082 } 3083 3084 /* Only enable the hotplug irq if we need it, to work around noisy 3085 * hotplug lines. 3086 */ 3087 if (intel_sdvo->hotplug_active) { 3088 intel_encoder->hpd_pin = 3089 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; 3090 } 3091 3092 /* 3093 * Cloning SDVO with anything is often impossible, since the SDVO 3094 * encoder can request a special input timing mode. And even if that's 3095 * not the case we have evidence that cloning a plain unscaled mode with 3096 * VGA doesn't really work. Furthermore the cloning flags are way too 3097 * simplistic anyway to express such constraints, so just give up on 3098 * cloning for SDVO encoders. 3099 */ 3100 intel_sdvo->base.cloneable = 0; 3101 3102 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); 3103 3104 /* Set the input timing to the screen. Assume always input 0. */ 3105 if (!intel_sdvo_set_target_input(intel_sdvo)) 3106 goto err_output; 3107 3108 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3109 &intel_sdvo->pixel_clock_min, 3110 &intel_sdvo->pixel_clock_max)) 3111 goto err_output; 3112 3113 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 3114 "clock range %dMHz - %dMHz, " 3115 "input 1: %c, input 2: %c, " 3116 "output 1: %c, output 2: %c\n", 3117 SDVO_NAME(intel_sdvo), 3118 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3119 intel_sdvo->caps.device_rev_id, 3120 intel_sdvo->pixel_clock_min / 1000, 3121 intel_sdvo->pixel_clock_max / 1000, 3122 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3123 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3124 /* check currently supported outputs */ 3125 intel_sdvo->caps.output_flags & 3126 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3127 intel_sdvo->caps.output_flags & 3128 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3129 return true; 3130 3131 err_output: 3132 intel_sdvo_output_cleanup(intel_sdvo); 3133 3134 err: 3135 drm_encoder_cleanup(&intel_encoder->base); 3136 err_i2c_bus: 3137 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3138 kfree(intel_sdvo); 3139 3140 return false; 3141 } 3142