1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 #include <linux/delay.h> 31 #include <linux/export.h> 32 #include <drm/drmP.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_edid.h> 36 #include "intel_drv.h" 37 #include <drm/i915_drm.h> 38 #include "i915_drv.h" 39 #include "intel_sdvo_regs.h" 40 41 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 42 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 43 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 44 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 45 46 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 47 SDVO_TV_MASK) 48 49 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 50 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 51 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 52 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 53 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 54 55 56 static const char * const tv_format_names[] = { 57 "NTSC_M" , "NTSC_J" , "NTSC_443", 58 "PAL_B" , "PAL_D" , "PAL_G" , 59 "PAL_H" , "PAL_I" , "PAL_M" , 60 "PAL_N" , "PAL_NC" , "PAL_60" , 61 "SECAM_B" , "SECAM_D" , "SECAM_G" , 62 "SECAM_K" , "SECAM_K1", "SECAM_L" , 63 "SECAM_60" 64 }; 65 66 #define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names) 67 68 struct intel_sdvo { 69 struct intel_encoder base; 70 71 struct i2c_adapter *i2c; 72 u8 slave_addr; 73 74 struct i2c_adapter ddc; 75 76 /* Register for the SDVO device: SDVOB or SDVOC */ 77 i915_reg_t sdvo_reg; 78 79 /* Active outputs controlled by this SDVO output */ 80 uint16_t controlled_output; 81 82 /* 83 * Capabilities of the SDVO device returned by 84 * intel_sdvo_get_capabilities() 85 */ 86 struct intel_sdvo_caps caps; 87 88 /* Pixel clock limitations reported by the SDVO device, in kHz */ 89 int pixel_clock_min, pixel_clock_max; 90 91 /* 92 * For multiple function SDVO device, 93 * this is for current attached outputs. 94 */ 95 uint16_t attached_output; 96 97 /* 98 * Hotplug activation bits for this device 99 */ 100 uint16_t hotplug_active; 101 102 /** 103 * This is used to select the color range of RBG outputs in HDMI mode. 104 * It is only valid when using TMDS encoding and 8 bit per color mode. 105 */ 106 uint32_t color_range; 107 bool color_range_auto; 108 109 /** 110 * HDMI user specified aspect ratio 111 */ 112 enum hdmi_picture_aspect aspect_ratio; 113 114 /** 115 * This is set if we're going to treat the device as TV-out. 116 * 117 * While we have these nice friendly flags for output types that ought 118 * to decide this for us, the S-Video output on our HDMI+S-Video card 119 * shows up as RGB1 (VGA). 120 */ 121 bool is_tv; 122 123 enum port port; 124 125 /* This is for current tv format name */ 126 int tv_format_index; 127 128 /** 129 * This is set if we treat the device as HDMI, instead of DVI. 130 */ 131 bool is_hdmi; 132 bool has_hdmi_monitor; 133 bool has_hdmi_audio; 134 bool rgb_quant_range_selectable; 135 136 /** 137 * This is set if we detect output of sdvo device as LVDS and 138 * have a valid fixed mode to use with the panel. 139 */ 140 bool is_lvds; 141 142 /** 143 * This is sdvo fixed pannel mode pointer 144 */ 145 struct drm_display_mode *sdvo_lvds_fixed_mode; 146 147 /* DDC bus used by this SDVO encoder */ 148 uint8_t ddc_bus; 149 150 /* 151 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 152 */ 153 uint8_t dtd_sdvo_flags; 154 }; 155 156 struct intel_sdvo_connector { 157 struct intel_connector base; 158 159 /* Mark the type of connector */ 160 uint16_t output_flag; 161 162 enum hdmi_force_audio force_audio; 163 164 /* This contains all current supported TV format */ 165 u8 tv_format_supported[TV_FORMAT_NUM]; 166 int format_supported_num; 167 struct drm_property *tv_format; 168 169 /* add the property for the SDVO-TV */ 170 struct drm_property *left; 171 struct drm_property *right; 172 struct drm_property *top; 173 struct drm_property *bottom; 174 struct drm_property *hpos; 175 struct drm_property *vpos; 176 struct drm_property *contrast; 177 struct drm_property *saturation; 178 struct drm_property *hue; 179 struct drm_property *sharpness; 180 struct drm_property *flicker_filter; 181 struct drm_property *flicker_filter_adaptive; 182 struct drm_property *flicker_filter_2d; 183 struct drm_property *tv_chroma_filter; 184 struct drm_property *tv_luma_filter; 185 struct drm_property *dot_crawl; 186 187 /* add the property for the SDVO-TV/LVDS */ 188 struct drm_property *brightness; 189 190 /* Add variable to record current setting for the above property */ 191 u32 left_margin, right_margin, top_margin, bottom_margin; 192 193 /* this is to get the range of margin.*/ 194 u32 max_hscan, max_vscan; 195 u32 max_hpos, cur_hpos; 196 u32 max_vpos, cur_vpos; 197 u32 cur_brightness, max_brightness; 198 u32 cur_contrast, max_contrast; 199 u32 cur_saturation, max_saturation; 200 u32 cur_hue, max_hue; 201 u32 cur_sharpness, max_sharpness; 202 u32 cur_flicker_filter, max_flicker_filter; 203 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 204 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 205 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 206 u32 cur_tv_luma_filter, max_tv_luma_filter; 207 u32 cur_dot_crawl, max_dot_crawl; 208 }; 209 210 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 211 { 212 return container_of(encoder, struct intel_sdvo, base); 213 } 214 215 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 216 { 217 return to_sdvo(intel_attached_encoder(connector)); 218 } 219 220 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 221 { 222 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 223 } 224 225 static bool 226 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 227 static bool 228 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 229 struct intel_sdvo_connector *intel_sdvo_connector, 230 int type); 231 static bool 232 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 233 struct intel_sdvo_connector *intel_sdvo_connector); 234 235 /** 236 * Writes the SDVOB or SDVOC with the given value, but always writes both 237 * SDVOB and SDVOC to work around apparent hardware issues (according to 238 * comments in the BIOS). 239 */ 240 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 241 { 242 struct drm_device *dev = intel_sdvo->base.base.dev; 243 struct drm_i915_private *dev_priv = to_i915(dev); 244 u32 bval = val, cval = val; 245 int i; 246 247 if (HAS_PCH_SPLIT(dev_priv)) { 248 I915_WRITE(intel_sdvo->sdvo_reg, val); 249 POSTING_READ(intel_sdvo->sdvo_reg); 250 /* 251 * HW workaround, need to write this twice for issue 252 * that may result in first write getting masked. 253 */ 254 if (HAS_PCH_IBX(dev_priv)) { 255 I915_WRITE(intel_sdvo->sdvo_reg, val); 256 POSTING_READ(intel_sdvo->sdvo_reg); 257 } 258 return; 259 } 260 261 if (intel_sdvo->port == PORT_B) 262 cval = I915_READ(GEN3_SDVOC); 263 else 264 bval = I915_READ(GEN3_SDVOB); 265 266 /* 267 * Write the registers twice for luck. Sometimes, 268 * writing them only once doesn't appear to 'stick'. 269 * The BIOS does this too. Yay, magic 270 */ 271 for (i = 0; i < 2; i++) 272 { 273 I915_WRITE(GEN3_SDVOB, bval); 274 POSTING_READ(GEN3_SDVOB); 275 I915_WRITE(GEN3_SDVOC, cval); 276 POSTING_READ(GEN3_SDVOC); 277 } 278 } 279 280 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 281 { 282 struct i2c_msg msgs[] = { 283 { 284 .addr = intel_sdvo->slave_addr, 285 .flags = 0, 286 .len = 1, 287 .buf = &addr, 288 }, 289 { 290 .addr = intel_sdvo->slave_addr, 291 .flags = I2C_M_RD, 292 .len = 1, 293 .buf = ch, 294 } 295 }; 296 int ret; 297 298 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) 299 return true; 300 301 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 302 return false; 303 } 304 305 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 306 /** Mapping of command numbers to names, for debug output */ 307 static const struct _sdvo_cmd_name { 308 u8 cmd; 309 const char *name; 310 } __attribute__ ((packed)) sdvo_cmd_names[] = { 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 354 355 /* Add the op code for SDVO enhancements */ 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 400 401 /* HDMI op code */ 402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 412 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 413 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 414 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 415 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 416 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 417 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 418 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 419 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 420 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 421 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 422 }; 423 424 #define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC") 425 426 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 427 const void *args, int args_len) 428 { 429 int i, pos = 0; 430 #define BUF_LEN 256 431 char buffer[BUF_LEN]; 432 433 #define BUF_PRINT(args...) \ 434 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 435 436 437 for (i = 0; i < args_len; i++) { 438 BUF_PRINT("%02X ", ((u8 *)args)[i]); 439 } 440 for (; i < 8; i++) { 441 BUF_PRINT(" "); 442 } 443 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 444 if (cmd == sdvo_cmd_names[i].cmd) { 445 BUF_PRINT("(%s)", sdvo_cmd_names[i].name); 446 break; 447 } 448 } 449 if (i == ARRAY_SIZE(sdvo_cmd_names)) { 450 BUF_PRINT("(%02X)", cmd); 451 } 452 BUG_ON(pos >= BUF_LEN - 1); 453 #undef BUF_PRINT 454 #undef BUF_LEN 455 456 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 457 } 458 459 static const char * const cmd_status_names[] = { 460 "Power on", 461 "Success", 462 "Not supported", 463 "Invalid arg", 464 "Pending", 465 "Target not specified", 466 "Scaling not supported" 467 }; 468 469 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 470 const void *args, int args_len) 471 { 472 u8 *buf, status; 473 struct i2c_msg *msgs; 474 int i, ret = true; 475 476 /* Would be simpler to allocate both in one go ? */ 477 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 478 if (!buf) 479 return false; 480 481 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 482 if (!msgs) { 483 kfree(buf); 484 return false; 485 } 486 487 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 488 489 for (i = 0; i < args_len; i++) { 490 msgs[i].addr = intel_sdvo->slave_addr; 491 msgs[i].flags = 0; 492 msgs[i].len = 2; 493 msgs[i].buf = buf + 2 *i; 494 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 495 buf[2*i + 1] = ((u8*)args)[i]; 496 } 497 msgs[i].addr = intel_sdvo->slave_addr; 498 msgs[i].flags = 0; 499 msgs[i].len = 2; 500 msgs[i].buf = buf + 2*i; 501 buf[2*i + 0] = SDVO_I2C_OPCODE; 502 buf[2*i + 1] = cmd; 503 504 /* the following two are to read the response */ 505 status = SDVO_I2C_CMD_STATUS; 506 msgs[i+1].addr = intel_sdvo->slave_addr; 507 msgs[i+1].flags = 0; 508 msgs[i+1].len = 1; 509 msgs[i+1].buf = &status; 510 511 msgs[i+2].addr = intel_sdvo->slave_addr; 512 msgs[i+2].flags = I2C_M_RD; 513 msgs[i+2].len = 1; 514 msgs[i+2].buf = &status; 515 516 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); 517 if (ret < 0) { 518 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 519 ret = false; 520 goto out; 521 } 522 if (ret != i+3) { 523 /* failure in I2C transfer */ 524 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 525 ret = false; 526 } 527 528 out: 529 kfree(msgs); 530 kfree(buf); 531 return ret; 532 } 533 534 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 535 void *response, int response_len) 536 { 537 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 538 u8 status; 539 int i, pos = 0; 540 #define BUF_LEN 256 541 char buffer[BUF_LEN]; 542 543 544 /* 545 * The documentation states that all commands will be 546 * processed within 15µs, and that we need only poll 547 * the status byte a maximum of 3 times in order for the 548 * command to be complete. 549 * 550 * Check 5 times in case the hardware failed to read the docs. 551 * 552 * Also beware that the first response by many devices is to 553 * reply PENDING and stall for time. TVs are notorious for 554 * requiring longer than specified to complete their replies. 555 * Originally (in the DDX long ago), the delay was only ever 15ms 556 * with an additional delay of 30ms applied for TVs added later after 557 * many experiments. To accommodate both sets of delays, we do a 558 * sequence of slow checks if the device is falling behind and fails 559 * to reply within 5*15µs. 560 */ 561 if (!intel_sdvo_read_byte(intel_sdvo, 562 SDVO_I2C_CMD_STATUS, 563 &status)) 564 goto log_fail; 565 566 while ((status == SDVO_CMD_STATUS_PENDING || 567 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 568 if (retry < 10) 569 msleep(15); 570 else 571 udelay(15); 572 573 if (!intel_sdvo_read_byte(intel_sdvo, 574 SDVO_I2C_CMD_STATUS, 575 &status)) 576 goto log_fail; 577 } 578 579 #define BUF_PRINT(args...) \ 580 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 581 582 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 583 BUF_PRINT("(%s)", cmd_status_names[status]); 584 else 585 BUF_PRINT("(??? %d)", status); 586 587 if (status != SDVO_CMD_STATUS_SUCCESS) 588 goto log_fail; 589 590 /* Read the command response */ 591 for (i = 0; i < response_len; i++) { 592 if (!intel_sdvo_read_byte(intel_sdvo, 593 SDVO_I2C_RETURN_0 + i, 594 &((u8 *)response)[i])) 595 goto log_fail; 596 BUF_PRINT(" %02X", ((u8 *)response)[i]); 597 } 598 BUG_ON(pos >= BUF_LEN - 1); 599 #undef BUF_PRINT 600 #undef BUF_LEN 601 602 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 603 return true; 604 605 log_fail: 606 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); 607 return false; 608 } 609 610 static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode) 611 { 612 if (adjusted_mode->crtc_clock >= 100000) 613 return 1; 614 else if (adjusted_mode->crtc_clock >= 50000) 615 return 2; 616 else 617 return 4; 618 } 619 620 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 621 u8 ddc_bus) 622 { 623 /* This must be the immediately preceding write before the i2c xfer */ 624 return intel_sdvo_write_cmd(intel_sdvo, 625 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 626 &ddc_bus, 1); 627 } 628 629 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 630 { 631 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 632 return false; 633 634 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 635 } 636 637 static bool 638 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 639 { 640 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 641 return false; 642 643 return intel_sdvo_read_response(intel_sdvo, value, len); 644 } 645 646 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 647 { 648 struct intel_sdvo_set_target_input_args targets = {0}; 649 return intel_sdvo_set_value(intel_sdvo, 650 SDVO_CMD_SET_TARGET_INPUT, 651 &targets, sizeof(targets)); 652 } 653 654 /** 655 * Return whether each input is trained. 656 * 657 * This function is making an assumption about the layout of the response, 658 * which should be checked against the docs. 659 */ 660 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 661 { 662 struct intel_sdvo_get_trained_inputs_response response; 663 664 BUILD_BUG_ON(sizeof(response) != 1); 665 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 666 &response, sizeof(response))) 667 return false; 668 669 *input_1 = response.input0_trained; 670 *input_2 = response.input1_trained; 671 return true; 672 } 673 674 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 675 u16 outputs) 676 { 677 return intel_sdvo_set_value(intel_sdvo, 678 SDVO_CMD_SET_ACTIVE_OUTPUTS, 679 &outputs, sizeof(outputs)); 680 } 681 682 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 683 u16 *outputs) 684 { 685 return intel_sdvo_get_value(intel_sdvo, 686 SDVO_CMD_GET_ACTIVE_OUTPUTS, 687 outputs, sizeof(*outputs)); 688 } 689 690 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 691 int mode) 692 { 693 u8 state = SDVO_ENCODER_STATE_ON; 694 695 switch (mode) { 696 case DRM_MODE_DPMS_ON: 697 state = SDVO_ENCODER_STATE_ON; 698 break; 699 case DRM_MODE_DPMS_STANDBY: 700 state = SDVO_ENCODER_STATE_STANDBY; 701 break; 702 case DRM_MODE_DPMS_SUSPEND: 703 state = SDVO_ENCODER_STATE_SUSPEND; 704 break; 705 case DRM_MODE_DPMS_OFF: 706 state = SDVO_ENCODER_STATE_OFF; 707 break; 708 } 709 710 return intel_sdvo_set_value(intel_sdvo, 711 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 712 } 713 714 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 715 int *clock_min, 716 int *clock_max) 717 { 718 struct intel_sdvo_pixel_clock_range clocks; 719 720 BUILD_BUG_ON(sizeof(clocks) != 4); 721 if (!intel_sdvo_get_value(intel_sdvo, 722 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 723 &clocks, sizeof(clocks))) 724 return false; 725 726 /* Convert the values from units of 10 kHz to kHz. */ 727 *clock_min = clocks.min * 10; 728 *clock_max = clocks.max * 10; 729 return true; 730 } 731 732 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 733 u16 outputs) 734 { 735 return intel_sdvo_set_value(intel_sdvo, 736 SDVO_CMD_SET_TARGET_OUTPUT, 737 &outputs, sizeof(outputs)); 738 } 739 740 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 741 struct intel_sdvo_dtd *dtd) 742 { 743 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 744 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 745 } 746 747 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 748 struct intel_sdvo_dtd *dtd) 749 { 750 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 751 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 752 } 753 754 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 755 struct intel_sdvo_dtd *dtd) 756 { 757 return intel_sdvo_set_timing(intel_sdvo, 758 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 759 } 760 761 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 762 struct intel_sdvo_dtd *dtd) 763 { 764 return intel_sdvo_set_timing(intel_sdvo, 765 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 766 } 767 768 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 769 struct intel_sdvo_dtd *dtd) 770 { 771 return intel_sdvo_get_timing(intel_sdvo, 772 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 773 } 774 775 static bool 776 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 777 uint16_t clock, 778 uint16_t width, 779 uint16_t height) 780 { 781 struct intel_sdvo_preferred_input_timing_args args; 782 783 memset(&args, 0, sizeof(args)); 784 args.clock = clock; 785 args.width = width; 786 args.height = height; 787 args.interlace = 0; 788 789 if (intel_sdvo->is_lvds && 790 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 791 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 792 args.scaled = 1; 793 794 return intel_sdvo_set_value(intel_sdvo, 795 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 796 &args, sizeof(args)); 797 } 798 799 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 800 struct intel_sdvo_dtd *dtd) 801 { 802 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 803 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 804 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 805 &dtd->part1, sizeof(dtd->part1)) && 806 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 807 &dtd->part2, sizeof(dtd->part2)); 808 } 809 810 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 811 { 812 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 813 } 814 815 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 816 const struct drm_display_mode *mode) 817 { 818 uint16_t width, height; 819 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 820 uint16_t h_sync_offset, v_sync_offset; 821 int mode_clock; 822 823 memset(dtd, 0, sizeof(*dtd)); 824 825 width = mode->hdisplay; 826 height = mode->vdisplay; 827 828 /* do some mode translations */ 829 h_blank_len = mode->htotal - mode->hdisplay; 830 h_sync_len = mode->hsync_end - mode->hsync_start; 831 832 v_blank_len = mode->vtotal - mode->vdisplay; 833 v_sync_len = mode->vsync_end - mode->vsync_start; 834 835 h_sync_offset = mode->hsync_start - mode->hdisplay; 836 v_sync_offset = mode->vsync_start - mode->vdisplay; 837 838 mode_clock = mode->clock; 839 mode_clock /= 10; 840 dtd->part1.clock = mode_clock; 841 842 dtd->part1.h_active = width & 0xff; 843 dtd->part1.h_blank = h_blank_len & 0xff; 844 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 845 ((h_blank_len >> 8) & 0xf); 846 dtd->part1.v_active = height & 0xff; 847 dtd->part1.v_blank = v_blank_len & 0xff; 848 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 849 ((v_blank_len >> 8) & 0xf); 850 851 dtd->part2.h_sync_off = h_sync_offset & 0xff; 852 dtd->part2.h_sync_width = h_sync_len & 0xff; 853 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 854 (v_sync_len & 0xf); 855 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 856 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 857 ((v_sync_len & 0x30) >> 4); 858 859 dtd->part2.dtd_flags = 0x18; 860 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 861 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 862 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 863 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 864 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 865 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 866 867 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 868 } 869 870 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 871 const struct intel_sdvo_dtd *dtd) 872 { 873 struct drm_display_mode mode = {}; 874 875 mode.hdisplay = dtd->part1.h_active; 876 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 877 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 878 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 879 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 880 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 881 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 882 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 883 884 mode.vdisplay = dtd->part1.v_active; 885 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 886 mode.vsync_start = mode.vdisplay; 887 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 888 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 889 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 890 mode.vsync_end = mode.vsync_start + 891 (dtd->part2.v_sync_off_width & 0xf); 892 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 893 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 894 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 895 896 mode.clock = dtd->part1.clock * 10; 897 898 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 899 mode.flags |= DRM_MODE_FLAG_INTERLACE; 900 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 901 mode.flags |= DRM_MODE_FLAG_PHSYNC; 902 else 903 mode.flags |= DRM_MODE_FLAG_NHSYNC; 904 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 905 mode.flags |= DRM_MODE_FLAG_PVSYNC; 906 else 907 mode.flags |= DRM_MODE_FLAG_NVSYNC; 908 909 drm_mode_set_crtcinfo(&mode, 0); 910 911 drm_mode_copy(pmode, &mode); 912 } 913 914 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 915 { 916 struct intel_sdvo_encode encode; 917 918 BUILD_BUG_ON(sizeof(encode) != 2); 919 return intel_sdvo_get_value(intel_sdvo, 920 SDVO_CMD_GET_SUPP_ENCODE, 921 &encode, sizeof(encode)); 922 } 923 924 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 925 uint8_t mode) 926 { 927 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 928 } 929 930 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 931 uint8_t mode) 932 { 933 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 934 } 935 936 #if 0 937 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 938 { 939 int i, j; 940 uint8_t set_buf_index[2]; 941 uint8_t av_split; 942 uint8_t buf_size; 943 uint8_t buf[48]; 944 uint8_t *pos; 945 946 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 947 948 for (i = 0; i <= av_split; i++) { 949 set_buf_index[0] = i; set_buf_index[1] = 0; 950 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 951 set_buf_index, 2); 952 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 953 intel_sdvo_read_response(encoder, &buf_size, 1); 954 955 pos = buf; 956 for (j = 0; j <= buf_size; j += 8) { 957 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 958 NULL, 0); 959 intel_sdvo_read_response(encoder, pos, 8); 960 pos += 8; 961 } 962 } 963 } 964 #endif 965 966 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 967 unsigned if_index, uint8_t tx_rate, 968 const uint8_t *data, unsigned length) 969 { 970 uint8_t set_buf_index[2] = { if_index, 0 }; 971 uint8_t hbuf_size, tmp[8]; 972 int i; 973 974 if (!intel_sdvo_set_value(intel_sdvo, 975 SDVO_CMD_SET_HBUF_INDEX, 976 set_buf_index, 2)) 977 return false; 978 979 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 980 &hbuf_size, 1)) 981 return false; 982 983 /* Buffer size is 0 based, hooray! */ 984 hbuf_size++; 985 986 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", 987 if_index, length, hbuf_size); 988 989 for (i = 0; i < hbuf_size; i += 8) { 990 memset(tmp, 0, 8); 991 if (i < length) 992 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 993 994 if (!intel_sdvo_set_value(intel_sdvo, 995 SDVO_CMD_SET_HBUF_DATA, 996 tmp, 8)) 997 return false; 998 } 999 1000 return intel_sdvo_set_value(intel_sdvo, 1001 SDVO_CMD_SET_HBUF_TXRATE, 1002 &tx_rate, 1); 1003 } 1004 1005 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1006 struct intel_crtc_state *pipe_config) 1007 { 1008 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1009 union hdmi_infoframe frame; 1010 int ret; 1011 ssize_t len; 1012 1013 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 1014 &pipe_config->base.adjusted_mode); 1015 if (ret < 0) { 1016 DRM_ERROR("couldn't fill AVI infoframe\n"); 1017 return false; 1018 } 1019 1020 if (intel_sdvo->rgb_quant_range_selectable) { 1021 if (pipe_config->limited_color_range) 1022 frame.avi.quantization_range = 1023 HDMI_QUANTIZATION_RANGE_LIMITED; 1024 else 1025 frame.avi.quantization_range = 1026 HDMI_QUANTIZATION_RANGE_FULL; 1027 } 1028 1029 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); 1030 if (len < 0) 1031 return false; 1032 1033 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1034 SDVO_HBUF_TX_VSYNC, 1035 sdvo_data, sizeof(sdvo_data)); 1036 } 1037 1038 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 1039 { 1040 struct intel_sdvo_tv_format format; 1041 uint32_t format_map; 1042 1043 format_map = 1 << intel_sdvo->tv_format_index; 1044 memset(&format, 0, sizeof(format)); 1045 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1046 1047 BUILD_BUG_ON(sizeof(format) != 6); 1048 return intel_sdvo_set_value(intel_sdvo, 1049 SDVO_CMD_SET_TV_FORMAT, 1050 &format, sizeof(format)); 1051 } 1052 1053 static bool 1054 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1055 const struct drm_display_mode *mode) 1056 { 1057 struct intel_sdvo_dtd output_dtd; 1058 1059 if (!intel_sdvo_set_target_output(intel_sdvo, 1060 intel_sdvo->attached_output)) 1061 return false; 1062 1063 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1064 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1065 return false; 1066 1067 return true; 1068 } 1069 1070 /* Asks the sdvo controller for the preferred input mode given the output mode. 1071 * Unfortunately we have to set up the full output mode to do that. */ 1072 static bool 1073 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1074 const struct drm_display_mode *mode, 1075 struct drm_display_mode *adjusted_mode) 1076 { 1077 struct intel_sdvo_dtd input_dtd; 1078 1079 /* Reset the input timing to the screen. Assume always input 0. */ 1080 if (!intel_sdvo_set_target_input(intel_sdvo)) 1081 return false; 1082 1083 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1084 mode->clock / 10, 1085 mode->hdisplay, 1086 mode->vdisplay)) 1087 return false; 1088 1089 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1090 &input_dtd)) 1091 return false; 1092 1093 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1094 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1095 1096 return true; 1097 } 1098 1099 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1100 { 1101 unsigned dotclock = pipe_config->port_clock; 1102 struct dpll *clock = &pipe_config->dpll; 1103 1104 /* SDVO TV has fixed PLL values depend on its clock range, 1105 this mirrors vbios setting. */ 1106 if (dotclock >= 100000 && dotclock < 140500) { 1107 clock->p1 = 2; 1108 clock->p2 = 10; 1109 clock->n = 3; 1110 clock->m1 = 16; 1111 clock->m2 = 8; 1112 } else if (dotclock >= 140500 && dotclock <= 200000) { 1113 clock->p1 = 1; 1114 clock->p2 = 10; 1115 clock->n = 6; 1116 clock->m1 = 12; 1117 clock->m2 = 8; 1118 } else { 1119 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1120 } 1121 1122 pipe_config->clock_set = true; 1123 } 1124 1125 static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 1126 struct intel_crtc_state *pipe_config, 1127 struct drm_connector_state *conn_state) 1128 { 1129 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1130 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1131 struct drm_display_mode *mode = &pipe_config->base.mode; 1132 1133 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1134 pipe_config->pipe_bpp = 8*3; 1135 1136 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) 1137 pipe_config->has_pch_encoder = true; 1138 1139 /* We need to construct preferred input timings based on our 1140 * output timings. To do that, we have to set the output 1141 * timings, even though this isn't really the right place in 1142 * the sequence to do it. Oh well. 1143 */ 1144 if (intel_sdvo->is_tv) { 1145 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1146 return false; 1147 1148 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1149 mode, 1150 adjusted_mode); 1151 pipe_config->sdvo_tv_clock = true; 1152 } else if (intel_sdvo->is_lvds) { 1153 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1154 intel_sdvo->sdvo_lvds_fixed_mode)) 1155 return false; 1156 1157 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1158 mode, 1159 adjusted_mode); 1160 } 1161 1162 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1163 * SDVO device will factor out the multiplier during mode_set. 1164 */ 1165 pipe_config->pixel_multiplier = 1166 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1167 1168 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; 1169 1170 if (intel_sdvo->color_range_auto) { 1171 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1172 /* FIXME: This bit is only valid when using TMDS encoding and 8 1173 * bit per color mode. */ 1174 if (pipe_config->has_hdmi_sink && 1175 drm_match_cea_mode(adjusted_mode) > 1) 1176 pipe_config->limited_color_range = true; 1177 } else { 1178 if (pipe_config->has_hdmi_sink && 1179 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) 1180 pipe_config->limited_color_range = true; 1181 } 1182 1183 /* Clock computation needs to happen after pixel multiplier. */ 1184 if (intel_sdvo->is_tv) 1185 i9xx_adjust_sdvo_tv_clock(pipe_config); 1186 1187 /* Set user selected PAR to incoming mode's member */ 1188 if (intel_sdvo->is_hdmi) 1189 adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio; 1190 1191 return true; 1192 } 1193 1194 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, 1195 struct intel_crtc_state *crtc_state, 1196 struct drm_connector_state *conn_state) 1197 { 1198 struct drm_device *dev = intel_encoder->base.dev; 1199 struct drm_i915_private *dev_priv = to_i915(dev); 1200 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 1201 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; 1202 struct drm_display_mode *mode = &crtc_state->base.mode; 1203 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1204 u32 sdvox; 1205 struct intel_sdvo_in_out_map in_out; 1206 struct intel_sdvo_dtd input_dtd, output_dtd; 1207 int rate; 1208 1209 /* First, set the input mapping for the first input to our controlled 1210 * output. This is only correct if we're a single-input device, in 1211 * which case the first input is the output from the appropriate SDVO 1212 * channel on the motherboard. In a two-input device, the first input 1213 * will be SDVOB and the second SDVOC. 1214 */ 1215 in_out.in0 = intel_sdvo->attached_output; 1216 in_out.in1 = 0; 1217 1218 intel_sdvo_set_value(intel_sdvo, 1219 SDVO_CMD_SET_IN_OUT_MAP, 1220 &in_out, sizeof(in_out)); 1221 1222 /* Set the output timings to the screen */ 1223 if (!intel_sdvo_set_target_output(intel_sdvo, 1224 intel_sdvo->attached_output)) 1225 return; 1226 1227 /* lvds has a special fixed output timing. */ 1228 if (intel_sdvo->is_lvds) 1229 intel_sdvo_get_dtd_from_mode(&output_dtd, 1230 intel_sdvo->sdvo_lvds_fixed_mode); 1231 else 1232 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1233 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1234 DRM_INFO("Setting output timings on %s failed\n", 1235 SDVO_NAME(intel_sdvo)); 1236 1237 /* Set the input timing to the screen. Assume always input 0. */ 1238 if (!intel_sdvo_set_target_input(intel_sdvo)) 1239 return; 1240 1241 if (crtc_state->has_hdmi_sink) { 1242 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1243 intel_sdvo_set_colorimetry(intel_sdvo, 1244 SDVO_COLORIMETRY_RGB256); 1245 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state); 1246 } else 1247 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1248 1249 if (intel_sdvo->is_tv && 1250 !intel_sdvo_set_tv_format(intel_sdvo)) 1251 return; 1252 1253 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1254 1255 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) 1256 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1257 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1258 DRM_INFO("Setting input timings on %s failed\n", 1259 SDVO_NAME(intel_sdvo)); 1260 1261 switch (crtc_state->pixel_multiplier) { 1262 default: 1263 WARN(1, "unknown pixel multiplier specified\n"); 1264 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1265 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1266 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1267 } 1268 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1269 return; 1270 1271 /* Set the SDVO control regs. */ 1272 if (INTEL_INFO(dev)->gen >= 4) { 1273 /* The real mode polarity is set by the SDVO commands, using 1274 * struct intel_sdvo_dtd. */ 1275 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1276 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 1277 sdvox |= HDMI_COLOR_RANGE_16_235; 1278 if (INTEL_INFO(dev)->gen < 5) 1279 sdvox |= SDVO_BORDER_ENABLE; 1280 } else { 1281 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1282 if (intel_sdvo->port == PORT_B) 1283 sdvox &= SDVOB_PRESERVE_MASK; 1284 else 1285 sdvox &= SDVOC_PRESERVE_MASK; 1286 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1287 } 1288 1289 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CPT) 1290 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1291 else 1292 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1293 1294 if (intel_sdvo->has_hdmi_audio) 1295 sdvox |= SDVO_AUDIO_ENABLE; 1296 1297 if (INTEL_INFO(dev)->gen >= 4) { 1298 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1299 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 1300 IS_G33(dev_priv)) { 1301 /* done in crtc_mode_set as it lives inside the dpll register */ 1302 } else { 1303 sdvox |= (crtc_state->pixel_multiplier - 1) 1304 << SDVO_PORT_MULTIPLY_SHIFT; 1305 } 1306 1307 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1308 INTEL_INFO(dev)->gen < 5) 1309 sdvox |= SDVO_STALL_SELECT; 1310 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1311 } 1312 1313 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1314 { 1315 struct intel_sdvo_connector *intel_sdvo_connector = 1316 to_intel_sdvo_connector(&connector->base); 1317 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1318 u16 active_outputs = 0; 1319 1320 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1321 1322 if (active_outputs & intel_sdvo_connector->output_flag) 1323 return true; 1324 else 1325 return false; 1326 } 1327 1328 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1329 enum i915_pipe *pipe) 1330 { 1331 struct drm_device *dev = encoder->base.dev; 1332 struct drm_i915_private *dev_priv = to_i915(dev); 1333 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1334 u16 active_outputs = 0; 1335 u32 tmp; 1336 1337 tmp = I915_READ(intel_sdvo->sdvo_reg); 1338 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1339 1340 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) 1341 return false; 1342 1343 if (HAS_PCH_CPT(dev_priv)) 1344 *pipe = PORT_TO_PIPE_CPT(tmp); 1345 else 1346 *pipe = PORT_TO_PIPE(tmp); 1347 1348 return true; 1349 } 1350 1351 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1352 struct intel_crtc_state *pipe_config) 1353 { 1354 struct drm_device *dev = encoder->base.dev; 1355 struct drm_i915_private *dev_priv = to_i915(dev); 1356 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1357 struct intel_sdvo_dtd dtd; 1358 int encoder_pixel_multiplier = 0; 1359 int dotclock; 1360 u32 flags = 0, sdvox; 1361 u8 val; 1362 bool ret; 1363 1364 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1365 1366 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1367 if (!ret) { 1368 /* Some sdvo encoders are not spec compliant and don't 1369 * implement the mandatory get_timings function. */ 1370 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1371 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1372 } else { 1373 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1374 flags |= DRM_MODE_FLAG_PHSYNC; 1375 else 1376 flags |= DRM_MODE_FLAG_NHSYNC; 1377 1378 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1379 flags |= DRM_MODE_FLAG_PVSYNC; 1380 else 1381 flags |= DRM_MODE_FLAG_NVSYNC; 1382 } 1383 1384 pipe_config->base.adjusted_mode.flags |= flags; 1385 1386 /* 1387 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1388 * the sdvo port register, on all other platforms it is part of the dpll 1389 * state. Since the general pipe state readout happens before the 1390 * encoder->get_config we so already have a valid pixel multplier on all 1391 * other platfroms. 1392 */ 1393 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { 1394 pipe_config->pixel_multiplier = 1395 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1396 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1397 } 1398 1399 dotclock = pipe_config->port_clock; 1400 1401 if (pipe_config->pixel_multiplier) 1402 dotclock /= pipe_config->pixel_multiplier; 1403 1404 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1405 1406 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1407 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1408 &val, 1)) { 1409 switch (val) { 1410 case SDVO_CLOCK_RATE_MULT_1X: 1411 encoder_pixel_multiplier = 1; 1412 break; 1413 case SDVO_CLOCK_RATE_MULT_2X: 1414 encoder_pixel_multiplier = 2; 1415 break; 1416 case SDVO_CLOCK_RATE_MULT_4X: 1417 encoder_pixel_multiplier = 4; 1418 break; 1419 } 1420 } 1421 1422 if (sdvox & HDMI_COLOR_RANGE_16_235) 1423 pipe_config->limited_color_range = true; 1424 1425 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1426 &val, 1)) { 1427 if (val == SDVO_ENCODE_HDMI) 1428 pipe_config->has_hdmi_sink = true; 1429 } 1430 1431 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1432 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1433 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1434 } 1435 1436 static void intel_disable_sdvo(struct intel_encoder *encoder, 1437 struct intel_crtc_state *old_crtc_state, 1438 struct drm_connector_state *conn_state) 1439 { 1440 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1441 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1442 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1443 u32 temp; 1444 1445 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1446 if (0) 1447 intel_sdvo_set_encoder_power_state(intel_sdvo, 1448 DRM_MODE_DPMS_OFF); 1449 1450 temp = I915_READ(intel_sdvo->sdvo_reg); 1451 1452 temp &= ~SDVO_ENABLE; 1453 intel_sdvo_write_sdvox(intel_sdvo, temp); 1454 1455 /* 1456 * HW workaround for IBX, we need to move the port 1457 * to transcoder A after disabling it to allow the 1458 * matching DP port to be enabled on transcoder A. 1459 */ 1460 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1461 /* 1462 * We get CPU/PCH FIFO underruns on the other pipe when 1463 * doing the workaround. Sweep them under the rug. 1464 */ 1465 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1466 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 1467 1468 temp &= ~SDVO_PIPE_B_SELECT; 1469 temp |= SDVO_ENABLE; 1470 intel_sdvo_write_sdvox(intel_sdvo, temp); 1471 1472 temp &= ~SDVO_ENABLE; 1473 intel_sdvo_write_sdvox(intel_sdvo, temp); 1474 1475 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); 1476 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1477 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 1478 } 1479 } 1480 1481 static void pch_disable_sdvo(struct intel_encoder *encoder, 1482 struct intel_crtc_state *old_crtc_state, 1483 struct drm_connector_state *old_conn_state) 1484 { 1485 } 1486 1487 static void pch_post_disable_sdvo(struct intel_encoder *encoder, 1488 struct intel_crtc_state *old_crtc_state, 1489 struct drm_connector_state *old_conn_state) 1490 { 1491 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state); 1492 } 1493 1494 static void intel_enable_sdvo(struct intel_encoder *encoder, 1495 struct intel_crtc_state *pipe_config, 1496 struct drm_connector_state *conn_state) 1497 { 1498 struct drm_device *dev = encoder->base.dev; 1499 struct drm_i915_private *dev_priv = to_i915(dev); 1500 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1501 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1502 u32 temp; 1503 bool input1, input2; 1504 int i; 1505 bool success; 1506 1507 temp = I915_READ(intel_sdvo->sdvo_reg); 1508 temp |= SDVO_ENABLE; 1509 intel_sdvo_write_sdvox(intel_sdvo, temp); 1510 1511 for (i = 0; i < 2; i++) 1512 intel_wait_for_vblank(dev, intel_crtc->pipe); 1513 1514 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1515 /* Warn if the device reported failure to sync. 1516 * A lot of SDVO devices fail to notify of sync, but it's 1517 * a given it the status is a success, we succeeded. 1518 */ 1519 if (success && !input1) { 1520 DRM_DEBUG_KMS("First %s output reported failure to " 1521 "sync\n", SDVO_NAME(intel_sdvo)); 1522 } 1523 1524 if (0) 1525 intel_sdvo_set_encoder_power_state(intel_sdvo, 1526 DRM_MODE_DPMS_ON); 1527 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1528 } 1529 1530 static enum drm_mode_status 1531 intel_sdvo_mode_valid(struct drm_connector *connector, 1532 struct drm_display_mode *mode) 1533 { 1534 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1535 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1536 1537 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1538 return MODE_NO_DBLESCAN; 1539 1540 if (intel_sdvo->pixel_clock_min > mode->clock) 1541 return MODE_CLOCK_LOW; 1542 1543 if (intel_sdvo->pixel_clock_max < mode->clock) 1544 return MODE_CLOCK_HIGH; 1545 1546 if (mode->clock > max_dotclk) 1547 return MODE_CLOCK_HIGH; 1548 1549 if (intel_sdvo->is_lvds) { 1550 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1551 return MODE_PANEL; 1552 1553 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1554 return MODE_PANEL; 1555 } 1556 1557 return MODE_OK; 1558 } 1559 1560 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1561 { 1562 BUILD_BUG_ON(sizeof(*caps) != 8); 1563 if (!intel_sdvo_get_value(intel_sdvo, 1564 SDVO_CMD_GET_DEVICE_CAPS, 1565 caps, sizeof(*caps))) 1566 return false; 1567 1568 DRM_DEBUG_KMS("SDVO capabilities:\n" 1569 " vendor_id: %d\n" 1570 " device_id: %d\n" 1571 " device_rev_id: %d\n" 1572 " sdvo_version_major: %d\n" 1573 " sdvo_version_minor: %d\n" 1574 " sdvo_inputs_mask: %d\n" 1575 " smooth_scaling: %d\n" 1576 " sharp_scaling: %d\n" 1577 " up_scaling: %d\n" 1578 " down_scaling: %d\n" 1579 " stall_support: %d\n" 1580 " output_flags: %d\n", 1581 caps->vendor_id, 1582 caps->device_id, 1583 caps->device_rev_id, 1584 caps->sdvo_version_major, 1585 caps->sdvo_version_minor, 1586 caps->sdvo_inputs_mask, 1587 caps->smooth_scaling, 1588 caps->sharp_scaling, 1589 caps->up_scaling, 1590 caps->down_scaling, 1591 caps->stall_support, 1592 caps->output_flags); 1593 1594 return true; 1595 } 1596 1597 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1598 { 1599 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev); 1600 uint16_t hotplug; 1601 1602 if (!I915_HAS_HOTPLUG(dev_priv)) 1603 return 0; 1604 1605 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1606 * on the line. */ 1607 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) 1608 return 0; 1609 1610 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1611 &hotplug, sizeof(hotplug))) 1612 return 0; 1613 1614 return hotplug; 1615 } 1616 1617 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1618 { 1619 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1620 1621 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1622 &intel_sdvo->hotplug_active, 2); 1623 } 1624 1625 static bool 1626 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1627 { 1628 /* Is there more than one type of output? */ 1629 return hweight16(intel_sdvo->caps.output_flags) > 1; 1630 } 1631 1632 static struct edid * 1633 intel_sdvo_get_edid(struct drm_connector *connector) 1634 { 1635 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 1636 return drm_get_edid(connector, &sdvo->ddc); 1637 } 1638 1639 /* Mac mini hack -- use the same DDC as the analog connector */ 1640 static struct edid * 1641 intel_sdvo_get_analog_edid(struct drm_connector *connector) 1642 { 1643 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1644 1645 return drm_get_edid(connector, 1646 intel_gmbus_get_adapter(dev_priv, 1647 dev_priv->vbt.crt_ddc_pin)); 1648 } 1649 1650 static enum drm_connector_status 1651 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1652 { 1653 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1654 enum drm_connector_status status; 1655 struct edid *edid; 1656 1657 edid = intel_sdvo_get_edid(connector); 1658 1659 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1660 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1661 1662 /* 1663 * Don't use the 1 as the argument of DDC bus switch to get 1664 * the EDID. It is used for SDVO SPD ROM. 1665 */ 1666 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1667 intel_sdvo->ddc_bus = ddc; 1668 edid = intel_sdvo_get_edid(connector); 1669 if (edid) 1670 break; 1671 } 1672 /* 1673 * If we found the EDID on the other bus, 1674 * assume that is the correct DDC bus. 1675 */ 1676 if (edid == NULL) 1677 intel_sdvo->ddc_bus = saved_ddc; 1678 } 1679 1680 /* 1681 * When there is no edid and no monitor is connected with VGA 1682 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1683 */ 1684 if (edid == NULL) 1685 edid = intel_sdvo_get_analog_edid(connector); 1686 1687 status = connector_status_unknown; 1688 if (edid != NULL) { 1689 /* DDC bus is shared, match EDID to connector type */ 1690 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1691 status = connector_status_connected; 1692 if (intel_sdvo->is_hdmi) { 1693 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1694 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1695 intel_sdvo->rgb_quant_range_selectable = 1696 drm_rgb_quant_range_selectable(edid); 1697 } 1698 } else 1699 status = connector_status_disconnected; 1700 kfree(edid); 1701 } 1702 1703 if (status == connector_status_connected) { 1704 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1705 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) 1706 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); 1707 } 1708 1709 return status; 1710 } 1711 1712 static bool 1713 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 1714 struct edid *edid) 1715 { 1716 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1717 bool connector_is_digital = !!IS_DIGITAL(sdvo); 1718 1719 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 1720 connector_is_digital, monitor_is_digital); 1721 return connector_is_digital == monitor_is_digital; 1722 } 1723 1724 static enum drm_connector_status 1725 intel_sdvo_detect(struct drm_connector *connector, bool force) 1726 { 1727 uint16_t response; 1728 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1729 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1730 enum drm_connector_status ret; 1731 1732 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1733 connector->base.id, connector->name); 1734 1735 if (!intel_sdvo_get_value(intel_sdvo, 1736 SDVO_CMD_GET_ATTACHED_DISPLAYS, 1737 &response, 2)) 1738 return connector_status_unknown; 1739 1740 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1741 response & 0xff, response >> 8, 1742 intel_sdvo_connector->output_flag); 1743 1744 if (response == 0) 1745 return connector_status_disconnected; 1746 1747 intel_sdvo->attached_output = response; 1748 1749 intel_sdvo->has_hdmi_monitor = false; 1750 intel_sdvo->has_hdmi_audio = false; 1751 intel_sdvo->rgb_quant_range_selectable = false; 1752 1753 if ((intel_sdvo_connector->output_flag & response) == 0) 1754 ret = connector_status_disconnected; 1755 else if (IS_TMDS(intel_sdvo_connector)) 1756 ret = intel_sdvo_tmds_sink_detect(connector); 1757 else { 1758 struct edid *edid; 1759 1760 /* if we have an edid check it matches the connection */ 1761 edid = intel_sdvo_get_edid(connector); 1762 if (edid == NULL) 1763 edid = intel_sdvo_get_analog_edid(connector); 1764 if (edid != NULL) { 1765 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 1766 edid)) 1767 ret = connector_status_connected; 1768 else 1769 ret = connector_status_disconnected; 1770 1771 kfree(edid); 1772 } else 1773 ret = connector_status_connected; 1774 } 1775 1776 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1777 if (ret == connector_status_connected) { 1778 intel_sdvo->is_tv = false; 1779 intel_sdvo->is_lvds = false; 1780 1781 if (response & SDVO_TV_MASK) 1782 intel_sdvo->is_tv = true; 1783 if (response & SDVO_LVDS_MASK) 1784 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1785 } 1786 1787 return ret; 1788 } 1789 1790 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1791 { 1792 struct edid *edid; 1793 1794 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1795 connector->base.id, connector->name); 1796 1797 /* set the bus switch and get the modes */ 1798 edid = intel_sdvo_get_edid(connector); 1799 1800 /* 1801 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1802 * link between analog and digital outputs. So, if the regular SDVO 1803 * DDC fails, check to see if the analog output is disconnected, in 1804 * which case we'll look there for the digital DDC data. 1805 */ 1806 if (edid == NULL) 1807 edid = intel_sdvo_get_analog_edid(connector); 1808 1809 if (edid != NULL) { 1810 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 1811 edid)) { 1812 drm_mode_connector_update_edid_property(connector, edid); 1813 drm_add_edid_modes(connector, edid); 1814 } 1815 1816 kfree(edid); 1817 } 1818 } 1819 1820 /* 1821 * Set of SDVO TV modes. 1822 * Note! This is in reply order (see loop in get_tv_modes). 1823 * XXX: all 60Hz refresh? 1824 */ 1825 static const struct drm_display_mode sdvo_tv_modes[] = { 1826 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1827 416, 0, 200, 201, 232, 233, 0, 1828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1829 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1830 416, 0, 240, 241, 272, 273, 0, 1831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1832 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1833 496, 0, 300, 301, 332, 333, 0, 1834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1835 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1836 736, 0, 350, 351, 382, 383, 0, 1837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1838 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1839 736, 0, 400, 401, 432, 433, 0, 1840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1841 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1842 736, 0, 480, 481, 512, 513, 0, 1843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1844 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1845 800, 0, 480, 481, 512, 513, 0, 1846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1847 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1848 800, 0, 576, 577, 608, 609, 0, 1849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1850 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1851 816, 0, 350, 351, 382, 383, 0, 1852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1853 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1854 816, 0, 400, 401, 432, 433, 0, 1855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1856 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1857 816, 0, 480, 481, 512, 513, 0, 1858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1859 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1860 816, 0, 540, 541, 572, 573, 0, 1861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1862 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1863 816, 0, 576, 577, 608, 609, 0, 1864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1865 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1866 864, 0, 576, 577, 608, 609, 0, 1867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1868 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1869 896, 0, 600, 601, 632, 633, 0, 1870 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1871 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1872 928, 0, 624, 625, 656, 657, 0, 1873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1874 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1875 1016, 0, 766, 767, 798, 799, 0, 1876 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1877 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1878 1120, 0, 768, 769, 800, 801, 0, 1879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1880 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1881 1376, 0, 1024, 1025, 1056, 1057, 0, 1882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1883 }; 1884 1885 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1886 { 1887 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1888 struct intel_sdvo_sdtv_resolution_request tv_res; 1889 uint32_t reply = 0, format_map = 0; 1890 int i; 1891 1892 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1893 connector->base.id, connector->name); 1894 1895 /* Read the list of supported input resolutions for the selected TV 1896 * format. 1897 */ 1898 format_map = 1 << intel_sdvo->tv_format_index; 1899 memcpy(&tv_res, &format_map, 1900 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1901 1902 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1903 return; 1904 1905 BUILD_BUG_ON(sizeof(tv_res) != 3); 1906 if (!intel_sdvo_write_cmd(intel_sdvo, 1907 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1908 &tv_res, sizeof(tv_res))) 1909 return; 1910 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1911 return; 1912 1913 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1914 if (reply & (1 << i)) { 1915 struct drm_display_mode *nmode; 1916 nmode = drm_mode_duplicate(connector->dev, 1917 &sdvo_tv_modes[i]); 1918 if (nmode) 1919 drm_mode_probed_add(connector, nmode); 1920 } 1921 } 1922 1923 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1924 { 1925 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1926 struct drm_i915_private *dev_priv = to_i915(connector->dev); 1927 struct drm_display_mode *newmode; 1928 1929 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1930 connector->base.id, connector->name); 1931 1932 /* 1933 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 1934 * SDVO->LVDS transcoders can't cope with the EDID mode. 1935 */ 1936 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 1937 newmode = drm_mode_duplicate(connector->dev, 1938 dev_priv->vbt.sdvo_lvds_vbt_mode); 1939 if (newmode != NULL) { 1940 /* Guarantee the mode is preferred */ 1941 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1942 DRM_MODE_TYPE_DRIVER); 1943 drm_mode_probed_add(connector, newmode); 1944 } 1945 } 1946 1947 /* 1948 * Attempt to get the mode list from DDC. 1949 * Assume that the preferred modes are 1950 * arranged in priority order. 1951 */ 1952 intel_ddc_get_modes(connector, &intel_sdvo->ddc); 1953 1954 list_for_each_entry(newmode, &connector->probed_modes, head) { 1955 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1956 intel_sdvo->sdvo_lvds_fixed_mode = 1957 drm_mode_duplicate(connector->dev, newmode); 1958 1959 intel_sdvo->is_lvds = true; 1960 break; 1961 } 1962 } 1963 } 1964 1965 static int intel_sdvo_get_modes(struct drm_connector *connector) 1966 { 1967 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1968 1969 if (IS_TV(intel_sdvo_connector)) 1970 intel_sdvo_get_tv_modes(connector); 1971 else if (IS_LVDS(intel_sdvo_connector)) 1972 intel_sdvo_get_lvds_modes(connector); 1973 else 1974 intel_sdvo_get_ddc_modes(connector); 1975 1976 return !list_empty(&connector->probed_modes); 1977 } 1978 1979 static void intel_sdvo_destroy(struct drm_connector *connector) 1980 { 1981 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1982 1983 drm_connector_cleanup(connector); 1984 kfree(intel_sdvo_connector); 1985 } 1986 1987 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 1988 { 1989 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1990 struct edid *edid; 1991 bool has_audio = false; 1992 1993 if (!intel_sdvo->is_hdmi) 1994 return false; 1995 1996 edid = intel_sdvo_get_edid(connector); 1997 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 1998 has_audio = drm_detect_monitor_audio(edid); 1999 kfree(edid); 2000 2001 return has_audio; 2002 } 2003 2004 static int 2005 intel_sdvo_set_property(struct drm_connector *connector, 2006 struct drm_property *property, 2007 uint64_t val) 2008 { 2009 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2010 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2011 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2012 uint16_t temp_value; 2013 uint8_t cmd; 2014 int ret; 2015 2016 ret = drm_object_property_set_value(&connector->base, property, val); 2017 if (ret) 2018 return ret; 2019 2020 if (property == dev_priv->force_audio_property) { 2021 int i = val; 2022 bool has_audio; 2023 2024 if (i == intel_sdvo_connector->force_audio) 2025 return 0; 2026 2027 intel_sdvo_connector->force_audio = i; 2028 2029 if (i == HDMI_AUDIO_AUTO) 2030 has_audio = intel_sdvo_detect_hdmi_audio(connector); 2031 else 2032 has_audio = (i == HDMI_AUDIO_ON); 2033 2034 if (has_audio == intel_sdvo->has_hdmi_audio) 2035 return 0; 2036 2037 intel_sdvo->has_hdmi_audio = has_audio; 2038 goto done; 2039 } 2040 2041 if (property == dev_priv->broadcast_rgb_property) { 2042 bool old_auto = intel_sdvo->color_range_auto; 2043 uint32_t old_range = intel_sdvo->color_range; 2044 2045 switch (val) { 2046 case INTEL_BROADCAST_RGB_AUTO: 2047 intel_sdvo->color_range_auto = true; 2048 break; 2049 case INTEL_BROADCAST_RGB_FULL: 2050 intel_sdvo->color_range_auto = false; 2051 intel_sdvo->color_range = 0; 2052 break; 2053 case INTEL_BROADCAST_RGB_LIMITED: 2054 intel_sdvo->color_range_auto = false; 2055 /* FIXME: this bit is only valid when using TMDS 2056 * encoding and 8 bit per color mode. */ 2057 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; 2058 break; 2059 default: 2060 return -EINVAL; 2061 } 2062 2063 if (old_auto == intel_sdvo->color_range_auto && 2064 old_range == intel_sdvo->color_range) 2065 return 0; 2066 2067 goto done; 2068 } 2069 2070 if (property == connector->dev->mode_config.aspect_ratio_property) { 2071 switch (val) { 2072 case DRM_MODE_PICTURE_ASPECT_NONE: 2073 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2074 break; 2075 case DRM_MODE_PICTURE_ASPECT_4_3: 2076 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; 2077 break; 2078 case DRM_MODE_PICTURE_ASPECT_16_9: 2079 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; 2080 break; 2081 default: 2082 return -EINVAL; 2083 } 2084 goto done; 2085 } 2086 2087 #define CHECK_PROPERTY(name, NAME) \ 2088 if (intel_sdvo_connector->name == property) { \ 2089 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 2090 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 2091 cmd = SDVO_CMD_SET_##NAME; \ 2092 intel_sdvo_connector->cur_##name = temp_value; \ 2093 goto set_value; \ 2094 } 2095 2096 if (property == intel_sdvo_connector->tv_format) { 2097 if (val >= TV_FORMAT_NUM) 2098 return -EINVAL; 2099 2100 if (intel_sdvo->tv_format_index == 2101 intel_sdvo_connector->tv_format_supported[val]) 2102 return 0; 2103 2104 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 2105 goto done; 2106 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 2107 temp_value = val; 2108 if (intel_sdvo_connector->left == property) { 2109 drm_object_property_set_value(&connector->base, 2110 intel_sdvo_connector->right, val); 2111 if (intel_sdvo_connector->left_margin == temp_value) 2112 return 0; 2113 2114 intel_sdvo_connector->left_margin = temp_value; 2115 intel_sdvo_connector->right_margin = temp_value; 2116 temp_value = intel_sdvo_connector->max_hscan - 2117 intel_sdvo_connector->left_margin; 2118 cmd = SDVO_CMD_SET_OVERSCAN_H; 2119 goto set_value; 2120 } else if (intel_sdvo_connector->right == property) { 2121 drm_object_property_set_value(&connector->base, 2122 intel_sdvo_connector->left, val); 2123 if (intel_sdvo_connector->right_margin == temp_value) 2124 return 0; 2125 2126 intel_sdvo_connector->left_margin = temp_value; 2127 intel_sdvo_connector->right_margin = temp_value; 2128 temp_value = intel_sdvo_connector->max_hscan - 2129 intel_sdvo_connector->left_margin; 2130 cmd = SDVO_CMD_SET_OVERSCAN_H; 2131 goto set_value; 2132 } else if (intel_sdvo_connector->top == property) { 2133 drm_object_property_set_value(&connector->base, 2134 intel_sdvo_connector->bottom, val); 2135 if (intel_sdvo_connector->top_margin == temp_value) 2136 return 0; 2137 2138 intel_sdvo_connector->top_margin = temp_value; 2139 intel_sdvo_connector->bottom_margin = temp_value; 2140 temp_value = intel_sdvo_connector->max_vscan - 2141 intel_sdvo_connector->top_margin; 2142 cmd = SDVO_CMD_SET_OVERSCAN_V; 2143 goto set_value; 2144 } else if (intel_sdvo_connector->bottom == property) { 2145 drm_object_property_set_value(&connector->base, 2146 intel_sdvo_connector->top, val); 2147 if (intel_sdvo_connector->bottom_margin == temp_value) 2148 return 0; 2149 2150 intel_sdvo_connector->top_margin = temp_value; 2151 intel_sdvo_connector->bottom_margin = temp_value; 2152 temp_value = intel_sdvo_connector->max_vscan - 2153 intel_sdvo_connector->top_margin; 2154 cmd = SDVO_CMD_SET_OVERSCAN_V; 2155 goto set_value; 2156 } 2157 CHECK_PROPERTY(hpos, HPOS) 2158 CHECK_PROPERTY(vpos, VPOS) 2159 CHECK_PROPERTY(saturation, SATURATION) 2160 CHECK_PROPERTY(contrast, CONTRAST) 2161 CHECK_PROPERTY(hue, HUE) 2162 CHECK_PROPERTY(brightness, BRIGHTNESS) 2163 CHECK_PROPERTY(sharpness, SHARPNESS) 2164 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 2165 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 2166 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 2167 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 2168 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 2169 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 2170 } 2171 2172 return -EINVAL; /* unknown property */ 2173 2174 set_value: 2175 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 2176 return -EIO; 2177 2178 2179 done: 2180 if (intel_sdvo->base.base.crtc) 2181 intel_crtc_restore_mode(intel_sdvo->base.base.crtc); 2182 2183 return 0; 2184 #undef CHECK_PROPERTY 2185 } 2186 2187 static int 2188 intel_sdvo_connector_register(struct drm_connector *connector) 2189 { 2190 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 2191 int ret; 2192 2193 ret = intel_connector_register(connector); 2194 if (ret) 2195 return ret; 2196 2197 return sysfs_create_link(&connector->kdev->kobj, 2198 &sdvo->ddc.dev.kobj, 2199 sdvo->ddc.dev.kobj.name); 2200 } 2201 2202 static void 2203 intel_sdvo_connector_unregister(struct drm_connector *connector) 2204 { 2205 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 2206 2207 sysfs_remove_link(&connector->kdev->kobj, 2208 sdvo->ddc.dev.kobj.name); 2209 intel_connector_unregister(connector); 2210 } 2211 2212 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2213 .dpms = drm_atomic_helper_connector_dpms, 2214 .detect = intel_sdvo_detect, 2215 .fill_modes = drm_helper_probe_single_connector_modes, 2216 .set_property = intel_sdvo_set_property, 2217 .atomic_get_property = intel_connector_atomic_get_property, 2218 .late_register = intel_sdvo_connector_register, 2219 .early_unregister = intel_sdvo_connector_unregister, 2220 .destroy = intel_sdvo_destroy, 2221 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2222 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2223 }; 2224 2225 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2226 .get_modes = intel_sdvo_get_modes, 2227 .mode_valid = intel_sdvo_mode_valid, 2228 }; 2229 2230 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2231 { 2232 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2233 2234 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 2235 drm_mode_destroy(encoder->dev, 2236 intel_sdvo->sdvo_lvds_fixed_mode); 2237 2238 i2c_del_adapter(&intel_sdvo->ddc); 2239 intel_encoder_destroy(encoder); 2240 } 2241 2242 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2243 .destroy = intel_sdvo_enc_destroy, 2244 }; 2245 2246 static void 2247 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2248 { 2249 uint16_t mask = 0; 2250 unsigned int num_bits; 2251 2252 /* Make a mask of outputs less than or equal to our own priority in the 2253 * list. 2254 */ 2255 switch (sdvo->controlled_output) { 2256 case SDVO_OUTPUT_LVDS1: 2257 mask |= SDVO_OUTPUT_LVDS1; 2258 case SDVO_OUTPUT_LVDS0: 2259 mask |= SDVO_OUTPUT_LVDS0; 2260 case SDVO_OUTPUT_TMDS1: 2261 mask |= SDVO_OUTPUT_TMDS1; 2262 case SDVO_OUTPUT_TMDS0: 2263 mask |= SDVO_OUTPUT_TMDS0; 2264 case SDVO_OUTPUT_RGB1: 2265 mask |= SDVO_OUTPUT_RGB1; 2266 case SDVO_OUTPUT_RGB0: 2267 mask |= SDVO_OUTPUT_RGB0; 2268 break; 2269 } 2270 2271 /* Count bits to find what number we are in the priority list. */ 2272 mask &= sdvo->caps.output_flags; 2273 num_bits = hweight16(mask); 2274 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2275 if (num_bits > 3) 2276 num_bits = 3; 2277 2278 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2279 sdvo->ddc_bus = 1 << num_bits; 2280 } 2281 2282 /** 2283 * Choose the appropriate DDC bus for control bus switch command for this 2284 * SDVO output based on the controlled output. 2285 * 2286 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2287 * outputs, then LVDS outputs. 2288 */ 2289 static void 2290 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2291 struct intel_sdvo *sdvo) 2292 { 2293 struct sdvo_device_mapping *mapping; 2294 2295 if (sdvo->port == PORT_B) 2296 mapping = &dev_priv->vbt.sdvo_mappings[0]; 2297 else 2298 mapping = &dev_priv->vbt.sdvo_mappings[1]; 2299 2300 if (mapping->initialized) 2301 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2302 else 2303 intel_sdvo_guess_ddc_bus(sdvo); 2304 } 2305 2306 static void 2307 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2308 struct intel_sdvo *sdvo) 2309 { 2310 struct sdvo_device_mapping *mapping; 2311 u8 pin; 2312 2313 if (sdvo->port == PORT_B) 2314 mapping = &dev_priv->vbt.sdvo_mappings[0]; 2315 else 2316 mapping = &dev_priv->vbt.sdvo_mappings[1]; 2317 2318 if (mapping->initialized && 2319 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2320 pin = mapping->i2c_pin; 2321 else 2322 pin = GMBUS_PIN_DPB; 2323 2324 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2325 2326 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2327 * our code totally fails once we start using gmbus. Hence fall back to 2328 * bit banging for now. */ 2329 intel_gmbus_force_bit(sdvo->i2c, true); 2330 } 2331 2332 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2333 static void 2334 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2335 { 2336 intel_gmbus_force_bit(sdvo->i2c, false); 2337 } 2338 2339 static bool 2340 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2341 { 2342 return intel_sdvo_check_supp_encode(intel_sdvo); 2343 } 2344 2345 static u8 2346 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) 2347 { 2348 struct drm_i915_private *dev_priv = to_i915(dev); 2349 struct sdvo_device_mapping *my_mapping, *other_mapping; 2350 2351 if (sdvo->port == PORT_B) { 2352 my_mapping = &dev_priv->vbt.sdvo_mappings[0]; 2353 other_mapping = &dev_priv->vbt.sdvo_mappings[1]; 2354 } else { 2355 my_mapping = &dev_priv->vbt.sdvo_mappings[1]; 2356 other_mapping = &dev_priv->vbt.sdvo_mappings[0]; 2357 } 2358 2359 /* If the BIOS described our SDVO device, take advantage of it. */ 2360 if (my_mapping->slave_addr) 2361 return my_mapping->slave_addr; 2362 2363 /* If the BIOS only described a different SDVO device, use the 2364 * address that it isn't using. 2365 */ 2366 if (other_mapping->slave_addr) { 2367 if (other_mapping->slave_addr == 0x70) 2368 return 0x72; 2369 else 2370 return 0x70; 2371 } 2372 2373 /* No SDVO device info is found for another DVO port, 2374 * so use mapping assumption we had before BIOS parsing. 2375 */ 2376 if (sdvo->port == PORT_B) 2377 return 0x70; 2378 else 2379 return 0x72; 2380 } 2381 2382 static int 2383 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2384 struct intel_sdvo *encoder) 2385 { 2386 struct drm_connector *drm_connector; 2387 int ret; 2388 2389 drm_connector = &connector->base.base; 2390 ret = drm_connector_init(encoder->base.base.dev, 2391 drm_connector, 2392 &intel_sdvo_connector_funcs, 2393 connector->base.base.connector_type); 2394 if (ret < 0) 2395 return ret; 2396 2397 drm_connector_helper_add(drm_connector, 2398 &intel_sdvo_connector_helper_funcs); 2399 2400 connector->base.base.interlace_allowed = 1; 2401 connector->base.base.doublescan_allowed = 0; 2402 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2403 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2404 2405 intel_connector_attach_encoder(&connector->base, &encoder->base); 2406 2407 return 0; 2408 } 2409 2410 static void 2411 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2412 struct intel_sdvo_connector *connector) 2413 { 2414 struct drm_device *dev = connector->base.base.dev; 2415 2416 intel_attach_force_audio_property(&connector->base.base); 2417 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { 2418 intel_attach_broadcast_rgb_property(&connector->base.base); 2419 intel_sdvo->color_range_auto = true; 2420 } 2421 intel_attach_aspect_ratio_property(&connector->base.base); 2422 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; 2423 } 2424 2425 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2426 { 2427 struct intel_sdvo_connector *sdvo_connector; 2428 2429 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2430 if (!sdvo_connector) 2431 return NULL; 2432 2433 if (intel_connector_init(&sdvo_connector->base) < 0) { 2434 kfree(sdvo_connector); 2435 return NULL; 2436 } 2437 2438 return sdvo_connector; 2439 } 2440 2441 static bool 2442 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2443 { 2444 struct drm_encoder *encoder = &intel_sdvo->base.base; 2445 struct drm_connector *connector; 2446 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2447 struct intel_connector *intel_connector; 2448 struct intel_sdvo_connector *intel_sdvo_connector; 2449 2450 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2451 2452 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2453 if (!intel_sdvo_connector) 2454 return false; 2455 2456 if (device == 0) { 2457 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2458 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2459 } else if (device == 1) { 2460 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2461 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2462 } 2463 2464 intel_connector = &intel_sdvo_connector->base; 2465 connector = &intel_connector->base; 2466 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2467 intel_sdvo_connector->output_flag) { 2468 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2469 /* Some SDVO devices have one-shot hotplug interrupts. 2470 * Ensure that they get re-enabled when an interrupt happens. 2471 */ 2472 intel_encoder->hot_plug = intel_sdvo_enable_hotplug; 2473 intel_sdvo_enable_hotplug(intel_encoder); 2474 } else { 2475 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2476 } 2477 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2478 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2479 2480 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2481 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2482 intel_sdvo->is_hdmi = true; 2483 } 2484 2485 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2486 kfree(intel_sdvo_connector); 2487 return false; 2488 } 2489 2490 if (intel_sdvo->is_hdmi) 2491 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2492 2493 return true; 2494 } 2495 2496 static bool 2497 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2498 { 2499 struct drm_encoder *encoder = &intel_sdvo->base.base; 2500 struct drm_connector *connector; 2501 struct intel_connector *intel_connector; 2502 struct intel_sdvo_connector *intel_sdvo_connector; 2503 2504 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2505 2506 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2507 if (!intel_sdvo_connector) 2508 return false; 2509 2510 intel_connector = &intel_sdvo_connector->base; 2511 connector = &intel_connector->base; 2512 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2513 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2514 2515 intel_sdvo->controlled_output |= type; 2516 intel_sdvo_connector->output_flag = type; 2517 2518 intel_sdvo->is_tv = true; 2519 2520 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2521 kfree(intel_sdvo_connector); 2522 return false; 2523 } 2524 2525 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2526 goto err; 2527 2528 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2529 goto err; 2530 2531 return true; 2532 2533 err: 2534 intel_sdvo_destroy(connector); 2535 return false; 2536 } 2537 2538 static bool 2539 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2540 { 2541 struct drm_encoder *encoder = &intel_sdvo->base.base; 2542 struct drm_connector *connector; 2543 struct intel_connector *intel_connector; 2544 struct intel_sdvo_connector *intel_sdvo_connector; 2545 2546 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2547 2548 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2549 if (!intel_sdvo_connector) 2550 return false; 2551 2552 intel_connector = &intel_sdvo_connector->base; 2553 connector = &intel_connector->base; 2554 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2555 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2556 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2557 2558 if (device == 0) { 2559 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2560 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2561 } else if (device == 1) { 2562 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2563 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2564 } 2565 2566 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2567 kfree(intel_sdvo_connector); 2568 return false; 2569 } 2570 2571 return true; 2572 } 2573 2574 static bool 2575 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2576 { 2577 struct drm_encoder *encoder = &intel_sdvo->base.base; 2578 struct drm_connector *connector; 2579 struct intel_connector *intel_connector; 2580 struct intel_sdvo_connector *intel_sdvo_connector; 2581 2582 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2583 2584 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2585 if (!intel_sdvo_connector) 2586 return false; 2587 2588 intel_connector = &intel_sdvo_connector->base; 2589 connector = &intel_connector->base; 2590 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2591 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2592 2593 if (device == 0) { 2594 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2595 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2596 } else if (device == 1) { 2597 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2598 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2599 } 2600 2601 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2602 kfree(intel_sdvo_connector); 2603 return false; 2604 } 2605 2606 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2607 goto err; 2608 2609 return true; 2610 2611 err: 2612 intel_sdvo_destroy(connector); 2613 return false; 2614 } 2615 2616 static bool 2617 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2618 { 2619 intel_sdvo->is_tv = false; 2620 intel_sdvo->is_lvds = false; 2621 2622 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2623 2624 if (flags & SDVO_OUTPUT_TMDS0) 2625 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2626 return false; 2627 2628 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2629 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2630 return false; 2631 2632 /* TV has no XXX1 function block */ 2633 if (flags & SDVO_OUTPUT_SVID0) 2634 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2635 return false; 2636 2637 if (flags & SDVO_OUTPUT_CVBS0) 2638 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2639 return false; 2640 2641 if (flags & SDVO_OUTPUT_YPRPB0) 2642 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2643 return false; 2644 2645 if (flags & SDVO_OUTPUT_RGB0) 2646 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2647 return false; 2648 2649 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2650 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2651 return false; 2652 2653 if (flags & SDVO_OUTPUT_LVDS0) 2654 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2655 return false; 2656 2657 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2658 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2659 return false; 2660 2661 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2662 unsigned char bytes[2]; 2663 2664 intel_sdvo->controlled_output = 0; 2665 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2666 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2667 SDVO_NAME(intel_sdvo), 2668 bytes[0], bytes[1]); 2669 return false; 2670 } 2671 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2672 2673 return true; 2674 } 2675 2676 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2677 { 2678 struct drm_device *dev = intel_sdvo->base.base.dev; 2679 struct drm_connector *connector, *tmp; 2680 2681 list_for_each_entry_safe(connector, tmp, 2682 &dev->mode_config.connector_list, head) { 2683 if (intel_attached_encoder(connector) == &intel_sdvo->base) { 2684 drm_connector_unregister(connector); 2685 intel_sdvo_destroy(connector); 2686 } 2687 } 2688 } 2689 2690 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2691 struct intel_sdvo_connector *intel_sdvo_connector, 2692 int type) 2693 { 2694 struct drm_device *dev = intel_sdvo->base.base.dev; 2695 struct intel_sdvo_tv_format format; 2696 uint32_t format_map, i; 2697 2698 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2699 return false; 2700 2701 BUILD_BUG_ON(sizeof(format) != 6); 2702 if (!intel_sdvo_get_value(intel_sdvo, 2703 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2704 &format, sizeof(format))) 2705 return false; 2706 2707 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2708 2709 if (format_map == 0) 2710 return false; 2711 2712 intel_sdvo_connector->format_supported_num = 0; 2713 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2714 if (format_map & (1 << i)) 2715 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2716 2717 2718 intel_sdvo_connector->tv_format = 2719 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2720 "mode", intel_sdvo_connector->format_supported_num); 2721 if (!intel_sdvo_connector->tv_format) 2722 return false; 2723 2724 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2725 drm_property_add_enum( 2726 intel_sdvo_connector->tv_format, i, 2727 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2728 2729 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2730 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2731 intel_sdvo_connector->tv_format, 0); 2732 return true; 2733 2734 } 2735 2736 #define ENHANCEMENT(name, NAME) do { \ 2737 if (enhancements.name) { \ 2738 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2739 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2740 return false; \ 2741 intel_sdvo_connector->max_##name = data_value[0]; \ 2742 intel_sdvo_connector->cur_##name = response; \ 2743 intel_sdvo_connector->name = \ 2744 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2745 if (!intel_sdvo_connector->name) return false; \ 2746 drm_object_attach_property(&connector->base, \ 2747 intel_sdvo_connector->name, \ 2748 intel_sdvo_connector->cur_##name); \ 2749 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2750 data_value[0], data_value[1], response); \ 2751 } \ 2752 } while (0) 2753 2754 static bool 2755 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2756 struct intel_sdvo_connector *intel_sdvo_connector, 2757 struct intel_sdvo_enhancements_reply enhancements) 2758 { 2759 struct drm_device *dev = intel_sdvo->base.base.dev; 2760 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2761 uint16_t response, data_value[2]; 2762 2763 /* when horizontal overscan is supported, Add the left/right property */ 2764 if (enhancements.overscan_h) { 2765 if (!intel_sdvo_get_value(intel_sdvo, 2766 SDVO_CMD_GET_MAX_OVERSCAN_H, 2767 &data_value, 4)) 2768 return false; 2769 2770 if (!intel_sdvo_get_value(intel_sdvo, 2771 SDVO_CMD_GET_OVERSCAN_H, 2772 &response, 2)) 2773 return false; 2774 2775 intel_sdvo_connector->max_hscan = data_value[0]; 2776 intel_sdvo_connector->left_margin = data_value[0] - response; 2777 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2778 intel_sdvo_connector->left = 2779 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2780 if (!intel_sdvo_connector->left) 2781 return false; 2782 2783 drm_object_attach_property(&connector->base, 2784 intel_sdvo_connector->left, 2785 intel_sdvo_connector->left_margin); 2786 2787 intel_sdvo_connector->right = 2788 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2789 if (!intel_sdvo_connector->right) 2790 return false; 2791 2792 drm_object_attach_property(&connector->base, 2793 intel_sdvo_connector->right, 2794 intel_sdvo_connector->right_margin); 2795 DRM_DEBUG_KMS("h_overscan: max %d, " 2796 "default %d, current %d\n", 2797 data_value[0], data_value[1], response); 2798 } 2799 2800 if (enhancements.overscan_v) { 2801 if (!intel_sdvo_get_value(intel_sdvo, 2802 SDVO_CMD_GET_MAX_OVERSCAN_V, 2803 &data_value, 4)) 2804 return false; 2805 2806 if (!intel_sdvo_get_value(intel_sdvo, 2807 SDVO_CMD_GET_OVERSCAN_V, 2808 &response, 2)) 2809 return false; 2810 2811 intel_sdvo_connector->max_vscan = data_value[0]; 2812 intel_sdvo_connector->top_margin = data_value[0] - response; 2813 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2814 intel_sdvo_connector->top = 2815 drm_property_create_range(dev, 0, 2816 "top_margin", 0, data_value[0]); 2817 if (!intel_sdvo_connector->top) 2818 return false; 2819 2820 drm_object_attach_property(&connector->base, 2821 intel_sdvo_connector->top, 2822 intel_sdvo_connector->top_margin); 2823 2824 intel_sdvo_connector->bottom = 2825 drm_property_create_range(dev, 0, 2826 "bottom_margin", 0, data_value[0]); 2827 if (!intel_sdvo_connector->bottom) 2828 return false; 2829 2830 drm_object_attach_property(&connector->base, 2831 intel_sdvo_connector->bottom, 2832 intel_sdvo_connector->bottom_margin); 2833 DRM_DEBUG_KMS("v_overscan: max %d, " 2834 "default %d, current %d\n", 2835 data_value[0], data_value[1], response); 2836 } 2837 2838 ENHANCEMENT(hpos, HPOS); 2839 ENHANCEMENT(vpos, VPOS); 2840 ENHANCEMENT(saturation, SATURATION); 2841 ENHANCEMENT(contrast, CONTRAST); 2842 ENHANCEMENT(hue, HUE); 2843 ENHANCEMENT(sharpness, SHARPNESS); 2844 ENHANCEMENT(brightness, BRIGHTNESS); 2845 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2846 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2847 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2848 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2849 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2850 2851 if (enhancements.dot_crawl) { 2852 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2853 return false; 2854 2855 intel_sdvo_connector->max_dot_crawl = 1; 2856 intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2857 intel_sdvo_connector->dot_crawl = 2858 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2859 if (!intel_sdvo_connector->dot_crawl) 2860 return false; 2861 2862 drm_object_attach_property(&connector->base, 2863 intel_sdvo_connector->dot_crawl, 2864 intel_sdvo_connector->cur_dot_crawl); 2865 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2866 } 2867 2868 return true; 2869 } 2870 2871 static bool 2872 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2873 struct intel_sdvo_connector *intel_sdvo_connector, 2874 struct intel_sdvo_enhancements_reply enhancements) 2875 { 2876 struct drm_device *dev = intel_sdvo->base.base.dev; 2877 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2878 uint16_t response, data_value[2]; 2879 2880 ENHANCEMENT(brightness, BRIGHTNESS); 2881 2882 return true; 2883 } 2884 #undef ENHANCEMENT 2885 2886 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2887 struct intel_sdvo_connector *intel_sdvo_connector) 2888 { 2889 union { 2890 struct intel_sdvo_enhancements_reply reply; 2891 uint16_t response; 2892 } enhancements; 2893 2894 BUILD_BUG_ON(sizeof(enhancements) != 2); 2895 2896 enhancements.response = 0; 2897 intel_sdvo_get_value(intel_sdvo, 2898 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2899 &enhancements, sizeof(enhancements)); 2900 if (enhancements.response == 0) { 2901 DRM_DEBUG_KMS("No enhancement is supported\n"); 2902 return true; 2903 } 2904 2905 if (IS_TV(intel_sdvo_connector)) 2906 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2907 else if (IS_LVDS(intel_sdvo_connector)) 2908 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2909 else 2910 return true; 2911 } 2912 2913 static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, 2914 struct i2c_msg *msgs, 2915 int num) 2916 { 2917 struct intel_sdvo *sdvo = adapter->algo_data; 2918 2919 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2920 return -EIO; 2921 2922 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); 2923 } 2924 2925 static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) 2926 { 2927 struct intel_sdvo *sdvo = adapter->algo_data; 2928 return sdvo->i2c->algo->functionality(sdvo->i2c); 2929 } 2930 2931 static const struct i2c_algorithm intel_sdvo_ddc_proxy = { 2932 .master_xfer = intel_sdvo_ddc_proxy_xfer, 2933 .functionality = intel_sdvo_ddc_proxy_func 2934 }; 2935 2936 static bool 2937 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, 2938 struct drm_device *dev) 2939 { 2940 #if 0 2941 sdvo->ddc.owner = THIS_MODULE; 2942 sdvo->ddc.class = I2C_CLASS_DDC; 2943 #endif 2944 ksnprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); 2945 sdvo->ddc.dev.parent = &dev->pdev->dev; 2946 sdvo->ddc.algo_data = sdvo; 2947 sdvo->ddc.algo = &intel_sdvo_ddc_proxy; 2948 2949 return i2c_add_adapter(&sdvo->ddc) == 0; 2950 } 2951 2952 static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, 2953 enum port port) 2954 { 2955 if (HAS_PCH_SPLIT(dev_priv)) 2956 WARN_ON(port != PORT_B); 2957 else 2958 WARN_ON(port != PORT_B && port != PORT_C); 2959 } 2960 2961 bool intel_sdvo_init(struct drm_device *dev, 2962 i915_reg_t sdvo_reg, enum port port) 2963 { 2964 struct drm_i915_private *dev_priv = to_i915(dev); 2965 struct intel_encoder *intel_encoder; 2966 struct intel_sdvo *intel_sdvo; 2967 int i; 2968 2969 assert_sdvo_port_valid(dev_priv, port); 2970 2971 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 2972 if (!intel_sdvo) 2973 return false; 2974 2975 intel_sdvo->sdvo_reg = sdvo_reg; 2976 intel_sdvo->port = port; 2977 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; 2978 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo); 2979 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) 2980 goto err_i2c_bus; 2981 2982 /* encoder type will be decided later */ 2983 intel_encoder = &intel_sdvo->base; 2984 intel_encoder->type = INTEL_OUTPUT_SDVO; 2985 intel_encoder->port = port; 2986 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0, 2987 "SDVO %c", port_name(port)); 2988 2989 /* Read the regs to test if we can talk to the device */ 2990 for (i = 0; i < 0x40; i++) { 2991 u8 byte; 2992 2993 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 2994 DRM_DEBUG_KMS("No SDVO device found on %s\n", 2995 SDVO_NAME(intel_sdvo)); 2996 goto err; 2997 } 2998 } 2999 3000 intel_encoder->compute_config = intel_sdvo_compute_config; 3001 if (HAS_PCH_SPLIT(dev_priv)) { 3002 intel_encoder->disable = pch_disable_sdvo; 3003 intel_encoder->post_disable = pch_post_disable_sdvo; 3004 } else { 3005 intel_encoder->disable = intel_disable_sdvo; 3006 } 3007 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3008 intel_encoder->enable = intel_enable_sdvo; 3009 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3010 intel_encoder->get_config = intel_sdvo_get_config; 3011 3012 /* In default case sdvo lvds is false */ 3013 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3014 goto err; 3015 3016 if (intel_sdvo_output_setup(intel_sdvo, 3017 intel_sdvo->caps.output_flags) != true) { 3018 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 3019 SDVO_NAME(intel_sdvo)); 3020 /* Output_setup can leave behind connectors! */ 3021 goto err_output; 3022 } 3023 3024 /* Only enable the hotplug irq if we need it, to work around noisy 3025 * hotplug lines. 3026 */ 3027 if (intel_sdvo->hotplug_active) { 3028 if (intel_sdvo->port == PORT_B) 3029 intel_encoder->hpd_pin = HPD_SDVO_B; 3030 else 3031 intel_encoder->hpd_pin = HPD_SDVO_C; 3032 } 3033 3034 /* 3035 * Cloning SDVO with anything is often impossible, since the SDVO 3036 * encoder can request a special input timing mode. And even if that's 3037 * not the case we have evidence that cloning a plain unscaled mode with 3038 * VGA doesn't really work. Furthermore the cloning flags are way too 3039 * simplistic anyway to express such constraints, so just give up on 3040 * cloning for SDVO encoders. 3041 */ 3042 intel_sdvo->base.cloneable = 0; 3043 3044 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo); 3045 3046 /* Set the input timing to the screen. Assume always input 0. */ 3047 if (!intel_sdvo_set_target_input(intel_sdvo)) 3048 goto err_output; 3049 3050 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3051 &intel_sdvo->pixel_clock_min, 3052 &intel_sdvo->pixel_clock_max)) 3053 goto err_output; 3054 3055 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 3056 "clock range %dMHz - %dMHz, " 3057 "input 1: %c, input 2: %c, " 3058 "output 1: %c, output 2: %c\n", 3059 SDVO_NAME(intel_sdvo), 3060 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3061 intel_sdvo->caps.device_rev_id, 3062 intel_sdvo->pixel_clock_min / 1000, 3063 intel_sdvo->pixel_clock_max / 1000, 3064 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3065 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3066 /* check currently supported outputs */ 3067 intel_sdvo->caps.output_flags & 3068 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3069 intel_sdvo->caps.output_flags & 3070 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3071 return true; 3072 3073 err_output: 3074 intel_sdvo_output_cleanup(intel_sdvo); 3075 3076 err: 3077 drm_encoder_cleanup(&intel_encoder->base); 3078 i2c_del_adapter(&intel_sdvo->ddc); 3079 err_i2c_bus: 3080 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3081 kfree(intel_sdvo); 3082 3083 return false; 3084 } 3085