1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 #include <linux/i2c.h> 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_atomic_helper.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_edid.h> 35 #include "intel_drv.h" 36 #include <drm/i915_drm.h> 37 #include "i915_drv.h" 38 #include "intel_sdvo_regs.h" 39 40 #include <bus/iicbus/iic.h> 41 #include <bus/iicbus/iiconf.h> 42 #include "iicbus_if.h" 43 44 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 45 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 46 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 47 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 48 49 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 50 SDVO_TV_MASK) 51 52 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 53 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 54 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 55 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 56 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 57 58 59 static const char *tv_format_names[] = { 60 "NTSC_M" , "NTSC_J" , "NTSC_443", 61 "PAL_B" , "PAL_D" , "PAL_G" , 62 "PAL_H" , "PAL_I" , "PAL_M" , 63 "PAL_N" , "PAL_NC" , "PAL_60" , 64 "SECAM_B" , "SECAM_D" , "SECAM_G" , 65 "SECAM_K" , "SECAM_K1", "SECAM_L" , 66 "SECAM_60" 67 }; 68 69 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) 70 71 struct intel_sdvo { 72 struct intel_encoder base; 73 74 struct device *i2c; 75 u8 slave_addr; 76 77 device_t ddc_iic_bus, ddc; 78 79 /* Register for the SDVO device: SDVOB or SDVOC */ 80 uint32_t sdvo_reg; 81 82 /* Active outputs controlled by this SDVO output */ 83 uint16_t controlled_output; 84 85 /* 86 * Capabilities of the SDVO device returned by 87 * intel_sdvo_get_capabilities() 88 */ 89 struct intel_sdvo_caps caps; 90 91 /* Pixel clock limitations reported by the SDVO device, in kHz */ 92 int pixel_clock_min, pixel_clock_max; 93 94 /* 95 * For multiple function SDVO device, 96 * this is for current attached outputs. 97 */ 98 uint16_t attached_output; 99 100 /* 101 * Hotplug activation bits for this device 102 */ 103 uint16_t hotplug_active; 104 105 /** 106 * This is used to select the color range of RBG outputs in HDMI mode. 107 * It is only valid when using TMDS encoding and 8 bit per color mode. 108 */ 109 uint32_t color_range; 110 bool color_range_auto; 111 112 /** 113 * This is set if we're going to treat the device as TV-out. 114 * 115 * While we have these nice friendly flags for output types that ought 116 * to decide this for us, the S-Video output on our HDMI+S-Video card 117 * shows up as RGB1 (VGA). 118 */ 119 bool is_tv; 120 121 /* On different gens SDVOB is at different places. */ 122 bool is_sdvob; 123 124 /* This is for current tv format name */ 125 int tv_format_index; 126 127 /** 128 * This is set if we treat the device as HDMI, instead of DVI. 129 */ 130 bool is_hdmi; 131 bool has_hdmi_monitor; 132 bool has_hdmi_audio; 133 bool rgb_quant_range_selectable; 134 135 /** 136 * This is set if we detect output of sdvo device as LVDS and 137 * have a valid fixed mode to use with the panel. 138 */ 139 bool is_lvds; 140 141 /** 142 * This is sdvo fixed pannel mode pointer 143 */ 144 struct drm_display_mode *sdvo_lvds_fixed_mode; 145 146 /* DDC bus used by this SDVO encoder */ 147 uint8_t ddc_bus; 148 149 /* 150 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 151 */ 152 uint8_t dtd_sdvo_flags; 153 }; 154 155 struct intel_sdvo_connector { 156 struct intel_connector base; 157 158 /* Mark the type of connector */ 159 uint16_t output_flag; 160 161 enum hdmi_force_audio force_audio; 162 163 /* This contains all current supported TV format */ 164 u8 tv_format_supported[TV_FORMAT_NUM]; 165 int format_supported_num; 166 struct drm_property *tv_format; 167 168 /* add the property for the SDVO-TV */ 169 struct drm_property *left; 170 struct drm_property *right; 171 struct drm_property *top; 172 struct drm_property *bottom; 173 struct drm_property *hpos; 174 struct drm_property *vpos; 175 struct drm_property *contrast; 176 struct drm_property *saturation; 177 struct drm_property *hue; 178 struct drm_property *sharpness; 179 struct drm_property *flicker_filter; 180 struct drm_property *flicker_filter_adaptive; 181 struct drm_property *flicker_filter_2d; 182 struct drm_property *tv_chroma_filter; 183 struct drm_property *tv_luma_filter; 184 struct drm_property *dot_crawl; 185 186 /* add the property for the SDVO-TV/LVDS */ 187 struct drm_property *brightness; 188 189 /* Add variable to record current setting for the above property */ 190 u32 left_margin, right_margin, top_margin, bottom_margin; 191 192 /* this is to get the range of margin.*/ 193 u32 max_hscan, max_vscan; 194 u32 max_hpos, cur_hpos; 195 u32 max_vpos, cur_vpos; 196 u32 cur_brightness, max_brightness; 197 u32 cur_contrast, max_contrast; 198 u32 cur_saturation, max_saturation; 199 u32 cur_hue, max_hue; 200 u32 cur_sharpness, max_sharpness; 201 u32 cur_flicker_filter, max_flicker_filter; 202 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 203 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 204 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 205 u32 cur_tv_luma_filter, max_tv_luma_filter; 206 u32 cur_dot_crawl, max_dot_crawl; 207 }; 208 209 static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) 210 { 211 return container_of(encoder, struct intel_sdvo, base); 212 } 213 214 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 215 { 216 return to_sdvo(intel_attached_encoder(connector)); 217 } 218 219 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 220 { 221 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 222 } 223 224 static bool 225 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 226 static bool 227 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 228 struct intel_sdvo_connector *intel_sdvo_connector, 229 int type); 230 static bool 231 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 232 struct intel_sdvo_connector *intel_sdvo_connector); 233 234 /** 235 * Writes the SDVOB or SDVOC with the given value, but always writes both 236 * SDVOB and SDVOC to work around apparent hardware issues (according to 237 * comments in the BIOS). 238 */ 239 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 240 { 241 struct drm_device *dev = intel_sdvo->base.base.dev; 242 struct drm_i915_private *dev_priv = dev->dev_private; 243 u32 bval = val, cval = val; 244 int i; 245 246 if (intel_sdvo->sdvo_reg == PCH_SDVOB) { 247 I915_WRITE(intel_sdvo->sdvo_reg, val); 248 POSTING_READ(intel_sdvo->sdvo_reg); 249 /* 250 * HW workaround, need to write this twice for issue 251 * that may result in first write getting masked. 252 */ 253 if (HAS_PCH_IBX(dev)) { 254 I915_WRITE(intel_sdvo->sdvo_reg, val); 255 POSTING_READ(intel_sdvo->sdvo_reg); 256 } 257 return; 258 } 259 260 if (intel_sdvo->sdvo_reg == GEN3_SDVOB) 261 cval = I915_READ(GEN3_SDVOC); 262 else 263 bval = I915_READ(GEN3_SDVOB); 264 265 /* 266 * Write the registers twice for luck. Sometimes, 267 * writing them only once doesn't appear to 'stick'. 268 * The BIOS does this too. Yay, magic 269 */ 270 for (i = 0; i < 2; i++) 271 { 272 I915_WRITE(GEN3_SDVOB, bval); 273 POSTING_READ(GEN3_SDVOB); 274 I915_WRITE(GEN3_SDVOC, cval); 275 POSTING_READ(GEN3_SDVOC); 276 } 277 } 278 279 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 280 { 281 struct i2c_msg msgs[] = { 282 { 283 .slave = intel_sdvo->slave_addr << 1, 284 .flags = 0, 285 .len = 1, 286 .buf = &addr, 287 }, 288 { 289 .slave = intel_sdvo->slave_addr << 1, 290 .flags = I2C_M_RD, 291 .len = 1, 292 .buf = ch, 293 } 294 }; 295 int ret; 296 297 if ((ret = iicbus_transfer(intel_sdvo->i2c, msgs, 2)) == 0) 298 return true; 299 300 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 301 return false; 302 } 303 304 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 305 /** Mapping of command numbers to names, for debug output */ 306 static const struct _sdvo_cmd_name { 307 u8 cmd; 308 const char *name; 309 } sdvo_cmd_names[] = { 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 353 354 /* Add the op code for SDVO enhancements */ 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 399 400 /* HDMI op code */ 401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 412 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 413 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 414 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 415 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 416 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 417 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 418 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 419 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 420 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 421 }; 422 423 #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") 424 425 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 426 const void *args, int args_len) 427 { 428 int i, pos = 0; 429 #define BUF_LEN 256 430 char buffer[BUF_LEN]; 431 432 #define BUF_PRINT(args...) \ 433 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 434 435 436 for (i = 0; i < args_len; i++) { 437 BUF_PRINT("%02X ", ((const u8 *)args)[i]); 438 } 439 for (; i < 8; i++) { 440 BUF_PRINT(" "); 441 } 442 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 443 if (cmd == sdvo_cmd_names[i].cmd) { 444 BUF_PRINT("(%s)", sdvo_cmd_names[i].name); 445 break; 446 } 447 } 448 if (i == ARRAY_SIZE(sdvo_cmd_names)) { 449 BUF_PRINT("(%02X)", cmd); 450 } 451 BUG_ON(pos >= BUF_LEN - 1); 452 #undef BUF_PRINT 453 #undef BUF_LEN 454 455 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); 456 } 457 458 static const char *cmd_status_names[] = { 459 "Power on", 460 "Success", 461 "Not supported", 462 "Invalid arg", 463 "Pending", 464 "Target not specified", 465 "Scaling not supported" 466 }; 467 468 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 469 const void *args, int args_len) 470 { 471 u8 *buf, status; 472 struct i2c_msg *msgs; 473 int i, ret = true; 474 475 /* Would be simpler to allocate both in one go ? */ 476 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 477 if (!buf) 478 return false; 479 480 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 481 if (!msgs) { 482 kfree(buf); 483 return false; 484 } 485 486 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 487 488 for (i = 0; i < args_len; i++) { 489 msgs[i].slave = intel_sdvo->slave_addr << 1; 490 msgs[i].flags = 0; 491 msgs[i].len = 2; 492 msgs[i].buf = buf + 2 *i; 493 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 494 buf[2*i + 1] = ((const u8*)args)[i]; 495 } 496 msgs[i].slave = intel_sdvo->slave_addr << 1; 497 msgs[i].flags = 0; 498 msgs[i].len = 2; 499 msgs[i].buf = buf + 2*i; 500 buf[2*i + 0] = SDVO_I2C_OPCODE; 501 buf[2*i + 1] = cmd; 502 503 /* the following two are to read the response */ 504 status = SDVO_I2C_CMD_STATUS; 505 msgs[i+1].slave = intel_sdvo->slave_addr << 1; 506 msgs[i+1].flags = 0; 507 msgs[i+1].len = 1; 508 msgs[i+1].buf = &status; 509 510 msgs[i+2].slave = intel_sdvo->slave_addr << 1; 511 msgs[i+2].flags = I2C_M_RD; 512 msgs[i+2].len = 1; 513 msgs[i+2].buf = &status; 514 515 ret = iicbus_transfer(intel_sdvo->i2c, msgs, i+3); 516 if (ret != 0) { 517 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 518 ret = false; 519 goto out; 520 } 521 #if 0 522 if (ret != i+3) { 523 /* failure in I2C transfer */ 524 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 525 ret = false; 526 } 527 #endif 528 529 out: 530 kfree(msgs); 531 kfree(buf); 532 return ret; 533 } 534 535 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 536 void *response, int response_len) 537 { 538 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 539 u8 status; 540 int i, pos = 0; 541 #define BUF_LEN 256 542 char buffer[BUF_LEN]; 543 544 545 /* 546 * The documentation states that all commands will be 547 * processed within 15µs, and that we need only poll 548 * the status byte a maximum of 3 times in order for the 549 * command to be complete. 550 * 551 * Check 5 times in case the hardware failed to read the docs. 552 * 553 * Also beware that the first response by many devices is to 554 * reply PENDING and stall for time. TVs are notorious for 555 * requiring longer than specified to complete their replies. 556 * Originally (in the DDX long ago), the delay was only ever 15ms 557 * with an additional delay of 30ms applied for TVs added later after 558 * many experiments. To accommodate both sets of delays, we do a 559 * sequence of slow checks if the device is falling behind and fails 560 * to reply within 5*15µs. 561 */ 562 if (!intel_sdvo_read_byte(intel_sdvo, 563 SDVO_I2C_CMD_STATUS, 564 &status)) 565 goto log_fail; 566 567 while ((status == SDVO_CMD_STATUS_PENDING || 568 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { 569 if (retry < 10) 570 msleep(15); 571 else 572 udelay(15); 573 574 if (!intel_sdvo_read_byte(intel_sdvo, 575 SDVO_I2C_CMD_STATUS, 576 &status)) 577 goto log_fail; 578 } 579 580 #define BUF_PRINT(args...) \ 581 pos += ksnprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) 582 583 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 584 BUF_PRINT("(%s)", cmd_status_names[status]); 585 else 586 BUF_PRINT("(??? %d)", status); 587 588 if (status != SDVO_CMD_STATUS_SUCCESS) 589 goto log_fail; 590 591 /* Read the command response */ 592 for (i = 0; i < response_len; i++) { 593 if (!intel_sdvo_read_byte(intel_sdvo, 594 SDVO_I2C_RETURN_0 + i, 595 &((u8 *)response)[i])) 596 goto log_fail; 597 BUF_PRINT(" %02X", ((u8 *)response)[i]); 598 } 599 BUG_ON(pos >= BUF_LEN - 1); 600 #undef BUF_PRINT 601 #undef BUF_LEN 602 603 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); 604 return true; 605 606 log_fail: 607 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); 608 return false; 609 } 610 611 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) 612 { 613 if (mode->clock >= 100000) 614 return 1; 615 else if (mode->clock >= 50000) 616 return 2; 617 else 618 return 4; 619 } 620 621 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 622 u8 ddc_bus) 623 { 624 /* This must be the immediately preceding write before the i2c xfer */ 625 return intel_sdvo_write_cmd(intel_sdvo, 626 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 627 &ddc_bus, 1); 628 } 629 630 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 631 { 632 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 633 return false; 634 635 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 636 } 637 638 static bool 639 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 640 { 641 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 642 return false; 643 644 return intel_sdvo_read_response(intel_sdvo, value, len); 645 } 646 647 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 648 { 649 struct intel_sdvo_set_target_input_args targets = {0}; 650 return intel_sdvo_set_value(intel_sdvo, 651 SDVO_CMD_SET_TARGET_INPUT, 652 &targets, sizeof(targets)); 653 } 654 655 /** 656 * Return whether each input is trained. 657 * 658 * This function is making an assumption about the layout of the response, 659 * which should be checked against the docs. 660 */ 661 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 662 { 663 struct intel_sdvo_get_trained_inputs_response response; 664 665 BUILD_BUG_ON(sizeof(response) != 1); 666 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 667 &response, sizeof(response))) 668 return false; 669 670 *input_1 = response.input0_trained; 671 *input_2 = response.input1_trained; 672 return true; 673 } 674 675 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 676 u16 outputs) 677 { 678 return intel_sdvo_set_value(intel_sdvo, 679 SDVO_CMD_SET_ACTIVE_OUTPUTS, 680 &outputs, sizeof(outputs)); 681 } 682 683 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 684 u16 *outputs) 685 { 686 return intel_sdvo_get_value(intel_sdvo, 687 SDVO_CMD_GET_ACTIVE_OUTPUTS, 688 outputs, sizeof(*outputs)); 689 } 690 691 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 692 int mode) 693 { 694 u8 state = SDVO_ENCODER_STATE_ON; 695 696 switch (mode) { 697 case DRM_MODE_DPMS_ON: 698 state = SDVO_ENCODER_STATE_ON; 699 break; 700 case DRM_MODE_DPMS_STANDBY: 701 state = SDVO_ENCODER_STATE_STANDBY; 702 break; 703 case DRM_MODE_DPMS_SUSPEND: 704 state = SDVO_ENCODER_STATE_SUSPEND; 705 break; 706 case DRM_MODE_DPMS_OFF: 707 state = SDVO_ENCODER_STATE_OFF; 708 break; 709 } 710 711 return intel_sdvo_set_value(intel_sdvo, 712 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 713 } 714 715 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 716 int *clock_min, 717 int *clock_max) 718 { 719 struct intel_sdvo_pixel_clock_range clocks; 720 721 BUILD_BUG_ON(sizeof(clocks) != 4); 722 if (!intel_sdvo_get_value(intel_sdvo, 723 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 724 &clocks, sizeof(clocks))) 725 return false; 726 727 /* Convert the values from units of 10 kHz to kHz. */ 728 *clock_min = clocks.min * 10; 729 *clock_max = clocks.max * 10; 730 return true; 731 } 732 733 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 734 u16 outputs) 735 { 736 return intel_sdvo_set_value(intel_sdvo, 737 SDVO_CMD_SET_TARGET_OUTPUT, 738 &outputs, sizeof(outputs)); 739 } 740 741 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 742 struct intel_sdvo_dtd *dtd) 743 { 744 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 745 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 746 } 747 748 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 749 struct intel_sdvo_dtd *dtd) 750 { 751 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 752 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 753 } 754 755 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 756 struct intel_sdvo_dtd *dtd) 757 { 758 return intel_sdvo_set_timing(intel_sdvo, 759 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 760 } 761 762 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 763 struct intel_sdvo_dtd *dtd) 764 { 765 return intel_sdvo_set_timing(intel_sdvo, 766 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 767 } 768 769 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 770 struct intel_sdvo_dtd *dtd) 771 { 772 return intel_sdvo_get_timing(intel_sdvo, 773 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 774 } 775 776 static bool 777 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 778 uint16_t clock, 779 uint16_t width, 780 uint16_t height) 781 { 782 struct intel_sdvo_preferred_input_timing_args args; 783 784 memset(&args, 0, sizeof(args)); 785 args.clock = clock; 786 args.width = width; 787 args.height = height; 788 args.interlace = 0; 789 790 if (intel_sdvo->is_lvds && 791 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 792 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 793 args.scaled = 1; 794 795 return intel_sdvo_set_value(intel_sdvo, 796 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 797 &args, sizeof(args)); 798 } 799 800 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 801 struct intel_sdvo_dtd *dtd) 802 { 803 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 804 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 805 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 806 &dtd->part1, sizeof(dtd->part1)) && 807 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 808 &dtd->part2, sizeof(dtd->part2)); 809 } 810 811 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 812 { 813 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 814 } 815 816 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 817 const struct drm_display_mode *mode) 818 { 819 uint16_t width, height; 820 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 821 uint16_t h_sync_offset, v_sync_offset; 822 int mode_clock; 823 824 memset(dtd, 0, sizeof(*dtd)); 825 826 width = mode->hdisplay; 827 height = mode->vdisplay; 828 829 /* do some mode translations */ 830 h_blank_len = mode->htotal - mode->hdisplay; 831 h_sync_len = mode->hsync_end - mode->hsync_start; 832 833 v_blank_len = mode->vtotal - mode->vdisplay; 834 v_sync_len = mode->vsync_end - mode->vsync_start; 835 836 h_sync_offset = mode->hsync_start - mode->hdisplay; 837 v_sync_offset = mode->vsync_start - mode->vdisplay; 838 839 mode_clock = mode->clock; 840 mode_clock /= 10; 841 dtd->part1.clock = mode_clock; 842 843 dtd->part1.h_active = width & 0xff; 844 dtd->part1.h_blank = h_blank_len & 0xff; 845 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 846 ((h_blank_len >> 8) & 0xf); 847 dtd->part1.v_active = height & 0xff; 848 dtd->part1.v_blank = v_blank_len & 0xff; 849 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 850 ((v_blank_len >> 8) & 0xf); 851 852 dtd->part2.h_sync_off = h_sync_offset & 0xff; 853 dtd->part2.h_sync_width = h_sync_len & 0xff; 854 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 855 (v_sync_len & 0xf); 856 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 857 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 858 ((v_sync_len & 0x30) >> 4); 859 860 dtd->part2.dtd_flags = 0x18; 861 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 862 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 863 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 864 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 865 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 866 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 867 868 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 869 } 870 871 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, 872 const struct intel_sdvo_dtd *dtd) 873 { 874 struct drm_display_mode mode = {}; 875 876 mode.hdisplay = dtd->part1.h_active; 877 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 878 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; 879 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 880 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; 881 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 882 mode.htotal = mode.hdisplay + dtd->part1.h_blank; 883 mode.htotal += (dtd->part1.h_high & 0xf) << 8; 884 885 mode.vdisplay = dtd->part1.v_active; 886 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 887 mode.vsync_start = mode.vdisplay; 888 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 889 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 890 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; 891 mode.vsync_end = mode.vsync_start + 892 (dtd->part2.v_sync_off_width & 0xf); 893 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 894 mode.vtotal = mode.vdisplay + dtd->part1.v_blank; 895 mode.vtotal += (dtd->part1.v_high & 0xf) << 8; 896 897 mode.clock = dtd->part1.clock * 10; 898 899 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 900 mode.flags |= DRM_MODE_FLAG_INTERLACE; 901 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 902 mode.flags |= DRM_MODE_FLAG_PHSYNC; 903 else 904 mode.flags |= DRM_MODE_FLAG_NHSYNC; 905 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 906 mode.flags |= DRM_MODE_FLAG_PVSYNC; 907 else 908 mode.flags |= DRM_MODE_FLAG_NVSYNC; 909 910 drm_mode_set_crtcinfo(&mode, 0); 911 912 drm_mode_copy(pmode, &mode); 913 } 914 915 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 916 { 917 struct intel_sdvo_encode encode; 918 919 BUILD_BUG_ON(sizeof(encode) != 2); 920 return intel_sdvo_get_value(intel_sdvo, 921 SDVO_CMD_GET_SUPP_ENCODE, 922 &encode, sizeof(encode)); 923 } 924 925 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 926 uint8_t mode) 927 { 928 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 929 } 930 931 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 932 uint8_t mode) 933 { 934 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 935 } 936 937 #if 0 938 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 939 { 940 int i, j; 941 uint8_t set_buf_index[2]; 942 uint8_t av_split; 943 uint8_t buf_size; 944 uint8_t buf[48]; 945 uint8_t *pos; 946 947 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 948 949 for (i = 0; i <= av_split; i++) { 950 set_buf_index[0] = i; set_buf_index[1] = 0; 951 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 952 set_buf_index, 2); 953 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 954 intel_sdvo_read_response(encoder, &buf_size, 1); 955 956 pos = buf; 957 for (j = 0; j <= buf_size; j += 8) { 958 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 959 NULL, 0); 960 intel_sdvo_read_response(encoder, pos, 8); 961 pos += 8; 962 } 963 } 964 } 965 #endif 966 967 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 968 unsigned if_index, uint8_t tx_rate, 969 const uint8_t *data, unsigned length) 970 { 971 uint8_t set_buf_index[2] = { if_index, 0 }; 972 uint8_t hbuf_size, tmp[8]; 973 int i; 974 975 if (!intel_sdvo_set_value(intel_sdvo, 976 SDVO_CMD_SET_HBUF_INDEX, 977 set_buf_index, 2)) 978 return false; 979 980 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 981 &hbuf_size, 1)) 982 return false; 983 984 /* Buffer size is 0 based, hooray! */ 985 hbuf_size++; 986 987 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", 988 if_index, length, hbuf_size); 989 990 for (i = 0; i < hbuf_size; i += 8) { 991 memset(tmp, 0, 8); 992 if (i < length) 993 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 994 995 if (!intel_sdvo_set_value(intel_sdvo, 996 SDVO_CMD_SET_HBUF_DATA, 997 tmp, 8)) 998 return false; 999 } 1000 1001 return intel_sdvo_set_value(intel_sdvo, 1002 SDVO_CMD_SET_HBUF_TXRATE, 1003 &tx_rate, 1); 1004 } 1005 1006 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 1007 const struct drm_display_mode *adjusted_mode) 1008 { 1009 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; 1010 struct drm_crtc *crtc = intel_sdvo->base.base.crtc; 1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1012 union hdmi_infoframe frame; 1013 int ret; 1014 ssize_t len; 1015 1016 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 1017 adjusted_mode); 1018 if (ret < 0) { 1019 DRM_ERROR("couldn't fill AVI infoframe\n"); 1020 return false; 1021 } 1022 1023 if (intel_sdvo->rgb_quant_range_selectable) { 1024 if (intel_crtc->config->limited_color_range) 1025 frame.avi.quantization_range = 1026 HDMI_QUANTIZATION_RANGE_LIMITED; 1027 else 1028 frame.avi.quantization_range = 1029 HDMI_QUANTIZATION_RANGE_FULL; 1030 } 1031 1032 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); 1033 if (len < 0) 1034 return false; 1035 1036 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 1037 SDVO_HBUF_TX_VSYNC, 1038 sdvo_data, sizeof(sdvo_data)); 1039 } 1040 1041 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 1042 { 1043 struct intel_sdvo_tv_format format; 1044 uint32_t format_map; 1045 1046 format_map = 1 << intel_sdvo->tv_format_index; 1047 memset(&format, 0, sizeof(format)); 1048 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1049 1050 BUILD_BUG_ON(sizeof(format) != 6); 1051 return intel_sdvo_set_value(intel_sdvo, 1052 SDVO_CMD_SET_TV_FORMAT, 1053 &format, sizeof(format)); 1054 } 1055 1056 static bool 1057 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1058 const struct drm_display_mode *mode) 1059 { 1060 struct intel_sdvo_dtd output_dtd; 1061 1062 if (!intel_sdvo_set_target_output(intel_sdvo, 1063 intel_sdvo->attached_output)) 1064 return false; 1065 1066 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1067 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1068 return false; 1069 1070 return true; 1071 } 1072 1073 /* Asks the sdvo controller for the preferred input mode given the output mode. 1074 * Unfortunately we have to set up the full output mode to do that. */ 1075 static bool 1076 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1077 const struct drm_display_mode *mode, 1078 struct drm_display_mode *adjusted_mode) 1079 { 1080 struct intel_sdvo_dtd input_dtd; 1081 1082 /* Reset the input timing to the screen. Assume always input 0. */ 1083 if (!intel_sdvo_set_target_input(intel_sdvo)) 1084 return false; 1085 1086 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1087 mode->clock / 10, 1088 mode->hdisplay, 1089 mode->vdisplay)) 1090 return false; 1091 1092 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1093 &input_dtd)) 1094 return false; 1095 1096 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1097 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1098 1099 return true; 1100 } 1101 1102 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) 1103 { 1104 unsigned dotclock = pipe_config->port_clock; 1105 struct dpll *clock = &pipe_config->dpll; 1106 1107 /* SDVO TV has fixed PLL values depend on its clock range, 1108 this mirrors vbios setting. */ 1109 if (dotclock >= 100000 && dotclock < 140500) { 1110 clock->p1 = 2; 1111 clock->p2 = 10; 1112 clock->n = 3; 1113 clock->m1 = 16; 1114 clock->m2 = 8; 1115 } else if (dotclock >= 140500 && dotclock <= 200000) { 1116 clock->p1 = 1; 1117 clock->p2 = 10; 1118 clock->n = 6; 1119 clock->m1 = 12; 1120 clock->m2 = 8; 1121 } else { 1122 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1123 } 1124 1125 pipe_config->clock_set = true; 1126 } 1127 1128 static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 1129 struct intel_crtc_state *pipe_config) 1130 { 1131 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1132 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1133 struct drm_display_mode *mode = &pipe_config->base.mode; 1134 1135 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1136 pipe_config->pipe_bpp = 8*3; 1137 1138 if (HAS_PCH_SPLIT(encoder->base.dev)) 1139 pipe_config->has_pch_encoder = true; 1140 1141 /* We need to construct preferred input timings based on our 1142 * output timings. To do that, we have to set the output 1143 * timings, even though this isn't really the right place in 1144 * the sequence to do it. Oh well. 1145 */ 1146 if (intel_sdvo->is_tv) { 1147 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1148 return false; 1149 1150 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1151 mode, 1152 adjusted_mode); 1153 pipe_config->sdvo_tv_clock = true; 1154 } else if (intel_sdvo->is_lvds) { 1155 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1156 intel_sdvo->sdvo_lvds_fixed_mode)) 1157 return false; 1158 1159 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1160 mode, 1161 adjusted_mode); 1162 } 1163 1164 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1165 * SDVO device will factor out the multiplier during mode_set. 1166 */ 1167 pipe_config->pixel_multiplier = 1168 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1169 1170 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; 1171 1172 if (intel_sdvo->color_range_auto) { 1173 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1174 /* FIXME: This bit is only valid when using TMDS encoding and 8 1175 * bit per color mode. */ 1176 if (pipe_config->has_hdmi_sink && 1177 drm_match_cea_mode(adjusted_mode) > 1) 1178 pipe_config->limited_color_range = true; 1179 } else { 1180 if (pipe_config->has_hdmi_sink && 1181 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) 1182 pipe_config->limited_color_range = true; 1183 } 1184 1185 /* Clock computation needs to happen after pixel multiplier. */ 1186 if (intel_sdvo->is_tv) 1187 i9xx_adjust_sdvo_tv_clock(pipe_config); 1188 1189 return true; 1190 } 1191 1192 static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) 1193 { 1194 struct drm_device *dev = intel_encoder->base.dev; 1195 struct drm_i915_private *dev_priv = dev->dev_private; 1196 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); 1197 struct drm_display_mode *adjusted_mode = 1198 &crtc->config->base.adjusted_mode; 1199 struct drm_display_mode *mode = &crtc->config->base.mode; 1200 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); 1201 u32 sdvox; 1202 struct intel_sdvo_in_out_map in_out; 1203 struct intel_sdvo_dtd input_dtd, output_dtd; 1204 int rate; 1205 1206 if (!mode) 1207 return; 1208 1209 /* First, set the input mapping for the first input to our controlled 1210 * output. This is only correct if we're a single-input device, in 1211 * which case the first input is the output from the appropriate SDVO 1212 * channel on the motherboard. In a two-input device, the first input 1213 * will be SDVOB and the second SDVOC. 1214 */ 1215 in_out.in0 = intel_sdvo->attached_output; 1216 in_out.in1 = 0; 1217 1218 intel_sdvo_set_value(intel_sdvo, 1219 SDVO_CMD_SET_IN_OUT_MAP, 1220 &in_out, sizeof(in_out)); 1221 1222 /* Set the output timings to the screen */ 1223 if (!intel_sdvo_set_target_output(intel_sdvo, 1224 intel_sdvo->attached_output)) 1225 return; 1226 1227 /* lvds has a special fixed output timing. */ 1228 if (intel_sdvo->is_lvds) 1229 intel_sdvo_get_dtd_from_mode(&output_dtd, 1230 intel_sdvo->sdvo_lvds_fixed_mode); 1231 else 1232 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1233 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1234 DRM_INFO("Setting output timings on %s failed\n", 1235 SDVO_NAME(intel_sdvo)); 1236 1237 /* Set the input timing to the screen. Assume always input 0. */ 1238 if (!intel_sdvo_set_target_input(intel_sdvo)) 1239 return; 1240 1241 if (crtc->config->has_hdmi_sink) { 1242 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1243 intel_sdvo_set_colorimetry(intel_sdvo, 1244 SDVO_COLORIMETRY_RGB256); 1245 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); 1246 } else 1247 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1248 1249 if (intel_sdvo->is_tv && 1250 !intel_sdvo_set_tv_format(intel_sdvo)) 1251 return; 1252 1253 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1254 1255 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) 1256 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1257 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1258 DRM_INFO("Setting input timings on %s failed\n", 1259 SDVO_NAME(intel_sdvo)); 1260 1261 switch (crtc->config->pixel_multiplier) { 1262 default: 1263 WARN(1, "unknown pixel multiplier specified\n"); 1264 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1265 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1266 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1267 } 1268 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1269 return; 1270 1271 /* Set the SDVO control regs. */ 1272 if (INTEL_INFO(dev)->gen >= 4) { 1273 /* The real mode polarity is set by the SDVO commands, using 1274 * struct intel_sdvo_dtd. */ 1275 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1276 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) 1277 sdvox |= HDMI_COLOR_RANGE_16_235; 1278 if (INTEL_INFO(dev)->gen < 5) 1279 sdvox |= SDVO_BORDER_ENABLE; 1280 } else { 1281 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1282 switch (intel_sdvo->sdvo_reg) { 1283 case GEN3_SDVOB: 1284 sdvox &= SDVOB_PRESERVE_MASK; 1285 break; 1286 case GEN3_SDVOC: 1287 sdvox &= SDVOC_PRESERVE_MASK; 1288 break; 1289 } 1290 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1291 } 1292 1293 if (INTEL_PCH_TYPE(dev) >= PCH_CPT) 1294 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1295 else 1296 sdvox |= SDVO_PIPE_SEL(crtc->pipe); 1297 1298 if (intel_sdvo->has_hdmi_audio) 1299 sdvox |= SDVO_AUDIO_ENABLE; 1300 1301 if (INTEL_INFO(dev)->gen >= 4) { 1302 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1303 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1304 /* done in crtc_mode_set as it lives inside the dpll register */ 1305 } else { 1306 sdvox |= (crtc->config->pixel_multiplier - 1) 1307 << SDVO_PORT_MULTIPLY_SHIFT; 1308 } 1309 1310 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1311 INTEL_INFO(dev)->gen < 5) 1312 sdvox |= SDVO_STALL_SELECT; 1313 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1314 } 1315 1316 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1317 { 1318 struct intel_sdvo_connector *intel_sdvo_connector = 1319 to_intel_sdvo_connector(&connector->base); 1320 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1321 u16 active_outputs = 0; 1322 1323 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1324 1325 if (active_outputs & intel_sdvo_connector->output_flag) 1326 return true; 1327 else 1328 return false; 1329 } 1330 1331 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1332 enum i915_pipe *pipe) 1333 { 1334 struct drm_device *dev = encoder->base.dev; 1335 struct drm_i915_private *dev_priv = dev->dev_private; 1336 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1337 u16 active_outputs = 0; 1338 u32 tmp; 1339 1340 tmp = I915_READ(intel_sdvo->sdvo_reg); 1341 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1342 1343 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) 1344 return false; 1345 1346 if (HAS_PCH_CPT(dev)) 1347 *pipe = PORT_TO_PIPE_CPT(tmp); 1348 else 1349 *pipe = PORT_TO_PIPE(tmp); 1350 1351 return true; 1352 } 1353 1354 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1355 struct intel_crtc_state *pipe_config) 1356 { 1357 struct drm_device *dev = encoder->base.dev; 1358 struct drm_i915_private *dev_priv = dev->dev_private; 1359 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1360 struct intel_sdvo_dtd dtd; 1361 int encoder_pixel_multiplier = 0; 1362 int dotclock; 1363 u32 flags = 0, sdvox; 1364 u8 val; 1365 bool ret; 1366 1367 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1368 1369 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1370 if (!ret) { 1371 /* Some sdvo encoders are not spec compliant and don't 1372 * implement the mandatory get_timings function. */ 1373 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1374 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1375 } else { 1376 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1377 flags |= DRM_MODE_FLAG_PHSYNC; 1378 else 1379 flags |= DRM_MODE_FLAG_NHSYNC; 1380 1381 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1382 flags |= DRM_MODE_FLAG_PVSYNC; 1383 else 1384 flags |= DRM_MODE_FLAG_NVSYNC; 1385 } 1386 1387 pipe_config->base.adjusted_mode.flags |= flags; 1388 1389 /* 1390 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1391 * the sdvo port register, on all other platforms it is part of the dpll 1392 * state. Since the general pipe state readout happens before the 1393 * encoder->get_config we so already have a valid pixel multplier on all 1394 * other platfroms. 1395 */ 1396 if (IS_I915G(dev) || IS_I915GM(dev)) { 1397 pipe_config->pixel_multiplier = 1398 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1399 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1400 } 1401 1402 dotclock = pipe_config->port_clock; 1403 if (pipe_config->pixel_multiplier) 1404 dotclock /= pipe_config->pixel_multiplier; 1405 1406 if (HAS_PCH_SPLIT(dev)) 1407 ironlake_check_encoder_dotclock(pipe_config, dotclock); 1408 1409 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1410 1411 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1412 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, 1413 &val, 1)) { 1414 switch (val) { 1415 case SDVO_CLOCK_RATE_MULT_1X: 1416 encoder_pixel_multiplier = 1; 1417 break; 1418 case SDVO_CLOCK_RATE_MULT_2X: 1419 encoder_pixel_multiplier = 2; 1420 break; 1421 case SDVO_CLOCK_RATE_MULT_4X: 1422 encoder_pixel_multiplier = 4; 1423 break; 1424 } 1425 } 1426 1427 if (sdvox & HDMI_COLOR_RANGE_16_235) 1428 pipe_config->limited_color_range = true; 1429 1430 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, 1431 &val, 1)) { 1432 if (val == SDVO_ENCODE_HDMI) 1433 pipe_config->has_hdmi_sink = true; 1434 } 1435 1436 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1437 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1438 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1439 } 1440 1441 static void intel_disable_sdvo(struct intel_encoder *encoder) 1442 { 1443 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1444 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1445 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 1446 u32 temp; 1447 1448 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1449 if (0) 1450 intel_sdvo_set_encoder_power_state(intel_sdvo, 1451 DRM_MODE_DPMS_OFF); 1452 1453 temp = I915_READ(intel_sdvo->sdvo_reg); 1454 1455 temp &= ~SDVO_ENABLE; 1456 intel_sdvo_write_sdvox(intel_sdvo, temp); 1457 1458 /* 1459 * HW workaround for IBX, we need to move the port 1460 * to transcoder A after disabling it to allow the 1461 * matching DP port to be enabled on transcoder A. 1462 */ 1463 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 1464 temp &= ~SDVO_PIPE_B_SELECT; 1465 temp |= SDVO_ENABLE; 1466 intel_sdvo_write_sdvox(intel_sdvo, temp); 1467 1468 temp &= ~SDVO_ENABLE; 1469 intel_sdvo_write_sdvox(intel_sdvo, temp); 1470 } 1471 } 1472 1473 static void pch_disable_sdvo(struct intel_encoder *encoder) 1474 { 1475 } 1476 1477 static void pch_post_disable_sdvo(struct intel_encoder *encoder) 1478 { 1479 intel_disable_sdvo(encoder); 1480 } 1481 1482 static void intel_enable_sdvo(struct intel_encoder *encoder) 1483 { 1484 struct drm_device *dev = encoder->base.dev; 1485 struct drm_i915_private *dev_priv = dev->dev_private; 1486 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1487 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1488 u32 temp; 1489 bool input1, input2; 1490 int i; 1491 bool success; 1492 1493 temp = I915_READ(intel_sdvo->sdvo_reg); 1494 temp |= SDVO_ENABLE; 1495 intel_sdvo_write_sdvox(intel_sdvo, temp); 1496 1497 for (i = 0; i < 2; i++) 1498 intel_wait_for_vblank(dev, intel_crtc->pipe); 1499 1500 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1501 /* Warn if the device reported failure to sync. 1502 * A lot of SDVO devices fail to notify of sync, but it's 1503 * a given it the status is a success, we succeeded. 1504 */ 1505 if (success && !input1) { 1506 DRM_DEBUG_KMS("First %s output reported failure to " 1507 "sync\n", SDVO_NAME(intel_sdvo)); 1508 } 1509 1510 if (0) 1511 intel_sdvo_set_encoder_power_state(intel_sdvo, 1512 DRM_MODE_DPMS_ON); 1513 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1514 } 1515 1516 static enum drm_mode_status 1517 intel_sdvo_mode_valid(struct drm_connector *connector, 1518 struct drm_display_mode *mode) 1519 { 1520 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1521 1522 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1523 return MODE_NO_DBLESCAN; 1524 1525 if (intel_sdvo->pixel_clock_min > mode->clock) 1526 return MODE_CLOCK_LOW; 1527 1528 if (intel_sdvo->pixel_clock_max < mode->clock) 1529 return MODE_CLOCK_HIGH; 1530 1531 if (intel_sdvo->is_lvds) { 1532 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1533 return MODE_PANEL; 1534 1535 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1536 return MODE_PANEL; 1537 } 1538 1539 return MODE_OK; 1540 } 1541 1542 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1543 { 1544 BUILD_BUG_ON(sizeof(*caps) != 8); 1545 if (!intel_sdvo_get_value(intel_sdvo, 1546 SDVO_CMD_GET_DEVICE_CAPS, 1547 caps, sizeof(*caps))) 1548 return false; 1549 1550 DRM_DEBUG_KMS("SDVO capabilities:\n" 1551 " vendor_id: %d\n" 1552 " device_id: %d\n" 1553 " device_rev_id: %d\n" 1554 " sdvo_version_major: %d\n" 1555 " sdvo_version_minor: %d\n" 1556 " sdvo_inputs_mask: %d\n" 1557 " smooth_scaling: %d\n" 1558 " sharp_scaling: %d\n" 1559 " up_scaling: %d\n" 1560 " down_scaling: %d\n" 1561 " stall_support: %d\n" 1562 " output_flags: %d\n", 1563 caps->vendor_id, 1564 caps->device_id, 1565 caps->device_rev_id, 1566 caps->sdvo_version_major, 1567 caps->sdvo_version_minor, 1568 caps->sdvo_inputs_mask, 1569 caps->smooth_scaling, 1570 caps->sharp_scaling, 1571 caps->up_scaling, 1572 caps->down_scaling, 1573 caps->stall_support, 1574 caps->output_flags); 1575 1576 return true; 1577 } 1578 1579 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1580 { 1581 struct drm_device *dev = intel_sdvo->base.base.dev; 1582 uint16_t hotplug; 1583 1584 if (!I915_HAS_HOTPLUG(dev)) 1585 return 0; 1586 1587 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1588 * on the line. */ 1589 if (IS_I945G(dev) || IS_I945GM(dev)) 1590 return 0; 1591 1592 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1593 &hotplug, sizeof(hotplug))) 1594 return 0; 1595 1596 return hotplug; 1597 } 1598 1599 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1600 { 1601 struct intel_sdvo *intel_sdvo = to_sdvo(encoder); 1602 1603 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1604 &intel_sdvo->hotplug_active, 2); 1605 } 1606 1607 static bool 1608 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1609 { 1610 /* Is there more than one type of output? */ 1611 return hweight16(intel_sdvo->caps.output_flags) > 1; 1612 } 1613 1614 static struct edid * 1615 intel_sdvo_get_edid(struct drm_connector *connector) 1616 { 1617 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 1618 return drm_get_edid(connector, sdvo->ddc); 1619 } 1620 1621 /* Mac mini hack -- use the same DDC as the analog connector */ 1622 static struct edid * 1623 intel_sdvo_get_analog_edid(struct drm_connector *connector) 1624 { 1625 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1626 1627 return drm_get_edid(connector, 1628 intel_gmbus_get_adapter(dev_priv, 1629 dev_priv->vbt.crt_ddc_pin)); 1630 } 1631 1632 static enum drm_connector_status 1633 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1634 { 1635 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1636 enum drm_connector_status status; 1637 struct edid *edid; 1638 1639 edid = intel_sdvo_get_edid(connector); 1640 1641 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1642 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1643 1644 /* 1645 * Don't use the 1 as the argument of DDC bus switch to get 1646 * the EDID. It is used for SDVO SPD ROM. 1647 */ 1648 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1649 intel_sdvo->ddc_bus = ddc; 1650 edid = intel_sdvo_get_edid(connector); 1651 if (edid) 1652 break; 1653 } 1654 /* 1655 * If we found the EDID on the other bus, 1656 * assume that is the correct DDC bus. 1657 */ 1658 if (edid == NULL) 1659 intel_sdvo->ddc_bus = saved_ddc; 1660 } 1661 1662 /* 1663 * When there is no edid and no monitor is connected with VGA 1664 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1665 */ 1666 if (edid == NULL) 1667 edid = intel_sdvo_get_analog_edid(connector); 1668 1669 status = connector_status_unknown; 1670 if (edid != NULL) { 1671 /* DDC bus is shared, match EDID to connector type */ 1672 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1673 status = connector_status_connected; 1674 if (intel_sdvo->is_hdmi) { 1675 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1676 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1677 intel_sdvo->rgb_quant_range_selectable = 1678 drm_rgb_quant_range_selectable(edid); 1679 } 1680 } else 1681 status = connector_status_disconnected; 1682 kfree(edid); 1683 } 1684 1685 if (status == connector_status_connected) { 1686 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1687 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) 1688 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); 1689 } 1690 1691 return status; 1692 } 1693 1694 static bool 1695 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 1696 struct edid *edid) 1697 { 1698 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1699 bool connector_is_digital = !!IS_DIGITAL(sdvo); 1700 1701 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 1702 connector_is_digital, monitor_is_digital); 1703 return connector_is_digital == monitor_is_digital; 1704 } 1705 1706 static enum drm_connector_status 1707 intel_sdvo_detect(struct drm_connector *connector, bool force) 1708 { 1709 uint16_t response; 1710 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1711 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1712 enum drm_connector_status ret; 1713 1714 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1715 connector->base.id, connector->name); 1716 1717 if (!intel_sdvo_get_value(intel_sdvo, 1718 SDVO_CMD_GET_ATTACHED_DISPLAYS, 1719 &response, 2)) 1720 return connector_status_unknown; 1721 1722 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1723 response & 0xff, response >> 8, 1724 intel_sdvo_connector->output_flag); 1725 1726 if (response == 0) 1727 return connector_status_disconnected; 1728 1729 intel_sdvo->attached_output = response; 1730 1731 intel_sdvo->has_hdmi_monitor = false; 1732 intel_sdvo->has_hdmi_audio = false; 1733 intel_sdvo->rgb_quant_range_selectable = false; 1734 1735 if ((intel_sdvo_connector->output_flag & response) == 0) 1736 ret = connector_status_disconnected; 1737 else if (IS_TMDS(intel_sdvo_connector)) 1738 ret = intel_sdvo_tmds_sink_detect(connector); 1739 else { 1740 struct edid *edid; 1741 1742 /* if we have an edid check it matches the connection */ 1743 edid = intel_sdvo_get_edid(connector); 1744 if (edid == NULL) 1745 edid = intel_sdvo_get_analog_edid(connector); 1746 if (edid != NULL) { 1747 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 1748 edid)) 1749 ret = connector_status_connected; 1750 else 1751 ret = connector_status_disconnected; 1752 1753 kfree(edid); 1754 } else 1755 ret = connector_status_connected; 1756 } 1757 1758 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1759 if (ret == connector_status_connected) { 1760 intel_sdvo->is_tv = false; 1761 intel_sdvo->is_lvds = false; 1762 1763 if (response & SDVO_TV_MASK) 1764 intel_sdvo->is_tv = true; 1765 if (response & SDVO_LVDS_MASK) 1766 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1767 } 1768 1769 return ret; 1770 } 1771 1772 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1773 { 1774 struct edid *edid; 1775 1776 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1777 connector->base.id, connector->name); 1778 1779 /* set the bus switch and get the modes */ 1780 edid = intel_sdvo_get_edid(connector); 1781 1782 /* 1783 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1784 * link between analog and digital outputs. So, if the regular SDVO 1785 * DDC fails, check to see if the analog output is disconnected, in 1786 * which case we'll look there for the digital DDC data. 1787 */ 1788 if (edid == NULL) 1789 edid = intel_sdvo_get_analog_edid(connector); 1790 1791 if (edid != NULL) { 1792 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 1793 edid)) { 1794 drm_mode_connector_update_edid_property(connector, edid); 1795 drm_add_edid_modes(connector, edid); 1796 } 1797 1798 kfree(edid); 1799 } 1800 } 1801 1802 /* 1803 * Set of SDVO TV modes. 1804 * Note! This is in reply order (see loop in get_tv_modes). 1805 * XXX: all 60Hz refresh? 1806 */ 1807 static const struct drm_display_mode sdvo_tv_modes[] = { 1808 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1809 416, 0, 200, 201, 232, 233, 0, 1810 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1811 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1812 416, 0, 240, 241, 272, 273, 0, 1813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1814 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1815 496, 0, 300, 301, 332, 333, 0, 1816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1817 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1818 736, 0, 350, 351, 382, 383, 0, 1819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1820 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1821 736, 0, 400, 401, 432, 433, 0, 1822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1823 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1824 736, 0, 480, 481, 512, 513, 0, 1825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1826 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1827 800, 0, 480, 481, 512, 513, 0, 1828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1829 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1830 800, 0, 576, 577, 608, 609, 0, 1831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1832 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1833 816, 0, 350, 351, 382, 383, 0, 1834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1835 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1836 816, 0, 400, 401, 432, 433, 0, 1837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1838 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1839 816, 0, 480, 481, 512, 513, 0, 1840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1841 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1842 816, 0, 540, 541, 572, 573, 0, 1843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1844 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1845 816, 0, 576, 577, 608, 609, 0, 1846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1847 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1848 864, 0, 576, 577, 608, 609, 0, 1849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1850 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1851 896, 0, 600, 601, 632, 633, 0, 1852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1853 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1854 928, 0, 624, 625, 656, 657, 0, 1855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1856 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1857 1016, 0, 766, 767, 798, 799, 0, 1858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1859 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1860 1120, 0, 768, 769, 800, 801, 0, 1861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1862 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1863 1376, 0, 1024, 1025, 1056, 1057, 0, 1864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1865 }; 1866 1867 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1868 { 1869 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1870 struct intel_sdvo_sdtv_resolution_request tv_res; 1871 uint32_t reply = 0, format_map = 0; 1872 int i; 1873 1874 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1875 connector->base.id, connector->name); 1876 1877 /* Read the list of supported input resolutions for the selected TV 1878 * format. 1879 */ 1880 format_map = 1 << intel_sdvo->tv_format_index; 1881 memcpy(&tv_res, &format_map, 1882 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1883 1884 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1885 return; 1886 1887 BUILD_BUG_ON(sizeof(tv_res) != 3); 1888 if (!intel_sdvo_write_cmd(intel_sdvo, 1889 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1890 &tv_res, sizeof(tv_res))) 1891 return; 1892 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1893 return; 1894 1895 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1896 if (reply & (1 << i)) { 1897 struct drm_display_mode *nmode; 1898 nmode = drm_mode_duplicate(connector->dev, 1899 &sdvo_tv_modes[i]); 1900 if (nmode) 1901 drm_mode_probed_add(connector, nmode); 1902 } 1903 } 1904 1905 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1906 { 1907 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1908 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1909 struct drm_display_mode *newmode; 1910 1911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 1912 connector->base.id, connector->name); 1913 1914 /* 1915 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 1916 * SDVO->LVDS transcoders can't cope with the EDID mode. 1917 */ 1918 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 1919 newmode = drm_mode_duplicate(connector->dev, 1920 dev_priv->vbt.sdvo_lvds_vbt_mode); 1921 if (newmode != NULL) { 1922 /* Guarantee the mode is preferred */ 1923 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1924 DRM_MODE_TYPE_DRIVER); 1925 drm_mode_probed_add(connector, newmode); 1926 } 1927 } 1928 1929 /* 1930 * Attempt to get the mode list from DDC. 1931 * Assume that the preferred modes are 1932 * arranged in priority order. 1933 */ 1934 intel_ddc_get_modes(connector, intel_sdvo->ddc); 1935 1936 list_for_each_entry(newmode, &connector->probed_modes, head) { 1937 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1938 intel_sdvo->sdvo_lvds_fixed_mode = 1939 drm_mode_duplicate(connector->dev, newmode); 1940 1941 intel_sdvo->is_lvds = true; 1942 break; 1943 } 1944 } 1945 } 1946 1947 static int intel_sdvo_get_modes(struct drm_connector *connector) 1948 { 1949 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1950 1951 if (IS_TV(intel_sdvo_connector)) 1952 intel_sdvo_get_tv_modes(connector); 1953 else if (IS_LVDS(intel_sdvo_connector)) 1954 intel_sdvo_get_lvds_modes(connector); 1955 else 1956 intel_sdvo_get_ddc_modes(connector); 1957 1958 return !list_empty(&connector->probed_modes); 1959 } 1960 1961 static void intel_sdvo_destroy(struct drm_connector *connector) 1962 { 1963 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1964 1965 drm_connector_cleanup(connector); 1966 kfree(intel_sdvo_connector); 1967 } 1968 1969 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 1970 { 1971 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1972 struct edid *edid; 1973 bool has_audio = false; 1974 1975 if (!intel_sdvo->is_hdmi) 1976 return false; 1977 1978 edid = intel_sdvo_get_edid(connector); 1979 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 1980 has_audio = drm_detect_monitor_audio(edid); 1981 kfree(edid); 1982 1983 return has_audio; 1984 } 1985 1986 static int 1987 intel_sdvo_set_property(struct drm_connector *connector, 1988 struct drm_property *property, 1989 uint64_t val) 1990 { 1991 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1992 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1993 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1994 uint16_t temp_value; 1995 uint8_t cmd; 1996 int ret; 1997 1998 ret = drm_object_property_set_value(&connector->base, property, val); 1999 if (ret) 2000 return ret; 2001 2002 if (property == dev_priv->force_audio_property) { 2003 int i = val; 2004 bool has_audio; 2005 2006 if (i == intel_sdvo_connector->force_audio) 2007 return 0; 2008 2009 intel_sdvo_connector->force_audio = i; 2010 2011 if (i == HDMI_AUDIO_AUTO) 2012 has_audio = intel_sdvo_detect_hdmi_audio(connector); 2013 else 2014 has_audio = (i == HDMI_AUDIO_ON); 2015 2016 if (has_audio == intel_sdvo->has_hdmi_audio) 2017 return 0; 2018 2019 intel_sdvo->has_hdmi_audio = has_audio; 2020 goto done; 2021 } 2022 2023 if (property == dev_priv->broadcast_rgb_property) { 2024 bool old_auto = intel_sdvo->color_range_auto; 2025 uint32_t old_range = intel_sdvo->color_range; 2026 2027 switch (val) { 2028 case INTEL_BROADCAST_RGB_AUTO: 2029 intel_sdvo->color_range_auto = true; 2030 break; 2031 case INTEL_BROADCAST_RGB_FULL: 2032 intel_sdvo->color_range_auto = false; 2033 intel_sdvo->color_range = 0; 2034 break; 2035 case INTEL_BROADCAST_RGB_LIMITED: 2036 intel_sdvo->color_range_auto = false; 2037 /* FIXME: this bit is only valid when using TMDS 2038 * encoding and 8 bit per color mode. */ 2039 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; 2040 break; 2041 default: 2042 return -EINVAL; 2043 } 2044 2045 if (old_auto == intel_sdvo->color_range_auto && 2046 old_range == intel_sdvo->color_range) 2047 return 0; 2048 2049 goto done; 2050 } 2051 2052 #define CHECK_PROPERTY(name, NAME) \ 2053 if (intel_sdvo_connector->name == property) { \ 2054 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 2055 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 2056 cmd = SDVO_CMD_SET_##NAME; \ 2057 intel_sdvo_connector->cur_##name = temp_value; \ 2058 goto set_value; \ 2059 } 2060 2061 if (property == intel_sdvo_connector->tv_format) { 2062 if (val >= TV_FORMAT_NUM) 2063 return -EINVAL; 2064 2065 if (intel_sdvo->tv_format_index == 2066 intel_sdvo_connector->tv_format_supported[val]) 2067 return 0; 2068 2069 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 2070 goto done; 2071 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 2072 temp_value = val; 2073 if (intel_sdvo_connector->left == property) { 2074 drm_object_property_set_value(&connector->base, 2075 intel_sdvo_connector->right, val); 2076 if (intel_sdvo_connector->left_margin == temp_value) 2077 return 0; 2078 2079 intel_sdvo_connector->left_margin = temp_value; 2080 intel_sdvo_connector->right_margin = temp_value; 2081 temp_value = intel_sdvo_connector->max_hscan - 2082 intel_sdvo_connector->left_margin; 2083 cmd = SDVO_CMD_SET_OVERSCAN_H; 2084 goto set_value; 2085 } else if (intel_sdvo_connector->right == property) { 2086 drm_object_property_set_value(&connector->base, 2087 intel_sdvo_connector->left, val); 2088 if (intel_sdvo_connector->right_margin == temp_value) 2089 return 0; 2090 2091 intel_sdvo_connector->left_margin = temp_value; 2092 intel_sdvo_connector->right_margin = temp_value; 2093 temp_value = intel_sdvo_connector->max_hscan - 2094 intel_sdvo_connector->left_margin; 2095 cmd = SDVO_CMD_SET_OVERSCAN_H; 2096 goto set_value; 2097 } else if (intel_sdvo_connector->top == property) { 2098 drm_object_property_set_value(&connector->base, 2099 intel_sdvo_connector->bottom, val); 2100 if (intel_sdvo_connector->top_margin == temp_value) 2101 return 0; 2102 2103 intel_sdvo_connector->top_margin = temp_value; 2104 intel_sdvo_connector->bottom_margin = temp_value; 2105 temp_value = intel_sdvo_connector->max_vscan - 2106 intel_sdvo_connector->top_margin; 2107 cmd = SDVO_CMD_SET_OVERSCAN_V; 2108 goto set_value; 2109 } else if (intel_sdvo_connector->bottom == property) { 2110 drm_object_property_set_value(&connector->base, 2111 intel_sdvo_connector->top, val); 2112 if (intel_sdvo_connector->bottom_margin == temp_value) 2113 return 0; 2114 2115 intel_sdvo_connector->top_margin = temp_value; 2116 intel_sdvo_connector->bottom_margin = temp_value; 2117 temp_value = intel_sdvo_connector->max_vscan - 2118 intel_sdvo_connector->top_margin; 2119 cmd = SDVO_CMD_SET_OVERSCAN_V; 2120 goto set_value; 2121 } 2122 CHECK_PROPERTY(hpos, HPOS) 2123 CHECK_PROPERTY(vpos, VPOS) 2124 CHECK_PROPERTY(saturation, SATURATION) 2125 CHECK_PROPERTY(contrast, CONTRAST) 2126 CHECK_PROPERTY(hue, HUE) 2127 CHECK_PROPERTY(brightness, BRIGHTNESS) 2128 CHECK_PROPERTY(sharpness, SHARPNESS) 2129 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 2130 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 2131 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 2132 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 2133 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 2134 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 2135 } 2136 2137 return -EINVAL; /* unknown property */ 2138 2139 set_value: 2140 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 2141 return -EIO; 2142 2143 2144 done: 2145 if (intel_sdvo->base.base.crtc) 2146 intel_crtc_restore_mode(intel_sdvo->base.base.crtc); 2147 2148 return 0; 2149 #undef CHECK_PROPERTY 2150 } 2151 2152 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2153 .dpms = drm_atomic_helper_connector_dpms, 2154 .detect = intel_sdvo_detect, 2155 .fill_modes = drm_helper_probe_single_connector_modes, 2156 .set_property = intel_sdvo_set_property, 2157 .atomic_get_property = intel_connector_atomic_get_property, 2158 .destroy = intel_sdvo_destroy, 2159 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2160 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2161 }; 2162 2163 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2164 .get_modes = intel_sdvo_get_modes, 2165 .mode_valid = intel_sdvo_mode_valid, 2166 .best_encoder = intel_best_encoder, 2167 }; 2168 2169 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2170 { 2171 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); 2172 2173 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 2174 drm_mode_destroy(encoder->dev, 2175 intel_sdvo->sdvo_lvds_fixed_mode); 2176 2177 device_delete_child(intel_sdvo->base.base.dev->dev, 2178 intel_sdvo->ddc_iic_bus); 2179 intel_encoder_destroy(encoder); 2180 } 2181 2182 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2183 .destroy = intel_sdvo_enc_destroy, 2184 }; 2185 2186 static void 2187 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2188 { 2189 uint16_t mask = 0; 2190 unsigned int num_bits; 2191 2192 /* Make a mask of outputs less than or equal to our own priority in the 2193 * list. 2194 */ 2195 switch (sdvo->controlled_output) { 2196 case SDVO_OUTPUT_LVDS1: 2197 mask |= SDVO_OUTPUT_LVDS1; 2198 case SDVO_OUTPUT_LVDS0: 2199 mask |= SDVO_OUTPUT_LVDS0; 2200 case SDVO_OUTPUT_TMDS1: 2201 mask |= SDVO_OUTPUT_TMDS1; 2202 case SDVO_OUTPUT_TMDS0: 2203 mask |= SDVO_OUTPUT_TMDS0; 2204 case SDVO_OUTPUT_RGB1: 2205 mask |= SDVO_OUTPUT_RGB1; 2206 case SDVO_OUTPUT_RGB0: 2207 mask |= SDVO_OUTPUT_RGB0; 2208 break; 2209 } 2210 2211 /* Count bits to find what number we are in the priority list. */ 2212 mask &= sdvo->caps.output_flags; 2213 num_bits = hweight16(mask); 2214 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2215 if (num_bits > 3) 2216 num_bits = 3; 2217 2218 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2219 sdvo->ddc_bus = 1 << num_bits; 2220 } 2221 2222 /** 2223 * Choose the appropriate DDC bus for control bus switch command for this 2224 * SDVO output based on the controlled output. 2225 * 2226 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2227 * outputs, then LVDS outputs. 2228 */ 2229 static void 2230 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2231 struct intel_sdvo *sdvo, u32 reg) 2232 { 2233 struct sdvo_device_mapping *mapping; 2234 2235 if (sdvo->is_sdvob) 2236 mapping = &(dev_priv->sdvo_mappings[0]); 2237 else 2238 mapping = &(dev_priv->sdvo_mappings[1]); 2239 2240 if (mapping->initialized) 2241 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2242 else 2243 intel_sdvo_guess_ddc_bus(sdvo); 2244 } 2245 2246 static void 2247 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2248 struct intel_sdvo *sdvo, u32 reg) 2249 { 2250 struct sdvo_device_mapping *mapping; 2251 u8 pin; 2252 2253 if (sdvo->is_sdvob) 2254 mapping = &dev_priv->sdvo_mappings[0]; 2255 else 2256 mapping = &dev_priv->sdvo_mappings[1]; 2257 2258 if (mapping->initialized && 2259 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) 2260 pin = mapping->i2c_pin; 2261 else 2262 pin = GMBUS_PIN_DPB; 2263 2264 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2265 2266 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2267 * our code totally fails once we start using gmbus. Hence fall back to 2268 * bit banging for now. */ 2269 intel_gmbus_force_bit(sdvo->i2c, true); 2270 } 2271 2272 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2273 static void 2274 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2275 { 2276 intel_gmbus_force_bit(sdvo->i2c, false); 2277 } 2278 2279 static bool 2280 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2281 { 2282 return intel_sdvo_check_supp_encode(intel_sdvo); 2283 } 2284 2285 static u8 2286 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) 2287 { 2288 struct drm_i915_private *dev_priv = dev->dev_private; 2289 struct sdvo_device_mapping *my_mapping, *other_mapping; 2290 2291 if (sdvo->is_sdvob) { 2292 my_mapping = &dev_priv->sdvo_mappings[0]; 2293 other_mapping = &dev_priv->sdvo_mappings[1]; 2294 } else { 2295 my_mapping = &dev_priv->sdvo_mappings[1]; 2296 other_mapping = &dev_priv->sdvo_mappings[0]; 2297 } 2298 2299 /* If the BIOS described our SDVO device, take advantage of it. */ 2300 if (my_mapping->slave_addr) 2301 return my_mapping->slave_addr; 2302 2303 /* If the BIOS only described a different SDVO device, use the 2304 * address that it isn't using. 2305 */ 2306 if (other_mapping->slave_addr) { 2307 if (other_mapping->slave_addr == 0x70) 2308 return 0x72; 2309 else 2310 return 0x70; 2311 } 2312 2313 /* No SDVO device info is found for another DVO port, 2314 * so use mapping assumption we had before BIOS parsing. 2315 */ 2316 if (sdvo->is_sdvob) 2317 return 0x70; 2318 else 2319 return 0x72; 2320 } 2321 2322 static void 2323 intel_sdvo_connector_unregister(struct intel_connector *intel_connector) 2324 { 2325 struct drm_connector *drm_connector; 2326 struct intel_sdvo *sdvo_encoder; 2327 2328 drm_connector = &intel_connector->base; 2329 sdvo_encoder = intel_attached_sdvo(&intel_connector->base); 2330 2331 intel_connector_unregister(intel_connector); 2332 } 2333 2334 static int 2335 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2336 struct intel_sdvo *encoder) 2337 { 2338 struct drm_connector *drm_connector; 2339 int ret; 2340 2341 drm_connector = &connector->base.base; 2342 ret = drm_connector_init(encoder->base.base.dev, 2343 drm_connector, 2344 &intel_sdvo_connector_funcs, 2345 connector->base.base.connector_type); 2346 if (ret < 0) 2347 return ret; 2348 2349 drm_connector_helper_add(drm_connector, 2350 &intel_sdvo_connector_helper_funcs); 2351 2352 connector->base.base.interlace_allowed = 1; 2353 connector->base.base.doublescan_allowed = 0; 2354 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2355 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2356 connector->base.unregister = intel_sdvo_connector_unregister; 2357 2358 intel_connector_attach_encoder(&connector->base, &encoder->base); 2359 ret = drm_connector_register(drm_connector); 2360 if (ret < 0) 2361 goto err1; 2362 2363 #if 0 2364 ret = sysfs_create_link(&encoder->ddc.dev.kobj, 2365 &drm_connector->kdev->kobj, 2366 encoder->ddc.dev.kobj.name); 2367 if (ret < 0) 2368 goto err2; 2369 2370 return 0; 2371 2372 err2: 2373 #endif 2374 drm_connector_unregister(drm_connector); 2375 err1: 2376 drm_connector_cleanup(drm_connector); 2377 2378 return ret; 2379 } 2380 2381 static void 2382 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2383 struct intel_sdvo_connector *connector) 2384 { 2385 struct drm_device *dev = connector->base.base.dev; 2386 2387 intel_attach_force_audio_property(&connector->base.base); 2388 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { 2389 intel_attach_broadcast_rgb_property(&connector->base.base); 2390 intel_sdvo->color_range_auto = true; 2391 } 2392 } 2393 2394 static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) 2395 { 2396 struct intel_sdvo_connector *sdvo_connector; 2397 2398 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); 2399 if (!sdvo_connector) 2400 return NULL; 2401 2402 if (intel_connector_init(&sdvo_connector->base) < 0) { 2403 kfree(sdvo_connector); 2404 return NULL; 2405 } 2406 2407 return sdvo_connector; 2408 } 2409 2410 static bool 2411 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2412 { 2413 struct drm_encoder *encoder = &intel_sdvo->base.base; 2414 struct drm_connector *connector; 2415 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2416 struct intel_connector *intel_connector; 2417 struct intel_sdvo_connector *intel_sdvo_connector; 2418 2419 DRM_DEBUG_KMS("initialising DVI device %d\n", device); 2420 2421 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2422 if (!intel_sdvo_connector) 2423 return false; 2424 2425 if (device == 0) { 2426 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2427 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2428 } else if (device == 1) { 2429 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2430 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2431 } 2432 2433 intel_connector = &intel_sdvo_connector->base; 2434 connector = &intel_connector->base; 2435 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2436 intel_sdvo_connector->output_flag) { 2437 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2438 /* Some SDVO devices have one-shot hotplug interrupts. 2439 * Ensure that they get re-enabled when an interrupt happens. 2440 */ 2441 intel_encoder->hot_plug = intel_sdvo_enable_hotplug; 2442 intel_sdvo_enable_hotplug(intel_encoder); 2443 } else { 2444 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2445 } 2446 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2447 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2448 2449 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2450 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2451 intel_sdvo->is_hdmi = true; 2452 } 2453 2454 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2455 kfree(intel_sdvo_connector); 2456 return false; 2457 } 2458 2459 if (intel_sdvo->is_hdmi) 2460 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2461 2462 return true; 2463 } 2464 2465 static bool 2466 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2467 { 2468 struct drm_encoder *encoder = &intel_sdvo->base.base; 2469 struct drm_connector *connector; 2470 struct intel_connector *intel_connector; 2471 struct intel_sdvo_connector *intel_sdvo_connector; 2472 2473 DRM_DEBUG_KMS("initialising TV type %d\n", type); 2474 2475 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2476 if (!intel_sdvo_connector) 2477 return false; 2478 2479 intel_connector = &intel_sdvo_connector->base; 2480 connector = &intel_connector->base; 2481 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2482 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2483 2484 intel_sdvo->controlled_output |= type; 2485 intel_sdvo_connector->output_flag = type; 2486 2487 intel_sdvo->is_tv = true; 2488 2489 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2490 kfree(intel_sdvo_connector); 2491 return false; 2492 } 2493 2494 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2495 goto err; 2496 2497 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2498 goto err; 2499 2500 return true; 2501 2502 err: 2503 drm_connector_unregister(connector); 2504 intel_sdvo_destroy(connector); 2505 return false; 2506 } 2507 2508 static bool 2509 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2510 { 2511 struct drm_encoder *encoder = &intel_sdvo->base.base; 2512 struct drm_connector *connector; 2513 struct intel_connector *intel_connector; 2514 struct intel_sdvo_connector *intel_sdvo_connector; 2515 2516 DRM_DEBUG_KMS("initialising analog device %d\n", device); 2517 2518 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2519 if (!intel_sdvo_connector) 2520 return false; 2521 2522 intel_connector = &intel_sdvo_connector->base; 2523 connector = &intel_connector->base; 2524 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2525 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2526 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2527 2528 if (device == 0) { 2529 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2530 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2531 } else if (device == 1) { 2532 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2533 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2534 } 2535 2536 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2537 kfree(intel_sdvo_connector); 2538 return false; 2539 } 2540 2541 return true; 2542 } 2543 2544 static bool 2545 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2546 { 2547 struct drm_encoder *encoder = &intel_sdvo->base.base; 2548 struct drm_connector *connector; 2549 struct intel_connector *intel_connector; 2550 struct intel_sdvo_connector *intel_sdvo_connector; 2551 2552 DRM_DEBUG_KMS("initialising LVDS device %d\n", device); 2553 2554 intel_sdvo_connector = intel_sdvo_connector_alloc(); 2555 if (!intel_sdvo_connector) 2556 return false; 2557 2558 intel_connector = &intel_sdvo_connector->base; 2559 connector = &intel_connector->base; 2560 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2561 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2562 2563 if (device == 0) { 2564 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2565 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2566 } else if (device == 1) { 2567 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2568 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2569 } 2570 2571 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { 2572 kfree(intel_sdvo_connector); 2573 return false; 2574 } 2575 2576 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2577 goto err; 2578 2579 return true; 2580 2581 err: 2582 drm_connector_unregister(connector); 2583 intel_sdvo_destroy(connector); 2584 return false; 2585 } 2586 2587 static bool 2588 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2589 { 2590 intel_sdvo->is_tv = false; 2591 intel_sdvo->is_lvds = false; 2592 2593 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2594 2595 if (flags & SDVO_OUTPUT_TMDS0) 2596 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2597 return false; 2598 2599 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2600 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2601 return false; 2602 2603 /* TV has no XXX1 function block */ 2604 if (flags & SDVO_OUTPUT_SVID0) 2605 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2606 return false; 2607 2608 if (flags & SDVO_OUTPUT_CVBS0) 2609 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2610 return false; 2611 2612 if (flags & SDVO_OUTPUT_YPRPB0) 2613 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2614 return false; 2615 2616 if (flags & SDVO_OUTPUT_RGB0) 2617 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2618 return false; 2619 2620 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2621 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2622 return false; 2623 2624 if (flags & SDVO_OUTPUT_LVDS0) 2625 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2626 return false; 2627 2628 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2629 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2630 return false; 2631 2632 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2633 unsigned char bytes[2]; 2634 2635 intel_sdvo->controlled_output = 0; 2636 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2637 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2638 SDVO_NAME(intel_sdvo), 2639 bytes[0], bytes[1]); 2640 return false; 2641 } 2642 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2643 2644 return true; 2645 } 2646 2647 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2648 { 2649 struct drm_device *dev = intel_sdvo->base.base.dev; 2650 struct drm_connector *connector, *tmp; 2651 2652 list_for_each_entry_safe(connector, tmp, 2653 &dev->mode_config.connector_list, head) { 2654 if (intel_attached_encoder(connector) == &intel_sdvo->base) { 2655 drm_connector_unregister(connector); 2656 intel_sdvo_destroy(connector); 2657 } 2658 } 2659 } 2660 2661 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2662 struct intel_sdvo_connector *intel_sdvo_connector, 2663 int type) 2664 { 2665 struct drm_device *dev = intel_sdvo->base.base.dev; 2666 struct intel_sdvo_tv_format format; 2667 uint32_t format_map, i; 2668 2669 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2670 return false; 2671 2672 BUILD_BUG_ON(sizeof(format) != 6); 2673 if (!intel_sdvo_get_value(intel_sdvo, 2674 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2675 &format, sizeof(format))) 2676 return false; 2677 2678 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2679 2680 if (format_map == 0) 2681 return false; 2682 2683 intel_sdvo_connector->format_supported_num = 0; 2684 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2685 if (format_map & (1 << i)) 2686 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2687 2688 2689 intel_sdvo_connector->tv_format = 2690 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2691 "mode", intel_sdvo_connector->format_supported_num); 2692 if (!intel_sdvo_connector->tv_format) 2693 return false; 2694 2695 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2696 drm_property_add_enum( 2697 intel_sdvo_connector->tv_format, i, 2698 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2699 2700 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2701 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2702 intel_sdvo_connector->tv_format, 0); 2703 return true; 2704 2705 } 2706 2707 #define ENHANCEMENT(name, NAME) do { \ 2708 if (enhancements.name) { \ 2709 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2710 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2711 return false; \ 2712 intel_sdvo_connector->max_##name = data_value[0]; \ 2713 intel_sdvo_connector->cur_##name = response; \ 2714 intel_sdvo_connector->name = \ 2715 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2716 if (!intel_sdvo_connector->name) return false; \ 2717 drm_object_attach_property(&connector->base, \ 2718 intel_sdvo_connector->name, \ 2719 intel_sdvo_connector->cur_##name); \ 2720 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2721 data_value[0], data_value[1], response); \ 2722 } \ 2723 } while (0) 2724 2725 static bool 2726 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2727 struct intel_sdvo_connector *intel_sdvo_connector, 2728 struct intel_sdvo_enhancements_reply enhancements) 2729 { 2730 struct drm_device *dev = intel_sdvo->base.base.dev; 2731 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2732 uint16_t response, data_value[2]; 2733 2734 /* when horizontal overscan is supported, Add the left/right property */ 2735 if (enhancements.overscan_h) { 2736 if (!intel_sdvo_get_value(intel_sdvo, 2737 SDVO_CMD_GET_MAX_OVERSCAN_H, 2738 &data_value, 4)) 2739 return false; 2740 2741 if (!intel_sdvo_get_value(intel_sdvo, 2742 SDVO_CMD_GET_OVERSCAN_H, 2743 &response, 2)) 2744 return false; 2745 2746 intel_sdvo_connector->max_hscan = data_value[0]; 2747 intel_sdvo_connector->left_margin = data_value[0] - response; 2748 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2749 intel_sdvo_connector->left = 2750 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2751 if (!intel_sdvo_connector->left) 2752 return false; 2753 2754 drm_object_attach_property(&connector->base, 2755 intel_sdvo_connector->left, 2756 intel_sdvo_connector->left_margin); 2757 2758 intel_sdvo_connector->right = 2759 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2760 if (!intel_sdvo_connector->right) 2761 return false; 2762 2763 drm_object_attach_property(&connector->base, 2764 intel_sdvo_connector->right, 2765 intel_sdvo_connector->right_margin); 2766 DRM_DEBUG_KMS("h_overscan: max %d, " 2767 "default %d, current %d\n", 2768 data_value[0], data_value[1], response); 2769 } 2770 2771 if (enhancements.overscan_v) { 2772 if (!intel_sdvo_get_value(intel_sdvo, 2773 SDVO_CMD_GET_MAX_OVERSCAN_V, 2774 &data_value, 4)) 2775 return false; 2776 2777 if (!intel_sdvo_get_value(intel_sdvo, 2778 SDVO_CMD_GET_OVERSCAN_V, 2779 &response, 2)) 2780 return false; 2781 2782 intel_sdvo_connector->max_vscan = data_value[0]; 2783 intel_sdvo_connector->top_margin = data_value[0] - response; 2784 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2785 intel_sdvo_connector->top = 2786 drm_property_create_range(dev, 0, 2787 "top_margin", 0, data_value[0]); 2788 if (!intel_sdvo_connector->top) 2789 return false; 2790 2791 drm_object_attach_property(&connector->base, 2792 intel_sdvo_connector->top, 2793 intel_sdvo_connector->top_margin); 2794 2795 intel_sdvo_connector->bottom = 2796 drm_property_create_range(dev, 0, 2797 "bottom_margin", 0, data_value[0]); 2798 if (!intel_sdvo_connector->bottom) 2799 return false; 2800 2801 drm_object_attach_property(&connector->base, 2802 intel_sdvo_connector->bottom, 2803 intel_sdvo_connector->bottom_margin); 2804 DRM_DEBUG_KMS("v_overscan: max %d, " 2805 "default %d, current %d\n", 2806 data_value[0], data_value[1], response); 2807 } 2808 2809 ENHANCEMENT(hpos, HPOS); 2810 ENHANCEMENT(vpos, VPOS); 2811 ENHANCEMENT(saturation, SATURATION); 2812 ENHANCEMENT(contrast, CONTRAST); 2813 ENHANCEMENT(hue, HUE); 2814 ENHANCEMENT(sharpness, SHARPNESS); 2815 ENHANCEMENT(brightness, BRIGHTNESS); 2816 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2817 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2818 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2819 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2820 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2821 2822 if (enhancements.dot_crawl) { 2823 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2824 return false; 2825 2826 intel_sdvo_connector->max_dot_crawl = 1; 2827 intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2828 intel_sdvo_connector->dot_crawl = 2829 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2830 if (!intel_sdvo_connector->dot_crawl) 2831 return false; 2832 2833 drm_object_attach_property(&connector->base, 2834 intel_sdvo_connector->dot_crawl, 2835 intel_sdvo_connector->cur_dot_crawl); 2836 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2837 } 2838 2839 return true; 2840 } 2841 2842 static bool 2843 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2844 struct intel_sdvo_connector *intel_sdvo_connector, 2845 struct intel_sdvo_enhancements_reply enhancements) 2846 { 2847 struct drm_device *dev = intel_sdvo->base.base.dev; 2848 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2849 uint16_t response, data_value[2]; 2850 2851 ENHANCEMENT(brightness, BRIGHTNESS); 2852 2853 return true; 2854 } 2855 #undef ENHANCEMENT 2856 2857 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2858 struct intel_sdvo_connector *intel_sdvo_connector) 2859 { 2860 union { 2861 struct intel_sdvo_enhancements_reply reply; 2862 uint16_t response; 2863 } enhancements; 2864 2865 BUILD_BUG_ON(sizeof(enhancements) != 2); 2866 2867 enhancements.response = 0; 2868 intel_sdvo_get_value(intel_sdvo, 2869 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2870 &enhancements, sizeof(enhancements)); 2871 if (enhancements.response == 0) { 2872 DRM_DEBUG_KMS("No enhancement is supported\n"); 2873 return true; 2874 } 2875 2876 if (IS_TV(intel_sdvo_connector)) 2877 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2878 else if (IS_LVDS(intel_sdvo_connector)) 2879 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2880 else 2881 return true; 2882 } 2883 2884 struct intel_sdvo_ddc_proxy_sc { 2885 struct intel_sdvo *intel_sdvo; 2886 device_t port; 2887 }; 2888 2889 static int 2890 intel_sdvo_ddc_proxy_probe(device_t idev) 2891 { 2892 2893 return (BUS_PROBE_DEFAULT); 2894 } 2895 2896 static int 2897 intel_sdvo_ddc_proxy_attach(device_t idev) 2898 { 2899 struct intel_sdvo_ddc_proxy_sc *sc; 2900 2901 sc = device_get_softc(idev); 2902 sc->port = device_add_child(idev, "iicbus", -1); 2903 if (sc->port == NULL) 2904 return (ENXIO); 2905 device_quiet(sc->port); 2906 bus_generic_attach(idev); 2907 return (0); 2908 } 2909 2910 static int 2911 intel_sdvo_ddc_proxy_detach(device_t idev) 2912 { 2913 struct intel_sdvo_ddc_proxy_sc *sc; 2914 device_t port; 2915 2916 sc = device_get_softc(idev); 2917 port = sc->port; 2918 bus_generic_detach(idev); 2919 if (port != NULL) 2920 device_delete_child(idev, port); 2921 return (0); 2922 } 2923 2924 static int 2925 intel_sdvo_ddc_proxy_reset(device_t idev, u_char speed, u_char addr, 2926 u_char *oldaddr) 2927 { 2928 struct intel_sdvo_ddc_proxy_sc *sc; 2929 struct intel_sdvo *sdvo; 2930 2931 sc = device_get_softc(idev); 2932 sdvo = sc->intel_sdvo; 2933 2934 return (IICBUS_RESET(device_get_parent(sdvo->i2c), speed, addr, 2935 oldaddr)); 2936 } 2937 2938 static int intel_sdvo_ddc_proxy_xfer(struct device *adapter, 2939 struct i2c_msg *msgs, 2940 int num) 2941 { 2942 struct intel_sdvo_ddc_proxy_sc *sc = device_get_softc(adapter); 2943 struct intel_sdvo *sdvo = sc->intel_sdvo; 2944 2945 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2946 return -EIO; 2947 2948 return (iicbus_transfer(sdvo->i2c, msgs, num)); 2949 } 2950 2951 static bool 2952 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, struct drm_device *dev, 2953 int sdvo_reg) 2954 { 2955 struct intel_sdvo_ddc_proxy_sc *sc; 2956 int ret; 2957 2958 sdvo->ddc_iic_bus = device_add_child(dev->dev, 2959 "intel_sdvo_ddc_proxy", sdvo_reg); 2960 if (sdvo->ddc_iic_bus == NULL) { 2961 DRM_ERROR("cannot create ddc proxy bus %d\n", sdvo_reg); 2962 return (false); 2963 } 2964 device_quiet(sdvo->ddc_iic_bus); 2965 ret = device_probe_and_attach(sdvo->ddc_iic_bus); 2966 if (ret != 0) { 2967 DRM_ERROR("cannot attach proxy bus %d error %d\n", 2968 sdvo_reg, ret); 2969 device_delete_child(dev->dev, sdvo->ddc_iic_bus); 2970 return (false); 2971 } 2972 sc = device_get_softc(sdvo->ddc_iic_bus); 2973 sc->intel_sdvo = sdvo; 2974 2975 sdvo->ddc = sc->port; 2976 return (true); 2977 } 2978 2979 static device_method_t intel_sdvo_ddc_proxy_methods[] = { 2980 DEVMETHOD(device_probe, intel_sdvo_ddc_proxy_probe), 2981 DEVMETHOD(device_attach, intel_sdvo_ddc_proxy_attach), 2982 DEVMETHOD(device_detach, intel_sdvo_ddc_proxy_detach), 2983 DEVMETHOD(iicbus_reset, intel_sdvo_ddc_proxy_reset), 2984 DEVMETHOD(iicbus_transfer, intel_sdvo_ddc_proxy_xfer), 2985 DEVMETHOD_END 2986 }; 2987 static driver_t intel_sdvo_ddc_proxy_driver = { 2988 "intel_sdvo_ddc_proxy", 2989 intel_sdvo_ddc_proxy_methods, 2990 sizeof(struct intel_sdvo_ddc_proxy_sc) 2991 }; 2992 static devclass_t intel_sdvo_devclass; 2993 DRIVER_MODULE_ORDERED(intel_sdvo_ddc_proxy, drm, intel_sdvo_ddc_proxy_driver, 2994 intel_sdvo_devclass, NULL, NULL, SI_ORDER_FIRST); 2995 2996 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) 2997 { 2998 struct drm_i915_private *dev_priv = dev->dev_private; 2999 struct intel_encoder *intel_encoder; 3000 struct intel_sdvo *intel_sdvo; 3001 int i; 3002 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); 3003 if (!intel_sdvo) 3004 return false; 3005 3006 intel_sdvo->sdvo_reg = sdvo_reg; 3007 intel_sdvo->is_sdvob = is_sdvob; 3008 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; 3009 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); 3010 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev, sdvo_reg)) 3011 goto err_i2c_bus; 3012 3013 /* encoder type will be decided later */ 3014 intel_encoder = &intel_sdvo->base; 3015 intel_encoder->type = INTEL_OUTPUT_SDVO; 3016 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); 3017 3018 /* Read the regs to test if we can talk to the device */ 3019 for (i = 0; i < 0x40; i++) { 3020 u8 byte; 3021 3022 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 3023 DRM_DEBUG_KMS("No SDVO device found on %s\n", 3024 SDVO_NAME(intel_sdvo)); 3025 goto err; 3026 } 3027 } 3028 3029 intel_encoder->compute_config = intel_sdvo_compute_config; 3030 if (HAS_PCH_SPLIT(dev)) { 3031 intel_encoder->disable = pch_disable_sdvo; 3032 intel_encoder->post_disable = pch_post_disable_sdvo; 3033 } else { 3034 intel_encoder->disable = intel_disable_sdvo; 3035 } 3036 intel_encoder->pre_enable = intel_sdvo_pre_enable; 3037 intel_encoder->enable = intel_enable_sdvo; 3038 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 3039 intel_encoder->get_config = intel_sdvo_get_config; 3040 3041 /* In default case sdvo lvds is false */ 3042 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 3043 goto err; 3044 3045 if (intel_sdvo_output_setup(intel_sdvo, 3046 intel_sdvo->caps.output_flags) != true) { 3047 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 3048 SDVO_NAME(intel_sdvo)); 3049 /* Output_setup can leave behind connectors! */ 3050 goto err_output; 3051 } 3052 3053 /* Only enable the hotplug irq if we need it, to work around noisy 3054 * hotplug lines. 3055 */ 3056 if (intel_sdvo->hotplug_active) { 3057 intel_encoder->hpd_pin = 3058 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; 3059 } 3060 3061 /* 3062 * Cloning SDVO with anything is often impossible, since the SDVO 3063 * encoder can request a special input timing mode. And even if that's 3064 * not the case we have evidence that cloning a plain unscaled mode with 3065 * VGA doesn't really work. Furthermore the cloning flags are way too 3066 * simplistic anyway to express such constraints, so just give up on 3067 * cloning for SDVO encoders. 3068 */ 3069 intel_sdvo->base.cloneable = 0; 3070 3071 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); 3072 3073 /* Set the input timing to the screen. Assume always input 0. */ 3074 if (!intel_sdvo_set_target_input(intel_sdvo)) 3075 goto err_output; 3076 3077 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3078 &intel_sdvo->pixel_clock_min, 3079 &intel_sdvo->pixel_clock_max)) 3080 goto err_output; 3081 3082 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 3083 "clock range %dMHz - %dMHz, " 3084 "input 1: %c, input 2: %c, " 3085 "output 1: %c, output 2: %c\n", 3086 SDVO_NAME(intel_sdvo), 3087 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3088 intel_sdvo->caps.device_rev_id, 3089 intel_sdvo->pixel_clock_min / 1000, 3090 intel_sdvo->pixel_clock_max / 1000, 3091 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3092 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3093 /* check currently supported outputs */ 3094 intel_sdvo->caps.output_flags & 3095 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3096 intel_sdvo->caps.output_flags & 3097 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3098 return true; 3099 3100 err_output: 3101 intel_sdvo_output_cleanup(intel_sdvo); 3102 3103 err: 3104 drm_encoder_cleanup(&intel_encoder->base); 3105 err_i2c_bus: 3106 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3107 kfree(intel_sdvo); 3108 3109 return false; 3110 } 3111