1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2007 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 */ 28 #include <linux/i2c.h> 29 #include <linux/delay.h> 30 #include <linux/export.h> 31 #include <drm/drmP.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 #include "intel_sdvo_regs.h" 38 39 #include <bus/iicbus/iic.h> 40 #include <bus/iicbus/iiconf.h> 41 #include "iicbus_if.h" 42 43 #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) 44 #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) 45 #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) 46 #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) 47 48 #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ 49 SDVO_TV_MASK) 50 51 #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) 52 #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) 53 #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) 54 #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) 55 #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) 56 57 58 static const char *tv_format_names[] = { 59 "NTSC_M" , "NTSC_J" , "NTSC_443", 60 "PAL_B" , "PAL_D" , "PAL_G" , 61 "PAL_H" , "PAL_I" , "PAL_M" , 62 "PAL_N" , "PAL_NC" , "PAL_60" , 63 "SECAM_B" , "SECAM_D" , "SECAM_G" , 64 "SECAM_K" , "SECAM_K1", "SECAM_L" , 65 "SECAM_60" 66 }; 67 68 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) 69 70 struct intel_sdvo { 71 struct intel_encoder base; 72 73 struct device *i2c; 74 u8 slave_addr; 75 76 device_t ddc_iic_bus, ddc; 77 78 /* Register for the SDVO device: SDVOB or SDVOC */ 79 uint32_t sdvo_reg; 80 81 /* Active outputs controlled by this SDVO output */ 82 uint16_t controlled_output; 83 84 /* 85 * Capabilities of the SDVO device returned by 86 * intel_sdvo_get_capabilities() 87 */ 88 struct intel_sdvo_caps caps; 89 90 /* Pixel clock limitations reported by the SDVO device, in kHz */ 91 int pixel_clock_min, pixel_clock_max; 92 93 /* 94 * For multiple function SDVO device, 95 * this is for current attached outputs. 96 */ 97 uint16_t attached_output; 98 99 /* 100 * Hotplug activation bits for this device 101 */ 102 uint16_t hotplug_active; 103 104 /** 105 * This is used to select the color range of RBG outputs in HDMI mode. 106 * It is only valid when using TMDS encoding and 8 bit per color mode. 107 */ 108 uint32_t color_range; 109 bool color_range_auto; 110 111 /** 112 * This is set if we're going to treat the device as TV-out. 113 * 114 * While we have these nice friendly flags for output types that ought 115 * to decide this for us, the S-Video output on our HDMI+S-Video card 116 * shows up as RGB1 (VGA). 117 */ 118 bool is_tv; 119 120 /* On different gens SDVOB is at different places. */ 121 bool is_sdvob; 122 123 /* This is for current tv format name */ 124 int tv_format_index; 125 126 /** 127 * This is set if we treat the device as HDMI, instead of DVI. 128 */ 129 bool is_hdmi; 130 bool has_hdmi_monitor; 131 bool has_hdmi_audio; 132 bool rgb_quant_range_selectable; 133 134 /** 135 * This is set if we detect output of sdvo device as LVDS and 136 * have a valid fixed mode to use with the panel. 137 */ 138 bool is_lvds; 139 140 /** 141 * This is sdvo fixed pannel mode pointer 142 */ 143 struct drm_display_mode *sdvo_lvds_fixed_mode; 144 145 /* DDC bus used by this SDVO encoder */ 146 uint8_t ddc_bus; 147 148 /* 149 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd 150 */ 151 uint8_t dtd_sdvo_flags; 152 }; 153 154 struct intel_sdvo_connector { 155 struct intel_connector base; 156 157 /* Mark the type of connector */ 158 uint16_t output_flag; 159 160 enum hdmi_force_audio force_audio; 161 162 /* This contains all current supported TV format */ 163 u8 tv_format_supported[TV_FORMAT_NUM]; 164 int format_supported_num; 165 struct drm_property *tv_format; 166 167 /* add the property for the SDVO-TV */ 168 struct drm_property *left; 169 struct drm_property *right; 170 struct drm_property *top; 171 struct drm_property *bottom; 172 struct drm_property *hpos; 173 struct drm_property *vpos; 174 struct drm_property *contrast; 175 struct drm_property *saturation; 176 struct drm_property *hue; 177 struct drm_property *sharpness; 178 struct drm_property *flicker_filter; 179 struct drm_property *flicker_filter_adaptive; 180 struct drm_property *flicker_filter_2d; 181 struct drm_property *tv_chroma_filter; 182 struct drm_property *tv_luma_filter; 183 struct drm_property *dot_crawl; 184 185 /* add the property for the SDVO-TV/LVDS */ 186 struct drm_property *brightness; 187 188 /* Add variable to record current setting for the above property */ 189 u32 left_margin, right_margin, top_margin, bottom_margin; 190 191 /* this is to get the range of margin.*/ 192 u32 max_hscan, max_vscan; 193 u32 max_hpos, cur_hpos; 194 u32 max_vpos, cur_vpos; 195 u32 cur_brightness, max_brightness; 196 u32 cur_contrast, max_contrast; 197 u32 cur_saturation, max_saturation; 198 u32 cur_hue, max_hue; 199 u32 cur_sharpness, max_sharpness; 200 u32 cur_flicker_filter, max_flicker_filter; 201 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; 202 u32 cur_flicker_filter_2d, max_flicker_filter_2d; 203 u32 cur_tv_chroma_filter, max_tv_chroma_filter; 204 u32 cur_tv_luma_filter, max_tv_luma_filter; 205 u32 cur_dot_crawl, max_dot_crawl; 206 }; 207 208 static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder) 209 { 210 return container_of(encoder, struct intel_sdvo, base.base); 211 } 212 213 static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) 214 { 215 return container_of(intel_attached_encoder(connector), 216 struct intel_sdvo, base); 217 } 218 219 static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) 220 { 221 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); 222 } 223 224 static bool 225 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); 226 static bool 227 intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 228 struct intel_sdvo_connector *intel_sdvo_connector, 229 int type); 230 static bool 231 intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 232 struct intel_sdvo_connector *intel_sdvo_connector); 233 234 /** 235 * Writes the SDVOB or SDVOC with the given value, but always writes both 236 * SDVOB and SDVOC to work around apparent hardware issues (according to 237 * comments in the BIOS). 238 */ 239 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) 240 { 241 struct drm_device *dev = intel_sdvo->base.base.dev; 242 struct drm_i915_private *dev_priv = dev->dev_private; 243 u32 bval = val, cval = val; 244 int i; 245 246 if (intel_sdvo->sdvo_reg == PCH_SDVOB) { 247 I915_WRITE(intel_sdvo->sdvo_reg, val); 248 I915_READ(intel_sdvo->sdvo_reg); 249 return; 250 } 251 252 if (intel_sdvo->sdvo_reg == GEN3_SDVOB) 253 cval = I915_READ(GEN3_SDVOC); 254 else 255 bval = I915_READ(GEN3_SDVOB); 256 257 /* 258 * Write the registers twice for luck. Sometimes, 259 * writing them only once doesn't appear to 'stick'. 260 * The BIOS does this too. Yay, magic 261 */ 262 for (i = 0; i < 2; i++) 263 { 264 I915_WRITE(GEN3_SDVOB, bval); 265 I915_READ(GEN3_SDVOB); 266 I915_WRITE(GEN3_SDVOC, cval); 267 I915_READ(GEN3_SDVOC); 268 } 269 } 270 271 static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) 272 { 273 struct i2c_msg msgs[] = { 274 { 275 .slave = intel_sdvo->slave_addr << 1, 276 .flags = 0, 277 .len = 1, 278 .buf = &addr, 279 }, 280 { 281 .slave = intel_sdvo->slave_addr << 1, 282 .flags = I2C_M_RD, 283 .len = 1, 284 .buf = ch, 285 } 286 }; 287 int ret; 288 289 if ((ret = iicbus_transfer(intel_sdvo->i2c, msgs, 2)) == 0) 290 return true; 291 292 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); 293 return false; 294 } 295 296 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} 297 /** Mapping of command numbers to names, for debug output */ 298 static const struct _sdvo_cmd_name { 299 u8 cmd; 300 const char *name; 301 } sdvo_cmd_names[] = { 302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), 303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), 304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), 305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), 306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), 307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), 308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), 309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), 310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), 312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), 313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), 314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), 315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), 316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), 317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), 318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), 319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), 321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), 322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), 323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), 324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), 325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), 326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), 327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), 328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), 329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), 330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), 331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), 332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), 335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), 342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), 345 346 /* Add the op code for SDVO enhancements */ 347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), 348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), 351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), 353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), 354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), 355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), 356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), 357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), 358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), 359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), 360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), 361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), 362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), 363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), 364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), 365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), 366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), 369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), 371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), 372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), 373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), 374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), 375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), 376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), 377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), 378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), 379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), 380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), 381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), 382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), 383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), 384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), 385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), 386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), 387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), 388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), 389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), 390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), 391 392 /* HDMI op code */ 393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), 394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), 395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), 396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), 397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), 398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), 399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), 400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), 401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), 402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), 403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), 404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), 405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), 406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), 407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), 408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), 409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), 410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), 411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), 412 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), 413 }; 414 415 #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") 416 417 static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 418 const void *args, int args_len) 419 { 420 int i; 421 422 DRM_DEBUG_KMS("%s: W: %02X ", 423 SDVO_NAME(intel_sdvo), cmd); 424 for (i = 0; i < args_len; i++) 425 kprintf("%02X ", ((const u8 *)args)[i]); 426 for (; i < 8; i++) 427 DRM_LOG_KMS(" "); 428 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 429 if (cmd == sdvo_cmd_names[i].cmd) { 430 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); 431 break; 432 } 433 } 434 if (i == ARRAY_SIZE(sdvo_cmd_names)) 435 DRM_LOG_KMS("(%02X)", cmd); 436 DRM_LOG_KMS("\n"); 437 } 438 439 static const char *cmd_status_names[] = { 440 "Power on", 441 "Success", 442 "Not supported", 443 "Invalid arg", 444 "Pending", 445 "Target not specified", 446 "Scaling not supported" 447 }; 448 449 static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, 450 const void *args, int args_len) 451 { 452 u8 *buf, status; 453 struct iic_msg msgs[args_len + 3]; 454 int i, ret = true; 455 456 /* Would be simpler to allocate both in one go ? */ 457 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); 458 if (!buf) 459 return false; 460 461 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 462 463 for (i = 0; i < args_len; i++) { 464 msgs[i].slave = intel_sdvo->slave_addr << 1; 465 msgs[i].flags = 0; 466 msgs[i].len = 2; 467 msgs[i].buf = buf + 2 *i; 468 buf[2*i + 0] = SDVO_I2C_ARG_0 - i; 469 buf[2*i + 1] = ((const u8*)args)[i]; 470 } 471 msgs[i].slave = intel_sdvo->slave_addr << 1; 472 msgs[i].flags = 0; 473 msgs[i].len = 2; 474 msgs[i].buf = buf + 2*i; 475 buf[2*i + 0] = SDVO_I2C_OPCODE; 476 buf[2*i + 1] = cmd; 477 478 /* the following two are to read the response */ 479 status = SDVO_I2C_CMD_STATUS; 480 msgs[i+1].slave = intel_sdvo->slave_addr << 1; 481 msgs[i+1].flags = 0; 482 msgs[i+1].len = 1; 483 msgs[i+1].buf = &status; 484 485 msgs[i+2].slave = intel_sdvo->slave_addr << 1; 486 msgs[i+2].flags = I2C_M_RD; 487 msgs[i+2].len = 1; 488 msgs[i+2].buf = &status; 489 490 ret = iicbus_transfer(intel_sdvo->i2c, msgs, i+3); 491 if (ret != 0) { 492 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); 493 ret = false; 494 goto out; 495 } 496 #if 0 497 if (ret != i+3) { 498 /* failure in I2C transfer */ 499 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); 500 ret = false; 501 } 502 #endif 503 504 out: 505 kfree(buf); 506 return ret; 507 } 508 509 static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, 510 void *response, int response_len) 511 { 512 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 513 u8 status; 514 int i; 515 516 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); 517 518 /* 519 * The documentation states that all commands will be 520 * processed within 15µs, and that we need only poll 521 * the status byte a maximum of 3 times in order for the 522 * command to be complete. 523 * 524 * Check 5 times in case the hardware failed to read the docs. 525 * 526 * Also beware that the first response by many devices is to 527 * reply PENDING and stall for time. TVs are notorious for 528 * requiring longer than specified to complete their replies. 529 * Originally (in the DDX long ago), the delay was only ever 15ms 530 * with an additional delay of 30ms applied for TVs added later after 531 * many experiments. To accommodate both sets of delays, we do a 532 * sequence of slow checks if the device is falling behind and fails 533 * to reply within 5*15µs. 534 */ 535 if (!intel_sdvo_read_byte(intel_sdvo, 536 SDVO_I2C_CMD_STATUS, 537 &status)) 538 goto log_fail; 539 540 while (status == SDVO_CMD_STATUS_PENDING && --retry) { 541 if (retry < 10) 542 msleep(15); 543 else 544 udelay(15); 545 546 if (!intel_sdvo_read_byte(intel_sdvo, 547 SDVO_I2C_CMD_STATUS, 548 &status)) 549 goto log_fail; 550 } 551 552 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 553 DRM_LOG_KMS("(%s)", cmd_status_names[status]); 554 else 555 DRM_LOG_KMS("(??? %d)", status); 556 557 if (status != SDVO_CMD_STATUS_SUCCESS) 558 goto log_fail; 559 560 /* Read the command response */ 561 for (i = 0; i < response_len; i++) { 562 if (!intel_sdvo_read_byte(intel_sdvo, 563 SDVO_I2C_RETURN_0 + i, 564 &((u8 *)response)[i])) 565 goto log_fail; 566 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); 567 } 568 DRM_LOG_KMS("\n"); 569 return true; 570 571 log_fail: 572 DRM_LOG_KMS("... failed\n"); 573 return false; 574 } 575 576 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) 577 { 578 if (mode->clock >= 100000) 579 return 1; 580 else if (mode->clock >= 50000) 581 return 2; 582 else 583 return 4; 584 } 585 586 static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, 587 u8 ddc_bus) 588 { 589 /* This must be the immediately preceding write before the i2c xfer */ 590 return intel_sdvo_write_cmd(intel_sdvo, 591 SDVO_CMD_SET_CONTROL_BUS_SWITCH, 592 &ddc_bus, 1); 593 } 594 595 static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) 596 { 597 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) 598 return false; 599 600 return intel_sdvo_read_response(intel_sdvo, NULL, 0); 601 } 602 603 static bool 604 intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) 605 { 606 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) 607 return false; 608 609 return intel_sdvo_read_response(intel_sdvo, value, len); 610 } 611 612 static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) 613 { 614 struct intel_sdvo_set_target_input_args targets = {0}; 615 return intel_sdvo_set_value(intel_sdvo, 616 SDVO_CMD_SET_TARGET_INPUT, 617 &targets, sizeof(targets)); 618 } 619 620 /** 621 * Return whether each input is trained. 622 * 623 * This function is making an assumption about the layout of the response, 624 * which should be checked against the docs. 625 */ 626 static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) 627 { 628 struct intel_sdvo_get_trained_inputs_response response; 629 630 BUILD_BUG_ON(sizeof(response) != 1); 631 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, 632 &response, sizeof(response))) 633 return false; 634 635 *input_1 = response.input0_trained; 636 *input_2 = response.input1_trained; 637 return true; 638 } 639 640 static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, 641 u16 outputs) 642 { 643 return intel_sdvo_set_value(intel_sdvo, 644 SDVO_CMD_SET_ACTIVE_OUTPUTS, 645 &outputs, sizeof(outputs)); 646 } 647 648 static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, 649 u16 *outputs) 650 { 651 return intel_sdvo_get_value(intel_sdvo, 652 SDVO_CMD_GET_ACTIVE_OUTPUTS, 653 outputs, sizeof(*outputs)); 654 } 655 656 static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, 657 int mode) 658 { 659 u8 state = SDVO_ENCODER_STATE_ON; 660 661 switch (mode) { 662 case DRM_MODE_DPMS_ON: 663 state = SDVO_ENCODER_STATE_ON; 664 break; 665 case DRM_MODE_DPMS_STANDBY: 666 state = SDVO_ENCODER_STATE_STANDBY; 667 break; 668 case DRM_MODE_DPMS_SUSPEND: 669 state = SDVO_ENCODER_STATE_SUSPEND; 670 break; 671 case DRM_MODE_DPMS_OFF: 672 state = SDVO_ENCODER_STATE_OFF; 673 break; 674 } 675 676 return intel_sdvo_set_value(intel_sdvo, 677 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); 678 } 679 680 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, 681 int *clock_min, 682 int *clock_max) 683 { 684 struct intel_sdvo_pixel_clock_range clocks; 685 686 BUILD_BUG_ON(sizeof(clocks) != 4); 687 if (!intel_sdvo_get_value(intel_sdvo, 688 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, 689 &clocks, sizeof(clocks))) 690 return false; 691 692 /* Convert the values from units of 10 kHz to kHz. */ 693 *clock_min = clocks.min * 10; 694 *clock_max = clocks.max * 10; 695 return true; 696 } 697 698 static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, 699 u16 outputs) 700 { 701 return intel_sdvo_set_value(intel_sdvo, 702 SDVO_CMD_SET_TARGET_OUTPUT, 703 &outputs, sizeof(outputs)); 704 } 705 706 static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 707 struct intel_sdvo_dtd *dtd) 708 { 709 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 710 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 711 } 712 713 static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, 714 struct intel_sdvo_dtd *dtd) 715 { 716 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && 717 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); 718 } 719 720 static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, 721 struct intel_sdvo_dtd *dtd) 722 { 723 return intel_sdvo_set_timing(intel_sdvo, 724 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); 725 } 726 727 static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, 728 struct intel_sdvo_dtd *dtd) 729 { 730 return intel_sdvo_set_timing(intel_sdvo, 731 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); 732 } 733 734 static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, 735 struct intel_sdvo_dtd *dtd) 736 { 737 return intel_sdvo_get_timing(intel_sdvo, 738 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); 739 } 740 741 static bool 742 intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, 743 uint16_t clock, 744 uint16_t width, 745 uint16_t height) 746 { 747 struct intel_sdvo_preferred_input_timing_args args; 748 749 memset(&args, 0, sizeof(args)); 750 args.clock = clock; 751 args.width = width; 752 args.height = height; 753 args.interlace = 0; 754 755 if (intel_sdvo->is_lvds && 756 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || 757 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) 758 args.scaled = 1; 759 760 return intel_sdvo_set_value(intel_sdvo, 761 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, 762 &args, sizeof(args)); 763 } 764 765 static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, 766 struct intel_sdvo_dtd *dtd) 767 { 768 BUILD_BUG_ON(sizeof(dtd->part1) != 8); 769 BUILD_BUG_ON(sizeof(dtd->part2) != 8); 770 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, 771 &dtd->part1, sizeof(dtd->part1)) && 772 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, 773 &dtd->part2, sizeof(dtd->part2)); 774 } 775 776 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) 777 { 778 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); 779 } 780 781 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, 782 const struct drm_display_mode *mode) 783 { 784 uint16_t width, height; 785 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; 786 uint16_t h_sync_offset, v_sync_offset; 787 int mode_clock; 788 789 width = mode->hdisplay; 790 height = mode->vdisplay; 791 792 /* do some mode translations */ 793 h_blank_len = mode->htotal - mode->hdisplay; 794 h_sync_len = mode->hsync_end - mode->hsync_start; 795 796 v_blank_len = mode->vtotal - mode->vdisplay; 797 v_sync_len = mode->vsync_end - mode->vsync_start; 798 799 h_sync_offset = mode->hsync_start - mode->hdisplay; 800 v_sync_offset = mode->vsync_start - mode->vdisplay; 801 802 mode_clock = mode->clock; 803 mode_clock /= 10; 804 dtd->part1.clock = mode_clock; 805 806 dtd->part1.h_active = width & 0xff; 807 dtd->part1.h_blank = h_blank_len & 0xff; 808 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | 809 ((h_blank_len >> 8) & 0xf); 810 dtd->part1.v_active = height & 0xff; 811 dtd->part1.v_blank = v_blank_len & 0xff; 812 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | 813 ((v_blank_len >> 8) & 0xf); 814 815 dtd->part2.h_sync_off = h_sync_offset & 0xff; 816 dtd->part2.h_sync_width = h_sync_len & 0xff; 817 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | 818 (v_sync_len & 0xf); 819 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | 820 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | 821 ((v_sync_len & 0x30) >> 4); 822 823 dtd->part2.dtd_flags = 0x18; 824 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 825 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; 826 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 827 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; 828 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 829 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; 830 831 dtd->part2.sdvo_flags = 0; 832 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; 833 dtd->part2.reserved = 0; 834 } 835 836 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, 837 const struct intel_sdvo_dtd *dtd) 838 { 839 mode->hdisplay = dtd->part1.h_active; 840 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; 841 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; 842 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; 843 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; 844 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; 845 mode->htotal = mode->hdisplay + dtd->part1.h_blank; 846 mode->htotal += (dtd->part1.h_high & 0xf) << 8; 847 848 mode->vdisplay = dtd->part1.v_active; 849 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; 850 mode->vsync_start = mode->vdisplay; 851 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; 852 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; 853 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; 854 mode->vsync_end = mode->vsync_start + 855 (dtd->part2.v_sync_off_width & 0xf); 856 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; 857 mode->vtotal = mode->vdisplay + dtd->part1.v_blank; 858 mode->vtotal += (dtd->part1.v_high & 0xf) << 8; 859 860 mode->clock = dtd->part1.clock * 10; 861 862 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 863 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) 864 mode->flags |= DRM_MODE_FLAG_INTERLACE; 865 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 866 mode->flags |= DRM_MODE_FLAG_PHSYNC; 867 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 868 mode->flags |= DRM_MODE_FLAG_PVSYNC; 869 } 870 871 static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) 872 { 873 struct intel_sdvo_encode encode; 874 875 BUILD_BUG_ON(sizeof(encode) != 2); 876 return intel_sdvo_get_value(intel_sdvo, 877 SDVO_CMD_GET_SUPP_ENCODE, 878 &encode, sizeof(encode)); 879 } 880 881 static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, 882 uint8_t mode) 883 { 884 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); 885 } 886 887 static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, 888 uint8_t mode) 889 { 890 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); 891 } 892 893 #if 0 894 static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) 895 { 896 int i, j; 897 uint8_t set_buf_index[2]; 898 uint8_t av_split; 899 uint8_t buf_size; 900 uint8_t buf[48]; 901 uint8_t *pos; 902 903 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); 904 905 for (i = 0; i <= av_split; i++) { 906 set_buf_index[0] = i; set_buf_index[1] = 0; 907 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, 908 set_buf_index, 2); 909 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); 910 intel_sdvo_read_response(encoder, &buf_size, 1); 911 912 pos = buf; 913 for (j = 0; j <= buf_size; j += 8) { 914 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, 915 NULL, 0); 916 intel_sdvo_read_response(encoder, pos, 8); 917 pos += 8; 918 } 919 } 920 } 921 #endif 922 923 static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, 924 unsigned if_index, uint8_t tx_rate, 925 uint8_t *data, unsigned length) 926 { 927 uint8_t set_buf_index[2] = { if_index, 0 }; 928 uint8_t hbuf_size, tmp[8]; 929 int i; 930 931 if (!intel_sdvo_set_value(intel_sdvo, 932 SDVO_CMD_SET_HBUF_INDEX, 933 set_buf_index, 2)) 934 return false; 935 936 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, 937 &hbuf_size, 1)) 938 return false; 939 940 /* Buffer size is 0 based, hooray! */ 941 hbuf_size++; 942 943 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", 944 if_index, length, hbuf_size); 945 946 for (i = 0; i < hbuf_size; i += 8) { 947 memset(tmp, 0, 8); 948 if (i < length) 949 memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); 950 951 if (!intel_sdvo_set_value(intel_sdvo, 952 SDVO_CMD_SET_HBUF_DATA, 953 tmp, 8)) 954 return false; 955 } 956 957 return intel_sdvo_set_value(intel_sdvo, 958 SDVO_CMD_SET_HBUF_TXRATE, 959 &tx_rate, 1); 960 } 961 962 static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, 963 const struct drm_display_mode *adjusted_mode) 964 { 965 struct dip_infoframe avi_if = { 966 .type = DIP_TYPE_AVI, 967 .ver = DIP_VERSION_AVI, 968 .len = DIP_LEN_AVI, 969 }; 970 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)]; 971 struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc); 972 973 if (intel_sdvo->rgb_quant_range_selectable) { 974 if (intel_crtc->config.limited_color_range) 975 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; 976 else 977 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; 978 } 979 980 avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode); 981 982 intel_dip_infoframe_csum(&avi_if); 983 984 /* sdvo spec says that the ecc is handled by the hw, and it looks like 985 * we must not send the ecc field, either. */ 986 memcpy(sdvo_data, &avi_if, 3); 987 sdvo_data[3] = avi_if.checksum; 988 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi)); 989 990 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, 991 SDVO_HBUF_TX_VSYNC, 992 sdvo_data, sizeof(sdvo_data)); 993 } 994 995 static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) 996 { 997 struct intel_sdvo_tv_format format; 998 uint32_t format_map; 999 1000 format_map = 1 << intel_sdvo->tv_format_index; 1001 memset(&format, 0, sizeof(format)); 1002 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); 1003 1004 BUILD_BUG_ON(sizeof(format) != 6); 1005 return intel_sdvo_set_value(intel_sdvo, 1006 SDVO_CMD_SET_TV_FORMAT, 1007 &format, sizeof(format)); 1008 } 1009 1010 static bool 1011 intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, 1012 const struct drm_display_mode *mode) 1013 { 1014 struct intel_sdvo_dtd output_dtd; 1015 1016 if (!intel_sdvo_set_target_output(intel_sdvo, 1017 intel_sdvo->attached_output)) 1018 return false; 1019 1020 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1021 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1022 return false; 1023 1024 return true; 1025 } 1026 1027 /* Asks the sdvo controller for the preferred input mode given the output mode. 1028 * Unfortunately we have to set up the full output mode to do that. */ 1029 static bool 1030 intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, 1031 const struct drm_display_mode *mode, 1032 struct drm_display_mode *adjusted_mode) 1033 { 1034 struct intel_sdvo_dtd input_dtd; 1035 1036 /* Reset the input timing to the screen. Assume always input 0. */ 1037 if (!intel_sdvo_set_target_input(intel_sdvo)) 1038 return false; 1039 1040 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, 1041 mode->clock / 10, 1042 mode->hdisplay, 1043 mode->vdisplay)) 1044 return false; 1045 1046 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, 1047 &input_dtd)) 1048 return false; 1049 1050 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); 1051 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; 1052 1053 return true; 1054 } 1055 1056 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config) 1057 { 1058 unsigned dotclock = pipe_config->adjusted_mode.clock; 1059 struct dpll *clock = &pipe_config->dpll; 1060 1061 /* SDVO TV has fixed PLL values depend on its clock range, 1062 this mirrors vbios setting. */ 1063 if (dotclock >= 100000 && dotclock < 140500) { 1064 clock->p1 = 2; 1065 clock->p2 = 10; 1066 clock->n = 3; 1067 clock->m1 = 16; 1068 clock->m2 = 8; 1069 } else if (dotclock >= 140500 && dotclock <= 200000) { 1070 clock->p1 = 1; 1071 clock->p2 = 10; 1072 clock->n = 6; 1073 clock->m1 = 12; 1074 clock->m2 = 8; 1075 } else { 1076 WARN(1, "SDVO TV clock out of range: %i\n", dotclock); 1077 } 1078 1079 pipe_config->clock_set = true; 1080 } 1081 1082 static bool intel_sdvo_compute_config(struct intel_encoder *encoder, 1083 struct intel_crtc_config *pipe_config) 1084 { 1085 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); 1086 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 1087 struct drm_display_mode *mode = &pipe_config->requested_mode; 1088 1089 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); 1090 pipe_config->pipe_bpp = 8*3; 1091 1092 if (HAS_PCH_SPLIT(encoder->base.dev)) 1093 pipe_config->has_pch_encoder = true; 1094 1095 /* We need to construct preferred input timings based on our 1096 * output timings. To do that, we have to set the output 1097 * timings, even though this isn't really the right place in 1098 * the sequence to do it. Oh well. 1099 */ 1100 if (intel_sdvo->is_tv) { 1101 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) 1102 return false; 1103 1104 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1105 mode, 1106 adjusted_mode); 1107 pipe_config->sdvo_tv_clock = true; 1108 } else if (intel_sdvo->is_lvds) { 1109 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, 1110 intel_sdvo->sdvo_lvds_fixed_mode)) 1111 return false; 1112 1113 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, 1114 mode, 1115 adjusted_mode); 1116 } 1117 1118 /* Make the CRTC code factor in the SDVO pixel multiplier. The 1119 * SDVO device will factor out the multiplier during mode_set. 1120 */ 1121 pipe_config->pixel_multiplier = 1122 intel_sdvo_get_pixel_multiplier(adjusted_mode); 1123 adjusted_mode->clock *= pipe_config->pixel_multiplier; 1124 1125 if (intel_sdvo->color_range_auto) { 1126 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 1127 /* FIXME: This bit is only valid when using TMDS encoding and 8 1128 * bit per color mode. */ 1129 if (intel_sdvo->has_hdmi_monitor && 1130 drm_match_cea_mode(adjusted_mode) > 1) 1131 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; 1132 else 1133 intel_sdvo->color_range = 0; 1134 } 1135 1136 if (intel_sdvo->color_range) 1137 pipe_config->limited_color_range = true; 1138 1139 /* Clock computation needs to happen after pixel multiplier. */ 1140 if (intel_sdvo->is_tv) 1141 i9xx_adjust_sdvo_tv_clock(pipe_config); 1142 1143 return true; 1144 } 1145 1146 static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder) 1147 { 1148 struct drm_device *dev = intel_encoder->base.dev; 1149 struct drm_i915_private *dev_priv = dev->dev_private; 1150 struct drm_crtc *crtc = intel_encoder->base.crtc; 1151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1152 struct drm_display_mode *adjusted_mode = 1153 &intel_crtc->config.adjusted_mode; 1154 struct drm_display_mode *mode = &intel_crtc->config.requested_mode; 1155 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base); 1156 u32 sdvox; 1157 struct intel_sdvo_in_out_map in_out; 1158 struct intel_sdvo_dtd input_dtd, output_dtd; 1159 int rate; 1160 1161 if (!mode) 1162 return; 1163 1164 /* First, set the input mapping for the first input to our controlled 1165 * output. This is only correct if we're a single-input device, in 1166 * which case the first input is the output from the appropriate SDVO 1167 * channel on the motherboard. In a two-input device, the first input 1168 * will be SDVOB and the second SDVOC. 1169 */ 1170 in_out.in0 = intel_sdvo->attached_output; 1171 in_out.in1 = 0; 1172 1173 intel_sdvo_set_value(intel_sdvo, 1174 SDVO_CMD_SET_IN_OUT_MAP, 1175 &in_out, sizeof(in_out)); 1176 1177 /* Set the output timings to the screen */ 1178 if (!intel_sdvo_set_target_output(intel_sdvo, 1179 intel_sdvo->attached_output)) 1180 return; 1181 1182 /* lvds has a special fixed output timing. */ 1183 if (intel_sdvo->is_lvds) 1184 intel_sdvo_get_dtd_from_mode(&output_dtd, 1185 intel_sdvo->sdvo_lvds_fixed_mode); 1186 else 1187 intel_sdvo_get_dtd_from_mode(&output_dtd, mode); 1188 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) 1189 DRM_INFO("Setting output timings on %s failed\n", 1190 SDVO_NAME(intel_sdvo)); 1191 1192 /* Set the input timing to the screen. Assume always input 0. */ 1193 if (!intel_sdvo_set_target_input(intel_sdvo)) 1194 return; 1195 1196 if (intel_sdvo->has_hdmi_monitor) { 1197 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); 1198 intel_sdvo_set_colorimetry(intel_sdvo, 1199 SDVO_COLORIMETRY_RGB256); 1200 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); 1201 } else 1202 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); 1203 1204 if (intel_sdvo->is_tv && 1205 !intel_sdvo_set_tv_format(intel_sdvo)) 1206 return; 1207 1208 /* We have tried to get input timing in mode_fixup, and filled into 1209 * adjusted_mode. 1210 */ 1211 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); 1212 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) 1213 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; 1214 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) 1215 DRM_INFO("Setting input timings on %s failed\n", 1216 SDVO_NAME(intel_sdvo)); 1217 1218 switch (intel_crtc->config.pixel_multiplier) { 1219 default: 1220 WARN(1, "unknown pixel mutlipler specified\n"); 1221 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; 1222 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; 1223 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; 1224 } 1225 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) 1226 return; 1227 1228 /* Set the SDVO control regs. */ 1229 if (INTEL_INFO(dev)->gen >= 4) { 1230 /* The real mode polarity is set by the SDVO commands, using 1231 * struct intel_sdvo_dtd. */ 1232 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; 1233 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi) 1234 sdvox |= intel_sdvo->color_range; 1235 if (INTEL_INFO(dev)->gen < 5) 1236 sdvox |= SDVO_BORDER_ENABLE; 1237 } else { 1238 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1239 switch (intel_sdvo->sdvo_reg) { 1240 case GEN3_SDVOB: 1241 sdvox &= SDVOB_PRESERVE_MASK; 1242 break; 1243 case GEN3_SDVOC: 1244 sdvox &= SDVOC_PRESERVE_MASK; 1245 break; 1246 } 1247 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; 1248 } 1249 1250 if (INTEL_PCH_TYPE(dev) >= PCH_CPT) 1251 sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe); 1252 else 1253 sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe); 1254 1255 if (intel_sdvo->has_hdmi_audio) 1256 sdvox |= SDVO_AUDIO_ENABLE; 1257 1258 if (INTEL_INFO(dev)->gen >= 4) { 1259 /* done in crtc_mode_set as the dpll_md reg must be written early */ 1260 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { 1261 /* done in crtc_mode_set as it lives inside the dpll register */ 1262 } else { 1263 sdvox |= (intel_crtc->config.pixel_multiplier - 1) 1264 << SDVO_PORT_MULTIPLY_SHIFT; 1265 } 1266 1267 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && 1268 INTEL_INFO(dev)->gen < 5) 1269 sdvox |= SDVO_STALL_SELECT; 1270 intel_sdvo_write_sdvox(intel_sdvo, sdvox); 1271 } 1272 1273 static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) 1274 { 1275 struct intel_sdvo_connector *intel_sdvo_connector = 1276 to_intel_sdvo_connector(&connector->base); 1277 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); 1278 u16 active_outputs = 0; 1279 1280 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1281 1282 if (active_outputs & intel_sdvo_connector->output_flag) 1283 return true; 1284 else 1285 return false; 1286 } 1287 1288 static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, 1289 enum i915_pipe *pipe) 1290 { 1291 struct drm_device *dev = encoder->base.dev; 1292 struct drm_i915_private *dev_priv = dev->dev_private; 1293 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); 1294 u16 active_outputs = 0; 1295 u32 tmp; 1296 1297 tmp = I915_READ(intel_sdvo->sdvo_reg); 1298 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); 1299 1300 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) 1301 return false; 1302 1303 if (HAS_PCH_CPT(dev)) 1304 *pipe = PORT_TO_PIPE_CPT(tmp); 1305 else 1306 *pipe = PORT_TO_PIPE(tmp); 1307 1308 return true; 1309 } 1310 1311 static void intel_sdvo_get_config(struct intel_encoder *encoder, 1312 struct intel_crtc_config *pipe_config) 1313 { 1314 struct drm_device *dev = encoder->base.dev; 1315 struct drm_i915_private *dev_priv = dev->dev_private; 1316 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); 1317 struct intel_sdvo_dtd dtd; 1318 int encoder_pixel_multiplier = 0; 1319 u32 flags = 0, sdvox; 1320 u8 val; 1321 bool ret; 1322 1323 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); 1324 if (!ret) { 1325 /* Some sdvo encoders are not spec compliant and don't 1326 * implement the mandatory get_timings function. */ 1327 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); 1328 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; 1329 } else { 1330 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) 1331 flags |= DRM_MODE_FLAG_PHSYNC; 1332 else 1333 flags |= DRM_MODE_FLAG_NHSYNC; 1334 1335 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) 1336 flags |= DRM_MODE_FLAG_PVSYNC; 1337 else 1338 flags |= DRM_MODE_FLAG_NVSYNC; 1339 } 1340 1341 pipe_config->adjusted_mode.flags |= flags; 1342 1343 /* 1344 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in 1345 * the sdvo port register, on all other platforms it is part of the dpll 1346 * state. Since the general pipe state readout happens before the 1347 * encoder->get_config we so already have a valid pixel multplier on all 1348 * other platfroms. 1349 */ 1350 if (IS_I915G(dev) || IS_I915GM(dev)) { 1351 sdvox = I915_READ(intel_sdvo->sdvo_reg); 1352 pipe_config->pixel_multiplier = 1353 ((sdvox & SDVO_PORT_MULTIPLY_MASK) 1354 >> SDVO_PORT_MULTIPLY_SHIFT) + 1; 1355 } 1356 1357 /* Cross check the port pixel multiplier with the sdvo encoder state. */ 1358 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1); 1359 switch (val) { 1360 case SDVO_CLOCK_RATE_MULT_1X: 1361 encoder_pixel_multiplier = 1; 1362 break; 1363 case SDVO_CLOCK_RATE_MULT_2X: 1364 encoder_pixel_multiplier = 2; 1365 break; 1366 case SDVO_CLOCK_RATE_MULT_4X: 1367 encoder_pixel_multiplier = 4; 1368 break; 1369 } 1370 1371 if(HAS_PCH_SPLIT(dev)) 1372 return; /* no pixel multiplier readout support yet */ 1373 1374 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, 1375 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", 1376 pipe_config->pixel_multiplier, encoder_pixel_multiplier); 1377 } 1378 1379 static void intel_disable_sdvo(struct intel_encoder *encoder) 1380 { 1381 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1382 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); 1383 u32 temp; 1384 1385 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1386 if (0) 1387 intel_sdvo_set_encoder_power_state(intel_sdvo, 1388 DRM_MODE_DPMS_OFF); 1389 1390 temp = I915_READ(intel_sdvo->sdvo_reg); 1391 if ((temp & SDVO_ENABLE) != 0) { 1392 /* HW workaround for IBX, we need to move the port to 1393 * transcoder A before disabling it. */ 1394 if (HAS_PCH_IBX(encoder->base.dev)) { 1395 struct drm_crtc *crtc = encoder->base.crtc; 1396 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; 1397 1398 if (temp & SDVO_PIPE_B_SELECT) { 1399 temp &= ~SDVO_PIPE_B_SELECT; 1400 I915_WRITE(intel_sdvo->sdvo_reg, temp); 1401 POSTING_READ(intel_sdvo->sdvo_reg); 1402 1403 /* Again we need to write this twice. */ 1404 I915_WRITE(intel_sdvo->sdvo_reg, temp); 1405 POSTING_READ(intel_sdvo->sdvo_reg); 1406 1407 /* Transcoder selection bits only update 1408 * effectively on vblank. */ 1409 if (crtc) 1410 intel_wait_for_vblank(encoder->base.dev, pipe); 1411 else 1412 msleep(50); 1413 } 1414 } 1415 1416 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); 1417 } 1418 } 1419 1420 static void intel_enable_sdvo(struct intel_encoder *encoder) 1421 { 1422 struct drm_device *dev = encoder->base.dev; 1423 struct drm_i915_private *dev_priv = dev->dev_private; 1424 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); 1425 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1426 u32 temp; 1427 bool input1, input2; 1428 int i; 1429 u8 status; 1430 1431 temp = I915_READ(intel_sdvo->sdvo_reg); 1432 if ((temp & SDVO_ENABLE) == 0) { 1433 /* HW workaround for IBX, we need to move the port 1434 * to transcoder A before disabling it, so restore it here. */ 1435 if (HAS_PCH_IBX(dev)) 1436 temp |= SDVO_PIPE_SEL(intel_crtc->pipe); 1437 1438 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); 1439 } 1440 for (i = 0; i < 2; i++) 1441 intel_wait_for_vblank(dev, intel_crtc->pipe); 1442 1443 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); 1444 /* Warn if the device reported failure to sync. 1445 * A lot of SDVO devices fail to notify of sync, but it's 1446 * a given it the status is a success, we succeeded. 1447 */ 1448 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { 1449 DRM_DEBUG_KMS("First %s output reported failure to " 1450 "sync\n", SDVO_NAME(intel_sdvo)); 1451 } 1452 1453 if (0) 1454 intel_sdvo_set_encoder_power_state(intel_sdvo, 1455 DRM_MODE_DPMS_ON); 1456 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1457 } 1458 1459 /* Special dpms function to support cloning between dvo/sdvo/crt. */ 1460 static void intel_sdvo_dpms(struct drm_connector *connector, int mode) 1461 { 1462 struct drm_crtc *crtc; 1463 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1464 1465 /* dvo supports only 2 dpms states. */ 1466 if (mode != DRM_MODE_DPMS_ON) 1467 mode = DRM_MODE_DPMS_OFF; 1468 1469 if (mode == connector->dpms) 1470 return; 1471 1472 connector->dpms = mode; 1473 1474 /* Only need to change hw state when actually enabled */ 1475 crtc = intel_sdvo->base.base.crtc; 1476 if (!crtc) { 1477 intel_sdvo->base.connectors_active = false; 1478 return; 1479 } 1480 1481 /* We set active outputs manually below in case pipe dpms doesn't change 1482 * due to cloning. */ 1483 if (mode != DRM_MODE_DPMS_ON) { 1484 intel_sdvo_set_active_outputs(intel_sdvo, 0); 1485 if (0) 1486 intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1487 1488 intel_sdvo->base.connectors_active = false; 1489 1490 intel_crtc_update_dpms(crtc); 1491 } else { 1492 intel_sdvo->base.connectors_active = true; 1493 1494 intel_crtc_update_dpms(crtc); 1495 1496 if (0) 1497 intel_sdvo_set_encoder_power_state(intel_sdvo, mode); 1498 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); 1499 } 1500 1501 intel_modeset_check_state(connector->dev); 1502 } 1503 1504 static int intel_sdvo_mode_valid(struct drm_connector *connector, 1505 struct drm_display_mode *mode) 1506 { 1507 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1508 1509 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1510 return MODE_NO_DBLESCAN; 1511 1512 if (intel_sdvo->pixel_clock_min > mode->clock) 1513 return MODE_CLOCK_LOW; 1514 1515 if (intel_sdvo->pixel_clock_max < mode->clock) 1516 return MODE_CLOCK_HIGH; 1517 1518 if (intel_sdvo->is_lvds) { 1519 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) 1520 return MODE_PANEL; 1521 1522 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) 1523 return MODE_PANEL; 1524 } 1525 1526 return MODE_OK; 1527 } 1528 1529 static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) 1530 { 1531 BUILD_BUG_ON(sizeof(*caps) != 8); 1532 if (!intel_sdvo_get_value(intel_sdvo, 1533 SDVO_CMD_GET_DEVICE_CAPS, 1534 caps, sizeof(*caps))) 1535 return false; 1536 1537 DRM_DEBUG_KMS("SDVO capabilities:\n" 1538 " vendor_id: %d\n" 1539 " device_id: %d\n" 1540 " device_rev_id: %d\n" 1541 " sdvo_version_major: %d\n" 1542 " sdvo_version_minor: %d\n" 1543 " sdvo_inputs_mask: %d\n" 1544 " smooth_scaling: %d\n" 1545 " sharp_scaling: %d\n" 1546 " up_scaling: %d\n" 1547 " down_scaling: %d\n" 1548 " stall_support: %d\n" 1549 " output_flags: %d\n", 1550 caps->vendor_id, 1551 caps->device_id, 1552 caps->device_rev_id, 1553 caps->sdvo_version_major, 1554 caps->sdvo_version_minor, 1555 caps->sdvo_inputs_mask, 1556 caps->smooth_scaling, 1557 caps->sharp_scaling, 1558 caps->up_scaling, 1559 caps->down_scaling, 1560 caps->stall_support, 1561 caps->output_flags); 1562 1563 return true; 1564 } 1565 1566 static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) 1567 { 1568 struct drm_device *dev = intel_sdvo->base.base.dev; 1569 uint16_t hotplug; 1570 1571 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise 1572 * on the line. */ 1573 if (IS_I945G(dev) || IS_I945GM(dev)) 1574 return 0; 1575 1576 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, 1577 &hotplug, sizeof(hotplug))) 1578 return 0; 1579 1580 return hotplug; 1581 } 1582 1583 static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) 1584 { 1585 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); 1586 1587 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, 1588 &intel_sdvo->hotplug_active, 2); 1589 } 1590 1591 static bool 1592 intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) 1593 { 1594 /* Is there more than one type of output? */ 1595 return hweight16(intel_sdvo->caps.output_flags) > 1; 1596 } 1597 1598 static struct edid * 1599 intel_sdvo_get_edid(struct drm_connector *connector) 1600 { 1601 struct intel_sdvo *sdvo = intel_attached_sdvo(connector); 1602 return drm_get_edid(connector, sdvo->ddc); 1603 } 1604 1605 /* Mac mini hack -- use the same DDC as the analog connector */ 1606 static struct edid * 1607 intel_sdvo_get_analog_edid(struct drm_connector *connector) 1608 { 1609 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1610 1611 return drm_get_edid(connector, 1612 intel_gmbus_get_adapter(dev_priv, 1613 dev_priv->vbt.crt_ddc_pin)); 1614 } 1615 1616 static enum drm_connector_status 1617 intel_sdvo_tmds_sink_detect(struct drm_connector *connector) 1618 { 1619 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1620 enum drm_connector_status status; 1621 struct edid *edid; 1622 1623 edid = intel_sdvo_get_edid(connector); 1624 1625 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { 1626 u8 ddc, saved_ddc = intel_sdvo->ddc_bus; 1627 1628 /* 1629 * Don't use the 1 as the argument of DDC bus switch to get 1630 * the EDID. It is used for SDVO SPD ROM. 1631 */ 1632 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { 1633 intel_sdvo->ddc_bus = ddc; 1634 edid = intel_sdvo_get_edid(connector); 1635 if (edid) 1636 break; 1637 } 1638 /* 1639 * If we found the EDID on the other bus, 1640 * assume that is the correct DDC bus. 1641 */ 1642 if (edid == NULL) 1643 intel_sdvo->ddc_bus = saved_ddc; 1644 } 1645 1646 /* 1647 * When there is no edid and no monitor is connected with VGA 1648 * port, try to use the CRT ddc to read the EDID for DVI-connector. 1649 */ 1650 if (edid == NULL) 1651 edid = intel_sdvo_get_analog_edid(connector); 1652 1653 status = connector_status_unknown; 1654 if (edid != NULL) { 1655 /* DDC bus is shared, match EDID to connector type */ 1656 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 1657 status = connector_status_connected; 1658 if (intel_sdvo->is_hdmi) { 1659 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); 1660 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); 1661 intel_sdvo->rgb_quant_range_selectable = 1662 drm_rgb_quant_range_selectable(edid); 1663 } 1664 } else 1665 status = connector_status_disconnected; 1666 kfree(edid); 1667 } 1668 1669 if (status == connector_status_connected) { 1670 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1671 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) 1672 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); 1673 } 1674 1675 return status; 1676 } 1677 1678 static bool 1679 intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, 1680 struct edid *edid) 1681 { 1682 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); 1683 bool connector_is_digital = !!IS_DIGITAL(sdvo); 1684 1685 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", 1686 connector_is_digital, monitor_is_digital); 1687 return connector_is_digital == monitor_is_digital; 1688 } 1689 1690 static enum drm_connector_status 1691 intel_sdvo_detect(struct drm_connector *connector, bool force) 1692 { 1693 uint16_t response; 1694 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1695 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1696 enum drm_connector_status ret; 1697 1698 if (!intel_sdvo_get_value(intel_sdvo, 1699 SDVO_CMD_GET_ATTACHED_DISPLAYS, 1700 &response, 2)) 1701 return connector_status_unknown; 1702 1703 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", 1704 response & 0xff, response >> 8, 1705 intel_sdvo_connector->output_flag); 1706 1707 if (response == 0) 1708 return connector_status_disconnected; 1709 1710 intel_sdvo->attached_output = response; 1711 1712 intel_sdvo->has_hdmi_monitor = false; 1713 intel_sdvo->has_hdmi_audio = false; 1714 intel_sdvo->rgb_quant_range_selectable = false; 1715 1716 if ((intel_sdvo_connector->output_flag & response) == 0) 1717 ret = connector_status_disconnected; 1718 else if (IS_TMDS(intel_sdvo_connector)) 1719 ret = intel_sdvo_tmds_sink_detect(connector); 1720 else { 1721 struct edid *edid; 1722 1723 /* if we have an edid check it matches the connection */ 1724 edid = intel_sdvo_get_edid(connector); 1725 if (edid == NULL) 1726 edid = intel_sdvo_get_analog_edid(connector); 1727 if (edid != NULL) { 1728 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, 1729 edid)) 1730 ret = connector_status_connected; 1731 else 1732 ret = connector_status_disconnected; 1733 1734 kfree(edid); 1735 } else 1736 ret = connector_status_connected; 1737 } 1738 1739 /* May update encoder flag for like clock for SDVO TV, etc.*/ 1740 if (ret == connector_status_connected) { 1741 intel_sdvo->is_tv = false; 1742 intel_sdvo->is_lvds = false; 1743 1744 if (response & SDVO_TV_MASK) 1745 intel_sdvo->is_tv = true; 1746 if (response & SDVO_LVDS_MASK) 1747 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; 1748 } 1749 1750 return ret; 1751 } 1752 1753 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) 1754 { 1755 struct edid *edid; 1756 1757 /* set the bus switch and get the modes */ 1758 edid = intel_sdvo_get_edid(connector); 1759 1760 /* 1761 * Mac mini hack. On this device, the DVI-I connector shares one DDC 1762 * link between analog and digital outputs. So, if the regular SDVO 1763 * DDC fails, check to see if the analog output is disconnected, in 1764 * which case we'll look there for the digital DDC data. 1765 */ 1766 if (edid == NULL) 1767 edid = intel_sdvo_get_analog_edid(connector); 1768 1769 if (edid != NULL) { 1770 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), 1771 edid)) { 1772 drm_mode_connector_update_edid_property(connector, edid); 1773 drm_add_edid_modes(connector, edid); 1774 } 1775 1776 kfree(edid); 1777 } 1778 } 1779 1780 /* 1781 * Set of SDVO TV modes. 1782 * Note! This is in reply order (see loop in get_tv_modes). 1783 * XXX: all 60Hz refresh? 1784 */ 1785 static const struct drm_display_mode sdvo_tv_modes[] = { 1786 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 1787 416, 0, 200, 201, 232, 233, 0, 1788 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1789 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, 1790 416, 0, 240, 241, 272, 273, 0, 1791 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1792 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, 1793 496, 0, 300, 301, 332, 333, 0, 1794 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1795 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, 1796 736, 0, 350, 351, 382, 383, 0, 1797 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1798 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, 1799 736, 0, 400, 401, 432, 433, 0, 1800 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1801 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, 1802 736, 0, 480, 481, 512, 513, 0, 1803 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1804 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, 1805 800, 0, 480, 481, 512, 513, 0, 1806 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1807 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, 1808 800, 0, 576, 577, 608, 609, 0, 1809 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1810 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, 1811 816, 0, 350, 351, 382, 383, 0, 1812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1813 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, 1814 816, 0, 400, 401, 432, 433, 0, 1815 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1816 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, 1817 816, 0, 480, 481, 512, 513, 0, 1818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1819 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, 1820 816, 0, 540, 541, 572, 573, 0, 1821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1822 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, 1823 816, 0, 576, 577, 608, 609, 0, 1824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1825 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, 1826 864, 0, 576, 577, 608, 609, 0, 1827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1828 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, 1829 896, 0, 600, 601, 632, 633, 0, 1830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1831 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, 1832 928, 0, 624, 625, 656, 657, 0, 1833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1834 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, 1835 1016, 0, 766, 767, 798, 799, 0, 1836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1837 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, 1838 1120, 0, 768, 769, 800, 801, 0, 1839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1840 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, 1841 1376, 0, 1024, 1025, 1056, 1057, 0, 1842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1843 }; 1844 1845 static void intel_sdvo_get_tv_modes(struct drm_connector *connector) 1846 { 1847 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1848 struct intel_sdvo_sdtv_resolution_request tv_res; 1849 uint32_t reply = 0, format_map = 0; 1850 int i; 1851 1852 /* Read the list of supported input resolutions for the selected TV 1853 * format. 1854 */ 1855 format_map = 1 << intel_sdvo->tv_format_index; 1856 memcpy(&tv_res, &format_map, 1857 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); 1858 1859 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) 1860 return; 1861 1862 BUILD_BUG_ON(sizeof(tv_res) != 3); 1863 if (!intel_sdvo_write_cmd(intel_sdvo, 1864 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, 1865 &tv_res, sizeof(tv_res))) 1866 return; 1867 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) 1868 return; 1869 1870 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) 1871 if (reply & (1 << i)) { 1872 struct drm_display_mode *nmode; 1873 nmode = drm_mode_duplicate(connector->dev, 1874 &sdvo_tv_modes[i]); 1875 if (nmode) 1876 drm_mode_probed_add(connector, nmode); 1877 } 1878 } 1879 1880 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) 1881 { 1882 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1883 struct drm_i915_private *dev_priv = connector->dev->dev_private; 1884 struct drm_display_mode *newmode; 1885 1886 /* 1887 * Fetch modes from VBT. For SDVO prefer the VBT mode since some 1888 * SDVO->LVDS transcoders can't cope with the EDID mode. 1889 */ 1890 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { 1891 newmode = drm_mode_duplicate(connector->dev, 1892 dev_priv->vbt.sdvo_lvds_vbt_mode); 1893 if (newmode != NULL) { 1894 /* Guarantee the mode is preferred */ 1895 newmode->type = (DRM_MODE_TYPE_PREFERRED | 1896 DRM_MODE_TYPE_DRIVER); 1897 drm_mode_probed_add(connector, newmode); 1898 } 1899 } 1900 1901 /* 1902 * Attempt to get the mode list from DDC. 1903 * Assume that the preferred modes are 1904 * arranged in priority order. 1905 */ 1906 intel_ddc_get_modes(connector, intel_sdvo->ddc); 1907 1908 list_for_each_entry(newmode, &connector->probed_modes, head) { 1909 if (newmode->type & DRM_MODE_TYPE_PREFERRED) { 1910 intel_sdvo->sdvo_lvds_fixed_mode = 1911 drm_mode_duplicate(connector->dev, newmode); 1912 1913 intel_sdvo->is_lvds = true; 1914 break; 1915 } 1916 } 1917 1918 } 1919 1920 static int intel_sdvo_get_modes(struct drm_connector *connector) 1921 { 1922 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1923 1924 if (IS_TV(intel_sdvo_connector)) 1925 intel_sdvo_get_tv_modes(connector); 1926 else if (IS_LVDS(intel_sdvo_connector)) 1927 intel_sdvo_get_lvds_modes(connector); 1928 else 1929 intel_sdvo_get_ddc_modes(connector); 1930 1931 return !list_empty(&connector->probed_modes); 1932 } 1933 1934 static void 1935 intel_sdvo_destroy_enhance_property(struct drm_connector *connector) 1936 { 1937 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1938 struct drm_device *dev = connector->dev; 1939 1940 if (intel_sdvo_connector->left) 1941 drm_property_destroy(dev, intel_sdvo_connector->left); 1942 if (intel_sdvo_connector->right) 1943 drm_property_destroy(dev, intel_sdvo_connector->right); 1944 if (intel_sdvo_connector->top) 1945 drm_property_destroy(dev, intel_sdvo_connector->top); 1946 if (intel_sdvo_connector->bottom) 1947 drm_property_destroy(dev, intel_sdvo_connector->bottom); 1948 if (intel_sdvo_connector->hpos) 1949 drm_property_destroy(dev, intel_sdvo_connector->hpos); 1950 if (intel_sdvo_connector->vpos) 1951 drm_property_destroy(dev, intel_sdvo_connector->vpos); 1952 if (intel_sdvo_connector->saturation) 1953 drm_property_destroy(dev, intel_sdvo_connector->saturation); 1954 if (intel_sdvo_connector->contrast) 1955 drm_property_destroy(dev, intel_sdvo_connector->contrast); 1956 if (intel_sdvo_connector->hue) 1957 drm_property_destroy(dev, intel_sdvo_connector->hue); 1958 if (intel_sdvo_connector->sharpness) 1959 drm_property_destroy(dev, intel_sdvo_connector->sharpness); 1960 if (intel_sdvo_connector->flicker_filter) 1961 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); 1962 if (intel_sdvo_connector->flicker_filter_2d) 1963 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); 1964 if (intel_sdvo_connector->flicker_filter_adaptive) 1965 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); 1966 if (intel_sdvo_connector->tv_luma_filter) 1967 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); 1968 if (intel_sdvo_connector->tv_chroma_filter) 1969 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); 1970 if (intel_sdvo_connector->dot_crawl) 1971 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); 1972 if (intel_sdvo_connector->brightness) 1973 drm_property_destroy(dev, intel_sdvo_connector->brightness); 1974 } 1975 1976 static void intel_sdvo_destroy(struct drm_connector *connector) 1977 { 1978 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 1979 1980 if (intel_sdvo_connector->tv_format) 1981 drm_property_destroy(connector->dev, 1982 intel_sdvo_connector->tv_format); 1983 1984 intel_sdvo_destroy_enhance_property(connector); 1985 drm_sysfs_connector_remove(connector); 1986 drm_connector_cleanup(connector); 1987 kfree(intel_sdvo_connector); 1988 } 1989 1990 static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) 1991 { 1992 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1993 struct edid *edid; 1994 bool has_audio = false; 1995 1996 if (!intel_sdvo->is_hdmi) 1997 return false; 1998 1999 edid = intel_sdvo_get_edid(connector); 2000 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) 2001 has_audio = drm_detect_monitor_audio(edid); 2002 kfree(edid); 2003 2004 return has_audio; 2005 } 2006 2007 static int 2008 intel_sdvo_set_property(struct drm_connector *connector, 2009 struct drm_property *property, 2010 uint64_t val) 2011 { 2012 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 2013 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); 2014 struct drm_i915_private *dev_priv = connector->dev->dev_private; 2015 uint16_t temp_value; 2016 uint8_t cmd; 2017 int ret; 2018 2019 ret = drm_object_property_set_value(&connector->base, property, val); 2020 if (ret) 2021 return ret; 2022 2023 if (property == dev_priv->force_audio_property) { 2024 int i = val; 2025 bool has_audio; 2026 2027 if (i == intel_sdvo_connector->force_audio) 2028 return 0; 2029 2030 intel_sdvo_connector->force_audio = i; 2031 2032 if (i == HDMI_AUDIO_AUTO) 2033 has_audio = intel_sdvo_detect_hdmi_audio(connector); 2034 else 2035 has_audio = (i == HDMI_AUDIO_ON); 2036 2037 if (has_audio == intel_sdvo->has_hdmi_audio) 2038 return 0; 2039 2040 intel_sdvo->has_hdmi_audio = has_audio; 2041 goto done; 2042 } 2043 2044 if (property == dev_priv->broadcast_rgb_property) { 2045 bool old_auto = intel_sdvo->color_range_auto; 2046 uint32_t old_range = intel_sdvo->color_range; 2047 2048 switch (val) { 2049 case INTEL_BROADCAST_RGB_AUTO: 2050 intel_sdvo->color_range_auto = true; 2051 break; 2052 case INTEL_BROADCAST_RGB_FULL: 2053 intel_sdvo->color_range_auto = false; 2054 intel_sdvo->color_range = 0; 2055 break; 2056 case INTEL_BROADCAST_RGB_LIMITED: 2057 intel_sdvo->color_range_auto = false; 2058 /* FIXME: this bit is only valid when using TMDS 2059 * encoding and 8 bit per color mode. */ 2060 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; 2061 break; 2062 default: 2063 return -EINVAL; 2064 } 2065 2066 if (old_auto == intel_sdvo->color_range_auto && 2067 old_range == intel_sdvo->color_range) 2068 return 0; 2069 2070 goto done; 2071 } 2072 2073 #define CHECK_PROPERTY(name, NAME) \ 2074 if (intel_sdvo_connector->name == property) { \ 2075 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ 2076 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ 2077 cmd = SDVO_CMD_SET_##NAME; \ 2078 intel_sdvo_connector->cur_##name = temp_value; \ 2079 goto set_value; \ 2080 } 2081 2082 if (property == intel_sdvo_connector->tv_format) { 2083 if (val >= TV_FORMAT_NUM) 2084 return -EINVAL; 2085 2086 if (intel_sdvo->tv_format_index == 2087 intel_sdvo_connector->tv_format_supported[val]) 2088 return 0; 2089 2090 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; 2091 goto done; 2092 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { 2093 temp_value = val; 2094 if (intel_sdvo_connector->left == property) { 2095 drm_object_property_set_value(&connector->base, 2096 intel_sdvo_connector->right, val); 2097 if (intel_sdvo_connector->left_margin == temp_value) 2098 return 0; 2099 2100 intel_sdvo_connector->left_margin = temp_value; 2101 intel_sdvo_connector->right_margin = temp_value; 2102 temp_value = intel_sdvo_connector->max_hscan - 2103 intel_sdvo_connector->left_margin; 2104 cmd = SDVO_CMD_SET_OVERSCAN_H; 2105 goto set_value; 2106 } else if (intel_sdvo_connector->right == property) { 2107 drm_object_property_set_value(&connector->base, 2108 intel_sdvo_connector->left, val); 2109 if (intel_sdvo_connector->right_margin == temp_value) 2110 return 0; 2111 2112 intel_sdvo_connector->left_margin = temp_value; 2113 intel_sdvo_connector->right_margin = temp_value; 2114 temp_value = intel_sdvo_connector->max_hscan - 2115 intel_sdvo_connector->left_margin; 2116 cmd = SDVO_CMD_SET_OVERSCAN_H; 2117 goto set_value; 2118 } else if (intel_sdvo_connector->top == property) { 2119 drm_object_property_set_value(&connector->base, 2120 intel_sdvo_connector->bottom, val); 2121 if (intel_sdvo_connector->top_margin == temp_value) 2122 return 0; 2123 2124 intel_sdvo_connector->top_margin = temp_value; 2125 intel_sdvo_connector->bottom_margin = temp_value; 2126 temp_value = intel_sdvo_connector->max_vscan - 2127 intel_sdvo_connector->top_margin; 2128 cmd = SDVO_CMD_SET_OVERSCAN_V; 2129 goto set_value; 2130 } else if (intel_sdvo_connector->bottom == property) { 2131 drm_object_property_set_value(&connector->base, 2132 intel_sdvo_connector->top, val); 2133 if (intel_sdvo_connector->bottom_margin == temp_value) 2134 return 0; 2135 2136 intel_sdvo_connector->top_margin = temp_value; 2137 intel_sdvo_connector->bottom_margin = temp_value; 2138 temp_value = intel_sdvo_connector->max_vscan - 2139 intel_sdvo_connector->top_margin; 2140 cmd = SDVO_CMD_SET_OVERSCAN_V; 2141 goto set_value; 2142 } 2143 CHECK_PROPERTY(hpos, HPOS) 2144 CHECK_PROPERTY(vpos, VPOS) 2145 CHECK_PROPERTY(saturation, SATURATION) 2146 CHECK_PROPERTY(contrast, CONTRAST) 2147 CHECK_PROPERTY(hue, HUE) 2148 CHECK_PROPERTY(brightness, BRIGHTNESS) 2149 CHECK_PROPERTY(sharpness, SHARPNESS) 2150 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) 2151 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) 2152 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) 2153 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) 2154 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) 2155 CHECK_PROPERTY(dot_crawl, DOT_CRAWL) 2156 } 2157 2158 return -EINVAL; /* unknown property */ 2159 2160 set_value: 2161 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) 2162 return -EIO; 2163 2164 2165 done: 2166 if (intel_sdvo->base.base.crtc) 2167 intel_crtc_restore_mode(intel_sdvo->base.base.crtc); 2168 2169 return 0; 2170 #undef CHECK_PROPERTY 2171 } 2172 2173 static const struct drm_connector_funcs intel_sdvo_connector_funcs = { 2174 .dpms = intel_sdvo_dpms, 2175 .detect = intel_sdvo_detect, 2176 .fill_modes = drm_helper_probe_single_connector_modes, 2177 .set_property = intel_sdvo_set_property, 2178 .destroy = intel_sdvo_destroy, 2179 }; 2180 2181 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { 2182 .get_modes = intel_sdvo_get_modes, 2183 .mode_valid = intel_sdvo_mode_valid, 2184 .best_encoder = intel_best_encoder, 2185 }; 2186 2187 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) 2188 { 2189 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); 2190 2191 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) 2192 drm_mode_destroy(encoder->dev, 2193 intel_sdvo->sdvo_lvds_fixed_mode); 2194 2195 device_delete_child(intel_sdvo->base.base.dev->dev, 2196 intel_sdvo->ddc_iic_bus); 2197 intel_encoder_destroy(encoder); 2198 } 2199 2200 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { 2201 .destroy = intel_sdvo_enc_destroy, 2202 }; 2203 2204 static void 2205 intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) 2206 { 2207 uint16_t mask = 0; 2208 unsigned int num_bits; 2209 2210 /* Make a mask of outputs less than or equal to our own priority in the 2211 * list. 2212 */ 2213 switch (sdvo->controlled_output) { 2214 case SDVO_OUTPUT_LVDS1: 2215 mask |= SDVO_OUTPUT_LVDS1; 2216 case SDVO_OUTPUT_LVDS0: 2217 mask |= SDVO_OUTPUT_LVDS0; 2218 case SDVO_OUTPUT_TMDS1: 2219 mask |= SDVO_OUTPUT_TMDS1; 2220 case SDVO_OUTPUT_TMDS0: 2221 mask |= SDVO_OUTPUT_TMDS0; 2222 case SDVO_OUTPUT_RGB1: 2223 mask |= SDVO_OUTPUT_RGB1; 2224 case SDVO_OUTPUT_RGB0: 2225 mask |= SDVO_OUTPUT_RGB0; 2226 break; 2227 } 2228 2229 /* Count bits to find what number we are in the priority list. */ 2230 mask &= sdvo->caps.output_flags; 2231 num_bits = hweight16(mask); 2232 /* If more than 3 outputs, default to DDC bus 3 for now. */ 2233 if (num_bits > 3) 2234 num_bits = 3; 2235 2236 /* Corresponds to SDVO_CONTROL_BUS_DDCx */ 2237 sdvo->ddc_bus = 1 << num_bits; 2238 } 2239 2240 /** 2241 * Choose the appropriate DDC bus for control bus switch command for this 2242 * SDVO output based on the controlled output. 2243 * 2244 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS 2245 * outputs, then LVDS outputs. 2246 */ 2247 static void 2248 intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, 2249 struct intel_sdvo *sdvo, u32 reg) 2250 { 2251 struct sdvo_device_mapping *mapping; 2252 2253 if (sdvo->is_sdvob) 2254 mapping = &(dev_priv->sdvo_mappings[0]); 2255 else 2256 mapping = &(dev_priv->sdvo_mappings[1]); 2257 2258 if (mapping->initialized) 2259 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); 2260 else 2261 intel_sdvo_guess_ddc_bus(sdvo); 2262 } 2263 2264 static void 2265 intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, 2266 struct intel_sdvo *sdvo, u32 reg) 2267 { 2268 struct sdvo_device_mapping *mapping; 2269 u8 pin; 2270 2271 if (sdvo->is_sdvob) 2272 mapping = &dev_priv->sdvo_mappings[0]; 2273 else 2274 mapping = &dev_priv->sdvo_mappings[1]; 2275 2276 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) 2277 pin = mapping->i2c_pin; 2278 else 2279 pin = GMBUS_PORT_DPB; 2280 2281 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); 2282 2283 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow 2284 * our code totally fails once we start using gmbus. Hence fall back to 2285 * bit banging for now. */ 2286 intel_gmbus_force_bit(sdvo->i2c, true); 2287 } 2288 2289 /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ 2290 static void 2291 intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) 2292 { 2293 intel_gmbus_force_bit(sdvo->i2c, false); 2294 } 2295 2296 static bool 2297 intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) 2298 { 2299 return intel_sdvo_check_supp_encode(intel_sdvo); 2300 } 2301 2302 static u8 2303 intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) 2304 { 2305 struct drm_i915_private *dev_priv = dev->dev_private; 2306 struct sdvo_device_mapping *my_mapping, *other_mapping; 2307 2308 if (sdvo->is_sdvob) { 2309 my_mapping = &dev_priv->sdvo_mappings[0]; 2310 other_mapping = &dev_priv->sdvo_mappings[1]; 2311 } else { 2312 my_mapping = &dev_priv->sdvo_mappings[1]; 2313 other_mapping = &dev_priv->sdvo_mappings[0]; 2314 } 2315 2316 /* If the BIOS described our SDVO device, take advantage of it. */ 2317 if (my_mapping->slave_addr) 2318 return my_mapping->slave_addr; 2319 2320 /* If the BIOS only described a different SDVO device, use the 2321 * address that it isn't using. 2322 */ 2323 if (other_mapping->slave_addr) { 2324 if (other_mapping->slave_addr == 0x70) 2325 return 0x72; 2326 else 2327 return 0x70; 2328 } 2329 2330 /* No SDVO device info is found for another DVO port, 2331 * so use mapping assumption we had before BIOS parsing. 2332 */ 2333 if (sdvo->is_sdvob) 2334 return 0x70; 2335 else 2336 return 0x72; 2337 } 2338 2339 static void 2340 intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2341 struct intel_sdvo *encoder) 2342 { 2343 drm_connector_init(encoder->base.base.dev, 2344 &connector->base.base, 2345 &intel_sdvo_connector_funcs, 2346 connector->base.base.connector_type); 2347 2348 drm_connector_helper_add(&connector->base.base, 2349 &intel_sdvo_connector_helper_funcs); 2350 2351 connector->base.base.interlace_allowed = 1; 2352 connector->base.base.doublescan_allowed = 0; 2353 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2354 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2355 2356 intel_connector_attach_encoder(&connector->base, &encoder->base); 2357 drm_sysfs_connector_add(&connector->base.base); 2358 } 2359 2360 static void 2361 intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, 2362 struct intel_sdvo_connector *connector) 2363 { 2364 struct drm_device *dev = connector->base.base.dev; 2365 2366 intel_attach_force_audio_property(&connector->base.base); 2367 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { 2368 intel_attach_broadcast_rgb_property(&connector->base.base); 2369 intel_sdvo->color_range_auto = true; 2370 } 2371 } 2372 2373 static bool 2374 intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) 2375 { 2376 struct drm_encoder *encoder = &intel_sdvo->base.base; 2377 struct drm_connector *connector; 2378 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 2379 struct intel_connector *intel_connector; 2380 struct intel_sdvo_connector *intel_sdvo_connector; 2381 2382 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2383 if (!intel_sdvo_connector) 2384 return false; 2385 2386 if (device == 0) { 2387 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; 2388 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; 2389 } else if (device == 1) { 2390 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; 2391 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; 2392 } 2393 2394 intel_connector = &intel_sdvo_connector->base; 2395 connector = &intel_connector->base; 2396 if (intel_sdvo_get_hotplug_support(intel_sdvo) & 2397 intel_sdvo_connector->output_flag) { 2398 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; 2399 /* Some SDVO devices have one-shot hotplug interrupts. 2400 * Ensure that they get re-enabled when an interrupt happens. 2401 */ 2402 intel_encoder->hot_plug = intel_sdvo_enable_hotplug; 2403 intel_sdvo_enable_hotplug(intel_encoder); 2404 } else { 2405 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; 2406 } 2407 encoder->encoder_type = DRM_MODE_ENCODER_TMDS; 2408 connector->connector_type = DRM_MODE_CONNECTOR_DVID; 2409 2410 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { 2411 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; 2412 intel_sdvo->is_hdmi = true; 2413 } 2414 2415 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2416 if (intel_sdvo->is_hdmi) 2417 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2418 2419 return true; 2420 } 2421 2422 static bool 2423 intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) 2424 { 2425 struct drm_encoder *encoder = &intel_sdvo->base.base; 2426 struct drm_connector *connector; 2427 struct intel_connector *intel_connector; 2428 struct intel_sdvo_connector *intel_sdvo_connector; 2429 2430 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2431 if (!intel_sdvo_connector) 2432 return false; 2433 2434 intel_connector = &intel_sdvo_connector->base; 2435 connector = &intel_connector->base; 2436 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; 2437 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; 2438 2439 intel_sdvo->controlled_output |= type; 2440 intel_sdvo_connector->output_flag = type; 2441 2442 intel_sdvo->is_tv = true; 2443 2444 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2445 2446 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2447 goto err; 2448 2449 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2450 goto err; 2451 2452 return true; 2453 2454 err: 2455 intel_sdvo_destroy(connector); 2456 return false; 2457 } 2458 2459 static bool 2460 intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) 2461 { 2462 struct drm_encoder *encoder = &intel_sdvo->base.base; 2463 struct drm_connector *connector; 2464 struct intel_connector *intel_connector; 2465 struct intel_sdvo_connector *intel_sdvo_connector; 2466 2467 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2468 if (!intel_sdvo_connector) 2469 return false; 2470 2471 intel_connector = &intel_sdvo_connector->base; 2472 connector = &intel_connector->base; 2473 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2474 encoder->encoder_type = DRM_MODE_ENCODER_DAC; 2475 connector->connector_type = DRM_MODE_CONNECTOR_VGA; 2476 2477 if (device == 0) { 2478 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; 2479 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; 2480 } else if (device == 1) { 2481 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; 2482 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2483 } 2484 2485 intel_sdvo_connector_init(intel_sdvo_connector, 2486 intel_sdvo); 2487 return true; 2488 } 2489 2490 static bool 2491 intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) 2492 { 2493 struct drm_encoder *encoder = &intel_sdvo->base.base; 2494 struct drm_connector *connector; 2495 struct intel_connector *intel_connector; 2496 struct intel_sdvo_connector *intel_sdvo_connector; 2497 2498 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); 2499 if (!intel_sdvo_connector) 2500 return false; 2501 2502 intel_connector = &intel_sdvo_connector->base; 2503 connector = &intel_connector->base; 2504 encoder->encoder_type = DRM_MODE_ENCODER_LVDS; 2505 connector->connector_type = DRM_MODE_CONNECTOR_LVDS; 2506 2507 if (device == 0) { 2508 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; 2509 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; 2510 } else if (device == 1) { 2511 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; 2512 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2513 } 2514 2515 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2516 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2517 goto err; 2518 2519 return true; 2520 2521 err: 2522 intel_sdvo_destroy(connector); 2523 return false; 2524 } 2525 2526 static bool 2527 intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) 2528 { 2529 intel_sdvo->is_tv = false; 2530 intel_sdvo->is_lvds = false; 2531 2532 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ 2533 2534 if (flags & SDVO_OUTPUT_TMDS0) 2535 if (!intel_sdvo_dvi_init(intel_sdvo, 0)) 2536 return false; 2537 2538 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) 2539 if (!intel_sdvo_dvi_init(intel_sdvo, 1)) 2540 return false; 2541 2542 /* TV has no XXX1 function block */ 2543 if (flags & SDVO_OUTPUT_SVID0) 2544 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) 2545 return false; 2546 2547 if (flags & SDVO_OUTPUT_CVBS0) 2548 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) 2549 return false; 2550 2551 if (flags & SDVO_OUTPUT_YPRPB0) 2552 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) 2553 return false; 2554 2555 if (flags & SDVO_OUTPUT_RGB0) 2556 if (!intel_sdvo_analog_init(intel_sdvo, 0)) 2557 return false; 2558 2559 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) 2560 if (!intel_sdvo_analog_init(intel_sdvo, 1)) 2561 return false; 2562 2563 if (flags & SDVO_OUTPUT_LVDS0) 2564 if (!intel_sdvo_lvds_init(intel_sdvo, 0)) 2565 return false; 2566 2567 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) 2568 if (!intel_sdvo_lvds_init(intel_sdvo, 1)) 2569 return false; 2570 2571 if ((flags & SDVO_OUTPUT_MASK) == 0) { 2572 unsigned char bytes[2]; 2573 2574 intel_sdvo->controlled_output = 0; 2575 memcpy(bytes, &intel_sdvo->caps.output_flags, 2); 2576 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", 2577 SDVO_NAME(intel_sdvo), 2578 bytes[0], bytes[1]); 2579 return false; 2580 } 2581 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2582 2583 return true; 2584 } 2585 2586 static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) 2587 { 2588 struct drm_device *dev = intel_sdvo->base.base.dev; 2589 struct drm_connector *connector, *tmp; 2590 2591 list_for_each_entry_safe(connector, tmp, 2592 &dev->mode_config.connector_list, head) { 2593 if (intel_attached_encoder(connector) == &intel_sdvo->base) 2594 intel_sdvo_destroy(connector); 2595 } 2596 } 2597 2598 static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, 2599 struct intel_sdvo_connector *intel_sdvo_connector, 2600 int type) 2601 { 2602 struct drm_device *dev = intel_sdvo->base.base.dev; 2603 struct intel_sdvo_tv_format format; 2604 uint32_t format_map, i; 2605 2606 if (!intel_sdvo_set_target_output(intel_sdvo, type)) 2607 return false; 2608 2609 BUILD_BUG_ON(sizeof(format) != 6); 2610 if (!intel_sdvo_get_value(intel_sdvo, 2611 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, 2612 &format, sizeof(format))) 2613 return false; 2614 2615 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); 2616 2617 if (format_map == 0) 2618 return false; 2619 2620 intel_sdvo_connector->format_supported_num = 0; 2621 for (i = 0 ; i < TV_FORMAT_NUM; i++) 2622 if (format_map & (1 << i)) 2623 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; 2624 2625 2626 intel_sdvo_connector->tv_format = 2627 drm_property_create(dev, DRM_MODE_PROP_ENUM, 2628 "mode", intel_sdvo_connector->format_supported_num); 2629 if (!intel_sdvo_connector->tv_format) 2630 return false; 2631 2632 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) 2633 drm_property_add_enum( 2634 intel_sdvo_connector->tv_format, i, 2635 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); 2636 2637 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; 2638 drm_object_attach_property(&intel_sdvo_connector->base.base.base, 2639 intel_sdvo_connector->tv_format, 0); 2640 return true; 2641 2642 } 2643 2644 #define ENHANCEMENT(name, NAME) do { \ 2645 if (enhancements.name) { \ 2646 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ 2647 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ 2648 return false; \ 2649 intel_sdvo_connector->max_##name = data_value[0]; \ 2650 intel_sdvo_connector->cur_##name = response; \ 2651 intel_sdvo_connector->name = \ 2652 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ 2653 if (!intel_sdvo_connector->name) return false; \ 2654 drm_object_attach_property(&connector->base, \ 2655 intel_sdvo_connector->name, \ 2656 intel_sdvo_connector->cur_##name); \ 2657 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ 2658 data_value[0], data_value[1], response); \ 2659 } \ 2660 } while (0) 2661 2662 static bool 2663 intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, 2664 struct intel_sdvo_connector *intel_sdvo_connector, 2665 struct intel_sdvo_enhancements_reply enhancements) 2666 { 2667 struct drm_device *dev = intel_sdvo->base.base.dev; 2668 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2669 uint16_t response, data_value[2]; 2670 2671 /* when horizontal overscan is supported, Add the left/right property */ 2672 if (enhancements.overscan_h) { 2673 if (!intel_sdvo_get_value(intel_sdvo, 2674 SDVO_CMD_GET_MAX_OVERSCAN_H, 2675 &data_value, 4)) 2676 return false; 2677 2678 if (!intel_sdvo_get_value(intel_sdvo, 2679 SDVO_CMD_GET_OVERSCAN_H, 2680 &response, 2)) 2681 return false; 2682 2683 intel_sdvo_connector->max_hscan = data_value[0]; 2684 intel_sdvo_connector->left_margin = data_value[0] - response; 2685 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; 2686 intel_sdvo_connector->left = 2687 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); 2688 if (!intel_sdvo_connector->left) 2689 return false; 2690 2691 drm_object_attach_property(&connector->base, 2692 intel_sdvo_connector->left, 2693 intel_sdvo_connector->left_margin); 2694 2695 intel_sdvo_connector->right = 2696 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); 2697 if (!intel_sdvo_connector->right) 2698 return false; 2699 2700 drm_object_attach_property(&connector->base, 2701 intel_sdvo_connector->right, 2702 intel_sdvo_connector->right_margin); 2703 DRM_DEBUG_KMS("h_overscan: max %d, " 2704 "default %d, current %d\n", 2705 data_value[0], data_value[1], response); 2706 } 2707 2708 if (enhancements.overscan_v) { 2709 if (!intel_sdvo_get_value(intel_sdvo, 2710 SDVO_CMD_GET_MAX_OVERSCAN_V, 2711 &data_value, 4)) 2712 return false; 2713 2714 if (!intel_sdvo_get_value(intel_sdvo, 2715 SDVO_CMD_GET_OVERSCAN_V, 2716 &response, 2)) 2717 return false; 2718 2719 intel_sdvo_connector->max_vscan = data_value[0]; 2720 intel_sdvo_connector->top_margin = data_value[0] - response; 2721 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; 2722 intel_sdvo_connector->top = 2723 drm_property_create_range(dev, 0, 2724 "top_margin", 0, data_value[0]); 2725 if (!intel_sdvo_connector->top) 2726 return false; 2727 2728 drm_object_attach_property(&connector->base, 2729 intel_sdvo_connector->top, 2730 intel_sdvo_connector->top_margin); 2731 2732 intel_sdvo_connector->bottom = 2733 drm_property_create_range(dev, 0, 2734 "bottom_margin", 0, data_value[0]); 2735 if (!intel_sdvo_connector->bottom) 2736 return false; 2737 2738 drm_object_attach_property(&connector->base, 2739 intel_sdvo_connector->bottom, 2740 intel_sdvo_connector->bottom_margin); 2741 DRM_DEBUG_KMS("v_overscan: max %d, " 2742 "default %d, current %d\n", 2743 data_value[0], data_value[1], response); 2744 } 2745 2746 ENHANCEMENT(hpos, HPOS); 2747 ENHANCEMENT(vpos, VPOS); 2748 ENHANCEMENT(saturation, SATURATION); 2749 ENHANCEMENT(contrast, CONTRAST); 2750 ENHANCEMENT(hue, HUE); 2751 ENHANCEMENT(sharpness, SHARPNESS); 2752 ENHANCEMENT(brightness, BRIGHTNESS); 2753 ENHANCEMENT(flicker_filter, FLICKER_FILTER); 2754 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); 2755 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); 2756 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); 2757 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); 2758 2759 if (enhancements.dot_crawl) { 2760 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) 2761 return false; 2762 2763 intel_sdvo_connector->max_dot_crawl = 1; 2764 intel_sdvo_connector->cur_dot_crawl = response & 0x1; 2765 intel_sdvo_connector->dot_crawl = 2766 drm_property_create_range(dev, 0, "dot_crawl", 0, 1); 2767 if (!intel_sdvo_connector->dot_crawl) 2768 return false; 2769 2770 drm_object_attach_property(&connector->base, 2771 intel_sdvo_connector->dot_crawl, 2772 intel_sdvo_connector->cur_dot_crawl); 2773 DRM_DEBUG_KMS("dot crawl: current %d\n", response); 2774 } 2775 2776 return true; 2777 } 2778 2779 static bool 2780 intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, 2781 struct intel_sdvo_connector *intel_sdvo_connector, 2782 struct intel_sdvo_enhancements_reply enhancements) 2783 { 2784 struct drm_device *dev = intel_sdvo->base.base.dev; 2785 struct drm_connector *connector = &intel_sdvo_connector->base.base; 2786 uint16_t response, data_value[2]; 2787 2788 ENHANCEMENT(brightness, BRIGHTNESS); 2789 2790 return true; 2791 } 2792 #undef ENHANCEMENT 2793 2794 static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, 2795 struct intel_sdvo_connector *intel_sdvo_connector) 2796 { 2797 union { 2798 struct intel_sdvo_enhancements_reply reply; 2799 uint16_t response; 2800 } enhancements; 2801 2802 BUILD_BUG_ON(sizeof(enhancements) != 2); 2803 2804 enhancements.response = 0; 2805 intel_sdvo_get_value(intel_sdvo, 2806 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, 2807 &enhancements, sizeof(enhancements)); 2808 if (enhancements.response == 0) { 2809 DRM_DEBUG_KMS("No enhancement is supported\n"); 2810 return true; 2811 } 2812 2813 if (IS_TV(intel_sdvo_connector)) 2814 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2815 else if (IS_LVDS(intel_sdvo_connector)) 2816 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); 2817 else 2818 return true; 2819 } 2820 2821 struct intel_sdvo_ddc_proxy_sc { 2822 struct intel_sdvo *intel_sdvo; 2823 device_t port; 2824 }; 2825 2826 static int 2827 intel_sdvo_ddc_proxy_probe(device_t idev) 2828 { 2829 2830 return (BUS_PROBE_DEFAULT); 2831 } 2832 2833 static int 2834 intel_sdvo_ddc_proxy_attach(device_t idev) 2835 { 2836 struct intel_sdvo_ddc_proxy_sc *sc; 2837 2838 sc = device_get_softc(idev); 2839 sc->port = device_add_child(idev, "iicbus", -1); 2840 if (sc->port == NULL) 2841 return (ENXIO); 2842 device_quiet(sc->port); 2843 bus_generic_attach(idev); 2844 return (0); 2845 } 2846 2847 static int 2848 intel_sdvo_ddc_proxy_detach(device_t idev) 2849 { 2850 struct intel_sdvo_ddc_proxy_sc *sc; 2851 device_t port; 2852 2853 sc = device_get_softc(idev); 2854 port = sc->port; 2855 bus_generic_detach(idev); 2856 if (port != NULL) 2857 device_delete_child(idev, port); 2858 return (0); 2859 } 2860 2861 static int 2862 intel_sdvo_ddc_proxy_reset(device_t idev, u_char speed, u_char addr, 2863 u_char *oldaddr) 2864 { 2865 struct intel_sdvo_ddc_proxy_sc *sc; 2866 struct intel_sdvo *sdvo; 2867 2868 sc = device_get_softc(idev); 2869 sdvo = sc->intel_sdvo; 2870 2871 return (IICBUS_RESET(device_get_parent(sdvo->i2c), speed, addr, 2872 oldaddr)); 2873 } 2874 2875 static int intel_sdvo_ddc_proxy_xfer(struct device *adapter, 2876 struct i2c_msg *msgs, 2877 int num) 2878 { 2879 struct intel_sdvo_ddc_proxy_sc *sc = device_get_softc(adapter); 2880 struct intel_sdvo *sdvo = sc->intel_sdvo; 2881 2882 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) 2883 return -EIO; 2884 2885 return (iicbus_transfer(sdvo->i2c, msgs, num)); 2886 } 2887 2888 static bool 2889 intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, struct drm_device *dev, 2890 int sdvo_reg) 2891 { 2892 struct intel_sdvo_ddc_proxy_sc *sc; 2893 int ret; 2894 2895 sdvo->ddc_iic_bus = device_add_child(dev->dev, 2896 "intel_sdvo_ddc_proxy", sdvo_reg); 2897 if (sdvo->ddc_iic_bus == NULL) { 2898 DRM_ERROR("cannot create ddc proxy bus %d\n", sdvo_reg); 2899 return (false); 2900 } 2901 device_quiet(sdvo->ddc_iic_bus); 2902 ret = device_probe_and_attach(sdvo->ddc_iic_bus); 2903 if (ret != 0) { 2904 DRM_ERROR("cannot attach proxy bus %d error %d\n", 2905 sdvo_reg, ret); 2906 device_delete_child(dev->dev, sdvo->ddc_iic_bus); 2907 return (false); 2908 } 2909 sc = device_get_softc(sdvo->ddc_iic_bus); 2910 sc->intel_sdvo = sdvo; 2911 2912 sdvo->ddc = sc->port; 2913 return (true); 2914 } 2915 2916 static device_method_t intel_sdvo_ddc_proxy_methods[] = { 2917 DEVMETHOD(device_probe, intel_sdvo_ddc_proxy_probe), 2918 DEVMETHOD(device_attach, intel_sdvo_ddc_proxy_attach), 2919 DEVMETHOD(device_detach, intel_sdvo_ddc_proxy_detach), 2920 DEVMETHOD(iicbus_reset, intel_sdvo_ddc_proxy_reset), 2921 DEVMETHOD(iicbus_transfer, intel_sdvo_ddc_proxy_xfer), 2922 DEVMETHOD_END 2923 }; 2924 static driver_t intel_sdvo_ddc_proxy_driver = { 2925 "intel_sdvo_ddc_proxy", 2926 intel_sdvo_ddc_proxy_methods, 2927 sizeof(struct intel_sdvo_ddc_proxy_sc) 2928 }; 2929 static devclass_t intel_sdvo_devclass; 2930 DRIVER_MODULE_ORDERED(intel_sdvo_ddc_proxy, drm, intel_sdvo_ddc_proxy_driver, 2931 intel_sdvo_devclass, 0, 0, SI_ORDER_FIRST); 2932 2933 bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) 2934 { 2935 struct drm_i915_private *dev_priv = dev->dev_private; 2936 struct intel_encoder *intel_encoder; 2937 struct intel_sdvo *intel_sdvo; 2938 int i; 2939 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); 2940 if (!intel_sdvo) 2941 return false; 2942 2943 intel_sdvo->sdvo_reg = sdvo_reg; 2944 intel_sdvo->is_sdvob = is_sdvob; 2945 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; 2946 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); 2947 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev, sdvo_reg)) 2948 goto err_i2c_bus; 2949 2950 /* encoder type will be decided later */ 2951 intel_encoder = &intel_sdvo->base; 2952 intel_encoder->type = INTEL_OUTPUT_SDVO; 2953 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); 2954 2955 /* Read the regs to test if we can talk to the device */ 2956 for (i = 0; i < 0x40; i++) { 2957 u8 byte; 2958 2959 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { 2960 DRM_DEBUG_KMS("No SDVO device found on %s\n", 2961 SDVO_NAME(intel_sdvo)); 2962 goto err; 2963 } 2964 } 2965 2966 intel_encoder->compute_config = intel_sdvo_compute_config; 2967 intel_encoder->disable = intel_disable_sdvo; 2968 intel_encoder->mode_set = intel_sdvo_mode_set; 2969 intel_encoder->enable = intel_enable_sdvo; 2970 intel_encoder->get_hw_state = intel_sdvo_get_hw_state; 2971 intel_encoder->get_config = intel_sdvo_get_config; 2972 2973 /* In default case sdvo lvds is false */ 2974 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) 2975 goto err; 2976 2977 if (intel_sdvo_output_setup(intel_sdvo, 2978 intel_sdvo->caps.output_flags) != true) { 2979 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", 2980 SDVO_NAME(intel_sdvo)); 2981 /* Output_setup can leave behind connectors! */ 2982 goto err_output; 2983 } 2984 2985 /* Only enable the hotplug irq if we need it, to work around noisy 2986 * hotplug lines. 2987 */ 2988 if (intel_sdvo->hotplug_active) { 2989 intel_encoder->hpd_pin = 2990 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; 2991 } 2992 2993 /* 2994 * Cloning SDVO with anything is often impossible, since the SDVO 2995 * encoder can request a special input timing mode. And even if that's 2996 * not the case we have evidence that cloning a plain unscaled mode with 2997 * VGA doesn't really work. Furthermore the cloning flags are way too 2998 * simplistic anyway to express such constraints, so just give up on 2999 * cloning for SDVO encoders. 3000 */ 3001 intel_sdvo->base.cloneable = false; 3002 3003 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); 3004 3005 /* Set the input timing to the screen. Assume always input 0. */ 3006 if (!intel_sdvo_set_target_input(intel_sdvo)) 3007 goto err_output; 3008 3009 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, 3010 &intel_sdvo->pixel_clock_min, 3011 &intel_sdvo->pixel_clock_max)) 3012 goto err_output; 3013 3014 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " 3015 "clock range %dMHz - %dMHz, " 3016 "input 1: %c, input 2: %c, " 3017 "output 1: %c, output 2: %c\n", 3018 SDVO_NAME(intel_sdvo), 3019 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, 3020 intel_sdvo->caps.device_rev_id, 3021 intel_sdvo->pixel_clock_min / 1000, 3022 intel_sdvo->pixel_clock_max / 1000, 3023 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', 3024 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', 3025 /* check currently supported outputs */ 3026 intel_sdvo->caps.output_flags & 3027 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', 3028 intel_sdvo->caps.output_flags & 3029 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); 3030 return true; 3031 3032 err_output: 3033 intel_sdvo_output_cleanup(intel_sdvo); 3034 3035 err: 3036 drm_encoder_cleanup(&intel_encoder->base); 3037 err_i2c_bus: 3038 intel_sdvo_unselect_i2c_bus(intel_sdvo); 3039 kfree(intel_sdvo); 3040 3041 return false; 3042 } 3043