1 /* 2 * Copyright © 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Jesse Barnes <jbarnes@virtuousgeek.org> 25 * 26 * New plane/sprite handling. 27 * 28 * The older chips had a separate interface for programming plane related 29 * registers; newer ones are much simpler and we can use the new DRM plane 30 * support. 31 */ 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_fourcc.h> 35 #include <drm/drm_rect.h> 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_plane_helper.h> 38 #include "intel_drv.h" 39 #include <drm/i915_drm.h> 40 #include "i915_drv.h" 41 42 static bool 43 format_is_yuv(uint32_t format) 44 { 45 switch (format) { 46 case DRM_FORMAT_YUYV: 47 case DRM_FORMAT_UYVY: 48 case DRM_FORMAT_VYUY: 49 case DRM_FORMAT_YVYU: 50 return true; 51 default: 52 return false; 53 } 54 } 55 56 static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 57 int usecs) 58 { 59 /* paranoia */ 60 if (!adjusted_mode->crtc_htotal) 61 return 1; 62 63 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, 64 1000 * adjusted_mode->crtc_htotal); 65 } 66 67 /** 68 * intel_pipe_update_start() - start update of a set of display registers 69 * @crtc: the crtc of which the registers are going to be updated 70 * @start_vbl_count: vblank counter return pointer used for error checking 71 * 72 * Mark the start of an update to pipe registers that should be updated 73 * atomically regarding vblank. If the next vblank will happens within 74 * the next 100 us, this function waits until the vblank passes. 75 * 76 * After a successful call to this function, interrupts will be disabled 77 * until a subsequent call to intel_pipe_update_end(). That is done to 78 * avoid random delays. The value written to @start_vbl_count should be 79 * supplied to intel_pipe_update_end() for error checking. 80 */ 81 void intel_pipe_update_start(struct intel_crtc *crtc) 82 { 83 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 84 long timeout = msecs_to_jiffies_timeout(1); 85 int scanline, min, max, vblank_start; 86 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 87 DEFINE_WAIT(wait); 88 89 vblank_start = adjusted_mode->crtc_vblank_start; 90 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 91 vblank_start = DIV_ROUND_UP(vblank_start, 2); 92 93 /* FIXME needs to be calibrated sensibly */ 94 min = vblank_start - usecs_to_scanlines(adjusted_mode, 100); 95 max = vblank_start - 1; 96 97 local_irq_disable(); 98 99 if (min <= 0 || max <= 0) 100 return; 101 102 if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) 103 return; 104 105 crtc->debug.min_vbl = min; 106 crtc->debug.max_vbl = max; 107 trace_i915_pipe_update_start(crtc); 108 109 for (;;) { 110 /* 111 * prepare_to_wait() has a memory barrier, which guarantees 112 * other CPUs can see the task state update by the time we 113 * read the scanline. 114 */ 115 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); 116 117 scanline = intel_get_crtc_scanline(crtc); 118 if (scanline < min || scanline > max) 119 break; 120 121 if (timeout <= 0) { 122 DRM_ERROR("Potential atomic update failure on pipe %c\n", 123 pipe_name(crtc->pipe)); 124 break; 125 } 126 127 local_irq_enable(); 128 129 timeout = schedule_timeout(timeout); 130 131 local_irq_disable(); 132 } 133 134 finish_wait(wq, &wait); 135 136 drm_crtc_vblank_put(&crtc->base); 137 138 crtc->debug.scanline_start = scanline; 139 crtc->debug.start_vbl_time = ktime_get(); 140 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc); 141 142 trace_i915_pipe_update_vblank_evaded(crtc); 143 } 144 145 /** 146 * intel_pipe_update_end() - end update of a set of display registers 147 * @crtc: the crtc of which the registers were updated 148 * @start_vbl_count: start vblank counter (used for error checking) 149 * 150 * Mark the end of an update started with intel_pipe_update_start(). This 151 * re-enables interrupts and verifies the update was actually completed 152 * before a vblank using the value of @start_vbl_count. 153 */ 154 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work) 155 { 156 enum i915_pipe pipe = crtc->pipe; 157 int scanline_end = intel_get_crtc_scanline(crtc); 158 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); 159 ktime_t end_vbl_time = ktime_get(); 160 161 if (work) { 162 work->flip_queued_vblank = end_vbl_count; 163 smp_mb__before_atomic(); 164 atomic_set(&work->pending, 1); 165 } 166 167 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); 168 169 /* We're still in the vblank-evade critical section, this can't race. 170 * Would be slightly nice to just grab the vblank count and arm the 171 * event outside of the critical section - the spinlock might spin for a 172 * while ... */ 173 if (crtc->base.state->event) { 174 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); 175 176 lockmgr(&crtc->base.dev->event_lock, LK_EXCLUSIVE); 177 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event); 178 lockmgr(&crtc->base.dev->event_lock, LK_RELEASE); 179 180 crtc->base.state->event = NULL; 181 } 182 183 local_irq_enable(); 184 185 if (crtc->debug.start_vbl_count && 186 crtc->debug.start_vbl_count != end_vbl_count) { 187 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", 188 pipe_name(pipe), crtc->debug.start_vbl_count, 189 end_vbl_count, 190 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), 191 crtc->debug.min_vbl, crtc->debug.max_vbl, 192 crtc->debug.scanline_start, scanline_end); 193 } 194 } 195 196 static void 197 skl_update_plane(struct drm_plane *drm_plane, 198 const struct intel_crtc_state *crtc_state, 199 const struct intel_plane_state *plane_state) 200 { 201 struct drm_device *dev = drm_plane->dev; 202 struct drm_i915_private *dev_priv = dev->dev_private; 203 struct intel_plane *intel_plane = to_intel_plane(drm_plane); 204 struct drm_framebuffer *fb = plane_state->base.fb; 205 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 206 const int pipe = intel_plane->pipe; 207 const int plane = intel_plane->plane + 1; 208 u32 plane_ctl, stride_div, stride; 209 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 210 u32 surf_addr; 211 u32 tile_height, plane_offset, plane_size; 212 unsigned int rotation = plane_state->base.rotation; 213 int x_offset, y_offset; 214 int crtc_x = plane_state->dst.x1; 215 int crtc_y = plane_state->dst.y1; 216 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 217 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 218 uint32_t x = plane_state->src.x1 >> 16; 219 uint32_t y = plane_state->src.y1 >> 16; 220 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 221 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 222 223 plane_ctl = PLANE_CTL_ENABLE | 224 PLANE_CTL_PIPE_GAMMA_ENABLE | 225 PLANE_CTL_PIPE_CSC_ENABLE; 226 227 plane_ctl |= skl_plane_ctl_format(fb->pixel_format); 228 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); 229 230 plane_ctl |= skl_plane_ctl_rotation(rotation); 231 232 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], 233 fb->pixel_format); 234 235 /* Sizes are 0 based */ 236 src_w--; 237 src_h--; 238 crtc_w--; 239 crtc_h--; 240 241 if (key->flags) { 242 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); 243 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); 244 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); 245 } 246 247 if (key->flags & I915_SET_COLORKEY_DESTINATION) 248 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; 249 else if (key->flags & I915_SET_COLORKEY_SOURCE) 250 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; 251 252 surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); 253 254 if (intel_rotation_90_or_270(rotation)) { 255 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 256 257 /* stride: Surface height in tiles */ 258 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); 259 stride = DIV_ROUND_UP(fb->height, tile_height); 260 plane_size = (src_w << 16) | src_h; 261 x_offset = stride * tile_height - y - (src_h + 1); 262 y_offset = x; 263 } else { 264 stride = fb->pitches[0] / stride_div; 265 plane_size = (src_h << 16) | src_w; 266 x_offset = x; 267 y_offset = y; 268 } 269 plane_offset = y_offset << 16 | x_offset; 270 271 I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); 272 I915_WRITE(PLANE_STRIDE(pipe, plane), stride); 273 I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); 274 275 /* program plane scaler */ 276 if (plane_state->scaler_id >= 0) { 277 int scaler_id = plane_state->scaler_id; 278 const struct intel_scaler *scaler; 279 280 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, 281 PS_PLANE_SEL(plane)); 282 283 scaler = &crtc_state->scaler_state.scalers[scaler_id]; 284 285 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), 286 PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode); 287 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); 288 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); 289 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), 290 ((crtc_w + 1) << 16)|(crtc_h + 1)); 291 292 I915_WRITE(PLANE_POS(pipe, plane), 0); 293 } else { 294 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); 295 } 296 297 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); 298 I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); 299 POSTING_READ(PLANE_SURF(pipe, plane)); 300 } 301 302 static void 303 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) 304 { 305 struct drm_device *dev = dplane->dev; 306 struct drm_i915_private *dev_priv = dev->dev_private; 307 struct intel_plane *intel_plane = to_intel_plane(dplane); 308 const int pipe = intel_plane->pipe; 309 const int plane = intel_plane->plane + 1; 310 311 I915_WRITE(PLANE_CTL(pipe, plane), 0); 312 313 I915_WRITE(PLANE_SURF(pipe, plane), 0); 314 POSTING_READ(PLANE_SURF(pipe, plane)); 315 } 316 317 static void 318 chv_update_csc(struct intel_plane *intel_plane, uint32_t format) 319 { 320 struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private; 321 int plane = intel_plane->plane; 322 323 /* Seems RGB data bypasses the CSC always */ 324 if (!format_is_yuv(format)) 325 return; 326 327 /* 328 * BT.601 limited range YCbCr -> full range RGB 329 * 330 * |r| | 6537 4769 0| |cr | 331 * |g| = |-3330 4769 -1605| x |y-64| 332 * |b| | 0 4769 8263| |cb | 333 * 334 * Cb and Cr apparently come in as signed already, so no 335 * need for any offset. For Y we need to remove the offset. 336 */ 337 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); 338 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 339 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 340 341 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); 342 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); 343 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); 344 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); 345 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); 346 347 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); 348 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); 349 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); 350 351 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 352 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 353 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 354 } 355 356 static void 357 vlv_update_plane(struct drm_plane *dplane, 358 const struct intel_crtc_state *crtc_state, 359 const struct intel_plane_state *plane_state) 360 { 361 struct drm_device *dev = dplane->dev; 362 struct drm_i915_private *dev_priv = dev->dev_private; 363 struct intel_plane *intel_plane = to_intel_plane(dplane); 364 struct drm_framebuffer *fb = plane_state->base.fb; 365 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 366 int pipe = intel_plane->pipe; 367 int plane = intel_plane->plane; 368 u32 sprctl; 369 u32 sprsurf_offset, linear_offset; 370 unsigned int rotation = dplane->state->rotation; 371 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 372 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 373 int crtc_x = plane_state->dst.x1; 374 int crtc_y = plane_state->dst.y1; 375 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 376 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 377 uint32_t x = plane_state->src.x1 >> 16; 378 uint32_t y = plane_state->src.y1 >> 16; 379 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 380 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 381 382 sprctl = SP_ENABLE; 383 384 switch (fb->pixel_format) { 385 case DRM_FORMAT_YUYV: 386 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; 387 break; 388 case DRM_FORMAT_YVYU: 389 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; 390 break; 391 case DRM_FORMAT_UYVY: 392 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; 393 break; 394 case DRM_FORMAT_VYUY: 395 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; 396 break; 397 case DRM_FORMAT_RGB565: 398 sprctl |= SP_FORMAT_BGR565; 399 break; 400 case DRM_FORMAT_XRGB8888: 401 sprctl |= SP_FORMAT_BGRX8888; 402 break; 403 case DRM_FORMAT_ARGB8888: 404 sprctl |= SP_FORMAT_BGRA8888; 405 break; 406 case DRM_FORMAT_XBGR2101010: 407 sprctl |= SP_FORMAT_RGBX1010102; 408 break; 409 case DRM_FORMAT_ABGR2101010: 410 sprctl |= SP_FORMAT_RGBA1010102; 411 break; 412 case DRM_FORMAT_XBGR8888: 413 sprctl |= SP_FORMAT_RGBX8888; 414 break; 415 case DRM_FORMAT_ABGR8888: 416 sprctl |= SP_FORMAT_RGBA8888; 417 break; 418 default: 419 /* 420 * If we get here one of the upper layers failed to filter 421 * out the unsupported plane formats 422 */ 423 BUG(); 424 break; 425 } 426 427 /* 428 * Enable gamma to match primary/cursor plane behaviour. 429 * FIXME should be user controllable via propertiesa. 430 */ 431 sprctl |= SP_GAMMA_ENABLE; 432 433 if (obj->tiling_mode != I915_TILING_NONE) 434 sprctl |= SP_TILED; 435 436 /* Sizes are 0 based */ 437 src_w--; 438 src_h--; 439 crtc_w--; 440 crtc_h--; 441 442 linear_offset = y * fb->pitches[0] + x * cpp; 443 sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, 444 fb->pitches[0], rotation); 445 linear_offset -= sprsurf_offset; 446 447 if (rotation == DRM_ROTATE_180) { 448 sprctl |= SP_ROTATE_180; 449 450 x += src_w; 451 y += src_h; 452 linear_offset += src_h * fb->pitches[0] + src_w * cpp; 453 } 454 455 if (key->flags) { 456 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); 457 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); 458 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); 459 } 460 461 if (key->flags & I915_SET_COLORKEY_SOURCE) 462 sprctl |= SP_SOURCE_KEY; 463 464 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) 465 chv_update_csc(intel_plane, fb->pixel_format); 466 467 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); 468 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); 469 470 if (obj->tiling_mode != I915_TILING_NONE) 471 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); 472 else 473 I915_WRITE(SPLINOFF(pipe, plane), linear_offset); 474 475 I915_WRITE(SPCONSTALPHA(pipe, plane), 0); 476 477 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); 478 I915_WRITE(SPCNTR(pipe, plane), sprctl); 479 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + 480 sprsurf_offset); 481 POSTING_READ(SPSURF(pipe, plane)); 482 } 483 484 static void 485 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) 486 { 487 struct drm_device *dev = dplane->dev; 488 struct drm_i915_private *dev_priv = dev->dev_private; 489 struct intel_plane *intel_plane = to_intel_plane(dplane); 490 int pipe = intel_plane->pipe; 491 int plane = intel_plane->plane; 492 493 I915_WRITE(SPCNTR(pipe, plane), 0); 494 495 I915_WRITE(SPSURF(pipe, plane), 0); 496 POSTING_READ(SPSURF(pipe, plane)); 497 } 498 499 static void 500 ivb_update_plane(struct drm_plane *plane, 501 const struct intel_crtc_state *crtc_state, 502 const struct intel_plane_state *plane_state) 503 { 504 struct drm_device *dev = plane->dev; 505 struct drm_i915_private *dev_priv = dev->dev_private; 506 struct intel_plane *intel_plane = to_intel_plane(plane); 507 struct drm_framebuffer *fb = plane_state->base.fb; 508 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 509 enum i915_pipe pipe = intel_plane->pipe; 510 u32 sprctl, sprscale = 0; 511 u32 sprsurf_offset, linear_offset; 512 unsigned int rotation = plane_state->base.rotation; 513 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 514 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 515 int crtc_x = plane_state->dst.x1; 516 int crtc_y = plane_state->dst.y1; 517 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 518 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 519 uint32_t x = plane_state->src.x1 >> 16; 520 uint32_t y = plane_state->src.y1 >> 16; 521 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 522 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 523 524 sprctl = SPRITE_ENABLE; 525 526 switch (fb->pixel_format) { 527 case DRM_FORMAT_XBGR8888: 528 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; 529 break; 530 case DRM_FORMAT_XRGB8888: 531 sprctl |= SPRITE_FORMAT_RGBX888; 532 break; 533 case DRM_FORMAT_YUYV: 534 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; 535 break; 536 case DRM_FORMAT_YVYU: 537 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; 538 break; 539 case DRM_FORMAT_UYVY: 540 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; 541 break; 542 case DRM_FORMAT_VYUY: 543 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; 544 break; 545 default: 546 BUG(); 547 } 548 549 /* 550 * Enable gamma to match primary/cursor plane behaviour. 551 * FIXME should be user controllable via propertiesa. 552 */ 553 sprctl |= SPRITE_GAMMA_ENABLE; 554 555 if (obj->tiling_mode != I915_TILING_NONE) 556 sprctl |= SPRITE_TILED; 557 558 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 559 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; 560 else 561 sprctl |= SPRITE_TRICKLE_FEED_DISABLE; 562 563 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 564 sprctl |= SPRITE_PIPE_CSC_ENABLE; 565 566 /* Sizes are 0 based */ 567 src_w--; 568 src_h--; 569 crtc_w--; 570 crtc_h--; 571 572 if (crtc_w != src_w || crtc_h != src_h) 573 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; 574 575 linear_offset = y * fb->pitches[0] + x * cpp; 576 sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, 577 fb->pitches[0], rotation); 578 linear_offset -= sprsurf_offset; 579 580 if (rotation == DRM_ROTATE_180) { 581 sprctl |= SPRITE_ROTATE_180; 582 583 /* HSW and BDW does this automagically in hardware */ 584 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { 585 x += src_w; 586 y += src_h; 587 linear_offset += src_h * fb->pitches[0] + src_w * cpp; 588 } 589 } 590 591 if (key->flags) { 592 I915_WRITE(SPRKEYVAL(pipe), key->min_value); 593 I915_WRITE(SPRKEYMAX(pipe), key->max_value); 594 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); 595 } 596 597 if (key->flags & I915_SET_COLORKEY_DESTINATION) 598 sprctl |= SPRITE_DEST_KEY; 599 else if (key->flags & I915_SET_COLORKEY_SOURCE) 600 sprctl |= SPRITE_SOURCE_KEY; 601 602 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); 603 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); 604 605 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET 606 * register */ 607 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 608 I915_WRITE(SPROFFSET(pipe), (y << 16) | x); 609 else if (obj->tiling_mode != I915_TILING_NONE) 610 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); 611 else 612 I915_WRITE(SPRLINOFF(pipe), linear_offset); 613 614 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); 615 if (intel_plane->can_scale) 616 I915_WRITE(SPRSCALE(pipe), sprscale); 617 I915_WRITE(SPRCTL(pipe), sprctl); 618 I915_WRITE(SPRSURF(pipe), 619 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); 620 POSTING_READ(SPRSURF(pipe)); 621 } 622 623 static void 624 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) 625 { 626 struct drm_device *dev = plane->dev; 627 struct drm_i915_private *dev_priv = dev->dev_private; 628 struct intel_plane *intel_plane = to_intel_plane(plane); 629 int pipe = intel_plane->pipe; 630 631 I915_WRITE(SPRCTL(pipe), 0); 632 /* Can't leave the scaler enabled... */ 633 if (intel_plane->can_scale) 634 I915_WRITE(SPRSCALE(pipe), 0); 635 636 I915_WRITE(SPRSURF(pipe), 0); 637 POSTING_READ(SPRSURF(pipe)); 638 } 639 640 static void 641 ilk_update_plane(struct drm_plane *plane, 642 const struct intel_crtc_state *crtc_state, 643 const struct intel_plane_state *plane_state) 644 { 645 struct drm_device *dev = plane->dev; 646 struct drm_i915_private *dev_priv = dev->dev_private; 647 struct intel_plane *intel_plane = to_intel_plane(plane); 648 struct drm_framebuffer *fb = plane_state->base.fb; 649 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 650 int pipe = intel_plane->pipe; 651 u32 dvscntr, dvsscale; 652 u32 dvssurf_offset, linear_offset; 653 unsigned int rotation = plane_state->base.rotation; 654 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 655 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 656 int crtc_x = plane_state->dst.x1; 657 int crtc_y = plane_state->dst.y1; 658 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 659 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 660 uint32_t x = plane_state->src.x1 >> 16; 661 uint32_t y = plane_state->src.y1 >> 16; 662 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 663 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 664 665 dvscntr = DVS_ENABLE; 666 667 switch (fb->pixel_format) { 668 case DRM_FORMAT_XBGR8888: 669 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; 670 break; 671 case DRM_FORMAT_XRGB8888: 672 dvscntr |= DVS_FORMAT_RGBX888; 673 break; 674 case DRM_FORMAT_YUYV: 675 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; 676 break; 677 case DRM_FORMAT_YVYU: 678 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; 679 break; 680 case DRM_FORMAT_UYVY: 681 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; 682 break; 683 case DRM_FORMAT_VYUY: 684 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; 685 break; 686 default: 687 BUG(); 688 } 689 690 /* 691 * Enable gamma to match primary/cursor plane behaviour. 692 * FIXME should be user controllable via propertiesa. 693 */ 694 dvscntr |= DVS_GAMMA_ENABLE; 695 696 if (obj->tiling_mode != I915_TILING_NONE) 697 dvscntr |= DVS_TILED; 698 699 if (IS_GEN6(dev)) 700 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ 701 702 /* Sizes are 0 based */ 703 src_w--; 704 src_h--; 705 crtc_w--; 706 crtc_h--; 707 708 dvsscale = 0; 709 if (crtc_w != src_w || crtc_h != src_h) 710 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; 711 712 linear_offset = y * fb->pitches[0] + x * cpp; 713 dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, 714 fb->pitches[0], rotation); 715 linear_offset -= dvssurf_offset; 716 717 if (rotation == DRM_ROTATE_180) { 718 dvscntr |= DVS_ROTATE_180; 719 720 x += src_w; 721 y += src_h; 722 linear_offset += src_h * fb->pitches[0] + src_w * cpp; 723 } 724 725 if (key->flags) { 726 I915_WRITE(DVSKEYVAL(pipe), key->min_value); 727 I915_WRITE(DVSKEYMAX(pipe), key->max_value); 728 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); 729 } 730 731 if (key->flags & I915_SET_COLORKEY_DESTINATION) 732 dvscntr |= DVS_DEST_KEY; 733 else if (key->flags & I915_SET_COLORKEY_SOURCE) 734 dvscntr |= DVS_SOURCE_KEY; 735 736 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); 737 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); 738 739 if (obj->tiling_mode != I915_TILING_NONE) 740 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); 741 else 742 I915_WRITE(DVSLINOFF(pipe), linear_offset); 743 744 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); 745 I915_WRITE(DVSSCALE(pipe), dvsscale); 746 I915_WRITE(DVSCNTR(pipe), dvscntr); 747 I915_WRITE(DVSSURF(pipe), 748 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); 749 POSTING_READ(DVSSURF(pipe)); 750 } 751 752 static void 753 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) 754 { 755 struct drm_device *dev = plane->dev; 756 struct drm_i915_private *dev_priv = dev->dev_private; 757 struct intel_plane *intel_plane = to_intel_plane(plane); 758 int pipe = intel_plane->pipe; 759 760 I915_WRITE(DVSCNTR(pipe), 0); 761 /* Disable the scaler */ 762 I915_WRITE(DVSSCALE(pipe), 0); 763 764 I915_WRITE(DVSSURF(pipe), 0); 765 POSTING_READ(DVSSURF(pipe)); 766 } 767 768 static int 769 intel_check_sprite_plane(struct drm_plane *plane, 770 struct intel_crtc_state *crtc_state, 771 struct intel_plane_state *state) 772 { 773 struct drm_device *dev = plane->dev; 774 struct drm_crtc *crtc = state->base.crtc; 775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 776 struct intel_plane *intel_plane = to_intel_plane(plane); 777 struct drm_framebuffer *fb = state->base.fb; 778 int crtc_x, crtc_y; 779 unsigned int crtc_w, crtc_h; 780 uint32_t src_x, src_y, src_w, src_h; 781 struct drm_rect *src = &state->src; 782 struct drm_rect *dst = &state->dst; 783 const struct drm_rect *clip = &state->clip; 784 int hscale, vscale; 785 int max_scale, min_scale; 786 bool can_scale; 787 788 if (!fb) { 789 state->visible = false; 790 return 0; 791 } 792 793 /* Don't modify another pipe's plane */ 794 if (intel_plane->pipe != intel_crtc->pipe) { 795 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); 796 return -EINVAL; 797 } 798 799 /* FIXME check all gen limits */ 800 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { 801 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); 802 return -EINVAL; 803 } 804 805 /* setup can_scale, min_scale, max_scale */ 806 if (INTEL_INFO(dev)->gen >= 9) { 807 /* use scaler when colorkey is not required */ 808 if (state->ckey.flags == I915_SET_COLORKEY_NONE) { 809 can_scale = 1; 810 min_scale = 1; 811 max_scale = skl_max_scale(intel_crtc, crtc_state); 812 } else { 813 can_scale = 0; 814 min_scale = DRM_PLANE_HELPER_NO_SCALING; 815 max_scale = DRM_PLANE_HELPER_NO_SCALING; 816 } 817 } else { 818 can_scale = intel_plane->can_scale; 819 max_scale = intel_plane->max_downscale << 16; 820 min_scale = intel_plane->can_scale ? 1 : (1 << 16); 821 } 822 823 /* 824 * FIXME the following code does a bunch of fuzzy adjustments to the 825 * coordinates and sizes. We probably need some way to decide whether 826 * more strict checking should be done instead. 827 */ 828 drm_rect_rotate(src, fb->width << 16, fb->height << 16, 829 state->base.rotation); 830 831 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); 832 BUG_ON(hscale < 0); 833 834 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); 835 BUG_ON(vscale < 0); 836 837 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); 838 839 crtc_x = dst->x1; 840 crtc_y = dst->y1; 841 crtc_w = drm_rect_width(dst); 842 crtc_h = drm_rect_height(dst); 843 844 if (state->visible) { 845 /* check again in case clipping clamped the results */ 846 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); 847 if (hscale < 0) { 848 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); 849 drm_rect_debug_print("src: ", src, true); 850 drm_rect_debug_print("dst: ", dst, false); 851 852 return hscale; 853 } 854 855 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); 856 if (vscale < 0) { 857 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); 858 drm_rect_debug_print("src: ", src, true); 859 drm_rect_debug_print("dst: ", dst, false); 860 861 return vscale; 862 } 863 864 /* Make the source viewport size an exact multiple of the scaling factors. */ 865 drm_rect_adjust_size(src, 866 drm_rect_width(dst) * hscale - drm_rect_width(src), 867 drm_rect_height(dst) * vscale - drm_rect_height(src)); 868 869 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, 870 state->base.rotation); 871 872 /* sanity check to make sure the src viewport wasn't enlarged */ 873 WARN_ON(src->x1 < (int) state->base.src_x || 874 src->y1 < (int) state->base.src_y || 875 src->x2 > (int) state->base.src_x + state->base.src_w || 876 src->y2 > (int) state->base.src_y + state->base.src_h); 877 878 /* 879 * Hardware doesn't handle subpixel coordinates. 880 * Adjust to (macro)pixel boundary, but be careful not to 881 * increase the source viewport size, because that could 882 * push the downscaling factor out of bounds. 883 */ 884 src_x = src->x1 >> 16; 885 src_w = drm_rect_width(src) >> 16; 886 src_y = src->y1 >> 16; 887 src_h = drm_rect_height(src) >> 16; 888 889 if (format_is_yuv(fb->pixel_format)) { 890 src_x &= ~1; 891 src_w &= ~1; 892 893 /* 894 * Must keep src and dst the 895 * same if we can't scale. 896 */ 897 if (!can_scale) 898 crtc_w &= ~1; 899 900 if (crtc_w == 0) 901 state->visible = false; 902 } 903 } 904 905 /* Check size restrictions when scaling */ 906 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { 907 unsigned int width_bytes; 908 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 909 910 WARN_ON(!can_scale); 911 912 /* FIXME interlacing min height is 6 */ 913 914 if (crtc_w < 3 || crtc_h < 3) 915 state->visible = false; 916 917 if (src_w < 3 || src_h < 3) 918 state->visible = false; 919 920 width_bytes = ((src_x * cpp) & 63) + src_w * cpp; 921 922 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || 923 width_bytes > 4096 || fb->pitches[0] > 4096)) { 924 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); 925 return -EINVAL; 926 } 927 } 928 929 if (state->visible) { 930 src->x1 = src_x << 16; 931 src->x2 = (src_x + src_w) << 16; 932 src->y1 = src_y << 16; 933 src->y2 = (src_y + src_h) << 16; 934 } 935 936 dst->x1 = crtc_x; 937 dst->x2 = crtc_x + crtc_w; 938 dst->y1 = crtc_y; 939 dst->y2 = crtc_y + crtc_h; 940 941 return 0; 942 } 943 944 int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 945 struct drm_file *file_priv) 946 { 947 struct drm_intel_sprite_colorkey *set = data; 948 struct drm_plane *plane; 949 struct drm_plane_state *plane_state; 950 struct drm_atomic_state *state; 951 struct drm_modeset_acquire_ctx ctx; 952 int ret = 0; 953 954 /* Make sure we don't try to enable both src & dest simultaneously */ 955 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) 956 return -EINVAL; 957 958 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 959 set->flags & I915_SET_COLORKEY_DESTINATION) 960 return -EINVAL; 961 962 plane = drm_plane_find(dev, set->plane_id); 963 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) 964 return -ENOENT; 965 966 drm_modeset_acquire_init(&ctx, 0); 967 968 state = drm_atomic_state_alloc(plane->dev); 969 if (!state) { 970 ret = -ENOMEM; 971 goto out; 972 } 973 state->acquire_ctx = &ctx; 974 975 while (1) { 976 plane_state = drm_atomic_get_plane_state(state, plane); 977 ret = PTR_ERR_OR_ZERO(plane_state); 978 if (!ret) { 979 to_intel_plane_state(plane_state)->ckey = *set; 980 ret = drm_atomic_commit(state); 981 } 982 983 if (ret != -EDEADLK) 984 break; 985 986 drm_atomic_state_clear(state); 987 drm_modeset_backoff(&ctx); 988 } 989 990 if (ret) 991 drm_atomic_state_free(state); 992 993 out: 994 drm_modeset_drop_locks(&ctx); 995 drm_modeset_acquire_fini(&ctx); 996 return ret; 997 } 998 999 static const uint32_t ilk_plane_formats[] = { 1000 DRM_FORMAT_XRGB8888, 1001 DRM_FORMAT_YUYV, 1002 DRM_FORMAT_YVYU, 1003 DRM_FORMAT_UYVY, 1004 DRM_FORMAT_VYUY, 1005 }; 1006 1007 static const uint32_t snb_plane_formats[] = { 1008 DRM_FORMAT_XBGR8888, 1009 DRM_FORMAT_XRGB8888, 1010 DRM_FORMAT_YUYV, 1011 DRM_FORMAT_YVYU, 1012 DRM_FORMAT_UYVY, 1013 DRM_FORMAT_VYUY, 1014 }; 1015 1016 static const uint32_t vlv_plane_formats[] = { 1017 DRM_FORMAT_RGB565, 1018 DRM_FORMAT_ABGR8888, 1019 DRM_FORMAT_ARGB8888, 1020 DRM_FORMAT_XBGR8888, 1021 DRM_FORMAT_XRGB8888, 1022 DRM_FORMAT_XBGR2101010, 1023 DRM_FORMAT_ABGR2101010, 1024 DRM_FORMAT_YUYV, 1025 DRM_FORMAT_YVYU, 1026 DRM_FORMAT_UYVY, 1027 DRM_FORMAT_VYUY, 1028 }; 1029 1030 static uint32_t skl_plane_formats[] = { 1031 DRM_FORMAT_RGB565, 1032 DRM_FORMAT_ABGR8888, 1033 DRM_FORMAT_ARGB8888, 1034 DRM_FORMAT_XBGR8888, 1035 DRM_FORMAT_XRGB8888, 1036 DRM_FORMAT_YUYV, 1037 DRM_FORMAT_YVYU, 1038 DRM_FORMAT_UYVY, 1039 DRM_FORMAT_VYUY, 1040 }; 1041 1042 int 1043 intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane) 1044 { 1045 struct intel_plane *intel_plane = NULL; 1046 struct intel_plane_state *state = NULL; 1047 unsigned long possible_crtcs; 1048 const uint32_t *plane_formats; 1049 int num_plane_formats; 1050 int ret; 1051 1052 if (INTEL_INFO(dev)->gen < 5) 1053 return -ENODEV; 1054 1055 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); 1056 if (!intel_plane) { 1057 ret = -ENOMEM; 1058 goto fail; 1059 } 1060 1061 state = intel_create_plane_state(&intel_plane->base); 1062 if (!state) { 1063 ret = -ENOMEM; 1064 goto fail; 1065 } 1066 intel_plane->base.state = &state->base; 1067 1068 switch (INTEL_INFO(dev)->gen) { 1069 case 5: 1070 case 6: 1071 intel_plane->can_scale = true; 1072 intel_plane->max_downscale = 16; 1073 intel_plane->update_plane = ilk_update_plane; 1074 intel_plane->disable_plane = ilk_disable_plane; 1075 1076 if (IS_GEN6(dev)) { 1077 plane_formats = snb_plane_formats; 1078 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1079 } else { 1080 plane_formats = ilk_plane_formats; 1081 num_plane_formats = ARRAY_SIZE(ilk_plane_formats); 1082 } 1083 break; 1084 1085 case 7: 1086 case 8: 1087 if (IS_IVYBRIDGE(dev)) { 1088 intel_plane->can_scale = true; 1089 intel_plane->max_downscale = 2; 1090 } else { 1091 intel_plane->can_scale = false; 1092 intel_plane->max_downscale = 1; 1093 } 1094 1095 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 1096 intel_plane->update_plane = vlv_update_plane; 1097 intel_plane->disable_plane = vlv_disable_plane; 1098 1099 plane_formats = vlv_plane_formats; 1100 num_plane_formats = ARRAY_SIZE(vlv_plane_formats); 1101 } else { 1102 intel_plane->update_plane = ivb_update_plane; 1103 intel_plane->disable_plane = ivb_disable_plane; 1104 1105 plane_formats = snb_plane_formats; 1106 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1107 } 1108 break; 1109 case 9: 1110 intel_plane->can_scale = true; 1111 intel_plane->update_plane = skl_update_plane; 1112 intel_plane->disable_plane = skl_disable_plane; 1113 state->scaler_id = -1; 1114 1115 plane_formats = skl_plane_formats; 1116 num_plane_formats = ARRAY_SIZE(skl_plane_formats); 1117 break; 1118 default: 1119 MISSING_CASE(INTEL_INFO(dev)->gen); 1120 ret = -ENODEV; 1121 goto fail; 1122 } 1123 1124 intel_plane->pipe = pipe; 1125 intel_plane->plane = plane; 1126 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); 1127 intel_plane->check_plane = intel_check_sprite_plane; 1128 1129 possible_crtcs = (1 << pipe); 1130 1131 if (INTEL_INFO(dev)->gen >= 9) 1132 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, 1133 &intel_plane_funcs, 1134 plane_formats, num_plane_formats, 1135 DRM_PLANE_TYPE_OVERLAY, 1136 "plane %d%c", plane + 2, pipe_name(pipe)); 1137 else 1138 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, 1139 &intel_plane_funcs, 1140 plane_formats, num_plane_formats, 1141 DRM_PLANE_TYPE_OVERLAY, 1142 "sprite %c", sprite_name(pipe, plane)); 1143 if (ret) 1144 goto fail; 1145 1146 intel_create_rotation_property(dev, intel_plane); 1147 1148 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); 1149 1150 return 0; 1151 1152 fail: 1153 kfree(state); 1154 kfree(intel_plane); 1155 1156 return ret; 1157 } 1158