1 /* 2 * Copyright © 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Jesse Barnes <jbarnes@virtuousgeek.org> 25 * 26 * New plane/sprite handling. 27 * 28 * The older chips had a separate interface for programming plane related 29 * registers; newer ones are much simpler and we can use the new DRM plane 30 * support. 31 */ 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_fourcc.h> 35 #include <drm/drm_rect.h> 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_plane_helper.h> 38 #include "intel_drv.h" 39 #include "intel_frontbuffer.h" 40 #include <drm/i915_drm.h> 41 #include "i915_drv.h" 42 43 static bool 44 format_is_yuv(uint32_t format) 45 { 46 switch (format) { 47 case DRM_FORMAT_YUYV: 48 case DRM_FORMAT_UYVY: 49 case DRM_FORMAT_VYUY: 50 case DRM_FORMAT_YVYU: 51 return true; 52 default: 53 return false; 54 } 55 } 56 57 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 58 int usecs) 59 { 60 /* paranoia */ 61 if (!adjusted_mode->crtc_htotal) 62 return 1; 63 64 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, 65 1000 * adjusted_mode->crtc_htotal); 66 } 67 68 /** 69 * intel_pipe_update_start() - start update of a set of display registers 70 * @crtc: the crtc of which the registers are going to be updated 71 * @start_vbl_count: vblank counter return pointer used for error checking 72 * 73 * Mark the start of an update to pipe registers that should be updated 74 * atomically regarding vblank. If the next vblank will happens within 75 * the next 100 us, this function waits until the vblank passes. 76 * 77 * After a successful call to this function, interrupts will be disabled 78 * until a subsequent call to intel_pipe_update_end(). That is done to 79 * avoid random delays. The value written to @start_vbl_count should be 80 * supplied to intel_pipe_update_end() for error checking. 81 */ 82 void intel_pipe_update_start(struct intel_crtc *crtc) 83 { 84 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 85 long timeout = msecs_to_jiffies_timeout(1); 86 int scanline, min, max, vblank_start; 87 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 88 DEFINE_WAIT(wait); 89 90 vblank_start = adjusted_mode->crtc_vblank_start; 91 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 92 vblank_start = DIV_ROUND_UP(vblank_start, 2); 93 94 /* FIXME needs to be calibrated sensibly */ 95 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100); 96 max = vblank_start - 1; 97 98 local_irq_disable(); 99 100 if (min <= 0 || max <= 0) 101 return; 102 103 if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) 104 return; 105 106 crtc->debug.min_vbl = min; 107 crtc->debug.max_vbl = max; 108 trace_i915_pipe_update_start(crtc); 109 110 for (;;) { 111 /* 112 * prepare_to_wait() has a memory barrier, which guarantees 113 * other CPUs can see the task state update by the time we 114 * read the scanline. 115 */ 116 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); 117 118 scanline = intel_get_crtc_scanline(crtc); 119 if (scanline < min || scanline > max) 120 break; 121 122 if (timeout <= 0) { 123 DRM_ERROR("Potential atomic update failure on pipe %c\n", 124 pipe_name(crtc->pipe)); 125 break; 126 } 127 128 local_irq_enable(); 129 130 timeout = schedule_timeout(timeout); 131 132 local_irq_disable(); 133 } 134 135 finish_wait(wq, &wait); 136 137 drm_crtc_vblank_put(&crtc->base); 138 139 crtc->debug.scanline_start = scanline; 140 crtc->debug.start_vbl_time = ktime_get(); 141 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc); 142 143 trace_i915_pipe_update_vblank_evaded(crtc); 144 } 145 146 /** 147 * intel_pipe_update_end() - end update of a set of display registers 148 * @crtc: the crtc of which the registers were updated 149 * @start_vbl_count: start vblank counter (used for error checking) 150 * 151 * Mark the end of an update started with intel_pipe_update_start(). This 152 * re-enables interrupts and verifies the update was actually completed 153 * before a vblank using the value of @start_vbl_count. 154 */ 155 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work) 156 { 157 enum i915_pipe pipe = crtc->pipe; 158 int scanline_end = intel_get_crtc_scanline(crtc); 159 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); 160 ktime_t end_vbl_time = ktime_get(); 161 162 if (work) { 163 work->flip_queued_vblank = end_vbl_count; 164 smp_mb__before_atomic(); 165 atomic_set(&work->pending, 1); 166 } 167 168 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); 169 170 /* We're still in the vblank-evade critical section, this can't race. 171 * Would be slightly nice to just grab the vblank count and arm the 172 * event outside of the critical section - the spinlock might spin for a 173 * while ... */ 174 if (crtc->base.state->event) { 175 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); 176 177 lockmgr(&crtc->base.dev->event_lock, LK_EXCLUSIVE); 178 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event); 179 lockmgr(&crtc->base.dev->event_lock, LK_RELEASE); 180 181 crtc->base.state->event = NULL; 182 } 183 184 local_irq_enable(); 185 186 if (crtc->debug.start_vbl_count && 187 crtc->debug.start_vbl_count != end_vbl_count) { 188 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", 189 pipe_name(pipe), crtc->debug.start_vbl_count, 190 end_vbl_count, 191 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), 192 crtc->debug.min_vbl, crtc->debug.max_vbl, 193 crtc->debug.scanline_start, scanline_end); 194 } 195 } 196 197 static void 198 skl_update_plane(struct drm_plane *drm_plane, 199 const struct intel_crtc_state *crtc_state, 200 const struct intel_plane_state *plane_state) 201 { 202 struct drm_device *dev = drm_plane->dev; 203 struct drm_i915_private *dev_priv = to_i915(dev); 204 struct intel_plane *intel_plane = to_intel_plane(drm_plane); 205 struct drm_framebuffer *fb = plane_state->base.fb; 206 const struct skl_wm_values *wm = &dev_priv->wm.skl_results; 207 struct drm_crtc *crtc = crtc_state->base.crtc; 208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 209 const int pipe = intel_plane->pipe; 210 const int plane = intel_plane->plane + 1; 211 const struct skl_plane_wm *p_wm = 212 &crtc_state->wm.skl.optimal.planes[plane]; 213 u32 plane_ctl; 214 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 215 u32 surf_addr = plane_state->main.offset; 216 unsigned int rotation = plane_state->base.rotation; 217 u32 stride = skl_plane_stride(fb, 0, rotation); 218 int crtc_x = plane_state->base.dst.x1; 219 int crtc_y = plane_state->base.dst.y1; 220 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst); 221 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst); 222 uint32_t x = plane_state->main.x; 223 uint32_t y = plane_state->main.y; 224 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; 225 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; 226 227 plane_ctl = PLANE_CTL_ENABLE | 228 PLANE_CTL_PIPE_GAMMA_ENABLE | 229 PLANE_CTL_PIPE_CSC_ENABLE; 230 231 plane_ctl |= skl_plane_ctl_format(fb->pixel_format); 232 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); 233 234 plane_ctl |= skl_plane_ctl_rotation(rotation); 235 236 if (wm->dirty_pipes & drm_crtc_mask(crtc)) 237 skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, plane); 238 239 if (key->flags) { 240 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); 241 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); 242 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); 243 } 244 245 if (key->flags & I915_SET_COLORKEY_DESTINATION) 246 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; 247 else if (key->flags & I915_SET_COLORKEY_SOURCE) 248 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; 249 250 /* Sizes are 0 based */ 251 src_w--; 252 src_h--; 253 crtc_w--; 254 crtc_h--; 255 256 I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x); 257 I915_WRITE(PLANE_STRIDE(pipe, plane), stride); 258 I915_WRITE(PLANE_SIZE(pipe, plane), (src_h << 16) | src_w); 259 260 /* program plane scaler */ 261 if (plane_state->scaler_id >= 0) { 262 int scaler_id = plane_state->scaler_id; 263 const struct intel_scaler *scaler; 264 265 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, 266 PS_PLANE_SEL(plane)); 267 268 scaler = &crtc_state->scaler_state.scalers[scaler_id]; 269 270 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), 271 PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode); 272 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); 273 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); 274 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), 275 ((crtc_w + 1) << 16)|(crtc_h + 1)); 276 277 I915_WRITE(PLANE_POS(pipe, plane), 0); 278 } else { 279 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); 280 } 281 282 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); 283 I915_WRITE(PLANE_SURF(pipe, plane), 284 intel_fb_gtt_offset(fb, rotation) + surf_addr); 285 POSTING_READ(PLANE_SURF(pipe, plane)); 286 } 287 288 static void 289 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) 290 { 291 struct drm_device *dev = dplane->dev; 292 struct drm_i915_private *dev_priv = to_i915(dev); 293 struct intel_plane *intel_plane = to_intel_plane(dplane); 294 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); 295 const int pipe = intel_plane->pipe; 296 const int plane = intel_plane->plane + 1; 297 298 /* 299 * We only populate skl_results on watermark updates, and if the 300 * plane's visiblity isn't actually changing neither is its watermarks. 301 */ 302 if (!dplane->state->visible) 303 skl_write_plane_wm(to_intel_crtc(crtc), 304 &cstate->wm.skl.optimal.planes[plane], 305 &dev_priv->wm.skl_results.ddb, plane); 306 307 I915_WRITE(PLANE_CTL(pipe, plane), 0); 308 309 I915_WRITE(PLANE_SURF(pipe, plane), 0); 310 POSTING_READ(PLANE_SURF(pipe, plane)); 311 } 312 313 static void 314 chv_update_csc(struct intel_plane *intel_plane, uint32_t format) 315 { 316 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); 317 int plane = intel_plane->plane; 318 319 /* Seems RGB data bypasses the CSC always */ 320 if (!format_is_yuv(format)) 321 return; 322 323 /* 324 * BT.601 limited range YCbCr -> full range RGB 325 * 326 * |r| | 6537 4769 0| |cr | 327 * |g| = |-3330 4769 -1605| x |y-64| 328 * |b| | 0 4769 8263| |cb | 329 * 330 * Cb and Cr apparently come in as signed already, so no 331 * need for any offset. For Y we need to remove the offset. 332 */ 333 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); 334 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 335 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 336 337 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); 338 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); 339 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); 340 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); 341 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); 342 343 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); 344 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); 345 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); 346 347 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 348 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 349 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 350 } 351 352 static void 353 vlv_update_plane(struct drm_plane *dplane, 354 const struct intel_crtc_state *crtc_state, 355 const struct intel_plane_state *plane_state) 356 { 357 struct drm_device *dev = dplane->dev; 358 struct drm_i915_private *dev_priv = to_i915(dev); 359 struct intel_plane *intel_plane = to_intel_plane(dplane); 360 struct drm_framebuffer *fb = plane_state->base.fb; 361 int pipe = intel_plane->pipe; 362 int plane = intel_plane->plane; 363 u32 sprctl; 364 u32 sprsurf_offset, linear_offset; 365 unsigned int rotation = dplane->state->rotation; 366 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 367 int crtc_x = plane_state->base.dst.x1; 368 int crtc_y = plane_state->base.dst.y1; 369 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst); 370 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst); 371 uint32_t x = plane_state->base.src.x1 >> 16; 372 uint32_t y = plane_state->base.src.y1 >> 16; 373 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; 374 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; 375 376 sprctl = SP_ENABLE; 377 378 switch (fb->pixel_format) { 379 case DRM_FORMAT_YUYV: 380 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; 381 break; 382 case DRM_FORMAT_YVYU: 383 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; 384 break; 385 case DRM_FORMAT_UYVY: 386 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; 387 break; 388 case DRM_FORMAT_VYUY: 389 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; 390 break; 391 case DRM_FORMAT_RGB565: 392 sprctl |= SP_FORMAT_BGR565; 393 break; 394 case DRM_FORMAT_XRGB8888: 395 sprctl |= SP_FORMAT_BGRX8888; 396 break; 397 case DRM_FORMAT_ARGB8888: 398 sprctl |= SP_FORMAT_BGRA8888; 399 break; 400 case DRM_FORMAT_XBGR2101010: 401 sprctl |= SP_FORMAT_RGBX1010102; 402 break; 403 case DRM_FORMAT_ABGR2101010: 404 sprctl |= SP_FORMAT_RGBA1010102; 405 break; 406 case DRM_FORMAT_XBGR8888: 407 sprctl |= SP_FORMAT_RGBX8888; 408 break; 409 case DRM_FORMAT_ABGR8888: 410 sprctl |= SP_FORMAT_RGBA8888; 411 break; 412 default: 413 /* 414 * If we get here one of the upper layers failed to filter 415 * out the unsupported plane formats 416 */ 417 BUG(); 418 break; 419 } 420 421 /* 422 * Enable gamma to match primary/cursor plane behaviour. 423 * FIXME should be user controllable via propertiesa. 424 */ 425 sprctl |= SP_GAMMA_ENABLE; 426 427 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) 428 sprctl |= SP_TILED; 429 430 /* Sizes are 0 based */ 431 src_w--; 432 src_h--; 433 crtc_w--; 434 crtc_h--; 435 436 intel_add_fb_offsets(&x, &y, plane_state, 0); 437 sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); 438 439 if (rotation == DRM_ROTATE_180) { 440 sprctl |= SP_ROTATE_180; 441 442 x += src_w; 443 y += src_h; 444 } 445 446 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 447 448 if (key->flags) { 449 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); 450 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); 451 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); 452 } 453 454 if (key->flags & I915_SET_COLORKEY_SOURCE) 455 sprctl |= SP_SOURCE_KEY; 456 457 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) 458 chv_update_csc(intel_plane, fb->pixel_format); 459 460 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); 461 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); 462 463 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) 464 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); 465 else 466 I915_WRITE(SPLINOFF(pipe, plane), linear_offset); 467 468 I915_WRITE(SPCONSTALPHA(pipe, plane), 0); 469 470 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); 471 I915_WRITE(SPCNTR(pipe, plane), sprctl); 472 I915_WRITE(SPSURF(pipe, plane), 473 intel_fb_gtt_offset(fb, rotation) + sprsurf_offset); 474 POSTING_READ(SPSURF(pipe, plane)); 475 } 476 477 static void 478 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) 479 { 480 struct drm_device *dev = dplane->dev; 481 struct drm_i915_private *dev_priv = to_i915(dev); 482 struct intel_plane *intel_plane = to_intel_plane(dplane); 483 int pipe = intel_plane->pipe; 484 int plane = intel_plane->plane; 485 486 I915_WRITE(SPCNTR(pipe, plane), 0); 487 488 I915_WRITE(SPSURF(pipe, plane), 0); 489 POSTING_READ(SPSURF(pipe, plane)); 490 } 491 492 static void 493 ivb_update_plane(struct drm_plane *plane, 494 const struct intel_crtc_state *crtc_state, 495 const struct intel_plane_state *plane_state) 496 { 497 struct drm_device *dev = plane->dev; 498 struct drm_i915_private *dev_priv = to_i915(dev); 499 struct intel_plane *intel_plane = to_intel_plane(plane); 500 struct drm_framebuffer *fb = plane_state->base.fb; 501 enum i915_pipe pipe = intel_plane->pipe; 502 u32 sprctl, sprscale = 0; 503 u32 sprsurf_offset, linear_offset; 504 unsigned int rotation = plane_state->base.rotation; 505 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 506 int crtc_x = plane_state->base.dst.x1; 507 int crtc_y = plane_state->base.dst.y1; 508 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst); 509 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst); 510 uint32_t x = plane_state->base.src.x1 >> 16; 511 uint32_t y = plane_state->base.src.y1 >> 16; 512 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; 513 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; 514 515 sprctl = SPRITE_ENABLE; 516 517 switch (fb->pixel_format) { 518 case DRM_FORMAT_XBGR8888: 519 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; 520 break; 521 case DRM_FORMAT_XRGB8888: 522 sprctl |= SPRITE_FORMAT_RGBX888; 523 break; 524 case DRM_FORMAT_YUYV: 525 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; 526 break; 527 case DRM_FORMAT_YVYU: 528 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; 529 break; 530 case DRM_FORMAT_UYVY: 531 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; 532 break; 533 case DRM_FORMAT_VYUY: 534 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; 535 break; 536 default: 537 BUG(); 538 } 539 540 /* 541 * Enable gamma to match primary/cursor plane behaviour. 542 * FIXME should be user controllable via propertiesa. 543 */ 544 sprctl |= SPRITE_GAMMA_ENABLE; 545 546 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) 547 sprctl |= SPRITE_TILED; 548 549 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 550 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; 551 else 552 sprctl |= SPRITE_TRICKLE_FEED_DISABLE; 553 554 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 555 sprctl |= SPRITE_PIPE_CSC_ENABLE; 556 557 /* Sizes are 0 based */ 558 src_w--; 559 src_h--; 560 crtc_w--; 561 crtc_h--; 562 563 if (crtc_w != src_w || crtc_h != src_h) 564 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; 565 566 intel_add_fb_offsets(&x, &y, plane_state, 0); 567 sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); 568 569 if (rotation == DRM_ROTATE_180) { 570 sprctl |= SPRITE_ROTATE_180; 571 572 /* HSW and BDW does this automagically in hardware */ 573 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { 574 x += src_w; 575 y += src_h; 576 } 577 } 578 579 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 580 581 if (key->flags) { 582 I915_WRITE(SPRKEYVAL(pipe), key->min_value); 583 I915_WRITE(SPRKEYMAX(pipe), key->max_value); 584 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); 585 } 586 587 if (key->flags & I915_SET_COLORKEY_DESTINATION) 588 sprctl |= SPRITE_DEST_KEY; 589 else if (key->flags & I915_SET_COLORKEY_SOURCE) 590 sprctl |= SPRITE_SOURCE_KEY; 591 592 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); 593 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); 594 595 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET 596 * register */ 597 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 598 I915_WRITE(SPROFFSET(pipe), (y << 16) | x); 599 else if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) 600 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); 601 else 602 I915_WRITE(SPRLINOFF(pipe), linear_offset); 603 604 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); 605 if (intel_plane->can_scale) 606 I915_WRITE(SPRSCALE(pipe), sprscale); 607 I915_WRITE(SPRCTL(pipe), sprctl); 608 I915_WRITE(SPRSURF(pipe), 609 intel_fb_gtt_offset(fb, rotation) + sprsurf_offset); 610 POSTING_READ(SPRSURF(pipe)); 611 } 612 613 static void 614 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) 615 { 616 struct drm_device *dev = plane->dev; 617 struct drm_i915_private *dev_priv = to_i915(dev); 618 struct intel_plane *intel_plane = to_intel_plane(plane); 619 int pipe = intel_plane->pipe; 620 621 I915_WRITE(SPRCTL(pipe), 0); 622 /* Can't leave the scaler enabled... */ 623 if (intel_plane->can_scale) 624 I915_WRITE(SPRSCALE(pipe), 0); 625 626 I915_WRITE(SPRSURF(pipe), 0); 627 POSTING_READ(SPRSURF(pipe)); 628 } 629 630 static void 631 ilk_update_plane(struct drm_plane *plane, 632 const struct intel_crtc_state *crtc_state, 633 const struct intel_plane_state *plane_state) 634 { 635 struct drm_device *dev = plane->dev; 636 struct drm_i915_private *dev_priv = to_i915(dev); 637 struct intel_plane *intel_plane = to_intel_plane(plane); 638 struct drm_framebuffer *fb = plane_state->base.fb; 639 int pipe = intel_plane->pipe; 640 u32 dvscntr, dvsscale; 641 u32 dvssurf_offset, linear_offset; 642 unsigned int rotation = plane_state->base.rotation; 643 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 644 int crtc_x = plane_state->base.dst.x1; 645 int crtc_y = plane_state->base.dst.y1; 646 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst); 647 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst); 648 uint32_t x = plane_state->base.src.x1 >> 16; 649 uint32_t y = plane_state->base.src.y1 >> 16; 650 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16; 651 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16; 652 653 dvscntr = DVS_ENABLE; 654 655 switch (fb->pixel_format) { 656 case DRM_FORMAT_XBGR8888: 657 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; 658 break; 659 case DRM_FORMAT_XRGB8888: 660 dvscntr |= DVS_FORMAT_RGBX888; 661 break; 662 case DRM_FORMAT_YUYV: 663 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; 664 break; 665 case DRM_FORMAT_YVYU: 666 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; 667 break; 668 case DRM_FORMAT_UYVY: 669 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; 670 break; 671 case DRM_FORMAT_VYUY: 672 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; 673 break; 674 default: 675 BUG(); 676 } 677 678 /* 679 * Enable gamma to match primary/cursor plane behaviour. 680 * FIXME should be user controllable via propertiesa. 681 */ 682 dvscntr |= DVS_GAMMA_ENABLE; 683 684 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) 685 dvscntr |= DVS_TILED; 686 687 if (IS_GEN6(dev_priv)) 688 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ 689 690 /* Sizes are 0 based */ 691 src_w--; 692 src_h--; 693 crtc_w--; 694 crtc_h--; 695 696 dvsscale = 0; 697 if (crtc_w != src_w || crtc_h != src_h) 698 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; 699 700 intel_add_fb_offsets(&x, &y, plane_state, 0); 701 dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0); 702 703 if (rotation == DRM_ROTATE_180) { 704 dvscntr |= DVS_ROTATE_180; 705 706 x += src_w; 707 y += src_h; 708 } 709 710 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 711 712 if (key->flags) { 713 I915_WRITE(DVSKEYVAL(pipe), key->min_value); 714 I915_WRITE(DVSKEYMAX(pipe), key->max_value); 715 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); 716 } 717 718 if (key->flags & I915_SET_COLORKEY_DESTINATION) 719 dvscntr |= DVS_DEST_KEY; 720 else if (key->flags & I915_SET_COLORKEY_SOURCE) 721 dvscntr |= DVS_SOURCE_KEY; 722 723 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); 724 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); 725 726 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) 727 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); 728 else 729 I915_WRITE(DVSLINOFF(pipe), linear_offset); 730 731 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); 732 I915_WRITE(DVSSCALE(pipe), dvsscale); 733 I915_WRITE(DVSCNTR(pipe), dvscntr); 734 I915_WRITE(DVSSURF(pipe), 735 intel_fb_gtt_offset(fb, rotation) + dvssurf_offset); 736 POSTING_READ(DVSSURF(pipe)); 737 } 738 739 static void 740 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) 741 { 742 struct drm_device *dev = plane->dev; 743 struct drm_i915_private *dev_priv = to_i915(dev); 744 struct intel_plane *intel_plane = to_intel_plane(plane); 745 int pipe = intel_plane->pipe; 746 747 I915_WRITE(DVSCNTR(pipe), 0); 748 /* Disable the scaler */ 749 I915_WRITE(DVSSCALE(pipe), 0); 750 751 I915_WRITE(DVSSURF(pipe), 0); 752 POSTING_READ(DVSSURF(pipe)); 753 } 754 755 static int 756 intel_check_sprite_plane(struct drm_plane *plane, 757 struct intel_crtc_state *crtc_state, 758 struct intel_plane_state *state) 759 { 760 struct drm_i915_private *dev_priv = to_i915(plane->dev); 761 struct drm_crtc *crtc = state->base.crtc; 762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 763 struct intel_plane *intel_plane = to_intel_plane(plane); 764 struct drm_framebuffer *fb = state->base.fb; 765 int crtc_x, crtc_y; 766 unsigned int crtc_w, crtc_h; 767 uint32_t src_x, src_y, src_w, src_h; 768 struct drm_rect *src = &state->base.src; 769 struct drm_rect *dst = &state->base.dst; 770 const struct drm_rect *clip = &state->clip; 771 int hscale, vscale; 772 int max_scale, min_scale; 773 bool can_scale; 774 int ret; 775 776 src->x1 = state->base.src_x; 777 src->y1 = state->base.src_y; 778 src->x2 = state->base.src_x + state->base.src_w; 779 src->y2 = state->base.src_y + state->base.src_h; 780 781 dst->x1 = state->base.crtc_x; 782 dst->y1 = state->base.crtc_y; 783 dst->x2 = state->base.crtc_x + state->base.crtc_w; 784 dst->y2 = state->base.crtc_y + state->base.crtc_h; 785 786 if (!fb) { 787 state->base.visible = false; 788 return 0; 789 } 790 791 /* Don't modify another pipe's plane */ 792 if (intel_plane->pipe != intel_crtc->pipe) { 793 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); 794 return -EINVAL; 795 } 796 797 /* FIXME check all gen limits */ 798 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { 799 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); 800 return -EINVAL; 801 } 802 803 /* setup can_scale, min_scale, max_scale */ 804 if (INTEL_GEN(dev_priv) >= 9) { 805 /* use scaler when colorkey is not required */ 806 if (state->ckey.flags == I915_SET_COLORKEY_NONE) { 807 can_scale = 1; 808 min_scale = 1; 809 max_scale = skl_max_scale(intel_crtc, crtc_state); 810 } else { 811 can_scale = 0; 812 min_scale = DRM_PLANE_HELPER_NO_SCALING; 813 max_scale = DRM_PLANE_HELPER_NO_SCALING; 814 } 815 } else { 816 can_scale = intel_plane->can_scale; 817 max_scale = intel_plane->max_downscale << 16; 818 min_scale = intel_plane->can_scale ? 1 : (1 << 16); 819 } 820 821 /* 822 * FIXME the following code does a bunch of fuzzy adjustments to the 823 * coordinates and sizes. We probably need some way to decide whether 824 * more strict checking should be done instead. 825 */ 826 drm_rect_rotate(src, fb->width << 16, fb->height << 16, 827 state->base.rotation); 828 829 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); 830 BUG_ON(hscale < 0); 831 832 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); 833 BUG_ON(vscale < 0); 834 835 state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); 836 837 crtc_x = dst->x1; 838 crtc_y = dst->y1; 839 crtc_w = drm_rect_width(dst); 840 crtc_h = drm_rect_height(dst); 841 842 if (state->base.visible) { 843 /* check again in case clipping clamped the results */ 844 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); 845 if (hscale < 0) { 846 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); 847 drm_rect_debug_print("src: ", src, true); 848 drm_rect_debug_print("dst: ", dst, false); 849 850 return hscale; 851 } 852 853 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); 854 if (vscale < 0) { 855 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); 856 drm_rect_debug_print("src: ", src, true); 857 drm_rect_debug_print("dst: ", dst, false); 858 859 return vscale; 860 } 861 862 /* Make the source viewport size an exact multiple of the scaling factors. */ 863 drm_rect_adjust_size(src, 864 drm_rect_width(dst) * hscale - drm_rect_width(src), 865 drm_rect_height(dst) * vscale - drm_rect_height(src)); 866 867 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, 868 state->base.rotation); 869 870 /* sanity check to make sure the src viewport wasn't enlarged */ 871 WARN_ON(src->x1 < (int) state->base.src_x || 872 src->y1 < (int) state->base.src_y || 873 src->x2 > (int) state->base.src_x + state->base.src_w || 874 src->y2 > (int) state->base.src_y + state->base.src_h); 875 876 /* 877 * Hardware doesn't handle subpixel coordinates. 878 * Adjust to (macro)pixel boundary, but be careful not to 879 * increase the source viewport size, because that could 880 * push the downscaling factor out of bounds. 881 */ 882 src_x = src->x1 >> 16; 883 src_w = drm_rect_width(src) >> 16; 884 src_y = src->y1 >> 16; 885 src_h = drm_rect_height(src) >> 16; 886 887 if (format_is_yuv(fb->pixel_format)) { 888 src_x &= ~1; 889 src_w &= ~1; 890 891 /* 892 * Must keep src and dst the 893 * same if we can't scale. 894 */ 895 if (!can_scale) 896 crtc_w &= ~1; 897 898 if (crtc_w == 0) 899 state->base.visible = false; 900 } 901 } 902 903 /* Check size restrictions when scaling */ 904 if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) { 905 unsigned int width_bytes; 906 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 907 908 WARN_ON(!can_scale); 909 910 /* FIXME interlacing min height is 6 */ 911 912 if (crtc_w < 3 || crtc_h < 3) 913 state->base.visible = false; 914 915 if (src_w < 3 || src_h < 3) 916 state->base.visible = false; 917 918 width_bytes = ((src_x * cpp) & 63) + src_w * cpp; 919 920 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 || 921 width_bytes > 4096 || fb->pitches[0] > 4096)) { 922 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); 923 return -EINVAL; 924 } 925 } 926 927 if (state->base.visible) { 928 src->x1 = src_x << 16; 929 src->x2 = (src_x + src_w) << 16; 930 src->y1 = src_y << 16; 931 src->y2 = (src_y + src_h) << 16; 932 } 933 934 dst->x1 = crtc_x; 935 dst->x2 = crtc_x + crtc_w; 936 dst->y1 = crtc_y; 937 dst->y2 = crtc_y + crtc_h; 938 939 if (INTEL_GEN(dev_priv) >= 9) { 940 ret = skl_check_plane_surface(state); 941 if (ret) 942 return ret; 943 } 944 945 return 0; 946 } 947 948 int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 949 struct drm_file *file_priv) 950 { 951 struct drm_i915_private *dev_priv = to_i915(dev); 952 struct drm_intel_sprite_colorkey *set = data; 953 struct drm_plane *plane; 954 struct drm_plane_state *plane_state; 955 struct drm_atomic_state *state; 956 struct drm_modeset_acquire_ctx ctx; 957 int ret = 0; 958 959 /* Make sure we don't try to enable both src & dest simultaneously */ 960 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) 961 return -EINVAL; 962 963 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 964 set->flags & I915_SET_COLORKEY_DESTINATION) 965 return -EINVAL; 966 967 plane = drm_plane_find(dev, set->plane_id); 968 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) 969 return -ENOENT; 970 971 drm_modeset_acquire_init(&ctx, 0); 972 973 state = drm_atomic_state_alloc(plane->dev); 974 if (!state) { 975 ret = -ENOMEM; 976 goto out; 977 } 978 state->acquire_ctx = &ctx; 979 980 while (1) { 981 plane_state = drm_atomic_get_plane_state(state, plane); 982 ret = PTR_ERR_OR_ZERO(plane_state); 983 if (!ret) { 984 to_intel_plane_state(plane_state)->ckey = *set; 985 ret = drm_atomic_commit(state); 986 } 987 988 if (ret != -EDEADLK) 989 break; 990 991 drm_atomic_state_clear(state); 992 drm_modeset_backoff(&ctx); 993 } 994 995 if (ret) 996 drm_atomic_state_free(state); 997 998 out: 999 drm_modeset_drop_locks(&ctx); 1000 drm_modeset_acquire_fini(&ctx); 1001 return ret; 1002 } 1003 1004 static const uint32_t ilk_plane_formats[] = { 1005 DRM_FORMAT_XRGB8888, 1006 DRM_FORMAT_YUYV, 1007 DRM_FORMAT_YVYU, 1008 DRM_FORMAT_UYVY, 1009 DRM_FORMAT_VYUY, 1010 }; 1011 1012 static const uint32_t snb_plane_formats[] = { 1013 DRM_FORMAT_XBGR8888, 1014 DRM_FORMAT_XRGB8888, 1015 DRM_FORMAT_YUYV, 1016 DRM_FORMAT_YVYU, 1017 DRM_FORMAT_UYVY, 1018 DRM_FORMAT_VYUY, 1019 }; 1020 1021 static const uint32_t vlv_plane_formats[] = { 1022 DRM_FORMAT_RGB565, 1023 DRM_FORMAT_ABGR8888, 1024 DRM_FORMAT_ARGB8888, 1025 DRM_FORMAT_XBGR8888, 1026 DRM_FORMAT_XRGB8888, 1027 DRM_FORMAT_XBGR2101010, 1028 DRM_FORMAT_ABGR2101010, 1029 DRM_FORMAT_YUYV, 1030 DRM_FORMAT_YVYU, 1031 DRM_FORMAT_UYVY, 1032 DRM_FORMAT_VYUY, 1033 }; 1034 1035 static uint32_t skl_plane_formats[] = { 1036 DRM_FORMAT_RGB565, 1037 DRM_FORMAT_ABGR8888, 1038 DRM_FORMAT_ARGB8888, 1039 DRM_FORMAT_XBGR8888, 1040 DRM_FORMAT_XRGB8888, 1041 DRM_FORMAT_YUYV, 1042 DRM_FORMAT_YVYU, 1043 DRM_FORMAT_UYVY, 1044 DRM_FORMAT_VYUY, 1045 }; 1046 1047 int 1048 intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane) 1049 { 1050 struct drm_i915_private *dev_priv = to_i915(dev); 1051 struct intel_plane *intel_plane = NULL; 1052 struct intel_plane_state *state = NULL; 1053 unsigned long possible_crtcs; 1054 const uint32_t *plane_formats; 1055 int num_plane_formats; 1056 int ret; 1057 1058 if (INTEL_INFO(dev)->gen < 5) 1059 return -ENODEV; 1060 1061 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); 1062 if (!intel_plane) { 1063 ret = -ENOMEM; 1064 goto fail; 1065 } 1066 1067 state = intel_create_plane_state(&intel_plane->base); 1068 if (!state) { 1069 ret = -ENOMEM; 1070 goto fail; 1071 } 1072 intel_plane->base.state = &state->base; 1073 1074 switch (INTEL_INFO(dev)->gen) { 1075 case 5: 1076 case 6: 1077 intel_plane->can_scale = true; 1078 intel_plane->max_downscale = 16; 1079 intel_plane->update_plane = ilk_update_plane; 1080 intel_plane->disable_plane = ilk_disable_plane; 1081 1082 if (IS_GEN6(dev_priv)) { 1083 plane_formats = snb_plane_formats; 1084 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1085 } else { 1086 plane_formats = ilk_plane_formats; 1087 num_plane_formats = ARRAY_SIZE(ilk_plane_formats); 1088 } 1089 break; 1090 1091 case 7: 1092 case 8: 1093 if (IS_IVYBRIDGE(dev_priv)) { 1094 intel_plane->can_scale = true; 1095 intel_plane->max_downscale = 2; 1096 } else { 1097 intel_plane->can_scale = false; 1098 intel_plane->max_downscale = 1; 1099 } 1100 1101 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1102 intel_plane->update_plane = vlv_update_plane; 1103 intel_plane->disable_plane = vlv_disable_plane; 1104 1105 plane_formats = vlv_plane_formats; 1106 num_plane_formats = ARRAY_SIZE(vlv_plane_formats); 1107 } else { 1108 intel_plane->update_plane = ivb_update_plane; 1109 intel_plane->disable_plane = ivb_disable_plane; 1110 1111 plane_formats = snb_plane_formats; 1112 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1113 } 1114 break; 1115 case 9: 1116 intel_plane->can_scale = true; 1117 intel_plane->update_plane = skl_update_plane; 1118 intel_plane->disable_plane = skl_disable_plane; 1119 state->scaler_id = -1; 1120 1121 plane_formats = skl_plane_formats; 1122 num_plane_formats = ARRAY_SIZE(skl_plane_formats); 1123 break; 1124 default: 1125 MISSING_CASE(INTEL_INFO(dev)->gen); 1126 ret = -ENODEV; 1127 goto fail; 1128 } 1129 1130 intel_plane->pipe = pipe; 1131 intel_plane->plane = plane; 1132 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); 1133 intel_plane->check_plane = intel_check_sprite_plane; 1134 1135 possible_crtcs = (1 << pipe); 1136 1137 if (INTEL_INFO(dev)->gen >= 9) 1138 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, 1139 &intel_plane_funcs, 1140 plane_formats, num_plane_formats, 1141 DRM_PLANE_TYPE_OVERLAY, 1142 "plane %d%c", plane + 2, pipe_name(pipe)); 1143 else 1144 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, 1145 &intel_plane_funcs, 1146 plane_formats, num_plane_formats, 1147 DRM_PLANE_TYPE_OVERLAY, 1148 "sprite %c", sprite_name(pipe, plane)); 1149 if (ret) 1150 goto fail; 1151 1152 intel_create_rotation_property(dev, intel_plane); 1153 1154 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); 1155 1156 return 0; 1157 1158 fail: 1159 kfree(state); 1160 kfree(intel_plane); 1161 1162 return ret; 1163 } 1164