1 /* 2 * Copyright © 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Jesse Barnes <jbarnes@virtuousgeek.org> 25 * 26 * New plane/sprite handling. 27 * 28 * The older chips had a separate interface for programming plane related 29 * registers; newer ones are much simpler and we can use the new DRM plane 30 * support. 31 */ 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_fourcc.h> 35 #include <drm/drm_rect.h> 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_plane_helper.h> 38 #include "intel_drv.h" 39 #include <drm/i915_drm.h> 40 #include "i915_drv.h" 41 42 static bool 43 format_is_yuv(uint32_t format) 44 { 45 switch (format) { 46 case DRM_FORMAT_YUYV: 47 case DRM_FORMAT_UYVY: 48 case DRM_FORMAT_VYUY: 49 case DRM_FORMAT_YVYU: 50 return true; 51 default: 52 return false; 53 } 54 } 55 56 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 57 int usecs) 58 { 59 /* paranoia */ 60 if (!adjusted_mode->crtc_htotal) 61 return 1; 62 63 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, 64 1000 * adjusted_mode->crtc_htotal); 65 } 66 67 /** 68 * intel_pipe_update_start() - start update of a set of display registers 69 * @crtc: the crtc of which the registers are going to be updated 70 * @start_vbl_count: vblank counter return pointer used for error checking 71 * 72 * Mark the start of an update to pipe registers that should be updated 73 * atomically regarding vblank. If the next vblank will happens within 74 * the next 100 us, this function waits until the vblank passes. 75 * 76 * After a successful call to this function, interrupts will be disabled 77 * until a subsequent call to intel_pipe_update_end(). That is done to 78 * avoid random delays. The value written to @start_vbl_count should be 79 * supplied to intel_pipe_update_end() for error checking. 80 */ 81 void intel_pipe_update_start(struct intel_crtc *crtc) 82 { 83 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 84 long timeout = msecs_to_jiffies_timeout(1); 85 int scanline, min, max, vblank_start; 86 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 87 DEFINE_WAIT(wait); 88 89 vblank_start = adjusted_mode->crtc_vblank_start; 90 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 91 vblank_start = DIV_ROUND_UP(vblank_start, 2); 92 93 /* FIXME needs to be calibrated sensibly */ 94 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 100); 95 max = vblank_start - 1; 96 97 local_irq_disable(); 98 99 if (min <= 0 || max <= 0) 100 return; 101 102 if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) 103 return; 104 105 crtc->debug.min_vbl = min; 106 crtc->debug.max_vbl = max; 107 trace_i915_pipe_update_start(crtc); 108 109 for (;;) { 110 /* 111 * prepare_to_wait() has a memory barrier, which guarantees 112 * other CPUs can see the task state update by the time we 113 * read the scanline. 114 */ 115 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); 116 117 scanline = intel_get_crtc_scanline(crtc); 118 if (scanline < min || scanline > max) 119 break; 120 121 if (timeout <= 0) { 122 DRM_ERROR("Potential atomic update failure on pipe %c\n", 123 pipe_name(crtc->pipe)); 124 break; 125 } 126 127 local_irq_enable(); 128 129 timeout = schedule_timeout(timeout); 130 131 local_irq_disable(); 132 } 133 134 finish_wait(wq, &wait); 135 136 drm_crtc_vblank_put(&crtc->base); 137 138 crtc->debug.scanline_start = scanline; 139 crtc->debug.start_vbl_time = ktime_get(); 140 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc); 141 142 trace_i915_pipe_update_vblank_evaded(crtc); 143 } 144 145 /** 146 * intel_pipe_update_end() - end update of a set of display registers 147 * @crtc: the crtc of which the registers were updated 148 * @start_vbl_count: start vblank counter (used for error checking) 149 * 150 * Mark the end of an update started with intel_pipe_update_start(). This 151 * re-enables interrupts and verifies the update was actually completed 152 * before a vblank using the value of @start_vbl_count. 153 */ 154 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work) 155 { 156 enum i915_pipe pipe = crtc->pipe; 157 int scanline_end = intel_get_crtc_scanline(crtc); 158 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); 159 ktime_t end_vbl_time = ktime_get(); 160 161 if (work) { 162 work->flip_queued_vblank = end_vbl_count; 163 smp_mb__before_atomic(); 164 atomic_set(&work->pending, 1); 165 } 166 167 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); 168 169 /* We're still in the vblank-evade critical section, this can't race. 170 * Would be slightly nice to just grab the vblank count and arm the 171 * event outside of the critical section - the spinlock might spin for a 172 * while ... */ 173 if (crtc->base.state->event) { 174 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); 175 176 lockmgr(&crtc->base.dev->event_lock, LK_EXCLUSIVE); 177 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event); 178 lockmgr(&crtc->base.dev->event_lock, LK_RELEASE); 179 180 crtc->base.state->event = NULL; 181 } 182 183 local_irq_enable(); 184 185 if (crtc->debug.start_vbl_count && 186 crtc->debug.start_vbl_count != end_vbl_count) { 187 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", 188 pipe_name(pipe), crtc->debug.start_vbl_count, 189 end_vbl_count, 190 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), 191 crtc->debug.min_vbl, crtc->debug.max_vbl, 192 crtc->debug.scanline_start, scanline_end); 193 } 194 } 195 196 static void 197 skl_update_plane(struct drm_plane *drm_plane, 198 const struct intel_crtc_state *crtc_state, 199 const struct intel_plane_state *plane_state) 200 { 201 struct drm_device *dev = drm_plane->dev; 202 struct drm_i915_private *dev_priv = to_i915(dev); 203 struct intel_plane *intel_plane = to_intel_plane(drm_plane); 204 struct drm_framebuffer *fb = plane_state->base.fb; 205 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 206 const struct skl_wm_values *wm = &dev_priv->wm.skl_results; 207 struct drm_crtc *crtc = crtc_state->base.crtc; 208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 209 const int pipe = intel_plane->pipe; 210 const int plane = intel_plane->plane + 1; 211 u32 plane_ctl, stride_div, stride; 212 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 213 u32 surf_addr; 214 u32 tile_height, plane_offset, plane_size; 215 unsigned int rotation = plane_state->base.rotation; 216 int x_offset, y_offset; 217 int crtc_x = plane_state->dst.x1; 218 int crtc_y = plane_state->dst.y1; 219 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 220 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 221 uint32_t x = plane_state->src.x1 >> 16; 222 uint32_t y = plane_state->src.y1 >> 16; 223 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 224 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 225 226 plane_ctl = PLANE_CTL_ENABLE | 227 PLANE_CTL_PIPE_GAMMA_ENABLE | 228 PLANE_CTL_PIPE_CSC_ENABLE; 229 230 plane_ctl |= skl_plane_ctl_format(fb->pixel_format); 231 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); 232 233 plane_ctl |= skl_plane_ctl_rotation(rotation); 234 235 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], 236 fb->pixel_format); 237 238 /* Sizes are 0 based */ 239 src_w--; 240 src_h--; 241 crtc_w--; 242 crtc_h--; 243 244 if (wm->dirty_pipes & drm_crtc_mask(crtc)) 245 skl_write_plane_wm(intel_crtc, wm, plane); 246 247 if (key->flags) { 248 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); 249 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); 250 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); 251 } 252 253 if (key->flags & I915_SET_COLORKEY_DESTINATION) 254 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; 255 else if (key->flags & I915_SET_COLORKEY_SOURCE) 256 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; 257 258 surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); 259 260 if (intel_rotation_90_or_270(rotation)) { 261 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 262 263 /* stride: Surface height in tiles */ 264 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); 265 stride = DIV_ROUND_UP(fb->height, tile_height); 266 plane_size = (src_w << 16) | src_h; 267 x_offset = stride * tile_height - y - (src_h + 1); 268 y_offset = x; 269 } else { 270 stride = fb->pitches[0] / stride_div; 271 plane_size = (src_h << 16) | src_w; 272 x_offset = x; 273 y_offset = y; 274 } 275 plane_offset = y_offset << 16 | x_offset; 276 277 I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); 278 I915_WRITE(PLANE_STRIDE(pipe, plane), stride); 279 I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); 280 281 /* program plane scaler */ 282 if (plane_state->scaler_id >= 0) { 283 int scaler_id = plane_state->scaler_id; 284 const struct intel_scaler *scaler; 285 286 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, 287 PS_PLANE_SEL(plane)); 288 289 scaler = &crtc_state->scaler_state.scalers[scaler_id]; 290 291 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), 292 PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode); 293 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); 294 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); 295 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), 296 ((crtc_w + 1) << 16)|(crtc_h + 1)); 297 298 I915_WRITE(PLANE_POS(pipe, plane), 0); 299 } else { 300 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); 301 } 302 303 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); 304 I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); 305 POSTING_READ(PLANE_SURF(pipe, plane)); 306 } 307 308 static void 309 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) 310 { 311 struct drm_device *dev = dplane->dev; 312 struct drm_i915_private *dev_priv = to_i915(dev); 313 struct intel_plane *intel_plane = to_intel_plane(dplane); 314 const int pipe = intel_plane->pipe; 315 const int plane = intel_plane->plane + 1; 316 317 /* 318 * We only populate skl_results on watermark updates, and if the 319 * plane's visiblity isn't actually changing neither is its watermarks. 320 */ 321 if (!to_intel_plane_state(dplane->state)->visible) 322 skl_write_plane_wm(to_intel_crtc(crtc), 323 &dev_priv->wm.skl_results, plane); 324 325 I915_WRITE(PLANE_CTL(pipe, plane), 0); 326 327 I915_WRITE(PLANE_SURF(pipe, plane), 0); 328 POSTING_READ(PLANE_SURF(pipe, plane)); 329 } 330 331 static void 332 chv_update_csc(struct intel_plane *intel_plane, uint32_t format) 333 { 334 struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); 335 int plane = intel_plane->plane; 336 337 /* Seems RGB data bypasses the CSC always */ 338 if (!format_is_yuv(format)) 339 return; 340 341 /* 342 * BT.601 limited range YCbCr -> full range RGB 343 * 344 * |r| | 6537 4769 0| |cr | 345 * |g| = |-3330 4769 -1605| x |y-64| 346 * |b| | 0 4769 8263| |cb | 347 * 348 * Cb and Cr apparently come in as signed already, so no 349 * need for any offset. For Y we need to remove the offset. 350 */ 351 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); 352 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 353 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 354 355 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); 356 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); 357 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); 358 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); 359 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); 360 361 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); 362 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); 363 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); 364 365 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 366 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 367 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 368 } 369 370 static void 371 vlv_update_plane(struct drm_plane *dplane, 372 const struct intel_crtc_state *crtc_state, 373 const struct intel_plane_state *plane_state) 374 { 375 struct drm_device *dev = dplane->dev; 376 struct drm_i915_private *dev_priv = to_i915(dev); 377 struct intel_plane *intel_plane = to_intel_plane(dplane); 378 struct drm_framebuffer *fb = plane_state->base.fb; 379 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 380 int pipe = intel_plane->pipe; 381 int plane = intel_plane->plane; 382 u32 sprctl; 383 u32 sprsurf_offset, linear_offset; 384 unsigned int rotation = dplane->state->rotation; 385 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 386 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 387 int crtc_x = plane_state->dst.x1; 388 int crtc_y = plane_state->dst.y1; 389 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 390 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 391 uint32_t x = plane_state->src.x1 >> 16; 392 uint32_t y = plane_state->src.y1 >> 16; 393 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 394 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 395 396 sprctl = SP_ENABLE; 397 398 switch (fb->pixel_format) { 399 case DRM_FORMAT_YUYV: 400 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; 401 break; 402 case DRM_FORMAT_YVYU: 403 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; 404 break; 405 case DRM_FORMAT_UYVY: 406 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; 407 break; 408 case DRM_FORMAT_VYUY: 409 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; 410 break; 411 case DRM_FORMAT_RGB565: 412 sprctl |= SP_FORMAT_BGR565; 413 break; 414 case DRM_FORMAT_XRGB8888: 415 sprctl |= SP_FORMAT_BGRX8888; 416 break; 417 case DRM_FORMAT_ARGB8888: 418 sprctl |= SP_FORMAT_BGRA8888; 419 break; 420 case DRM_FORMAT_XBGR2101010: 421 sprctl |= SP_FORMAT_RGBX1010102; 422 break; 423 case DRM_FORMAT_ABGR2101010: 424 sprctl |= SP_FORMAT_RGBA1010102; 425 break; 426 case DRM_FORMAT_XBGR8888: 427 sprctl |= SP_FORMAT_RGBX8888; 428 break; 429 case DRM_FORMAT_ABGR8888: 430 sprctl |= SP_FORMAT_RGBA8888; 431 break; 432 default: 433 /* 434 * If we get here one of the upper layers failed to filter 435 * out the unsupported plane formats 436 */ 437 BUG(); 438 break; 439 } 440 441 /* 442 * Enable gamma to match primary/cursor plane behaviour. 443 * FIXME should be user controllable via propertiesa. 444 */ 445 sprctl |= SP_GAMMA_ENABLE; 446 447 if (obj->tiling_mode != I915_TILING_NONE) 448 sprctl |= SP_TILED; 449 450 /* Sizes are 0 based */ 451 src_w--; 452 src_h--; 453 crtc_w--; 454 crtc_h--; 455 456 linear_offset = y * fb->pitches[0] + x * cpp; 457 sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, 458 fb->pitches[0], rotation); 459 linear_offset -= sprsurf_offset; 460 461 if (rotation == DRM_ROTATE_180) { 462 sprctl |= SP_ROTATE_180; 463 464 x += src_w; 465 y += src_h; 466 linear_offset += src_h * fb->pitches[0] + src_w * cpp; 467 } 468 469 if (key->flags) { 470 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); 471 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); 472 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); 473 } 474 475 if (key->flags & I915_SET_COLORKEY_SOURCE) 476 sprctl |= SP_SOURCE_KEY; 477 478 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) 479 chv_update_csc(intel_plane, fb->pixel_format); 480 481 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); 482 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); 483 484 if (obj->tiling_mode != I915_TILING_NONE) 485 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); 486 else 487 I915_WRITE(SPLINOFF(pipe, plane), linear_offset); 488 489 I915_WRITE(SPCONSTALPHA(pipe, plane), 0); 490 491 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); 492 I915_WRITE(SPCNTR(pipe, plane), sprctl); 493 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + 494 sprsurf_offset); 495 POSTING_READ(SPSURF(pipe, plane)); 496 } 497 498 static void 499 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) 500 { 501 struct drm_device *dev = dplane->dev; 502 struct drm_i915_private *dev_priv = to_i915(dev); 503 struct intel_plane *intel_plane = to_intel_plane(dplane); 504 int pipe = intel_plane->pipe; 505 int plane = intel_plane->plane; 506 507 I915_WRITE(SPCNTR(pipe, plane), 0); 508 509 I915_WRITE(SPSURF(pipe, plane), 0); 510 POSTING_READ(SPSURF(pipe, plane)); 511 } 512 513 static void 514 ivb_update_plane(struct drm_plane *plane, 515 const struct intel_crtc_state *crtc_state, 516 const struct intel_plane_state *plane_state) 517 { 518 struct drm_device *dev = plane->dev; 519 struct drm_i915_private *dev_priv = to_i915(dev); 520 struct intel_plane *intel_plane = to_intel_plane(plane); 521 struct drm_framebuffer *fb = plane_state->base.fb; 522 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 523 enum i915_pipe pipe = intel_plane->pipe; 524 u32 sprctl, sprscale = 0; 525 u32 sprsurf_offset, linear_offset; 526 unsigned int rotation = plane_state->base.rotation; 527 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 528 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 529 int crtc_x = plane_state->dst.x1; 530 int crtc_y = plane_state->dst.y1; 531 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 532 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 533 uint32_t x = plane_state->src.x1 >> 16; 534 uint32_t y = plane_state->src.y1 >> 16; 535 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 536 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 537 538 sprctl = SPRITE_ENABLE; 539 540 switch (fb->pixel_format) { 541 case DRM_FORMAT_XBGR8888: 542 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; 543 break; 544 case DRM_FORMAT_XRGB8888: 545 sprctl |= SPRITE_FORMAT_RGBX888; 546 break; 547 case DRM_FORMAT_YUYV: 548 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; 549 break; 550 case DRM_FORMAT_YVYU: 551 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; 552 break; 553 case DRM_FORMAT_UYVY: 554 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; 555 break; 556 case DRM_FORMAT_VYUY: 557 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; 558 break; 559 default: 560 BUG(); 561 } 562 563 /* 564 * Enable gamma to match primary/cursor plane behaviour. 565 * FIXME should be user controllable via propertiesa. 566 */ 567 sprctl |= SPRITE_GAMMA_ENABLE; 568 569 if (obj->tiling_mode != I915_TILING_NONE) 570 sprctl |= SPRITE_TILED; 571 572 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 573 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; 574 else 575 sprctl |= SPRITE_TRICKLE_FEED_DISABLE; 576 577 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 578 sprctl |= SPRITE_PIPE_CSC_ENABLE; 579 580 /* Sizes are 0 based */ 581 src_w--; 582 src_h--; 583 crtc_w--; 584 crtc_h--; 585 586 if (crtc_w != src_w || crtc_h != src_h) 587 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; 588 589 linear_offset = y * fb->pitches[0] + x * cpp; 590 sprsurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, 591 fb->pitches[0], rotation); 592 linear_offset -= sprsurf_offset; 593 594 if (rotation == DRM_ROTATE_180) { 595 sprctl |= SPRITE_ROTATE_180; 596 597 /* HSW and BDW does this automagically in hardware */ 598 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { 599 x += src_w; 600 y += src_h; 601 linear_offset += src_h * fb->pitches[0] + src_w * cpp; 602 } 603 } 604 605 if (key->flags) { 606 I915_WRITE(SPRKEYVAL(pipe), key->min_value); 607 I915_WRITE(SPRKEYMAX(pipe), key->max_value); 608 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); 609 } 610 611 if (key->flags & I915_SET_COLORKEY_DESTINATION) 612 sprctl |= SPRITE_DEST_KEY; 613 else if (key->flags & I915_SET_COLORKEY_SOURCE) 614 sprctl |= SPRITE_SOURCE_KEY; 615 616 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); 617 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); 618 619 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET 620 * register */ 621 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 622 I915_WRITE(SPROFFSET(pipe), (y << 16) | x); 623 else if (obj->tiling_mode != I915_TILING_NONE) 624 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); 625 else 626 I915_WRITE(SPRLINOFF(pipe), linear_offset); 627 628 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); 629 if (intel_plane->can_scale) 630 I915_WRITE(SPRSCALE(pipe), sprscale); 631 I915_WRITE(SPRCTL(pipe), sprctl); 632 I915_WRITE(SPRSURF(pipe), 633 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); 634 POSTING_READ(SPRSURF(pipe)); 635 } 636 637 static void 638 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) 639 { 640 struct drm_device *dev = plane->dev; 641 struct drm_i915_private *dev_priv = to_i915(dev); 642 struct intel_plane *intel_plane = to_intel_plane(plane); 643 int pipe = intel_plane->pipe; 644 645 I915_WRITE(SPRCTL(pipe), 0); 646 /* Can't leave the scaler enabled... */ 647 if (intel_plane->can_scale) 648 I915_WRITE(SPRSCALE(pipe), 0); 649 650 I915_WRITE(SPRSURF(pipe), 0); 651 POSTING_READ(SPRSURF(pipe)); 652 } 653 654 static void 655 ilk_update_plane(struct drm_plane *plane, 656 const struct intel_crtc_state *crtc_state, 657 const struct intel_plane_state *plane_state) 658 { 659 struct drm_device *dev = plane->dev; 660 struct drm_i915_private *dev_priv = to_i915(dev); 661 struct intel_plane *intel_plane = to_intel_plane(plane); 662 struct drm_framebuffer *fb = plane_state->base.fb; 663 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 664 int pipe = intel_plane->pipe; 665 u32 dvscntr, dvsscale; 666 u32 dvssurf_offset, linear_offset; 667 unsigned int rotation = plane_state->base.rotation; 668 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 669 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 670 int crtc_x = plane_state->dst.x1; 671 int crtc_y = plane_state->dst.y1; 672 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 673 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 674 uint32_t x = plane_state->src.x1 >> 16; 675 uint32_t y = plane_state->src.y1 >> 16; 676 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 677 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 678 679 dvscntr = DVS_ENABLE; 680 681 switch (fb->pixel_format) { 682 case DRM_FORMAT_XBGR8888: 683 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; 684 break; 685 case DRM_FORMAT_XRGB8888: 686 dvscntr |= DVS_FORMAT_RGBX888; 687 break; 688 case DRM_FORMAT_YUYV: 689 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; 690 break; 691 case DRM_FORMAT_YVYU: 692 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; 693 break; 694 case DRM_FORMAT_UYVY: 695 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; 696 break; 697 case DRM_FORMAT_VYUY: 698 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; 699 break; 700 default: 701 BUG(); 702 } 703 704 /* 705 * Enable gamma to match primary/cursor plane behaviour. 706 * FIXME should be user controllable via propertiesa. 707 */ 708 dvscntr |= DVS_GAMMA_ENABLE; 709 710 if (obj->tiling_mode != I915_TILING_NONE) 711 dvscntr |= DVS_TILED; 712 713 if (IS_GEN6(dev)) 714 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ 715 716 /* Sizes are 0 based */ 717 src_w--; 718 src_h--; 719 crtc_w--; 720 crtc_h--; 721 722 dvsscale = 0; 723 if (crtc_w != src_w || crtc_h != src_h) 724 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; 725 726 linear_offset = y * fb->pitches[0] + x * cpp; 727 dvssurf_offset = intel_compute_tile_offset(&x, &y, fb, 0, 728 fb->pitches[0], rotation); 729 linear_offset -= dvssurf_offset; 730 731 if (rotation == DRM_ROTATE_180) { 732 dvscntr |= DVS_ROTATE_180; 733 734 x += src_w; 735 y += src_h; 736 linear_offset += src_h * fb->pitches[0] + src_w * cpp; 737 } 738 739 if (key->flags) { 740 I915_WRITE(DVSKEYVAL(pipe), key->min_value); 741 I915_WRITE(DVSKEYMAX(pipe), key->max_value); 742 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); 743 } 744 745 if (key->flags & I915_SET_COLORKEY_DESTINATION) 746 dvscntr |= DVS_DEST_KEY; 747 else if (key->flags & I915_SET_COLORKEY_SOURCE) 748 dvscntr |= DVS_SOURCE_KEY; 749 750 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); 751 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); 752 753 if (obj->tiling_mode != I915_TILING_NONE) 754 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); 755 else 756 I915_WRITE(DVSLINOFF(pipe), linear_offset); 757 758 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); 759 I915_WRITE(DVSSCALE(pipe), dvsscale); 760 I915_WRITE(DVSCNTR(pipe), dvscntr); 761 I915_WRITE(DVSSURF(pipe), 762 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); 763 POSTING_READ(DVSSURF(pipe)); 764 } 765 766 static void 767 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) 768 { 769 struct drm_device *dev = plane->dev; 770 struct drm_i915_private *dev_priv = to_i915(dev); 771 struct intel_plane *intel_plane = to_intel_plane(plane); 772 int pipe = intel_plane->pipe; 773 774 I915_WRITE(DVSCNTR(pipe), 0); 775 /* Disable the scaler */ 776 I915_WRITE(DVSSCALE(pipe), 0); 777 778 I915_WRITE(DVSSURF(pipe), 0); 779 POSTING_READ(DVSSURF(pipe)); 780 } 781 782 static int 783 intel_check_sprite_plane(struct drm_plane *plane, 784 struct intel_crtc_state *crtc_state, 785 struct intel_plane_state *state) 786 { 787 struct drm_device *dev = plane->dev; 788 struct drm_crtc *crtc = state->base.crtc; 789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 790 struct intel_plane *intel_plane = to_intel_plane(plane); 791 struct drm_framebuffer *fb = state->base.fb; 792 int crtc_x, crtc_y; 793 unsigned int crtc_w, crtc_h; 794 uint32_t src_x, src_y, src_w, src_h; 795 struct drm_rect *src = &state->src; 796 struct drm_rect *dst = &state->dst; 797 const struct drm_rect *clip = &state->clip; 798 int hscale, vscale; 799 int max_scale, min_scale; 800 bool can_scale; 801 802 if (!fb) { 803 state->visible = false; 804 return 0; 805 } 806 807 /* Don't modify another pipe's plane */ 808 if (intel_plane->pipe != intel_crtc->pipe) { 809 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); 810 return -EINVAL; 811 } 812 813 /* FIXME check all gen limits */ 814 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { 815 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); 816 return -EINVAL; 817 } 818 819 /* setup can_scale, min_scale, max_scale */ 820 if (INTEL_INFO(dev)->gen >= 9) { 821 /* use scaler when colorkey is not required */ 822 if (state->ckey.flags == I915_SET_COLORKEY_NONE) { 823 can_scale = 1; 824 min_scale = 1; 825 max_scale = skl_max_scale(intel_crtc, crtc_state); 826 } else { 827 can_scale = 0; 828 min_scale = DRM_PLANE_HELPER_NO_SCALING; 829 max_scale = DRM_PLANE_HELPER_NO_SCALING; 830 } 831 } else { 832 can_scale = intel_plane->can_scale; 833 max_scale = intel_plane->max_downscale << 16; 834 min_scale = intel_plane->can_scale ? 1 : (1 << 16); 835 } 836 837 /* 838 * FIXME the following code does a bunch of fuzzy adjustments to the 839 * coordinates and sizes. We probably need some way to decide whether 840 * more strict checking should be done instead. 841 */ 842 drm_rect_rotate(src, fb->width << 16, fb->height << 16, 843 state->base.rotation); 844 845 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); 846 BUG_ON(hscale < 0); 847 848 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); 849 BUG_ON(vscale < 0); 850 851 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); 852 853 crtc_x = dst->x1; 854 crtc_y = dst->y1; 855 crtc_w = drm_rect_width(dst); 856 crtc_h = drm_rect_height(dst); 857 858 if (state->visible) { 859 /* check again in case clipping clamped the results */ 860 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); 861 if (hscale < 0) { 862 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); 863 drm_rect_debug_print("src: ", src, true); 864 drm_rect_debug_print("dst: ", dst, false); 865 866 return hscale; 867 } 868 869 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); 870 if (vscale < 0) { 871 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); 872 drm_rect_debug_print("src: ", src, true); 873 drm_rect_debug_print("dst: ", dst, false); 874 875 return vscale; 876 } 877 878 /* Make the source viewport size an exact multiple of the scaling factors. */ 879 drm_rect_adjust_size(src, 880 drm_rect_width(dst) * hscale - drm_rect_width(src), 881 drm_rect_height(dst) * vscale - drm_rect_height(src)); 882 883 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, 884 state->base.rotation); 885 886 /* sanity check to make sure the src viewport wasn't enlarged */ 887 WARN_ON(src->x1 < (int) state->base.src_x || 888 src->y1 < (int) state->base.src_y || 889 src->x2 > (int) state->base.src_x + state->base.src_w || 890 src->y2 > (int) state->base.src_y + state->base.src_h); 891 892 /* 893 * Hardware doesn't handle subpixel coordinates. 894 * Adjust to (macro)pixel boundary, but be careful not to 895 * increase the source viewport size, because that could 896 * push the downscaling factor out of bounds. 897 */ 898 src_x = src->x1 >> 16; 899 src_w = drm_rect_width(src) >> 16; 900 src_y = src->y1 >> 16; 901 src_h = drm_rect_height(src) >> 16; 902 903 if (format_is_yuv(fb->pixel_format)) { 904 src_x &= ~1; 905 src_w &= ~1; 906 907 /* 908 * Must keep src and dst the 909 * same if we can't scale. 910 */ 911 if (!can_scale) 912 crtc_w &= ~1; 913 914 if (crtc_w == 0) 915 state->visible = false; 916 } 917 } 918 919 /* Check size restrictions when scaling */ 920 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { 921 unsigned int width_bytes; 922 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 923 924 WARN_ON(!can_scale); 925 926 /* FIXME interlacing min height is 6 */ 927 928 if (crtc_w < 3 || crtc_h < 3) 929 state->visible = false; 930 931 if (src_w < 3 || src_h < 3) 932 state->visible = false; 933 934 width_bytes = ((src_x * cpp) & 63) + src_w * cpp; 935 936 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || 937 width_bytes > 4096 || fb->pitches[0] > 4096)) { 938 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); 939 return -EINVAL; 940 } 941 } 942 943 if (state->visible) { 944 src->x1 = src_x << 16; 945 src->x2 = (src_x + src_w) << 16; 946 src->y1 = src_y << 16; 947 src->y2 = (src_y + src_h) << 16; 948 } 949 950 dst->x1 = crtc_x; 951 dst->x2 = crtc_x + crtc_w; 952 dst->y1 = crtc_y; 953 dst->y2 = crtc_y + crtc_h; 954 955 return 0; 956 } 957 958 int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 959 struct drm_file *file_priv) 960 { 961 struct drm_intel_sprite_colorkey *set = data; 962 struct drm_plane *plane; 963 struct drm_plane_state *plane_state; 964 struct drm_atomic_state *state; 965 struct drm_modeset_acquire_ctx ctx; 966 int ret = 0; 967 968 /* Make sure we don't try to enable both src & dest simultaneously */ 969 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) 970 return -EINVAL; 971 972 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 973 set->flags & I915_SET_COLORKEY_DESTINATION) 974 return -EINVAL; 975 976 plane = drm_plane_find(dev, set->plane_id); 977 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) 978 return -ENOENT; 979 980 drm_modeset_acquire_init(&ctx, 0); 981 982 state = drm_atomic_state_alloc(plane->dev); 983 if (!state) { 984 ret = -ENOMEM; 985 goto out; 986 } 987 state->acquire_ctx = &ctx; 988 989 while (1) { 990 plane_state = drm_atomic_get_plane_state(state, plane); 991 ret = PTR_ERR_OR_ZERO(plane_state); 992 if (!ret) { 993 to_intel_plane_state(plane_state)->ckey = *set; 994 ret = drm_atomic_commit(state); 995 } 996 997 if (ret != -EDEADLK) 998 break; 999 1000 drm_atomic_state_clear(state); 1001 drm_modeset_backoff(&ctx); 1002 } 1003 1004 if (ret) 1005 drm_atomic_state_free(state); 1006 1007 out: 1008 drm_modeset_drop_locks(&ctx); 1009 drm_modeset_acquire_fini(&ctx); 1010 return ret; 1011 } 1012 1013 static const uint32_t ilk_plane_formats[] = { 1014 DRM_FORMAT_XRGB8888, 1015 DRM_FORMAT_YUYV, 1016 DRM_FORMAT_YVYU, 1017 DRM_FORMAT_UYVY, 1018 DRM_FORMAT_VYUY, 1019 }; 1020 1021 static const uint32_t snb_plane_formats[] = { 1022 DRM_FORMAT_XBGR8888, 1023 DRM_FORMAT_XRGB8888, 1024 DRM_FORMAT_YUYV, 1025 DRM_FORMAT_YVYU, 1026 DRM_FORMAT_UYVY, 1027 DRM_FORMAT_VYUY, 1028 }; 1029 1030 static const uint32_t vlv_plane_formats[] = { 1031 DRM_FORMAT_RGB565, 1032 DRM_FORMAT_ABGR8888, 1033 DRM_FORMAT_ARGB8888, 1034 DRM_FORMAT_XBGR8888, 1035 DRM_FORMAT_XRGB8888, 1036 DRM_FORMAT_XBGR2101010, 1037 DRM_FORMAT_ABGR2101010, 1038 DRM_FORMAT_YUYV, 1039 DRM_FORMAT_YVYU, 1040 DRM_FORMAT_UYVY, 1041 DRM_FORMAT_VYUY, 1042 }; 1043 1044 static uint32_t skl_plane_formats[] = { 1045 DRM_FORMAT_RGB565, 1046 DRM_FORMAT_ABGR8888, 1047 DRM_FORMAT_ARGB8888, 1048 DRM_FORMAT_XBGR8888, 1049 DRM_FORMAT_XRGB8888, 1050 DRM_FORMAT_YUYV, 1051 DRM_FORMAT_YVYU, 1052 DRM_FORMAT_UYVY, 1053 DRM_FORMAT_VYUY, 1054 }; 1055 1056 int 1057 intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane) 1058 { 1059 struct intel_plane *intel_plane = NULL; 1060 struct intel_plane_state *state = NULL; 1061 unsigned long possible_crtcs; 1062 const uint32_t *plane_formats; 1063 int num_plane_formats; 1064 int ret; 1065 1066 if (INTEL_INFO(dev)->gen < 5) 1067 return -ENODEV; 1068 1069 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); 1070 if (!intel_plane) { 1071 ret = -ENOMEM; 1072 goto fail; 1073 } 1074 1075 state = intel_create_plane_state(&intel_plane->base); 1076 if (!state) { 1077 ret = -ENOMEM; 1078 goto fail; 1079 } 1080 intel_plane->base.state = &state->base; 1081 1082 switch (INTEL_INFO(dev)->gen) { 1083 case 5: 1084 case 6: 1085 intel_plane->can_scale = true; 1086 intel_plane->max_downscale = 16; 1087 intel_plane->update_plane = ilk_update_plane; 1088 intel_plane->disable_plane = ilk_disable_plane; 1089 1090 if (IS_GEN6(dev)) { 1091 plane_formats = snb_plane_formats; 1092 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1093 } else { 1094 plane_formats = ilk_plane_formats; 1095 num_plane_formats = ARRAY_SIZE(ilk_plane_formats); 1096 } 1097 break; 1098 1099 case 7: 1100 case 8: 1101 if (IS_IVYBRIDGE(dev)) { 1102 intel_plane->can_scale = true; 1103 intel_plane->max_downscale = 2; 1104 } else { 1105 intel_plane->can_scale = false; 1106 intel_plane->max_downscale = 1; 1107 } 1108 1109 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 1110 intel_plane->update_plane = vlv_update_plane; 1111 intel_plane->disable_plane = vlv_disable_plane; 1112 1113 plane_formats = vlv_plane_formats; 1114 num_plane_formats = ARRAY_SIZE(vlv_plane_formats); 1115 } else { 1116 intel_plane->update_plane = ivb_update_plane; 1117 intel_plane->disable_plane = ivb_disable_plane; 1118 1119 plane_formats = snb_plane_formats; 1120 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1121 } 1122 break; 1123 case 9: 1124 intel_plane->can_scale = true; 1125 intel_plane->update_plane = skl_update_plane; 1126 intel_plane->disable_plane = skl_disable_plane; 1127 state->scaler_id = -1; 1128 1129 plane_formats = skl_plane_formats; 1130 num_plane_formats = ARRAY_SIZE(skl_plane_formats); 1131 break; 1132 default: 1133 MISSING_CASE(INTEL_INFO(dev)->gen); 1134 ret = -ENODEV; 1135 goto fail; 1136 } 1137 1138 intel_plane->pipe = pipe; 1139 intel_plane->plane = plane; 1140 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); 1141 intel_plane->check_plane = intel_check_sprite_plane; 1142 1143 possible_crtcs = (1 << pipe); 1144 1145 if (INTEL_INFO(dev)->gen >= 9) 1146 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, 1147 &intel_plane_funcs, 1148 plane_formats, num_plane_formats, 1149 DRM_PLANE_TYPE_OVERLAY, 1150 "plane %d%c", plane + 2, pipe_name(pipe)); 1151 else 1152 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, 1153 &intel_plane_funcs, 1154 plane_formats, num_plane_formats, 1155 DRM_PLANE_TYPE_OVERLAY, 1156 "sprite %c", sprite_name(pipe, plane)); 1157 if (ret) 1158 goto fail; 1159 1160 intel_create_rotation_property(dev, intel_plane); 1161 1162 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); 1163 1164 return 0; 1165 1166 fail: 1167 kfree(state); 1168 kfree(intel_plane); 1169 1170 return ret; 1171 } 1172