1 /* 2 * Copyright © 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Jesse Barnes <jbarnes@virtuousgeek.org> 25 * 26 * New plane/sprite handling. 27 * 28 * The older chips had a separate interface for programming plane related 29 * registers; newer ones are much simpler and we can use the new DRM plane 30 * support. 31 */ 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc.h> 34 #include <uapi_drm/drm_fourcc.h> 35 #include <drm/drm_rect.h> 36 #include <drm/drm_atomic.h> 37 #include <drm/drm_plane_helper.h> 38 #include "intel_drv.h" 39 #include <drm/i915_drm.h> 40 #include "i915_drv.h" 41 42 static bool 43 format_is_yuv(uint32_t format) 44 { 45 switch (format) { 46 case DRM_FORMAT_YUYV: 47 case DRM_FORMAT_UYVY: 48 case DRM_FORMAT_VYUY: 49 case DRM_FORMAT_YVYU: 50 return true; 51 default: 52 return false; 53 } 54 } 55 56 static int usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 57 int usecs) 58 { 59 /* paranoia */ 60 if (!adjusted_mode->crtc_htotal) 61 return 1; 62 63 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, 64 1000 * adjusted_mode->crtc_htotal); 65 } 66 67 /** 68 * intel_pipe_update_start() - start update of a set of display registers 69 * @crtc: the crtc of which the registers are going to be updated 70 * @start_vbl_count: vblank counter return pointer used for error checking 71 * 72 * Mark the start of an update to pipe registers that should be updated 73 * atomically regarding vblank. If the next vblank will happens within 74 * the next 100 us, this function waits until the vblank passes. 75 * 76 * After a successful call to this function, interrupts will be disabled 77 * until a subsequent call to intel_pipe_update_end(). That is done to 78 * avoid random delays. The value written to @start_vbl_count should be 79 * supplied to intel_pipe_update_end() for error checking. 80 */ 81 void intel_pipe_update_start(struct intel_crtc *crtc) 82 { 83 struct drm_device *dev = crtc->base.dev; 84 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 85 enum i915_pipe pipe = crtc->pipe; 86 long timeout = msecs_to_jiffies_timeout(1); 87 int scanline, min, max, vblank_start; 88 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 89 DEFINE_WAIT(wait); 90 91 vblank_start = adjusted_mode->crtc_vblank_start; 92 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 93 vblank_start = DIV_ROUND_UP(vblank_start, 2); 94 95 /* FIXME needs to be calibrated sensibly */ 96 min = vblank_start - usecs_to_scanlines(adjusted_mode, 100); 97 max = vblank_start - 1; 98 99 local_irq_disable(); 100 101 if (min <= 0 || max <= 0) 102 return; 103 104 if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) 105 return; 106 107 crtc->debug.min_vbl = min; 108 crtc->debug.max_vbl = max; 109 trace_i915_pipe_update_start(crtc); 110 111 for (;;) { 112 /* 113 * prepare_to_wait() has a memory barrier, which guarantees 114 * other CPUs can see the task state update by the time we 115 * read the scanline. 116 */ 117 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); 118 119 scanline = intel_get_crtc_scanline(crtc); 120 if (scanline < min || scanline > max) 121 break; 122 123 if (timeout <= 0) { 124 DRM_ERROR("Potential atomic update failure on pipe %c\n", 125 pipe_name(crtc->pipe)); 126 break; 127 } 128 129 local_irq_enable(); 130 131 timeout = schedule_timeout(timeout); 132 133 local_irq_disable(); 134 } 135 136 finish_wait(wq, &wait); 137 138 drm_crtc_vblank_put(&crtc->base); 139 140 crtc->debug.scanline_start = scanline; 141 crtc->debug.start_vbl_time = ktime_get(); 142 crtc->debug.start_vbl_count = 143 dev->driver->get_vblank_counter(dev, pipe); 144 145 trace_i915_pipe_update_vblank_evaded(crtc); 146 } 147 148 /** 149 * intel_pipe_update_end() - end update of a set of display registers 150 * @crtc: the crtc of which the registers were updated 151 * @start_vbl_count: start vblank counter (used for error checking) 152 * 153 * Mark the end of an update started with intel_pipe_update_start(). This 154 * re-enables interrupts and verifies the update was actually completed 155 * before a vblank using the value of @start_vbl_count. 156 */ 157 void intel_pipe_update_end(struct intel_crtc *crtc) 158 { 159 struct drm_device *dev = crtc->base.dev; 160 enum i915_pipe pipe = crtc->pipe; 161 int scanline_end = intel_get_crtc_scanline(crtc); 162 u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe); 163 ktime_t end_vbl_time = ktime_get(); 164 165 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end); 166 167 local_irq_enable(); 168 169 if (crtc->debug.start_vbl_count && 170 crtc->debug.start_vbl_count != end_vbl_count) { 171 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", 172 pipe_name(pipe), crtc->debug.start_vbl_count, 173 end_vbl_count, 174 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), 175 crtc->debug.min_vbl, crtc->debug.max_vbl, 176 crtc->debug.scanline_start, scanline_end); 177 } 178 } 179 180 static void 181 skl_update_plane(struct drm_plane *drm_plane, 182 const struct intel_crtc_state *crtc_state, 183 const struct intel_plane_state *plane_state) 184 { 185 struct drm_device *dev = drm_plane->dev; 186 struct drm_i915_private *dev_priv = dev->dev_private; 187 struct intel_plane *intel_plane = to_intel_plane(drm_plane); 188 struct drm_framebuffer *fb = plane_state->base.fb; 189 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 190 const int pipe = intel_plane->pipe; 191 const int plane = intel_plane->plane + 1; 192 u32 plane_ctl, stride_div, stride; 193 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 194 u32 surf_addr; 195 u32 tile_height, plane_offset, plane_size; 196 unsigned int rotation; 197 int x_offset, y_offset; 198 int crtc_x = plane_state->dst.x1; 199 int crtc_y = plane_state->dst.y1; 200 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 201 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 202 uint32_t x = plane_state->src.x1 >> 16; 203 uint32_t y = plane_state->src.y1 >> 16; 204 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 205 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 206 const struct intel_scaler *scaler = 207 &crtc_state->scaler_state.scalers[plane_state->scaler_id]; 208 209 plane_ctl = PLANE_CTL_ENABLE | 210 PLANE_CTL_PIPE_GAMMA_ENABLE | 211 PLANE_CTL_PIPE_CSC_ENABLE; 212 213 plane_ctl |= skl_plane_ctl_format(fb->pixel_format); 214 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); 215 216 rotation = plane_state->base.rotation; 217 plane_ctl |= skl_plane_ctl_rotation(rotation); 218 219 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], 220 fb->pixel_format); 221 222 /* Sizes are 0 based */ 223 src_w--; 224 src_h--; 225 crtc_w--; 226 crtc_h--; 227 228 if (key->flags) { 229 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); 230 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); 231 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); 232 } 233 234 if (key->flags & I915_SET_COLORKEY_DESTINATION) 235 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; 236 else if (key->flags & I915_SET_COLORKEY_SOURCE) 237 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; 238 239 surf_addr = intel_plane_obj_offset(intel_plane, obj, 0); 240 241 if (intel_rotation_90_or_270(rotation)) { 242 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 243 244 /* stride: Surface height in tiles */ 245 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); 246 stride = DIV_ROUND_UP(fb->height, tile_height); 247 plane_size = (src_w << 16) | src_h; 248 x_offset = stride * tile_height - y - (src_h + 1); 249 y_offset = x; 250 } else { 251 stride = fb->pitches[0] / stride_div; 252 plane_size = (src_h << 16) | src_w; 253 x_offset = x; 254 y_offset = y; 255 } 256 plane_offset = y_offset << 16 | x_offset; 257 258 I915_WRITE(PLANE_OFFSET(pipe, plane), plane_offset); 259 I915_WRITE(PLANE_STRIDE(pipe, plane), stride); 260 I915_WRITE(PLANE_SIZE(pipe, plane), plane_size); 261 262 /* program plane scaler */ 263 if (plane_state->scaler_id >= 0) { 264 uint32_t ps_ctrl = 0; 265 int scaler_id = plane_state->scaler_id; 266 267 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n", plane, 268 PS_PLANE_SEL(plane)); 269 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane) | scaler->mode; 270 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); 271 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); 272 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); 273 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), 274 ((crtc_w + 1) << 16)|(crtc_h + 1)); 275 276 I915_WRITE(PLANE_POS(pipe, plane), 0); 277 } else { 278 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x); 279 } 280 281 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl); 282 I915_WRITE(PLANE_SURF(pipe, plane), surf_addr); 283 POSTING_READ(PLANE_SURF(pipe, plane)); 284 } 285 286 static void 287 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) 288 { 289 struct drm_device *dev = dplane->dev; 290 struct drm_i915_private *dev_priv = dev->dev_private; 291 struct intel_plane *intel_plane = to_intel_plane(dplane); 292 const int pipe = intel_plane->pipe; 293 const int plane = intel_plane->plane + 1; 294 295 I915_WRITE(PLANE_CTL(pipe, plane), 0); 296 297 I915_WRITE(PLANE_SURF(pipe, plane), 0); 298 POSTING_READ(PLANE_SURF(pipe, plane)); 299 } 300 301 static void 302 chv_update_csc(struct intel_plane *intel_plane, uint32_t format) 303 { 304 struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private; 305 int plane = intel_plane->plane; 306 307 /* Seems RGB data bypasses the CSC always */ 308 if (!format_is_yuv(format)) 309 return; 310 311 /* 312 * BT.601 limited range YCbCr -> full range RGB 313 * 314 * |r| | 6537 4769 0| |cr | 315 * |g| = |-3330 4769 -1605| x |y-64| 316 * |b| | 0 4769 8263| |cb | 317 * 318 * Cb and Cr apparently come in as signed already, so no 319 * need for any offset. For Y we need to remove the offset. 320 */ 321 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64)); 322 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 323 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 324 325 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537)); 326 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0)); 327 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769)); 328 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0)); 329 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263)); 330 331 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64)); 332 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); 333 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448)); 334 335 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 336 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 337 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 338 } 339 340 static void 341 vlv_update_plane(struct drm_plane *dplane, 342 const struct intel_crtc_state *crtc_state, 343 const struct intel_plane_state *plane_state) 344 { 345 struct drm_device *dev = dplane->dev; 346 struct drm_i915_private *dev_priv = dev->dev_private; 347 struct intel_plane *intel_plane = to_intel_plane(dplane); 348 struct drm_framebuffer *fb = plane_state->base.fb; 349 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 350 int pipe = intel_plane->pipe; 351 int plane = intel_plane->plane; 352 u32 sprctl; 353 u32 sprsurf_offset, linear_offset; 354 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 355 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 356 int crtc_x = plane_state->dst.x1; 357 int crtc_y = plane_state->dst.y1; 358 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 359 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 360 uint32_t x = plane_state->src.x1 >> 16; 361 uint32_t y = plane_state->src.y1 >> 16; 362 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 363 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 364 365 sprctl = SP_ENABLE; 366 367 switch (fb->pixel_format) { 368 case DRM_FORMAT_YUYV: 369 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; 370 break; 371 case DRM_FORMAT_YVYU: 372 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; 373 break; 374 case DRM_FORMAT_UYVY: 375 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; 376 break; 377 case DRM_FORMAT_VYUY: 378 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; 379 break; 380 case DRM_FORMAT_RGB565: 381 sprctl |= SP_FORMAT_BGR565; 382 break; 383 case DRM_FORMAT_XRGB8888: 384 sprctl |= SP_FORMAT_BGRX8888; 385 break; 386 case DRM_FORMAT_ARGB8888: 387 sprctl |= SP_FORMAT_BGRA8888; 388 break; 389 case DRM_FORMAT_XBGR2101010: 390 sprctl |= SP_FORMAT_RGBX1010102; 391 break; 392 case DRM_FORMAT_ABGR2101010: 393 sprctl |= SP_FORMAT_RGBA1010102; 394 break; 395 case DRM_FORMAT_XBGR8888: 396 sprctl |= SP_FORMAT_RGBX8888; 397 break; 398 case DRM_FORMAT_ABGR8888: 399 sprctl |= SP_FORMAT_RGBA8888; 400 break; 401 default: 402 /* 403 * If we get here one of the upper layers failed to filter 404 * out the unsupported plane formats 405 */ 406 BUG(); 407 break; 408 } 409 410 /* 411 * Enable gamma to match primary/cursor plane behaviour. 412 * FIXME should be user controllable via propertiesa. 413 */ 414 sprctl |= SP_GAMMA_ENABLE; 415 416 if (obj->tiling_mode != I915_TILING_NONE) 417 sprctl |= SP_TILED; 418 419 /* Sizes are 0 based */ 420 src_w--; 421 src_h--; 422 crtc_w--; 423 crtc_h--; 424 425 linear_offset = y * fb->pitches[0] + x * cpp; 426 sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y, 427 fb->modifier[0], cpp, 428 fb->pitches[0]); 429 linear_offset -= sprsurf_offset; 430 431 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { 432 sprctl |= SP_ROTATE_180; 433 434 x += src_w; 435 y += src_h; 436 linear_offset += src_h * fb->pitches[0] + src_w * cpp; 437 } 438 439 if (key->flags) { 440 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value); 441 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value); 442 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask); 443 } 444 445 if (key->flags & I915_SET_COLORKEY_SOURCE) 446 sprctl |= SP_SOURCE_KEY; 447 448 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) 449 chv_update_csc(intel_plane, fb->pixel_format); 450 451 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]); 452 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x); 453 454 if (obj->tiling_mode != I915_TILING_NONE) 455 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x); 456 else 457 I915_WRITE(SPLINOFF(pipe, plane), linear_offset); 458 459 I915_WRITE(SPCONSTALPHA(pipe, plane), 0); 460 461 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); 462 I915_WRITE(SPCNTR(pipe, plane), sprctl); 463 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + 464 sprsurf_offset); 465 POSTING_READ(SPSURF(pipe, plane)); 466 } 467 468 static void 469 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) 470 { 471 struct drm_device *dev = dplane->dev; 472 struct drm_i915_private *dev_priv = dev->dev_private; 473 struct intel_plane *intel_plane = to_intel_plane(dplane); 474 int pipe = intel_plane->pipe; 475 int plane = intel_plane->plane; 476 477 I915_WRITE(SPCNTR(pipe, plane), 0); 478 479 I915_WRITE(SPSURF(pipe, plane), 0); 480 POSTING_READ(SPSURF(pipe, plane)); 481 } 482 483 static void 484 ivb_update_plane(struct drm_plane *plane, 485 const struct intel_crtc_state *crtc_state, 486 const struct intel_plane_state *plane_state) 487 { 488 struct drm_device *dev = plane->dev; 489 struct drm_i915_private *dev_priv = dev->dev_private; 490 struct intel_plane *intel_plane = to_intel_plane(plane); 491 struct drm_framebuffer *fb = plane_state->base.fb; 492 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 493 enum i915_pipe pipe = intel_plane->pipe; 494 u32 sprctl, sprscale = 0; 495 u32 sprsurf_offset, linear_offset; 496 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 497 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 498 int crtc_x = plane_state->dst.x1; 499 int crtc_y = plane_state->dst.y1; 500 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 501 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 502 uint32_t x = plane_state->src.x1 >> 16; 503 uint32_t y = plane_state->src.y1 >> 16; 504 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 505 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 506 507 sprctl = SPRITE_ENABLE; 508 509 switch (fb->pixel_format) { 510 case DRM_FORMAT_XBGR8888: 511 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; 512 break; 513 case DRM_FORMAT_XRGB8888: 514 sprctl |= SPRITE_FORMAT_RGBX888; 515 break; 516 case DRM_FORMAT_YUYV: 517 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; 518 break; 519 case DRM_FORMAT_YVYU: 520 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; 521 break; 522 case DRM_FORMAT_UYVY: 523 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; 524 break; 525 case DRM_FORMAT_VYUY: 526 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; 527 break; 528 default: 529 BUG(); 530 } 531 532 /* 533 * Enable gamma to match primary/cursor plane behaviour. 534 * FIXME should be user controllable via propertiesa. 535 */ 536 sprctl |= SPRITE_GAMMA_ENABLE; 537 538 if (obj->tiling_mode != I915_TILING_NONE) 539 sprctl |= SPRITE_TILED; 540 541 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 542 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; 543 else 544 sprctl |= SPRITE_TRICKLE_FEED_DISABLE; 545 546 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 547 sprctl |= SPRITE_PIPE_CSC_ENABLE; 548 549 /* Sizes are 0 based */ 550 src_w--; 551 src_h--; 552 crtc_w--; 553 crtc_h--; 554 555 if (crtc_w != src_w || crtc_h != src_h) 556 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; 557 558 linear_offset = y * fb->pitches[0] + x * cpp; 559 sprsurf_offset = intel_compute_tile_offset(dev_priv, &x, &y, 560 fb->modifier[0], cpp, 561 fb->pitches[0]); 562 linear_offset -= sprsurf_offset; 563 564 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { 565 sprctl |= SPRITE_ROTATE_180; 566 567 /* HSW and BDW does this automagically in hardware */ 568 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { 569 x += src_w; 570 y += src_h; 571 linear_offset += src_h * fb->pitches[0] + src_w * cpp; 572 } 573 } 574 575 if (key->flags) { 576 I915_WRITE(SPRKEYVAL(pipe), key->min_value); 577 I915_WRITE(SPRKEYMAX(pipe), key->max_value); 578 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask); 579 } 580 581 if (key->flags & I915_SET_COLORKEY_DESTINATION) 582 sprctl |= SPRITE_DEST_KEY; 583 else if (key->flags & I915_SET_COLORKEY_SOURCE) 584 sprctl |= SPRITE_SOURCE_KEY; 585 586 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]); 587 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); 588 589 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET 590 * register */ 591 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 592 I915_WRITE(SPROFFSET(pipe), (y << 16) | x); 593 else if (obj->tiling_mode != I915_TILING_NONE) 594 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); 595 else 596 I915_WRITE(SPRLINOFF(pipe), linear_offset); 597 598 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); 599 if (intel_plane->can_scale) 600 I915_WRITE(SPRSCALE(pipe), sprscale); 601 I915_WRITE(SPRCTL(pipe), sprctl); 602 I915_WRITE(SPRSURF(pipe), 603 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); 604 POSTING_READ(SPRSURF(pipe)); 605 } 606 607 static void 608 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) 609 { 610 struct drm_device *dev = plane->dev; 611 struct drm_i915_private *dev_priv = dev->dev_private; 612 struct intel_plane *intel_plane = to_intel_plane(plane); 613 int pipe = intel_plane->pipe; 614 615 I915_WRITE(SPRCTL(pipe), 0); 616 /* Can't leave the scaler enabled... */ 617 if (intel_plane->can_scale) 618 I915_WRITE(SPRSCALE(pipe), 0); 619 620 I915_WRITE(SPRSURF(pipe), 0); 621 POSTING_READ(SPRSURF(pipe)); 622 } 623 624 static void 625 ilk_update_plane(struct drm_plane *plane, 626 const struct intel_crtc_state *crtc_state, 627 const struct intel_plane_state *plane_state) 628 { 629 struct drm_device *dev = plane->dev; 630 struct drm_i915_private *dev_priv = dev->dev_private; 631 struct intel_plane *intel_plane = to_intel_plane(plane); 632 struct drm_framebuffer *fb = plane_state->base.fb; 633 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 634 int pipe = intel_plane->pipe; 635 u32 dvscntr, dvsscale; 636 u32 dvssurf_offset, linear_offset; 637 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 638 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 639 int crtc_x = plane_state->dst.x1; 640 int crtc_y = plane_state->dst.y1; 641 uint32_t crtc_w = drm_rect_width(&plane_state->dst); 642 uint32_t crtc_h = drm_rect_height(&plane_state->dst); 643 uint32_t x = plane_state->src.x1 >> 16; 644 uint32_t y = plane_state->src.y1 >> 16; 645 uint32_t src_w = drm_rect_width(&plane_state->src) >> 16; 646 uint32_t src_h = drm_rect_height(&plane_state->src) >> 16; 647 648 dvscntr = DVS_ENABLE; 649 650 switch (fb->pixel_format) { 651 case DRM_FORMAT_XBGR8888: 652 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; 653 break; 654 case DRM_FORMAT_XRGB8888: 655 dvscntr |= DVS_FORMAT_RGBX888; 656 break; 657 case DRM_FORMAT_YUYV: 658 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; 659 break; 660 case DRM_FORMAT_YVYU: 661 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; 662 break; 663 case DRM_FORMAT_UYVY: 664 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; 665 break; 666 case DRM_FORMAT_VYUY: 667 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; 668 break; 669 default: 670 BUG(); 671 } 672 673 /* 674 * Enable gamma to match primary/cursor plane behaviour. 675 * FIXME should be user controllable via propertiesa. 676 */ 677 dvscntr |= DVS_GAMMA_ENABLE; 678 679 if (obj->tiling_mode != I915_TILING_NONE) 680 dvscntr |= DVS_TILED; 681 682 if (IS_GEN6(dev)) 683 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ 684 685 /* Sizes are 0 based */ 686 src_w--; 687 src_h--; 688 crtc_w--; 689 crtc_h--; 690 691 dvsscale = 0; 692 if (crtc_w != src_w || crtc_h != src_h) 693 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; 694 695 linear_offset = y * fb->pitches[0] + x * cpp; 696 dvssurf_offset = intel_compute_tile_offset(dev_priv, &x, &y, 697 fb->modifier[0], cpp, 698 fb->pitches[0]); 699 linear_offset -= dvssurf_offset; 700 701 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { 702 dvscntr |= DVS_ROTATE_180; 703 704 x += src_w; 705 y += src_h; 706 linear_offset += src_h * fb->pitches[0] + src_w * cpp; 707 } 708 709 if (key->flags) { 710 I915_WRITE(DVSKEYVAL(pipe), key->min_value); 711 I915_WRITE(DVSKEYMAX(pipe), key->max_value); 712 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask); 713 } 714 715 if (key->flags & I915_SET_COLORKEY_DESTINATION) 716 dvscntr |= DVS_DEST_KEY; 717 else if (key->flags & I915_SET_COLORKEY_SOURCE) 718 dvscntr |= DVS_SOURCE_KEY; 719 720 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]); 721 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x); 722 723 if (obj->tiling_mode != I915_TILING_NONE) 724 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x); 725 else 726 I915_WRITE(DVSLINOFF(pipe), linear_offset); 727 728 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); 729 I915_WRITE(DVSSCALE(pipe), dvsscale); 730 I915_WRITE(DVSCNTR(pipe), dvscntr); 731 I915_WRITE(DVSSURF(pipe), 732 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); 733 POSTING_READ(DVSSURF(pipe)); 734 } 735 736 static void 737 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) 738 { 739 struct drm_device *dev = plane->dev; 740 struct drm_i915_private *dev_priv = dev->dev_private; 741 struct intel_plane *intel_plane = to_intel_plane(plane); 742 int pipe = intel_plane->pipe; 743 744 I915_WRITE(DVSCNTR(pipe), 0); 745 /* Disable the scaler */ 746 I915_WRITE(DVSSCALE(pipe), 0); 747 748 I915_WRITE(DVSSURF(pipe), 0); 749 POSTING_READ(DVSSURF(pipe)); 750 } 751 752 static int 753 intel_check_sprite_plane(struct drm_plane *plane, 754 struct intel_crtc_state *crtc_state, 755 struct intel_plane_state *state) 756 { 757 struct drm_device *dev = plane->dev; 758 struct drm_crtc *crtc = state->base.crtc; 759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 760 struct intel_plane *intel_plane = to_intel_plane(plane); 761 struct drm_framebuffer *fb = state->base.fb; 762 int crtc_x, crtc_y; 763 unsigned int crtc_w, crtc_h; 764 uint32_t src_x, src_y, src_w, src_h; 765 struct drm_rect *src = &state->src; 766 struct drm_rect *dst = &state->dst; 767 const struct drm_rect *clip = &state->clip; 768 int hscale, vscale; 769 int max_scale, min_scale; 770 bool can_scale; 771 772 if (!fb) { 773 state->visible = false; 774 return 0; 775 } 776 777 /* Don't modify another pipe's plane */ 778 if (intel_plane->pipe != intel_crtc->pipe) { 779 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n"); 780 return -EINVAL; 781 } 782 783 /* FIXME check all gen limits */ 784 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) { 785 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n"); 786 return -EINVAL; 787 } 788 789 /* setup can_scale, min_scale, max_scale */ 790 if (INTEL_INFO(dev)->gen >= 9) { 791 /* use scaler when colorkey is not required */ 792 if (state->ckey.flags == I915_SET_COLORKEY_NONE) { 793 can_scale = 1; 794 min_scale = 1; 795 max_scale = skl_max_scale(intel_crtc, crtc_state); 796 } else { 797 can_scale = 0; 798 min_scale = DRM_PLANE_HELPER_NO_SCALING; 799 max_scale = DRM_PLANE_HELPER_NO_SCALING; 800 } 801 } else { 802 can_scale = intel_plane->can_scale; 803 max_scale = intel_plane->max_downscale << 16; 804 min_scale = intel_plane->can_scale ? 1 : (1 << 16); 805 } 806 807 /* 808 * FIXME the following code does a bunch of fuzzy adjustments to the 809 * coordinates and sizes. We probably need some way to decide whether 810 * more strict checking should be done instead. 811 */ 812 drm_rect_rotate(src, fb->width << 16, fb->height << 16, 813 state->base.rotation); 814 815 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale); 816 BUG_ON(hscale < 0); 817 818 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale); 819 BUG_ON(vscale < 0); 820 821 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale); 822 823 crtc_x = dst->x1; 824 crtc_y = dst->y1; 825 crtc_w = drm_rect_width(dst); 826 crtc_h = drm_rect_height(dst); 827 828 if (state->visible) { 829 /* check again in case clipping clamped the results */ 830 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale); 831 if (hscale < 0) { 832 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n"); 833 drm_rect_debug_print("src: ", src, true); 834 drm_rect_debug_print("dst: ", dst, false); 835 836 return hscale; 837 } 838 839 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); 840 if (vscale < 0) { 841 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n"); 842 drm_rect_debug_print("src: ", src, true); 843 drm_rect_debug_print("dst: ", dst, false); 844 845 return vscale; 846 } 847 848 /* Make the source viewport size an exact multiple of the scaling factors. */ 849 drm_rect_adjust_size(src, 850 drm_rect_width(dst) * hscale - drm_rect_width(src), 851 drm_rect_height(dst) * vscale - drm_rect_height(src)); 852 853 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, 854 state->base.rotation); 855 856 /* sanity check to make sure the src viewport wasn't enlarged */ 857 WARN_ON(src->x1 < (int) state->base.src_x || 858 src->y1 < (int) state->base.src_y || 859 src->x2 > (int) state->base.src_x + state->base.src_w || 860 src->y2 > (int) state->base.src_y + state->base.src_h); 861 862 /* 863 * Hardware doesn't handle subpixel coordinates. 864 * Adjust to (macro)pixel boundary, but be careful not to 865 * increase the source viewport size, because that could 866 * push the downscaling factor out of bounds. 867 */ 868 src_x = src->x1 >> 16; 869 src_w = drm_rect_width(src) >> 16; 870 src_y = src->y1 >> 16; 871 src_h = drm_rect_height(src) >> 16; 872 873 if (format_is_yuv(fb->pixel_format)) { 874 src_x &= ~1; 875 src_w &= ~1; 876 877 /* 878 * Must keep src and dst the 879 * same if we can't scale. 880 */ 881 if (!can_scale) 882 crtc_w &= ~1; 883 884 if (crtc_w == 0) 885 state->visible = false; 886 } 887 } 888 889 /* Check size restrictions when scaling */ 890 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) { 891 unsigned int width_bytes; 892 int cpp = drm_format_plane_cpp(fb->pixel_format, 0); 893 894 WARN_ON(!can_scale); 895 896 /* FIXME interlacing min height is 6 */ 897 898 if (crtc_w < 3 || crtc_h < 3) 899 state->visible = false; 900 901 if (src_w < 3 || src_h < 3) 902 state->visible = false; 903 904 width_bytes = ((src_x * cpp) & 63) + src_w * cpp; 905 906 if (INTEL_INFO(dev)->gen < 9 && (src_w > 2048 || src_h > 2048 || 907 width_bytes > 4096 || fb->pitches[0] > 4096)) { 908 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n"); 909 return -EINVAL; 910 } 911 } 912 913 if (state->visible) { 914 src->x1 = src_x << 16; 915 src->x2 = (src_x + src_w) << 16; 916 src->y1 = src_y << 16; 917 src->y2 = (src_y + src_h) << 16; 918 } 919 920 dst->x1 = crtc_x; 921 dst->x2 = crtc_x + crtc_w; 922 dst->y1 = crtc_y; 923 dst->y2 = crtc_y + crtc_h; 924 925 return 0; 926 } 927 928 int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 929 struct drm_file *file_priv) 930 { 931 struct drm_intel_sprite_colorkey *set = data; 932 struct drm_plane *plane; 933 struct drm_plane_state *plane_state; 934 struct drm_atomic_state *state; 935 struct drm_modeset_acquire_ctx ctx; 936 int ret = 0; 937 938 /* Make sure we don't try to enable both src & dest simultaneously */ 939 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) 940 return -EINVAL; 941 942 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && 943 set->flags & I915_SET_COLORKEY_DESTINATION) 944 return -EINVAL; 945 946 plane = drm_plane_find(dev, set->plane_id); 947 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) 948 return -ENOENT; 949 950 drm_modeset_acquire_init(&ctx, 0); 951 952 state = drm_atomic_state_alloc(plane->dev); 953 if (!state) { 954 ret = -ENOMEM; 955 goto out; 956 } 957 state->acquire_ctx = &ctx; 958 959 while (1) { 960 plane_state = drm_atomic_get_plane_state(state, plane); 961 ret = PTR_ERR_OR_ZERO(plane_state); 962 if (!ret) { 963 to_intel_plane_state(plane_state)->ckey = *set; 964 ret = drm_atomic_commit(state); 965 } 966 967 if (ret != -EDEADLK) 968 break; 969 970 drm_atomic_state_clear(state); 971 drm_modeset_backoff(&ctx); 972 } 973 974 if (ret) 975 drm_atomic_state_free(state); 976 977 out: 978 drm_modeset_drop_locks(&ctx); 979 drm_modeset_acquire_fini(&ctx); 980 return ret; 981 } 982 983 static const uint32_t ilk_plane_formats[] = { 984 DRM_FORMAT_XRGB8888, 985 DRM_FORMAT_YUYV, 986 DRM_FORMAT_YVYU, 987 DRM_FORMAT_UYVY, 988 DRM_FORMAT_VYUY, 989 }; 990 991 static const uint32_t snb_plane_formats[] = { 992 DRM_FORMAT_XBGR8888, 993 DRM_FORMAT_XRGB8888, 994 DRM_FORMAT_YUYV, 995 DRM_FORMAT_YVYU, 996 DRM_FORMAT_UYVY, 997 DRM_FORMAT_VYUY, 998 }; 999 1000 static const uint32_t vlv_plane_formats[] = { 1001 DRM_FORMAT_RGB565, 1002 DRM_FORMAT_ABGR8888, 1003 DRM_FORMAT_ARGB8888, 1004 DRM_FORMAT_XBGR8888, 1005 DRM_FORMAT_XRGB8888, 1006 DRM_FORMAT_XBGR2101010, 1007 DRM_FORMAT_ABGR2101010, 1008 DRM_FORMAT_YUYV, 1009 DRM_FORMAT_YVYU, 1010 DRM_FORMAT_UYVY, 1011 DRM_FORMAT_VYUY, 1012 }; 1013 1014 static uint32_t skl_plane_formats[] = { 1015 DRM_FORMAT_RGB565, 1016 DRM_FORMAT_ABGR8888, 1017 DRM_FORMAT_ARGB8888, 1018 DRM_FORMAT_XBGR8888, 1019 DRM_FORMAT_XRGB8888, 1020 DRM_FORMAT_YUYV, 1021 DRM_FORMAT_YVYU, 1022 DRM_FORMAT_UYVY, 1023 DRM_FORMAT_VYUY, 1024 }; 1025 1026 int 1027 intel_plane_init(struct drm_device *dev, enum i915_pipe pipe, int plane) 1028 { 1029 struct intel_plane *intel_plane; 1030 struct intel_plane_state *state; 1031 unsigned long possible_crtcs; 1032 const uint32_t *plane_formats; 1033 int num_plane_formats; 1034 int ret; 1035 1036 if (INTEL_INFO(dev)->gen < 5) 1037 return -ENODEV; 1038 1039 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL); 1040 if (!intel_plane) 1041 return -ENOMEM; 1042 1043 state = intel_create_plane_state(&intel_plane->base); 1044 if (!state) { 1045 kfree(intel_plane); 1046 return -ENOMEM; 1047 } 1048 intel_plane->base.state = &state->base; 1049 1050 switch (INTEL_INFO(dev)->gen) { 1051 case 5: 1052 case 6: 1053 intel_plane->can_scale = true; 1054 intel_plane->max_downscale = 16; 1055 intel_plane->update_plane = ilk_update_plane; 1056 intel_plane->disable_plane = ilk_disable_plane; 1057 1058 if (IS_GEN6(dev)) { 1059 plane_formats = snb_plane_formats; 1060 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1061 } else { 1062 plane_formats = ilk_plane_formats; 1063 num_plane_formats = ARRAY_SIZE(ilk_plane_formats); 1064 } 1065 break; 1066 1067 case 7: 1068 case 8: 1069 if (IS_IVYBRIDGE(dev)) { 1070 intel_plane->can_scale = true; 1071 intel_plane->max_downscale = 2; 1072 } else { 1073 intel_plane->can_scale = false; 1074 intel_plane->max_downscale = 1; 1075 } 1076 1077 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 1078 intel_plane->update_plane = vlv_update_plane; 1079 intel_plane->disable_plane = vlv_disable_plane; 1080 1081 plane_formats = vlv_plane_formats; 1082 num_plane_formats = ARRAY_SIZE(vlv_plane_formats); 1083 } else { 1084 intel_plane->update_plane = ivb_update_plane; 1085 intel_plane->disable_plane = ivb_disable_plane; 1086 1087 plane_formats = snb_plane_formats; 1088 num_plane_formats = ARRAY_SIZE(snb_plane_formats); 1089 } 1090 break; 1091 case 9: 1092 intel_plane->can_scale = true; 1093 intel_plane->update_plane = skl_update_plane; 1094 intel_plane->disable_plane = skl_disable_plane; 1095 state->scaler_id = -1; 1096 1097 plane_formats = skl_plane_formats; 1098 num_plane_formats = ARRAY_SIZE(skl_plane_formats); 1099 break; 1100 default: 1101 kfree(intel_plane); 1102 return -ENODEV; 1103 } 1104 1105 intel_plane->pipe = pipe; 1106 intel_plane->plane = plane; 1107 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane); 1108 intel_plane->check_plane = intel_check_sprite_plane; 1109 possible_crtcs = (1 << pipe); 1110 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs, 1111 &intel_plane_funcs, 1112 plane_formats, num_plane_formats, 1113 DRM_PLANE_TYPE_OVERLAY, NULL); 1114 if (ret) { 1115 kfree(intel_plane); 1116 goto out; 1117 } 1118 1119 intel_create_rotation_property(dev, intel_plane); 1120 1121 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs); 1122 1123 out: 1124 return ret; 1125 } 1126