1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include "i915_drv.h" 26 #include "intel_uc.h" 27 #include <linux/firmware.h> 28 29 /* Cleans up uC firmware by releasing the firmware GEM obj. 30 */ 31 static void __intel_uc_fw_fini(struct intel_uc_fw *uc_fw) 32 { 33 struct drm_i915_gem_object *obj; 34 35 obj = fetch_and_zero(&uc_fw->obj); 36 if (obj) 37 i915_gem_object_put(obj); 38 39 uc_fw->fetch_status = INTEL_UC_FIRMWARE_NONE; 40 } 41 42 /* Reset GuC providing us with fresh state for both GuC and HuC. 43 */ 44 static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv) 45 { 46 int ret; 47 u32 guc_status; 48 49 ret = intel_guc_reset(dev_priv); 50 if (ret) { 51 DRM_ERROR("GuC reset failed, ret = %d\n", ret); 52 return ret; 53 } 54 55 guc_status = I915_READ(GUC_STATUS); 56 WARN(!(guc_status & GS_MIA_IN_RESET), 57 "GuC status: 0x%x, MIA core expected to be in reset\n", 58 guc_status); 59 60 return ret; 61 } 62 63 void intel_uc_sanitize_options(struct drm_i915_private *dev_priv) 64 { 65 if (!HAS_GUC(dev_priv)) { 66 if (i915.enable_guc_loading > 0 || 67 i915.enable_guc_submission > 0) 68 DRM_INFO("Ignoring GuC options, no hardware\n"); 69 70 i915.enable_guc_loading = 0; 71 i915.enable_guc_submission = 0; 72 return; 73 } 74 75 /* A negative value means "use platform default" */ 76 if (i915.enable_guc_loading < 0) 77 i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv); 78 79 /* Verify firmware version */ 80 if (i915.enable_guc_loading) { 81 if (HAS_HUC_UCODE(dev_priv)) 82 intel_huc_select_fw(&dev_priv->huc); 83 84 if (intel_guc_select_fw(&dev_priv->guc)) 85 i915.enable_guc_loading = 0; 86 } 87 88 /* Can't enable guc submission without guc loaded */ 89 if (!i915.enable_guc_loading) 90 i915.enable_guc_submission = 0; 91 92 /* A negative value means "use platform default" */ 93 if (i915.enable_guc_submission < 0) 94 i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv); 95 } 96 97 void intel_uc_init_early(struct drm_i915_private *dev_priv) 98 { 99 struct intel_guc *guc = &dev_priv->guc; 100 101 lockinit(&dev_priv->guc.send_mutex, "i9pgsm", 0, LK_CANRECURSE); 102 guc->send = intel_guc_send_mmio; 103 } 104 105 static void fetch_uc_fw(struct drm_i915_private *dev_priv, 106 struct intel_uc_fw *uc_fw) 107 { 108 struct pci_dev *pdev = dev_priv->drm.pdev; 109 struct drm_i915_gem_object *obj; 110 const struct firmware *fw = NULL; 111 struct uc_css_header *css; 112 size_t size; 113 int err; 114 115 if (!uc_fw->path) 116 return; 117 118 uc_fw->fetch_status = INTEL_UC_FIRMWARE_PENDING; 119 120 DRM_DEBUG_DRIVER("before requesting firmware: uC fw fetch status %s\n", 121 intel_uc_fw_status_repr(uc_fw->fetch_status)); 122 123 err = request_firmware(&fw, uc_fw->path, &pdev->dev); 124 if (err) 125 goto fail; 126 if (!fw) 127 goto fail; 128 129 DRM_DEBUG_DRIVER("fetch uC fw from %s succeeded, fw %p\n", 130 uc_fw->path, fw); 131 132 /* Check the size of the blob before examining buffer contents */ 133 if (fw->datasize < sizeof(struct uc_css_header)) { 134 DRM_NOTE("Firmware header is missing\n"); 135 goto fail; 136 } 137 138 css = (struct uc_css_header *)fw->data; 139 140 /* Firmware bits always start from header */ 141 uc_fw->header_offset = 0; 142 uc_fw->header_size = (css->header_size_dw - css->modulus_size_dw - 143 css->key_size_dw - css->exponent_size_dw) * sizeof(u32); 144 145 if (uc_fw->header_size != sizeof(struct uc_css_header)) { 146 DRM_NOTE("CSS header definition mismatch\n"); 147 goto fail; 148 } 149 150 /* then, uCode */ 151 uc_fw->ucode_offset = uc_fw->header_offset + uc_fw->header_size; 152 uc_fw->ucode_size = (css->size_dw - css->header_size_dw) * sizeof(u32); 153 154 /* now RSA */ 155 if (css->key_size_dw != UOS_RSA_SCRATCH_MAX_COUNT) { 156 DRM_NOTE("RSA key size is bad\n"); 157 goto fail; 158 } 159 uc_fw->rsa_offset = uc_fw->ucode_offset + uc_fw->ucode_size; 160 uc_fw->rsa_size = css->key_size_dw * sizeof(u32); 161 162 /* At least, it should have header, uCode and RSA. Size of all three. */ 163 size = uc_fw->header_size + uc_fw->ucode_size + uc_fw->rsa_size; 164 if (fw->datasize < size) { 165 DRM_NOTE("Missing firmware components\n"); 166 goto fail; 167 } 168 169 /* 170 * The GuC firmware image has the version number embedded at a 171 * well-known offset within the firmware blob; note that major / minor 172 * version are TWO bytes each (i.e. u16), although all pointers and 173 * offsets are defined in terms of bytes (u8). 174 */ 175 switch (uc_fw->type) { 176 case INTEL_UC_FW_TYPE_GUC: 177 /* Header and uCode will be loaded to WOPCM. Size of the two. */ 178 size = uc_fw->header_size + uc_fw->ucode_size; 179 180 /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */ 181 if (size > intel_guc_wopcm_size(dev_priv)) { 182 DRM_ERROR("Firmware is too large to fit in WOPCM\n"); 183 goto fail; 184 } 185 uc_fw->major_ver_found = css->guc.sw_version >> 16; 186 uc_fw->minor_ver_found = css->guc.sw_version & 0xFFFF; 187 break; 188 189 case INTEL_UC_FW_TYPE_HUC: 190 uc_fw->major_ver_found = css->huc.sw_version >> 16; 191 uc_fw->minor_ver_found = css->huc.sw_version & 0xFFFF; 192 break; 193 194 default: 195 DRM_ERROR("Unknown firmware type %d\n", uc_fw->type); 196 err = -ENOEXEC; 197 goto fail; 198 } 199 200 if (uc_fw->major_ver_wanted == 0 && uc_fw->minor_ver_wanted == 0) { 201 DRM_NOTE("Skipping %s firmware version check\n", 202 intel_uc_fw_type_repr(uc_fw->type)); 203 } else if (uc_fw->major_ver_found != uc_fw->major_ver_wanted || 204 uc_fw->minor_ver_found < uc_fw->minor_ver_wanted) { 205 DRM_NOTE("%s firmware version %d.%d, required %d.%d\n", 206 intel_uc_fw_type_repr(uc_fw->type), 207 uc_fw->major_ver_found, uc_fw->minor_ver_found, 208 uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted); 209 err = -ENOEXEC; 210 goto fail; 211 } 212 213 DRM_DEBUG_DRIVER("firmware version %d.%d OK (minimum %d.%d)\n", 214 uc_fw->major_ver_found, uc_fw->minor_ver_found, 215 uc_fw->major_ver_wanted, uc_fw->minor_ver_wanted); 216 217 obj = i915_gem_object_create_from_data(dev_priv, fw->data, fw->datasize); 218 if (IS_ERR(obj)) { 219 err = PTR_ERR(obj); 220 goto fail; 221 } 222 223 uc_fw->obj = obj; 224 uc_fw->size = fw->datasize; 225 226 DRM_DEBUG_DRIVER("uC fw fetch status SUCCESS, obj %p\n", 227 uc_fw->obj); 228 229 release_firmware(fw); 230 uc_fw->fetch_status = INTEL_UC_FIRMWARE_SUCCESS; 231 return; 232 233 fail: 234 DRM_WARN("Failed to fetch valid uC firmware from %s (error %d)\n", 235 uc_fw->path, err); 236 DRM_DEBUG_DRIVER("uC fw fetch status FAIL; err %d, fw %p, obj %p\n", 237 err, fw, uc_fw->obj); 238 239 release_firmware(fw); /* OK even if fw is NULL */ 240 uc_fw->fetch_status = INTEL_UC_FIRMWARE_FAIL; 241 } 242 243 void intel_uc_init_fw(struct drm_i915_private *dev_priv) 244 { 245 fetch_uc_fw(dev_priv, &dev_priv->huc.fw); 246 fetch_uc_fw(dev_priv, &dev_priv->guc.fw); 247 } 248 249 void intel_uc_fini_fw(struct drm_i915_private *dev_priv) 250 { 251 __intel_uc_fw_fini(&dev_priv->guc.fw); 252 __intel_uc_fw_fini(&dev_priv->huc.fw); 253 } 254 255 int intel_uc_init_hw(struct drm_i915_private *dev_priv) 256 { 257 int ret, attempts; 258 259 if (!i915.enable_guc_loading) 260 return 0; 261 262 gen9_reset_guc_interrupts(dev_priv); 263 264 /* We need to notify the guc whenever we change the GGTT */ 265 i915_ggtt_enable_guc(dev_priv); 266 267 if (i915.enable_guc_submission) { 268 /* 269 * This is stuff we need to have available at fw load time 270 * if we are planning to enable submission later 271 */ 272 ret = i915_guc_submission_init(dev_priv); 273 if (ret) 274 goto err_guc; 275 } 276 277 /* WaEnableuKernelHeaderValidFix:skl */ 278 /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */ 279 if (IS_GEN9(dev_priv)) 280 attempts = 3; 281 else 282 attempts = 1; 283 284 while (attempts--) { 285 /* 286 * Always reset the GuC just before (re)loading, so 287 * that the state and timing are fairly predictable 288 */ 289 ret = __intel_uc_reset_hw(dev_priv); 290 if (ret) 291 goto err_submission; 292 293 intel_huc_init_hw(&dev_priv->huc); 294 ret = intel_guc_init_hw(&dev_priv->guc); 295 if (ret == 0 || ret != -EAGAIN) 296 break; 297 298 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and " 299 "retry %d more time(s)\n", ret, attempts); 300 } 301 302 /* Did we succeded or run out of retries? */ 303 if (ret) 304 goto err_submission; 305 306 intel_guc_auth_huc(dev_priv); 307 if (i915.enable_guc_submission) { 308 if (i915.guc_log_level >= 0) 309 gen9_enable_guc_interrupts(dev_priv); 310 311 ret = i915_guc_submission_enable(dev_priv); 312 if (ret) 313 goto err_interrupts; 314 } 315 316 return 0; 317 318 /* 319 * We've failed to load the firmware :( 320 * 321 * Decide whether to disable GuC submission and fall back to 322 * execlist mode, and whether to hide the error by returning 323 * zero or to return -EIO, which the caller will treat as a 324 * nonfatal error (i.e. it doesn't prevent driver load, but 325 * marks the GPU as wedged until reset). 326 */ 327 err_interrupts: 328 gen9_disable_guc_interrupts(dev_priv); 329 err_submission: 330 if (i915.enable_guc_submission) 331 i915_guc_submission_fini(dev_priv); 332 err_guc: 333 i915_ggtt_disable_guc(dev_priv); 334 335 DRM_ERROR("GuC init failed\n"); 336 if (i915.enable_guc_loading > 1 || i915.enable_guc_submission > 1) 337 ret = -EIO; 338 else 339 ret = 0; 340 341 if (i915.enable_guc_submission) { 342 i915.enable_guc_submission = 0; 343 DRM_NOTE("Falling back from GuC submission to execlist mode\n"); 344 } 345 346 return ret; 347 } 348 349 void intel_uc_fini_hw(struct drm_i915_private *dev_priv) 350 { 351 if (!i915.enable_guc_loading) 352 return; 353 354 if (i915.enable_guc_submission) { 355 i915_guc_submission_disable(dev_priv); 356 gen9_disable_guc_interrupts(dev_priv); 357 i915_guc_submission_fini(dev_priv); 358 } 359 i915_ggtt_disable_guc(dev_priv); 360 } 361 362 /* 363 * Read GuC command/status register (SOFT_SCRATCH_0) 364 * Return true if it contains a response rather than a command 365 */ 366 static bool guc_recv(struct intel_guc *guc, u32 *status) 367 { 368 struct drm_i915_private *dev_priv = guc_to_i915(guc); 369 370 u32 val = I915_READ(SOFT_SCRATCH(0)); 371 *status = val; 372 return INTEL_GUC_RECV_IS_RESPONSE(val); 373 } 374 375 /* 376 * This function implements the MMIO based host to GuC interface. 377 */ 378 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len) 379 { 380 struct drm_i915_private *dev_priv = guc_to_i915(guc); 381 u32 status; 382 int i; 383 int ret; 384 385 if (WARN_ON(len < 1 || len > 15)) 386 return -EINVAL; 387 388 mutex_lock(&guc->send_mutex); 389 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER); 390 391 dev_priv->guc.action_count += 1; 392 dev_priv->guc.action_cmd = action[0]; 393 394 for (i = 0; i < len; i++) 395 I915_WRITE(SOFT_SCRATCH(i), action[i]); 396 397 POSTING_READ(SOFT_SCRATCH(i - 1)); 398 399 I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER); 400 401 /* 402 * Fast commands should complete in less than 10us, so sample quickly 403 * up to that length of time, then switch to a slower sleep-wait loop. 404 * No inte_guc_send command should ever take longer than 10ms. 405 */ 406 ret = wait_for_us(guc_recv(guc, &status), 10); 407 if (ret) 408 ret = wait_for(guc_recv(guc, &status), 10); 409 if (status != INTEL_GUC_STATUS_SUCCESS) { 410 /* 411 * Either the GuC explicitly returned an error (which 412 * we convert to -EIO here) or no response at all was 413 * received within the timeout limit (-ETIMEDOUT) 414 */ 415 if (ret != -ETIMEDOUT) 416 ret = -EIO; 417 418 DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;" 419 " ret=%d status=0x%08X response=0x%08X\n", 420 action[0], ret, status, I915_READ(SOFT_SCRATCH(15))); 421 422 dev_priv->guc.action_fail += 1; 423 dev_priv->guc.action_err = ret; 424 } 425 dev_priv->guc.action_status = status; 426 427 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER); 428 mutex_unlock(&guc->send_mutex); 429 430 return ret; 431 } 432 433 int intel_guc_sample_forcewake(struct intel_guc *guc) 434 { 435 struct drm_i915_private *dev_priv = guc_to_i915(guc); 436 u32 action[2]; 437 438 action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE; 439 /* WaRsDisableCoarsePowerGating:skl,bxt */ 440 if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) 441 action[1] = 0; 442 else 443 /* bit 0 and 1 are for Render and Media domain separately */ 444 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; 445 446 return intel_guc_send(guc, action, ARRAY_SIZE(action)); 447 } 448