1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "i915_drv.h" 25 #include "intel_drv.h" 26 27 #define FORCEWAKE_ACK_TIMEOUT_MS 2 28 29 #define __raw_i915_read8(dev_priv__, reg__) DRM_READ8(dev_priv__->mmio_map, reg__) 30 #define __raw_i915_write8(dev_priv__, reg__, val__) DRM_WRITE8(dev_priv__->mmio_map, reg__, val__) 31 32 #define __raw_i915_read16(dev_priv__, reg__) DRM_READ16(dev_priv__->mmio_map, reg__) 33 #define __raw_i915_write16(dev_priv__, reg__, val__) DRM_WRITE16(dev_priv__->mmio_map, reg__, val__) 34 35 #define __raw_i915_read32(dev_priv__, reg__) DRM_READ32(dev_priv__->mmio_map, reg__) 36 #define __raw_i915_write32(dev_priv__, reg__, val__) DRM_WRITE32(dev_priv__->mmio_map, reg__, val__) 37 38 #define __raw_i915_read64(dev_priv__, reg__) DRM_READ64(dev_priv__->mmio_map, reg__) 39 #define __raw_i915_write64(dev_priv__, reg__, val__) DRM_WRITE64(dev_priv__->mmio_map, reg__, val__) 40 41 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) 42 43 static void 44 assert_device_not_suspended(struct drm_i915_private *dev_priv) 45 { 46 WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, 47 "Device suspended\n"); 48 } 49 50 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) 51 { 52 u32 gt_thread_status_mask; 53 54 if (IS_HASWELL(dev_priv->dev)) 55 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; 56 else 57 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; 58 59 /* w/a for a sporadic read returning 0 by waiting for the GT 60 * thread to wake up. 61 */ 62 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) 63 DRM_ERROR("GT thread status wait timed out\n"); 64 } 65 66 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) 67 { 68 __raw_i915_write32(dev_priv, FORCEWAKE, 0); 69 /* something from same cacheline, but !FORCEWAKE */ 70 __raw_posting_read(dev_priv, ECOBUS); 71 } 72 73 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, 74 int fw_engine) 75 { 76 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, 77 FORCEWAKE_ACK_TIMEOUT_MS)) 78 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 79 80 __raw_i915_write32(dev_priv, FORCEWAKE, 1); 81 /* something from same cacheline, but !FORCEWAKE */ 82 __raw_posting_read(dev_priv, ECOBUS); 83 84 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), 85 FORCEWAKE_ACK_TIMEOUT_MS)) 86 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 87 88 /* WaRsForcewakeWaitTC0:snb */ 89 __gen6_gt_wait_for_thread_c0(dev_priv); 90 } 91 92 static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) 93 { 94 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); 95 /* something from same cacheline, but !FORCEWAKE_MT */ 96 __raw_posting_read(dev_priv, ECOBUS); 97 } 98 99 static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, 100 int fw_engine) 101 { 102 u32 forcewake_ack; 103 104 if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev)) 105 forcewake_ack = FORCEWAKE_ACK_HSW; 106 else 107 forcewake_ack = FORCEWAKE_MT_ACK; 108 109 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, 110 FORCEWAKE_ACK_TIMEOUT_MS)) 111 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 112 113 __raw_i915_write32(dev_priv, FORCEWAKE_MT, 114 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 115 /* something from same cacheline, but !FORCEWAKE_MT */ 116 __raw_posting_read(dev_priv, ECOBUS); 117 118 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), 119 FORCEWAKE_ACK_TIMEOUT_MS)) 120 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 121 122 /* WaRsForcewakeWaitTC0:ivb,hsw */ 123 if (INTEL_INFO(dev_priv->dev)->gen < 8) 124 __gen6_gt_wait_for_thread_c0(dev_priv); 125 } 126 127 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) 128 { 129 u32 gtfifodbg; 130 131 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); 132 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) 133 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); 134 } 135 136 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, 137 int fw_engine) 138 { 139 __raw_i915_write32(dev_priv, FORCEWAKE, 0); 140 /* something from same cacheline, but !FORCEWAKE */ 141 __raw_posting_read(dev_priv, ECOBUS); 142 gen6_gt_check_fifodbg(dev_priv); 143 } 144 145 static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, 146 int fw_engine) 147 { 148 __raw_i915_write32(dev_priv, FORCEWAKE_MT, 149 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 150 /* something from same cacheline, but !FORCEWAKE_MT */ 151 __raw_posting_read(dev_priv, ECOBUS); 152 153 if (IS_GEN7(dev_priv->dev)) 154 gen6_gt_check_fifodbg(dev_priv); 155 } 156 157 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 158 { 159 int ret = 0; 160 161 /* On VLV, FIFO will be shared by both SW and HW. 162 * So, we need to read the FREE_ENTRIES everytime */ 163 if (IS_VALLEYVIEW(dev_priv->dev)) 164 dev_priv->uncore.fifo_count = 165 __raw_i915_read32(dev_priv, GTFIFOCTL) & 166 GT_FIFO_FREE_ENTRIES_MASK; 167 168 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 169 int loop = 500; 170 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; 171 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 172 udelay(10); 173 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; 174 } 175 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) 176 ++ret; 177 dev_priv->uncore.fifo_count = fifo; 178 } 179 dev_priv->uncore.fifo_count--; 180 181 return ret; 182 } 183 184 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) 185 { 186 __raw_i915_write32(dev_priv, FORCEWAKE_VLV, 187 _MASKED_BIT_DISABLE(0xffff)); 188 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, 189 _MASKED_BIT_DISABLE(0xffff)); 190 /* something from same cacheline, but !FORCEWAKE_VLV */ 191 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); 192 } 193 194 static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, 195 int fw_engine) 196 { 197 /* Check for Render Engine */ 198 if (FORCEWAKE_RENDER & fw_engine) { 199 if (wait_for_atomic((__raw_i915_read32(dev_priv, 200 FORCEWAKE_ACK_VLV) & 201 FORCEWAKE_KERNEL) == 0, 202 FORCEWAKE_ACK_TIMEOUT_MS)) 203 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); 204 205 __raw_i915_write32(dev_priv, FORCEWAKE_VLV, 206 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 207 208 if (wait_for_atomic((__raw_i915_read32(dev_priv, 209 FORCEWAKE_ACK_VLV) & 210 FORCEWAKE_KERNEL), 211 FORCEWAKE_ACK_TIMEOUT_MS)) 212 DRM_ERROR("Timed out: waiting for Render to ack.\n"); 213 } 214 215 /* Check for Media Engine */ 216 if (FORCEWAKE_MEDIA & fw_engine) { 217 if (wait_for_atomic((__raw_i915_read32(dev_priv, 218 FORCEWAKE_ACK_MEDIA_VLV) & 219 FORCEWAKE_KERNEL) == 0, 220 FORCEWAKE_ACK_TIMEOUT_MS)) 221 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); 222 223 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, 224 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 225 226 if (wait_for_atomic((__raw_i915_read32(dev_priv, 227 FORCEWAKE_ACK_MEDIA_VLV) & 228 FORCEWAKE_KERNEL), 229 FORCEWAKE_ACK_TIMEOUT_MS)) 230 DRM_ERROR("Timed out: waiting for media to ack.\n"); 231 } 232 233 /* WaRsForcewakeWaitTC0:vlv */ 234 if (!IS_CHERRYVIEW(dev_priv->dev)) 235 __gen6_gt_wait_for_thread_c0(dev_priv); 236 } 237 238 static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, 239 int fw_engine) 240 { 241 242 /* Check for Render Engine */ 243 if (FORCEWAKE_RENDER & fw_engine) 244 __raw_i915_write32(dev_priv, FORCEWAKE_VLV, 245 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 246 247 248 /* Check for Media Engine */ 249 if (FORCEWAKE_MEDIA & fw_engine) 250 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, 251 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 252 253 /* something from same cacheline, but !FORCEWAKE_VLV */ 254 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); 255 if (!IS_CHERRYVIEW(dev_priv->dev)) 256 gen6_gt_check_fifodbg(dev_priv); 257 } 258 259 static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) 260 { 261 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 262 263 if (fw_engine & FORCEWAKE_RENDER && 264 dev_priv->uncore.fw_rendercount++ != 0) 265 fw_engine &= ~FORCEWAKE_RENDER; 266 if (fw_engine & FORCEWAKE_MEDIA && 267 dev_priv->uncore.fw_mediacount++ != 0) 268 fw_engine &= ~FORCEWAKE_MEDIA; 269 270 if (fw_engine) 271 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine); 272 273 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 274 } 275 276 static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) 277 { 278 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 279 280 if (fw_engine & FORCEWAKE_RENDER) { 281 WARN_ON(!dev_priv->uncore.fw_rendercount); 282 if (--dev_priv->uncore.fw_rendercount != 0) 283 fw_engine &= ~FORCEWAKE_RENDER; 284 } 285 286 if (fw_engine & FORCEWAKE_MEDIA) { 287 WARN_ON(!dev_priv->uncore.fw_mediacount); 288 if (--dev_priv->uncore.fw_mediacount != 0) 289 fw_engine &= ~FORCEWAKE_MEDIA; 290 } 291 292 if (fw_engine) 293 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); 294 295 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 296 } 297 298 static void gen6_force_wake_timer(unsigned long arg) 299 { 300 struct drm_i915_private *dev_priv = (void *)arg; 301 302 assert_device_not_suspended(dev_priv); 303 304 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 305 WARN_ON(!dev_priv->uncore.forcewake_count); 306 307 if (--dev_priv->uncore.forcewake_count == 0) 308 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); 309 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 310 311 intel_runtime_pm_put(dev_priv); 312 } 313 314 static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) 315 { 316 struct drm_i915_private *dev_priv = dev->dev_private; 317 318 if (del_timer_sync(&dev_priv->uncore.force_wake_timer)) 319 gen6_force_wake_timer((unsigned long)dev_priv); 320 321 /* Hold uncore.lock across reset to prevent any register access 322 * with forcewake not set correctly 323 */ 324 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 325 326 if (IS_VALLEYVIEW(dev)) 327 vlv_force_wake_reset(dev_priv); 328 else if (IS_GEN6(dev) || IS_GEN7(dev)) 329 __gen6_gt_force_wake_reset(dev_priv); 330 331 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) 332 __gen7_gt_force_wake_mt_reset(dev_priv); 333 334 if (restore) { /* If reset with a user forcewake, try to restore */ 335 unsigned fw = 0; 336 337 if (IS_VALLEYVIEW(dev)) { 338 if (dev_priv->uncore.fw_rendercount) 339 fw |= FORCEWAKE_RENDER; 340 341 if (dev_priv->uncore.fw_mediacount) 342 fw |= FORCEWAKE_MEDIA; 343 } else { 344 if (dev_priv->uncore.forcewake_count) 345 fw = FORCEWAKE_ALL; 346 } 347 348 if (fw) 349 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); 350 351 if (IS_GEN6(dev) || IS_GEN7(dev)) 352 dev_priv->uncore.fifo_count = 353 __raw_i915_read32(dev_priv, GTFIFOCTL) & 354 GT_FIFO_FREE_ENTRIES_MASK; 355 } 356 357 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 358 } 359 360 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) 361 { 362 struct drm_i915_private *dev_priv = dev->dev_private; 363 364 if (HAS_FPGA_DBG_UNCLAIMED(dev)) 365 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 366 367 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && 368 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { 369 /* The docs do not explain exactly how the calculation can be 370 * made. It is somewhat guessable, but for now, it's always 371 * 128MB. 372 * NB: We can't write IDICR yet because we do not have gt funcs 373 * set up */ 374 dev_priv->ellc_size = 128; 375 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); 376 } 377 378 /* clear out old GT FIFO errors */ 379 if (IS_GEN6(dev) || IS_GEN7(dev)) 380 __raw_i915_write32(dev_priv, GTFIFODBG, 381 __raw_i915_read32(dev_priv, GTFIFODBG)); 382 383 intel_uncore_forcewake_reset(dev, restore_forcewake); 384 } 385 386 void intel_uncore_sanitize(struct drm_device *dev) 387 { 388 /* BIOS often leaves RC6 enabled, but disable it for hw init */ 389 intel_disable_gt_powersave(dev); 390 } 391 392 /* 393 * Generally this is called implicitly by the register read function. However, 394 * if some sequence requires the GT to not power down then this function should 395 * be called at the beginning of the sequence followed by a call to 396 * gen6_gt_force_wake_put() at the end of the sequence. 397 */ 398 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) 399 { 400 if (!dev_priv->uncore.funcs.force_wake_get) 401 return; 402 403 intel_runtime_pm_get(dev_priv); 404 405 /* Redirect to VLV specific routine */ 406 if (IS_VALLEYVIEW(dev_priv->dev)) 407 return vlv_force_wake_get(dev_priv, fw_engine); 408 409 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 410 if (dev_priv->uncore.forcewake_count++ == 0) 411 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); 412 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 413 } 414 415 /* 416 * see gen6_gt_force_wake_get() 417 */ 418 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) 419 { 420 bool delayed = false; 421 422 if (!dev_priv->uncore.funcs.force_wake_put) 423 return; 424 425 /* Redirect to VLV specific routine */ 426 if (IS_VALLEYVIEW(dev_priv->dev)) { 427 vlv_force_wake_put(dev_priv, fw_engine); 428 goto out; 429 } 430 431 432 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 433 WARN_ON(!dev_priv->uncore.forcewake_count); 434 435 if (--dev_priv->uncore.forcewake_count == 0) { 436 dev_priv->uncore.forcewake_count++; 437 delayed = true; 438 mod_timer_pinned(&dev_priv->uncore.force_wake_timer, 439 jiffies + 1); 440 } 441 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 442 443 out: 444 if (!delayed) 445 intel_runtime_pm_put(dev_priv); 446 } 447 448 void assert_force_wake_inactive(struct drm_i915_private *dev_priv) 449 { 450 if (!dev_priv->uncore.funcs.force_wake_get) 451 return; 452 453 WARN_ON(dev_priv->uncore.forcewake_count > 0); 454 } 455 456 /* We give fast paths for the really cool registers */ 457 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ 458 ((reg) < 0x40000 && (reg) != FORCEWAKE) 459 460 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) 461 462 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ 463 (REG_RANGE((reg), 0x2000, 0x4000) || \ 464 REG_RANGE((reg), 0x5000, 0x8000) || \ 465 REG_RANGE((reg), 0xB000, 0x12000) || \ 466 REG_RANGE((reg), 0x2E000, 0x30000)) 467 468 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ 469 (REG_RANGE((reg), 0x12000, 0x14000) || \ 470 REG_RANGE((reg), 0x22000, 0x24000) || \ 471 REG_RANGE((reg), 0x30000, 0x40000)) 472 473 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ 474 (REG_RANGE((reg), 0x2000, 0x4000) || \ 475 REG_RANGE((reg), 0x5000, 0x8000) || \ 476 REG_RANGE((reg), 0x8300, 0x8500) || \ 477 REG_RANGE((reg), 0xB000, 0xC000) || \ 478 REG_RANGE((reg), 0xE000, 0xE800)) 479 480 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ 481 (REG_RANGE((reg), 0x8800, 0x8900) || \ 482 REG_RANGE((reg), 0xD000, 0xD800) || \ 483 REG_RANGE((reg), 0x12000, 0x14000) || \ 484 REG_RANGE((reg), 0x1A000, 0x1C000) || \ 485 REG_RANGE((reg), 0x1E800, 0x1EA00) || \ 486 REG_RANGE((reg), 0x30000, 0x40000)) 487 488 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ 489 (REG_RANGE((reg), 0x4000, 0x5000) || \ 490 REG_RANGE((reg), 0x8000, 0x8300) || \ 491 REG_RANGE((reg), 0x8500, 0x8600) || \ 492 REG_RANGE((reg), 0x9000, 0xB000) || \ 493 REG_RANGE((reg), 0xC000, 0xC800) || \ 494 REG_RANGE((reg), 0xF000, 0x10000) || \ 495 REG_RANGE((reg), 0x14000, 0x14400) || \ 496 REG_RANGE((reg), 0x22000, 0x24000)) 497 498 static void 499 ilk_dummy_write(struct drm_i915_private *dev_priv) 500 { 501 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up 502 * the chip from rc6 before touching it for real. MI_MODE is masked, 503 * hence harmless to write 0 into. */ 504 __raw_i915_write32(dev_priv, MI_MODE, 0); 505 } 506 507 static void 508 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read, 509 bool before) 510 { 511 const char *op = read ? "reading" : "writing to"; 512 const char *when = before ? "before" : "after"; 513 514 if (!i915.mmio_debug) 515 return; 516 517 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { 518 WARN(1, "Unclaimed register detected %s %s register 0x%x\n", 519 when, op, reg); 520 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 521 } 522 } 523 524 static void 525 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv) 526 { 527 if (i915.mmio_debug) 528 return; 529 530 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { 531 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem."); 532 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 533 } 534 } 535 536 #define REG_READ_HEADER(x) \ 537 u##x val = 0; \ 538 assert_device_not_suspended(dev_priv); \ 539 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE) 540 541 #define REG_READ_FOOTER \ 542 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); \ 543 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 544 return val 545 546 #define __gen4_read(x) \ 547 static u##x \ 548 gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 549 REG_READ_HEADER(x); \ 550 val = __raw_i915_read##x(dev_priv, reg); \ 551 REG_READ_FOOTER; \ 552 } 553 554 #define __gen5_read(x) \ 555 static u##x \ 556 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 557 REG_READ_HEADER(x); \ 558 ilk_dummy_write(dev_priv); \ 559 val = __raw_i915_read##x(dev_priv, reg); \ 560 REG_READ_FOOTER; \ 561 } 562 563 #define __gen6_read(x) \ 564 static u##x \ 565 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 566 REG_READ_HEADER(x); \ 567 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ 568 if (dev_priv->uncore.forcewake_count == 0 && \ 569 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 570 dev_priv->uncore.funcs.force_wake_get(dev_priv, \ 571 FORCEWAKE_ALL); \ 572 val = __raw_i915_read##x(dev_priv, reg); \ 573 dev_priv->uncore.funcs.force_wake_put(dev_priv, \ 574 FORCEWAKE_ALL); \ 575 } else { \ 576 val = __raw_i915_read##x(dev_priv, reg); \ 577 } \ 578 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ 579 REG_READ_FOOTER; \ 580 } 581 582 #define __vlv_read(x) \ 583 static u##x \ 584 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 585 unsigned fwengine = 0; \ 586 REG_READ_HEADER(x); \ 587 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \ 588 if (dev_priv->uncore.fw_rendercount == 0) \ 589 fwengine = FORCEWAKE_RENDER; \ 590 } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \ 591 if (dev_priv->uncore.fw_mediacount == 0) \ 592 fwengine = FORCEWAKE_MEDIA; \ 593 } \ 594 if (fwengine) \ 595 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ 596 val = __raw_i915_read##x(dev_priv, reg); \ 597 if (fwengine) \ 598 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ 599 REG_READ_FOOTER; \ 600 } 601 602 #define __chv_read(x) \ 603 static u##x \ 604 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ 605 unsigned fwengine = 0; \ 606 REG_READ_HEADER(x); \ 607 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ 608 if (dev_priv->uncore.fw_rendercount == 0) \ 609 fwengine = FORCEWAKE_RENDER; \ 610 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ 611 if (dev_priv->uncore.fw_mediacount == 0) \ 612 fwengine = FORCEWAKE_MEDIA; \ 613 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ 614 if (dev_priv->uncore.fw_rendercount == 0) \ 615 fwengine |= FORCEWAKE_RENDER; \ 616 if (dev_priv->uncore.fw_mediacount == 0) \ 617 fwengine |= FORCEWAKE_MEDIA; \ 618 } \ 619 if (fwengine) \ 620 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ 621 val = __raw_i915_read##x(dev_priv, reg); \ 622 if (fwengine) \ 623 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ 624 REG_READ_FOOTER; \ 625 } 626 627 __chv_read(8) 628 __chv_read(16) 629 __chv_read(32) 630 __chv_read(64) 631 __vlv_read(8) 632 __vlv_read(16) 633 __vlv_read(32) 634 __vlv_read(64) 635 __gen6_read(8) 636 __gen6_read(16) 637 __gen6_read(32) 638 __gen6_read(64) 639 __gen5_read(8) 640 __gen5_read(16) 641 __gen5_read(32) 642 __gen5_read(64) 643 __gen4_read(8) 644 __gen4_read(16) 645 __gen4_read(32) 646 __gen4_read(64) 647 648 #undef __chv_read 649 #undef __vlv_read 650 #undef __gen6_read 651 #undef __gen5_read 652 #undef __gen4_read 653 #undef REG_READ_FOOTER 654 #undef REG_READ_HEADER 655 656 #define REG_WRITE_HEADER \ 657 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 658 assert_device_not_suspended(dev_priv); \ 659 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE) 660 661 #define REG_WRITE_FOOTER \ 662 lockmgr(&dev_priv->uncore.lock, LK_RELEASE) 663 664 #define __gen4_write(x) \ 665 static void \ 666 gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 667 REG_WRITE_HEADER; \ 668 __raw_i915_write##x(dev_priv, reg, val); \ 669 REG_WRITE_FOOTER; \ 670 } 671 672 #define __gen5_write(x) \ 673 static void \ 674 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 675 REG_WRITE_HEADER; \ 676 ilk_dummy_write(dev_priv); \ 677 __raw_i915_write##x(dev_priv, reg, val); \ 678 REG_WRITE_FOOTER; \ 679 } 680 681 #define __gen6_write(x) \ 682 static void \ 683 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 684 u32 __fifo_ret = 0; \ 685 REG_WRITE_HEADER; \ 686 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 687 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 688 } \ 689 __raw_i915_write##x(dev_priv, reg, val); \ 690 if (unlikely(__fifo_ret)) { \ 691 gen6_gt_check_fifodbg(dev_priv); \ 692 } \ 693 REG_WRITE_FOOTER; \ 694 } 695 696 #define __hsw_write(x) \ 697 static void \ 698 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 699 u32 __fifo_ret = 0; \ 700 REG_WRITE_HEADER; \ 701 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 702 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ 703 } \ 704 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ 705 __raw_i915_write##x(dev_priv, reg, val); \ 706 if (unlikely(__fifo_ret)) { \ 707 gen6_gt_check_fifodbg(dev_priv); \ 708 } \ 709 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ 710 hsw_unclaimed_reg_detect(dev_priv); \ 711 REG_WRITE_FOOTER; \ 712 } 713 714 static const u32 gen8_shadowed_regs[] = { 715 FORCEWAKE_MT, 716 GEN6_RPNSWREQ, 717 GEN6_RC_VIDEO_FREQ, 718 RING_TAIL(RENDER_RING_BASE), 719 RING_TAIL(GEN6_BSD_RING_BASE), 720 RING_TAIL(VEBOX_RING_BASE), 721 RING_TAIL(BLT_RING_BASE), 722 /* TODO: Other registers are not yet used */ 723 }; 724 725 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) 726 { 727 int i; 728 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) 729 if (reg == gen8_shadowed_regs[i]) 730 return true; 731 732 return false; 733 } 734 735 #define __gen8_write(x) \ 736 static void \ 737 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 738 REG_WRITE_HEADER; \ 739 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ 740 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \ 741 if (dev_priv->uncore.forcewake_count == 0) \ 742 dev_priv->uncore.funcs.force_wake_get(dev_priv, \ 743 FORCEWAKE_ALL); \ 744 __raw_i915_write##x(dev_priv, reg, val); \ 745 if (dev_priv->uncore.forcewake_count == 0) \ 746 dev_priv->uncore.funcs.force_wake_put(dev_priv, \ 747 FORCEWAKE_ALL); \ 748 } else { \ 749 __raw_i915_write##x(dev_priv, reg, val); \ 750 } \ 751 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ 752 hsw_unclaimed_reg_detect(dev_priv); \ 753 REG_WRITE_FOOTER; \ 754 } 755 756 #define __chv_write(x) \ 757 static void \ 758 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ 759 unsigned fwengine = 0; \ 760 bool shadowed = is_gen8_shadowed(dev_priv, reg); \ 761 REG_WRITE_HEADER; \ 762 if (!shadowed) { \ 763 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ 764 if (dev_priv->uncore.fw_rendercount == 0) \ 765 fwengine = FORCEWAKE_RENDER; \ 766 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ 767 if (dev_priv->uncore.fw_mediacount == 0) \ 768 fwengine = FORCEWAKE_MEDIA; \ 769 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ 770 if (dev_priv->uncore.fw_rendercount == 0) \ 771 fwengine |= FORCEWAKE_RENDER; \ 772 if (dev_priv->uncore.fw_mediacount == 0) \ 773 fwengine |= FORCEWAKE_MEDIA; \ 774 } \ 775 } \ 776 if (fwengine) \ 777 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ 778 __raw_i915_write##x(dev_priv, reg, val); \ 779 if (fwengine) \ 780 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ 781 REG_WRITE_FOOTER; \ 782 } 783 784 __chv_write(8) 785 __chv_write(16) 786 __chv_write(32) 787 __chv_write(64) 788 __gen8_write(8) 789 __gen8_write(16) 790 __gen8_write(32) 791 __gen8_write(64) 792 __hsw_write(8) 793 __hsw_write(16) 794 __hsw_write(32) 795 __hsw_write(64) 796 __gen6_write(8) 797 __gen6_write(16) 798 __gen6_write(32) 799 __gen6_write(64) 800 __gen5_write(8) 801 __gen5_write(16) 802 __gen5_write(32) 803 __gen5_write(64) 804 __gen4_write(8) 805 __gen4_write(16) 806 __gen4_write(32) 807 __gen4_write(64) 808 809 #undef __chv_write 810 #undef __gen8_write 811 #undef __hsw_write 812 #undef __gen6_write 813 #undef __gen5_write 814 #undef __gen4_write 815 #undef REG_WRITE_FOOTER 816 #undef REG_WRITE_HEADER 817 818 void intel_uncore_init(struct drm_device *dev) 819 { 820 struct drm_i915_private *dev_priv = dev->dev_private; 821 822 setup_timer(&dev_priv->uncore.force_wake_timer, 823 gen6_force_wake_timer, (unsigned long)dev_priv); 824 825 intel_uncore_early_sanitize(dev, false); 826 827 if (IS_VALLEYVIEW(dev)) { 828 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; 829 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; 830 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 831 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; 832 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; 833 } else if (IS_IVYBRIDGE(dev)) { 834 u32 ecobus; 835 836 /* IVB configs may use multi-threaded forcewake */ 837 838 /* A small trick here - if the bios hasn't configured 839 * MT forcewake, and if the device is in RC6, then 840 * force_wake_mt_get will not wake the device and the 841 * ECOBUS read will return zero. Which will be 842 * (correctly) interpreted by the test below as MT 843 * forcewake being disabled. 844 */ 845 mutex_lock(&dev->struct_mutex); 846 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); 847 ecobus = __raw_i915_read32(dev_priv, ECOBUS); 848 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); 849 mutex_unlock(&dev->struct_mutex); 850 851 if (ecobus & FORCEWAKE_MT_ENABLE) { 852 dev_priv->uncore.funcs.force_wake_get = 853 __gen7_gt_force_wake_mt_get; 854 dev_priv->uncore.funcs.force_wake_put = 855 __gen7_gt_force_wake_mt_put; 856 } else { 857 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); 858 DRM_INFO("when using vblank-synced partial screen updates.\n"); 859 dev_priv->uncore.funcs.force_wake_get = 860 __gen6_gt_force_wake_get; 861 dev_priv->uncore.funcs.force_wake_put = 862 __gen6_gt_force_wake_put; 863 } 864 } else if (IS_GEN6(dev)) { 865 dev_priv->uncore.funcs.force_wake_get = 866 __gen6_gt_force_wake_get; 867 dev_priv->uncore.funcs.force_wake_put = 868 __gen6_gt_force_wake_put; 869 } 870 871 switch (INTEL_INFO(dev)->gen) { 872 default: 873 if (IS_CHERRYVIEW(dev)) { 874 dev_priv->uncore.funcs.mmio_writeb = chv_write8; 875 dev_priv->uncore.funcs.mmio_writew = chv_write16; 876 dev_priv->uncore.funcs.mmio_writel = chv_write32; 877 dev_priv->uncore.funcs.mmio_writeq = chv_write64; 878 dev_priv->uncore.funcs.mmio_readb = chv_read8; 879 dev_priv->uncore.funcs.mmio_readw = chv_read16; 880 dev_priv->uncore.funcs.mmio_readl = chv_read32; 881 dev_priv->uncore.funcs.mmio_readq = chv_read64; 882 883 } else { 884 dev_priv->uncore.funcs.mmio_writeb = gen8_write8; 885 dev_priv->uncore.funcs.mmio_writew = gen8_write16; 886 dev_priv->uncore.funcs.mmio_writel = gen8_write32; 887 dev_priv->uncore.funcs.mmio_writeq = gen8_write64; 888 dev_priv->uncore.funcs.mmio_readb = gen6_read8; 889 dev_priv->uncore.funcs.mmio_readw = gen6_read16; 890 dev_priv->uncore.funcs.mmio_readl = gen6_read32; 891 dev_priv->uncore.funcs.mmio_readq = gen6_read64; 892 } 893 break; 894 case 7: 895 case 6: 896 if (IS_HASWELL(dev)) { 897 dev_priv->uncore.funcs.mmio_writeb = hsw_write8; 898 dev_priv->uncore.funcs.mmio_writew = hsw_write16; 899 dev_priv->uncore.funcs.mmio_writel = hsw_write32; 900 dev_priv->uncore.funcs.mmio_writeq = hsw_write64; 901 } else { 902 dev_priv->uncore.funcs.mmio_writeb = gen6_write8; 903 dev_priv->uncore.funcs.mmio_writew = gen6_write16; 904 dev_priv->uncore.funcs.mmio_writel = gen6_write32; 905 dev_priv->uncore.funcs.mmio_writeq = gen6_write64; 906 } 907 908 if (IS_VALLEYVIEW(dev)) { 909 dev_priv->uncore.funcs.mmio_readb = vlv_read8; 910 dev_priv->uncore.funcs.mmio_readw = vlv_read16; 911 dev_priv->uncore.funcs.mmio_readl = vlv_read32; 912 dev_priv->uncore.funcs.mmio_readq = vlv_read64; 913 } else { 914 dev_priv->uncore.funcs.mmio_readb = gen6_read8; 915 dev_priv->uncore.funcs.mmio_readw = gen6_read16; 916 dev_priv->uncore.funcs.mmio_readl = gen6_read32; 917 dev_priv->uncore.funcs.mmio_readq = gen6_read64; 918 } 919 break; 920 case 5: 921 dev_priv->uncore.funcs.mmio_writeb = gen5_write8; 922 dev_priv->uncore.funcs.mmio_writew = gen5_write16; 923 dev_priv->uncore.funcs.mmio_writel = gen5_write32; 924 dev_priv->uncore.funcs.mmio_writeq = gen5_write64; 925 dev_priv->uncore.funcs.mmio_readb = gen5_read8; 926 dev_priv->uncore.funcs.mmio_readw = gen5_read16; 927 dev_priv->uncore.funcs.mmio_readl = gen5_read32; 928 dev_priv->uncore.funcs.mmio_readq = gen5_read64; 929 break; 930 case 4: 931 case 3: 932 case 2: 933 dev_priv->uncore.funcs.mmio_writeb = gen4_write8; 934 dev_priv->uncore.funcs.mmio_writew = gen4_write16; 935 dev_priv->uncore.funcs.mmio_writel = gen4_write32; 936 dev_priv->uncore.funcs.mmio_writeq = gen4_write64; 937 dev_priv->uncore.funcs.mmio_readb = gen4_read8; 938 dev_priv->uncore.funcs.mmio_readw = gen4_read16; 939 dev_priv->uncore.funcs.mmio_readl = gen4_read32; 940 dev_priv->uncore.funcs.mmio_readq = gen4_read64; 941 break; 942 } 943 } 944 945 void intel_uncore_fini(struct drm_device *dev) 946 { 947 /* Paranoia: make sure we have disabled everything before we exit. */ 948 intel_uncore_sanitize(dev); 949 intel_uncore_forcewake_reset(dev, false); 950 } 951 952 #define GEN_RANGE(l, h) GENMASK(h, l) 953 954 static const struct register_whitelist { 955 uint64_t offset; 956 uint32_t size; 957 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ 958 uint32_t gen_bitmask; 959 } whitelist[] = { 960 { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) }, 961 }; 962 963 int i915_reg_read_ioctl(struct drm_device *dev, 964 void *data, struct drm_file *file) 965 { 966 struct drm_i915_private *dev_priv = dev->dev_private; 967 struct drm_i915_reg_read *reg = data; 968 struct register_whitelist const *entry = whitelist; 969 int i, ret = 0; 970 971 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { 972 if (entry->offset == reg->offset && 973 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) 974 break; 975 } 976 977 if (i == ARRAY_SIZE(whitelist)) 978 return -EINVAL; 979 980 intel_runtime_pm_get(dev_priv); 981 982 switch (entry->size) { 983 case 8: 984 reg->val = I915_READ64(reg->offset); 985 break; 986 case 4: 987 reg->val = I915_READ(reg->offset); 988 break; 989 case 2: 990 reg->val = I915_READ16(reg->offset); 991 break; 992 case 1: 993 reg->val = I915_READ8(reg->offset); 994 break; 995 default: 996 WARN_ON(1); 997 ret = -EINVAL; 998 goto out; 999 } 1000 1001 out: 1002 intel_runtime_pm_put(dev_priv); 1003 return ret; 1004 } 1005 1006 int i915_get_reset_stats_ioctl(struct drm_device *dev, 1007 void *data, struct drm_file *file) 1008 { 1009 struct drm_i915_private *dev_priv = dev->dev_private; 1010 struct drm_i915_reset_stats *args = data; 1011 struct i915_ctx_hang_stats *hs; 1012 struct intel_context *ctx; 1013 int ret; 1014 1015 if (args->flags || args->pad) 1016 return -EINVAL; 1017 1018 ret = mutex_lock_interruptible(&dev->struct_mutex); 1019 if (ret) 1020 return ret; 1021 1022 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); 1023 if (IS_ERR(ctx)) { 1024 mutex_unlock(&dev->struct_mutex); 1025 return PTR_ERR(ctx); 1026 } 1027 hs = &ctx->hang_stats; 1028 1029 args->reset_count = i915_reset_count(&dev_priv->gpu_error); 1030 1031 args->batch_active = hs->batch_active; 1032 args->batch_pending = hs->batch_pending; 1033 1034 mutex_unlock(&dev->struct_mutex); 1035 1036 return 0; 1037 } 1038 1039 static int i965_reset_complete(struct drm_device *dev) 1040 { 1041 u8 gdrst; 1042 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); 1043 return (gdrst & GRDOM_RESET_ENABLE) == 0; 1044 } 1045 1046 static int i965_do_reset(struct drm_device *dev) 1047 { 1048 int ret; 1049 1050 /* FIXME: i965g/gm need a display save/restore for gpu reset. */ 1051 return -ENODEV; 1052 1053 /* 1054 * Set the domains we want to reset (GRDOM/bits 2 and 3) as 1055 * well as the reset bit (GR/bit 0). Setting the GR bit 1056 * triggers the reset; when done, the hardware will clear it. 1057 */ 1058 pci_write_config_byte(dev->pdev, I965_GDRST, 1059 GRDOM_RENDER | GRDOM_RESET_ENABLE); 1060 ret = wait_for(i965_reset_complete(dev), 500); 1061 if (ret) 1062 return ret; 1063 1064 pci_write_config_byte(dev->pdev, I965_GDRST, 1065 GRDOM_MEDIA | GRDOM_RESET_ENABLE); 1066 1067 ret = wait_for(i965_reset_complete(dev), 500); 1068 if (ret) 1069 return ret; 1070 1071 pci_write_config_byte(dev->pdev, I965_GDRST, 0); 1072 1073 return 0; 1074 } 1075 1076 static int g4x_do_reset(struct drm_device *dev) 1077 { 1078 struct drm_i915_private *dev_priv = dev->dev_private; 1079 int ret; 1080 1081 pci_write_config_byte(dev->pdev, I965_GDRST, 1082 GRDOM_RENDER | GRDOM_RESET_ENABLE); 1083 ret = wait_for(i965_reset_complete(dev), 500); 1084 if (ret) 1085 return ret; 1086 1087 /* WaVcpClkGateDisableForMediaReset:ctg,elk */ 1088 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); 1089 POSTING_READ(VDECCLK_GATE_D); 1090 1091 pci_write_config_byte(dev->pdev, I965_GDRST, 1092 GRDOM_MEDIA | GRDOM_RESET_ENABLE); 1093 ret = wait_for(i965_reset_complete(dev), 500); 1094 if (ret) 1095 return ret; 1096 1097 /* WaVcpClkGateDisableForMediaReset:ctg,elk */ 1098 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); 1099 POSTING_READ(VDECCLK_GATE_D); 1100 1101 pci_write_config_byte(dev->pdev, I965_GDRST, 0); 1102 1103 return 0; 1104 } 1105 1106 static int ironlake_do_reset(struct drm_device *dev) 1107 { 1108 struct drm_i915_private *dev_priv = dev->dev_private; 1109 int ret; 1110 1111 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 1112 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); 1113 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 1114 ILK_GRDOM_RESET_ENABLE) == 0, 500); 1115 if (ret) 1116 return ret; 1117 1118 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 1119 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); 1120 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 1121 ILK_GRDOM_RESET_ENABLE) == 0, 500); 1122 if (ret) 1123 return ret; 1124 1125 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0); 1126 1127 return 0; 1128 } 1129 1130 static int gen6_do_reset(struct drm_device *dev) 1131 { 1132 struct drm_i915_private *dev_priv = dev->dev_private; 1133 int ret; 1134 1135 /* Reset the chip */ 1136 1137 /* GEN6_GDRST is not in the gt power well, no need to check 1138 * for fifo space for the write or forcewake the chip for 1139 * the read 1140 */ 1141 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); 1142 1143 /* Spin waiting for the device to ack the reset request */ 1144 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); 1145 1146 intel_uncore_forcewake_reset(dev, true); 1147 1148 return ret; 1149 } 1150 1151 int intel_gpu_reset(struct drm_device *dev) 1152 { 1153 if (INTEL_INFO(dev)->gen >= 6) 1154 return gen6_do_reset(dev); 1155 else if (IS_GEN5(dev)) 1156 return ironlake_do_reset(dev); 1157 else if (IS_G4X(dev)) 1158 return g4x_do_reset(dev); 1159 else if (IS_GEN4(dev)) 1160 return i965_do_reset(dev); 1161 else 1162 return -ENODEV; 1163 } 1164 1165 void intel_uncore_check_errors(struct drm_device *dev) 1166 { 1167 struct drm_i915_private *dev_priv = dev->dev_private; 1168 1169 if (HAS_FPGA_DBG_UNCLAIMED(dev) && 1170 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { 1171 DRM_ERROR("Unclaimed register before interrupt\n"); 1172 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 1173 } 1174 } 1175