1 /* 2 * Copyright © 2006-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 /* 29 * This information is private to VBT parsing in intel_bios.c. 30 * 31 * Please do NOT include anywhere else. 32 */ 33 #ifndef _INTEL_BIOS_PRIVATE 34 #error "intel_vbt_defs.h is private to intel_bios.c" 35 #endif 36 37 #ifndef _INTEL_VBT_DEFS_H_ 38 #define _INTEL_VBT_DEFS_H_ 39 40 #include "intel_bios.h" 41 42 /** 43 * struct vbt_header - VBT Header structure 44 * @signature: VBT signature, always starts with "$VBT" 45 * @version: Version of this structure 46 * @header_size: Size of this structure 47 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) 48 * @vbt_checksum: Checksum 49 * @reserved0: Reserved 50 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT 51 * @aim_offset: Offsets of add-in data blocks from beginning of VBT 52 */ 53 struct vbt_header { 54 u8 signature[20]; 55 u16 version; 56 u16 header_size; 57 u16 vbt_size; 58 u8 vbt_checksum; 59 u8 reserved0; 60 u32 bdb_offset; 61 u32 aim_offset[4]; 62 } __packed; 63 64 /** 65 * struct bdb_header - BDB Header structure 66 * @signature: BDB signature "BIOS_DATA_BLOCK" 67 * @version: Version of the data block definitions 68 * @header_size: Size of this structure 69 * @bdb_size: Size of BDB (BDB Header and data blocks) 70 */ 71 struct bdb_header { 72 u8 signature[16]; 73 u16 version; 74 u16 header_size; 75 u16 bdb_size; 76 } __packed; 77 78 /* strictly speaking, this is a "skip" block, but it has interesting info */ 79 struct vbios_data { 80 u8 type; /* 0 == desktop, 1 == mobile */ 81 u8 relstage; 82 u8 chipset; 83 u8 lvds_present:1; 84 u8 tv_present:1; 85 u8 rsvd2:6; /* finish byte */ 86 u8 rsvd3[4]; 87 u8 signon[155]; 88 u8 copyright[61]; 89 u16 code_segment; 90 u8 dos_boot_mode; 91 u8 bandwidth_percent; 92 u8 rsvd4; /* popup memory size */ 93 u8 resize_pci_bios; 94 u8 rsvd5; /* is crt already on ddc2 */ 95 } __packed; 96 97 /* 98 * There are several types of BIOS data blocks (BDBs), each block has 99 * an ID and size in the first 3 bytes (ID in first, size in next 2). 100 * Known types are listed below. 101 */ 102 #define BDB_GENERAL_FEATURES 1 103 #define BDB_GENERAL_DEFINITIONS 2 104 #define BDB_OLD_TOGGLE_LIST 3 105 #define BDB_MODE_SUPPORT_LIST 4 106 #define BDB_GENERIC_MODE_TABLE 5 107 #define BDB_EXT_MMIO_REGS 6 108 #define BDB_SWF_IO 7 109 #define BDB_SWF_MMIO 8 110 #define BDB_PSR 9 111 #define BDB_MODE_REMOVAL_TABLE 10 112 #define BDB_CHILD_DEVICE_TABLE 11 113 #define BDB_DRIVER_FEATURES 12 114 #define BDB_DRIVER_PERSISTENCE 13 115 #define BDB_EXT_TABLE_PTRS 14 116 #define BDB_DOT_CLOCK_OVERRIDE 15 117 #define BDB_DISPLAY_SELECT 16 118 /* 17 rsvd */ 119 #define BDB_DRIVER_ROTATION 18 120 #define BDB_DISPLAY_REMOVE 19 121 #define BDB_OEM_CUSTOM 20 122 #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ 123 #define BDB_SDVO_LVDS_OPTIONS 22 124 #define BDB_SDVO_PANEL_DTDS 23 125 #define BDB_SDVO_LVDS_PNP_IDS 24 126 #define BDB_SDVO_LVDS_POWER_SEQ 25 127 #define BDB_TV_OPTIONS 26 128 #define BDB_EDP 27 129 #define BDB_LVDS_OPTIONS 40 130 #define BDB_LVDS_LFP_DATA_PTRS 41 131 #define BDB_LVDS_LFP_DATA 42 132 #define BDB_LVDS_BACKLIGHT 43 133 #define BDB_LVDS_POWER 44 134 #define BDB_MIPI_CONFIG 52 135 #define BDB_MIPI_SEQUENCE 53 136 #define BDB_SKIP 254 /* VBIOS private block, ignore */ 137 138 struct bdb_general_features { 139 /* bits 1 */ 140 u8 panel_fitting:2; 141 u8 flexaim:1; 142 u8 msg_enable:1; 143 u8 clear_screen:3; 144 u8 color_flip:1; 145 146 /* bits 2 */ 147 u8 download_ext_vbt:1; 148 u8 enable_ssc:1; 149 u8 ssc_freq:1; 150 u8 enable_lfp_on_override:1; 151 u8 disable_ssc_ddt:1; 152 u8 rsvd7:1; 153 u8 display_clock_mode:1; 154 u8 rsvd8:1; /* finish byte */ 155 156 /* bits 3 */ 157 u8 disable_smooth_vision:1; 158 u8 single_dvi:1; 159 u8 rsvd9:1; 160 u8 fdi_rx_polarity_inverted:1; 161 u8 rsvd10:4; /* finish byte */ 162 163 /* bits 4 */ 164 u8 legacy_monitor_detect; 165 166 /* bits 5 */ 167 u8 int_crt_support:1; 168 u8 int_tv_support:1; 169 u8 int_efp_support:1; 170 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ 171 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 172 u8 rsvd11:3; /* finish byte */ 173 } __packed; 174 175 /* pre-915 */ 176 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 177 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 178 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 179 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 180 181 /* Pre 915 */ 182 #define DEVICE_TYPE_NONE 0x00 183 #define DEVICE_TYPE_CRT 0x01 184 #define DEVICE_TYPE_TV 0x09 185 #define DEVICE_TYPE_EFP 0x12 186 #define DEVICE_TYPE_LFP 0x22 187 /* On 915+ */ 188 #define DEVICE_TYPE_CRT_DPMS 0x6001 189 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 190 #define DEVICE_TYPE_TV_COMPOSITE 0x0209 191 #define DEVICE_TYPE_TV_MACROVISION 0x0289 192 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 193 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 194 #define DEVICE_TYPE_TV_SCART 0x0209 195 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 196 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 197 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 198 #define DEVICE_TYPE_EFP_DVI_I 0x6053 199 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 200 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 201 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 202 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 203 #define DEVICE_TYPE_LFP_PANELLINK 0x5012 204 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 205 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 206 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 207 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 208 209 #define DEVICE_CFG_NONE 0x00 210 #define DEVICE_CFG_12BIT_DVOB 0x01 211 #define DEVICE_CFG_12BIT_DVOC 0x02 212 #define DEVICE_CFG_24BIT_DVOBC 0x09 213 #define DEVICE_CFG_24BIT_DVOCB 0x0a 214 #define DEVICE_CFG_DUAL_DVOB 0x11 215 #define DEVICE_CFG_DUAL_DVOC 0x12 216 #define DEVICE_CFG_DUAL_DVOBC 0x13 217 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 218 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 219 220 #define DEVICE_WIRE_NONE 0x00 221 #define DEVICE_WIRE_DVOB 0x01 222 #define DEVICE_WIRE_DVOC 0x02 223 #define DEVICE_WIRE_DVOBC 0x03 224 #define DEVICE_WIRE_DVOBB 0x05 225 #define DEVICE_WIRE_DVOCC 0x06 226 #define DEVICE_WIRE_DVOB_MASTER 0x0d 227 #define DEVICE_WIRE_DVOC_MASTER 0x0e 228 229 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 230 #define DEVICE_PORT_DVOB 0x01 231 #define DEVICE_PORT_DVOC 0x02 232 233 /* 234 * We used to keep this struct but without any version control. We should avoid 235 * using it in the future, but it should be safe to keep using it in the old 236 * code. Do not change; we rely on its size. 237 */ 238 struct old_child_dev_config { 239 u16 handle; 240 u16 device_type; 241 u8 device_id[10]; /* ascii string */ 242 u16 addin_offset; 243 u8 dvo_port; /* See Device_PORT_* above */ 244 u8 i2c_pin; 245 u8 slave_addr; 246 u8 ddc_pin; 247 u16 edid_ptr; 248 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 249 u8 dvo2_port; 250 u8 i2c2_pin; 251 u8 slave2_addr; 252 u8 ddc2_pin; 253 u8 capabilities; 254 u8 dvo_wiring;/* See DEVICE_WIRE_* above */ 255 u8 dvo2_wiring; 256 u16 extended_type; 257 u8 dvo_function; 258 } __packed; 259 260 /* This one contains field offsets that are known to be common for all BDB 261 * versions. Notice that the meaning of the contents contents may still change, 262 * but at least the offsets are consistent. */ 263 264 struct common_child_dev_config { 265 u16 handle; 266 u16 device_type; 267 u8 not_common1[12]; 268 u8 dvo_port; 269 u8 not_common2[2]; 270 u8 ddc_pin; 271 u16 edid_ptr; 272 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 273 u8 efp_routed:1; 274 u8 lane_reversal:1; 275 u8 lspcon:1; 276 u8 iboost:1; 277 u8 hpd_invert:1; 278 u8 flag_reserved:3; 279 u8 hdmi_support:1; 280 u8 dp_support:1; 281 u8 tmds_support:1; 282 u8 support_reserved:5; 283 u8 aux_channel; 284 u8 not_common3[11]; 285 u8 iboost_level; 286 } __packed; 287 288 289 /* This field changes depending on the BDB version, so the most reliable way to 290 * read it is by checking the BDB version and reading the raw pointer. */ 291 union child_device_config { 292 /* This one is safe to be used anywhere, but the code should still check 293 * the BDB version. */ 294 u8 raw[33]; 295 /* This one should only be kept for legacy code. */ 296 struct old_child_dev_config old; 297 /* This one should also be safe to use anywhere, even without version 298 * checks. */ 299 struct common_child_dev_config common; 300 } __packed; 301 302 struct bdb_general_definitions { 303 /* DDC GPIO */ 304 u8 crt_ddc_gmbus_pin; 305 306 /* DPMS bits */ 307 u8 dpms_acpi:1; 308 u8 skip_boot_crt_detect:1; 309 u8 dpms_aim:1; 310 u8 rsvd1:5; /* finish byte */ 311 312 /* boot device bits */ 313 u8 boot_display[2]; 314 u8 child_dev_size; 315 316 /* 317 * Device info: 318 * If TV is present, it'll be at devices[0]. 319 * LVDS will be next, either devices[0] or [1], if present. 320 * On some platforms the number of device is 6. But could be as few as 321 * 4 if both TV and LVDS are missing. 322 * And the device num is related with the size of general definition 323 * block. It is obtained by using the following formula: 324 * number = (block_size - sizeof(bdb_general_definitions))/ 325 * defs->child_dev_size; 326 */ 327 uint8_t devices[0]; 328 } __packed; 329 330 /* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ 331 #define MODE_MASK 0x3 332 333 struct bdb_lvds_options { 334 u8 panel_type; 335 u8 rsvd1; 336 /* LVDS capabilities, stored in a dword */ 337 u8 pfit_mode:2; 338 u8 pfit_text_mode_enhanced:1; 339 u8 pfit_gfx_mode_enhanced:1; 340 u8 pfit_ratio_auto:1; 341 u8 pixel_dither:1; 342 u8 lvds_edid:1; 343 u8 rsvd2:1; 344 u8 rsvd4; 345 /* LVDS Panel channel bits stored here */ 346 u32 lvds_panel_channel_bits; 347 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ 348 u16 ssc_bits; 349 u16 ssc_freq; 350 u16 ssc_ddt; 351 /* Panel color depth defined here */ 352 u16 panel_color_depth; 353 /* LVDS panel type bits stored here */ 354 u32 dps_panel_type_bits; 355 /* LVDS backlight control type bits stored here */ 356 u32 blt_control_type_bits; 357 } __packed; 358 359 /* LFP pointer table contains entries to the struct below */ 360 struct bdb_lvds_lfp_data_ptr { 361 u16 fp_timing_offset; /* offsets are from start of bdb */ 362 u8 fp_table_size; 363 u16 dvo_timing_offset; 364 u8 dvo_table_size; 365 u16 panel_pnp_id_offset; 366 u8 pnp_table_size; 367 } __packed; 368 369 struct bdb_lvds_lfp_data_ptrs { 370 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ 371 struct bdb_lvds_lfp_data_ptr ptr[16]; 372 } __packed; 373 374 /* LFP data has 3 blocks per entry */ 375 struct lvds_fp_timing { 376 u16 x_res; 377 u16 y_res; 378 u32 lvds_reg; 379 u32 lvds_reg_val; 380 u32 pp_on_reg; 381 u32 pp_on_reg_val; 382 u32 pp_off_reg; 383 u32 pp_off_reg_val; 384 u32 pp_cycle_reg; 385 u32 pp_cycle_reg_val; 386 u32 pfit_reg; 387 u32 pfit_reg_val; 388 u16 terminator; 389 } __packed; 390 391 struct lvds_dvo_timing { 392 u16 clock; /**< In 10khz */ 393 u8 hactive_lo; 394 u8 hblank_lo; 395 u8 hblank_hi:4; 396 u8 hactive_hi:4; 397 u8 vactive_lo; 398 u8 vblank_lo; 399 u8 vblank_hi:4; 400 u8 vactive_hi:4; 401 u8 hsync_off_lo; 402 u8 hsync_pulse_width_lo; 403 u8 vsync_pulse_width_lo:4; 404 u8 vsync_off_lo:4; 405 u8 vsync_pulse_width_hi:2; 406 u8 vsync_off_hi:2; 407 u8 hsync_pulse_width_hi:2; 408 u8 hsync_off_hi:2; 409 u8 himage_lo; 410 u8 vimage_lo; 411 u8 vimage_hi:4; 412 u8 himage_hi:4; 413 u8 h_border; 414 u8 v_border; 415 u8 rsvd1:3; 416 u8 digital:2; 417 u8 vsync_positive:1; 418 u8 hsync_positive:1; 419 u8 non_interlaced:1; 420 } __packed; 421 422 struct lvds_pnp_id { 423 u16 mfg_name; 424 u16 product_code; 425 u32 serial; 426 u8 mfg_week; 427 u8 mfg_year; 428 } __packed; 429 430 struct bdb_lvds_lfp_data_entry { 431 struct lvds_fp_timing fp_timing; 432 struct lvds_dvo_timing dvo_timing; 433 struct lvds_pnp_id pnp_id; 434 } __packed; 435 436 struct bdb_lvds_lfp_data { 437 struct bdb_lvds_lfp_data_entry data[16]; 438 } __packed; 439 440 #define BDB_BACKLIGHT_TYPE_NONE 0 441 #define BDB_BACKLIGHT_TYPE_PWM 2 442 443 struct bdb_lfp_backlight_data_entry { 444 u8 type:2; 445 u8 active_low_pwm:1; 446 u8 obsolete1:5; 447 u16 pwm_freq_hz; 448 u8 min_brightness; 449 u8 obsolete2; 450 u8 obsolete3; 451 } __packed; 452 453 struct bdb_lfp_backlight_control_method { 454 u8 type:4; 455 u8 controller:4; 456 } __packed; 457 458 struct bdb_lfp_backlight_data { 459 u8 entry_size; 460 struct bdb_lfp_backlight_data_entry data[16]; 461 u8 level[16]; 462 struct bdb_lfp_backlight_control_method backlight_control[16]; 463 } __packed; 464 465 struct aimdb_header { 466 char signature[16]; 467 char oem_device[20]; 468 u16 aimdb_version; 469 u16 aimdb_header_size; 470 u16 aimdb_size; 471 } __packed; 472 473 struct aimdb_block { 474 u8 aimdb_id; 475 u16 aimdb_size; 476 } __packed; 477 478 struct vch_panel_data { 479 u16 fp_timing_offset; 480 u8 fp_timing_size; 481 u16 dvo_timing_offset; 482 u8 dvo_timing_size; 483 u16 text_fitting_offset; 484 u8 text_fitting_size; 485 u16 graphics_fitting_offset; 486 u8 graphics_fitting_size; 487 } __packed; 488 489 struct vch_bdb_22 { 490 struct aimdb_block aimdb_block; 491 struct vch_panel_data panels[16]; 492 } __packed; 493 494 struct bdb_sdvo_lvds_options { 495 u8 panel_backlight; 496 u8 h40_set_panel_type; 497 u8 panel_type; 498 u8 ssc_clk_freq; 499 u16 als_low_trip; 500 u16 als_high_trip; 501 u8 sclalarcoeff_tab_row_num; 502 u8 sclalarcoeff_tab_row_size; 503 u8 coefficient[8]; 504 u8 panel_misc_bits_1; 505 u8 panel_misc_bits_2; 506 u8 panel_misc_bits_3; 507 u8 panel_misc_bits_4; 508 } __packed; 509 510 511 #define BDB_DRIVER_FEATURE_NO_LVDS 0 512 #define BDB_DRIVER_FEATURE_INT_LVDS 1 513 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 514 #define BDB_DRIVER_FEATURE_EDP 3 515 516 struct bdb_driver_features { 517 u8 boot_dev_algorithm:1; 518 u8 block_display_switch:1; 519 u8 allow_display_switch:1; 520 u8 hotplug_dvo:1; 521 u8 dual_view_zoom:1; 522 u8 int15h_hook:1; 523 u8 sprite_in_clone:1; 524 u8 primary_lfp_id:1; 525 526 u16 boot_mode_x; 527 u16 boot_mode_y; 528 u8 boot_mode_bpp; 529 u8 boot_mode_refresh; 530 531 u16 enable_lfp_primary:1; 532 u16 selective_mode_pruning:1; 533 u16 dual_frequency:1; 534 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 535 u16 nt_clone_support:1; 536 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 537 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 538 u16 cui_aspect_scaling:1; 539 u16 preserve_aspect_ratio:1; 540 u16 sdvo_device_power_down:1; 541 u16 crt_hotplug:1; 542 u16 lvds_config:2; 543 u16 tv_hotplug:1; 544 u16 hdmi_config:2; 545 546 u8 static_display:1; 547 u8 reserved2:7; 548 u16 legacy_crt_max_x; 549 u16 legacy_crt_max_y; 550 u8 legacy_crt_max_refresh; 551 552 u8 hdmi_termination; 553 u8 custom_vbt_version; 554 /* Driver features data block */ 555 u16 rmpm_enabled:1; 556 u16 s2ddt_enabled:1; 557 u16 dpst_enabled:1; 558 u16 bltclt_enabled:1; 559 u16 adb_enabled:1; 560 u16 drrs_enabled:1; 561 u16 grs_enabled:1; 562 u16 gpmt_enabled:1; 563 u16 tbt_enabled:1; 564 u16 psr_enabled:1; 565 u16 ips_enabled:1; 566 u16 reserved3:4; 567 u16 pc_feature_valid:1; 568 } __packed; 569 570 #define EDP_18BPP 0 571 #define EDP_24BPP 1 572 #define EDP_30BPP 2 573 #define EDP_RATE_1_62 0 574 #define EDP_RATE_2_7 1 575 #define EDP_LANE_1 0 576 #define EDP_LANE_2 1 577 #define EDP_LANE_4 3 578 #define EDP_PREEMPHASIS_NONE 0 579 #define EDP_PREEMPHASIS_3_5dB 1 580 #define EDP_PREEMPHASIS_6dB 2 581 #define EDP_PREEMPHASIS_9_5dB 3 582 #define EDP_VSWING_0_4V 0 583 #define EDP_VSWING_0_6V 1 584 #define EDP_VSWING_0_8V 2 585 #define EDP_VSWING_1_2V 3 586 587 588 struct edp_link_params { 589 u8 rate:4; 590 u8 lanes:4; 591 u8 preemphasis:4; 592 u8 vswing:4; 593 } __packed; 594 595 struct bdb_edp { 596 struct edp_power_seq power_seqs[16]; 597 u32 color_depth; 598 struct edp_link_params link_params[16]; 599 u32 sdrrs_msa_timing_delay; 600 601 /* ith bit indicates enabled/disabled for (i+1)th panel */ 602 u16 edp_s3d_feature; 603 u16 edp_t3_optimization; 604 u64 edp_vswing_preemph; /* v173 */ 605 } __packed; 606 607 struct psr_table { 608 /* Feature bits */ 609 u8 full_link:1; 610 u8 require_aux_to_wakeup:1; 611 u8 feature_bits_rsvd:6; 612 613 /* Wait times */ 614 u8 idle_frames:4; 615 u8 lines_to_wait:3; 616 u8 wait_times_rsvd:1; 617 618 /* TP wake up time in multiple of 100 */ 619 u16 tp1_wakeup_time; 620 u16 tp2_tp3_wakeup_time; 621 } __packed; 622 623 struct bdb_psr { 624 struct psr_table psr_table[16]; 625 } __packed; 626 627 /* 628 * Driver<->VBIOS interaction occurs through scratch bits in 629 * GR18 & SWF*. 630 */ 631 632 /* GR18 bits are set on display switch and hotkey events */ 633 #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ 634 #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ 635 #define GR18_HK_NONE (0x0<<3) 636 #define GR18_HK_LFP_STRETCH (0x1<<3) 637 #define GR18_HK_TOGGLE_DISP (0x2<<3) 638 #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ 639 #define GR18_HK_POPUP_DISABLED (0x6<<3) 640 #define GR18_HK_POPUP_ENABLED (0x7<<3) 641 #define GR18_HK_PFIT (0x8<<3) 642 #define GR18_HK_APM_CHANGE (0xa<<3) 643 #define GR18_HK_MULTIPLE (0xc<<3) 644 #define GR18_USER_INT_EN (1<<2) 645 #define GR18_A0000_FLUSH_EN (1<<1) 646 #define GR18_SMM_EN (1<<0) 647 648 /* Set by driver, cleared by VBIOS */ 649 #define SWF00_YRES_SHIFT 16 650 #define SWF00_XRES_SHIFT 0 651 #define SWF00_RES_MASK 0xffff 652 653 /* Set by VBIOS at boot time and driver at runtime */ 654 #define SWF01_TV2_FORMAT_SHIFT 8 655 #define SWF01_TV1_FORMAT_SHIFT 0 656 #define SWF01_TV_FORMAT_MASK 0xffff 657 658 #define SWF10_VBIOS_BLC_I2C_EN (1<<29) 659 #define SWF10_GTT_OVERRIDE_EN (1<<28) 660 #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ 661 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) 662 #define SWF10_OLD_TOGGLE 0x0 663 #define SWF10_TOGGLE_LIST_1 0x1 664 #define SWF10_TOGGLE_LIST_2 0x2 665 #define SWF10_TOGGLE_LIST_3 0x3 666 #define SWF10_TOGGLE_LIST_4 0x4 667 #define SWF10_PANNING_EN (1<<23) 668 #define SWF10_DRIVER_LOADED (1<<22) 669 #define SWF10_EXTENDED_DESKTOP (1<<21) 670 #define SWF10_EXCLUSIVE_MODE (1<<20) 671 #define SWF10_OVERLAY_EN (1<<19) 672 #define SWF10_PLANEB_HOLDOFF (1<<18) 673 #define SWF10_PLANEA_HOLDOFF (1<<17) 674 #define SWF10_VGA_HOLDOFF (1<<16) 675 #define SWF10_ACTIVE_DISP_MASK 0xffff 676 #define SWF10_PIPEB_LFP2 (1<<15) 677 #define SWF10_PIPEB_EFP2 (1<<14) 678 #define SWF10_PIPEB_TV2 (1<<13) 679 #define SWF10_PIPEB_CRT2 (1<<12) 680 #define SWF10_PIPEB_LFP (1<<11) 681 #define SWF10_PIPEB_EFP (1<<10) 682 #define SWF10_PIPEB_TV (1<<9) 683 #define SWF10_PIPEB_CRT (1<<8) 684 #define SWF10_PIPEA_LFP2 (1<<7) 685 #define SWF10_PIPEA_EFP2 (1<<6) 686 #define SWF10_PIPEA_TV2 (1<<5) 687 #define SWF10_PIPEA_CRT2 (1<<4) 688 #define SWF10_PIPEA_LFP (1<<3) 689 #define SWF10_PIPEA_EFP (1<<2) 690 #define SWF10_PIPEA_TV (1<<1) 691 #define SWF10_PIPEA_CRT (1<<0) 692 693 #define SWF11_MEMORY_SIZE_SHIFT 16 694 #define SWF11_SV_TEST_EN (1<<15) 695 #define SWF11_IS_AGP (1<<14) 696 #define SWF11_DISPLAY_HOLDOFF (1<<13) 697 #define SWF11_DPMS_REDUCED (1<<12) 698 #define SWF11_IS_VBE_MODE (1<<11) 699 #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ 700 #define SWF11_DPMS_MASK 0x07 701 #define SWF11_DPMS_OFF (1<<2) 702 #define SWF11_DPMS_SUSPEND (1<<1) 703 #define SWF11_DPMS_STANDBY (1<<0) 704 #define SWF11_DPMS_ON 0 705 706 #define SWF14_GFX_PFIT_EN (1<<31) 707 #define SWF14_TEXT_PFIT_EN (1<<30) 708 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ 709 #define SWF14_POPUP_EN (1<<28) 710 #define SWF14_DISPLAY_HOLDOFF (1<<27) 711 #define SWF14_DISP_DETECT_EN (1<<26) 712 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ 713 #define SWF14_DRIVER_STATUS (1<<24) 714 #define SWF14_OS_TYPE_WIN9X (1<<23) 715 #define SWF14_OS_TYPE_WINNT (1<<22) 716 /* 21:19 rsvd */ 717 #define SWF14_PM_TYPE_MASK 0x00070000 718 #define SWF14_PM_ACPI_VIDEO (0x4 << 16) 719 #define SWF14_PM_ACPI (0x3 << 16) 720 #define SWF14_PM_APM_12 (0x2 << 16) 721 #define SWF14_PM_APM_11 (0x1 << 16) 722 #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ 723 /* if GR18 indicates a display switch */ 724 #define SWF14_DS_PIPEB_LFP2_EN (1<<15) 725 #define SWF14_DS_PIPEB_EFP2_EN (1<<14) 726 #define SWF14_DS_PIPEB_TV2_EN (1<<13) 727 #define SWF14_DS_PIPEB_CRT2_EN (1<<12) 728 #define SWF14_DS_PIPEB_LFP_EN (1<<11) 729 #define SWF14_DS_PIPEB_EFP_EN (1<<10) 730 #define SWF14_DS_PIPEB_TV_EN (1<<9) 731 #define SWF14_DS_PIPEB_CRT_EN (1<<8) 732 #define SWF14_DS_PIPEA_LFP2_EN (1<<7) 733 #define SWF14_DS_PIPEA_EFP2_EN (1<<6) 734 #define SWF14_DS_PIPEA_TV2_EN (1<<5) 735 #define SWF14_DS_PIPEA_CRT2_EN (1<<4) 736 #define SWF14_DS_PIPEA_LFP_EN (1<<3) 737 #define SWF14_DS_PIPEA_EFP_EN (1<<2) 738 #define SWF14_DS_PIPEA_TV_EN (1<<1) 739 #define SWF14_DS_PIPEA_CRT_EN (1<<0) 740 /* if GR18 indicates a panel fitting request */ 741 #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ 742 /* if GR18 indicates an APM change request */ 743 #define SWF14_APM_HIBERNATE 0x4 744 #define SWF14_APM_SUSPEND 0x3 745 #define SWF14_APM_STANDBY 0x1 746 #define SWF14_APM_RESTORE 0x0 747 748 /* Add the device class for LFP, TV, HDMI */ 749 #define DEVICE_TYPE_INT_LFP 0x1022 750 #define DEVICE_TYPE_INT_TV 0x1009 751 #define DEVICE_TYPE_HDMI 0x60D2 752 #define DEVICE_TYPE_DP 0x68C6 753 #define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 754 #define DEVICE_TYPE_eDP 0x78C6 755 756 #define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 757 #define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 758 #define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 759 #define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 760 #define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 761 #define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 762 #define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 763 #define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 764 #define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 765 #define DEVICE_TYPE_LVDS_SINGALING (1 << 5) 766 #define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 767 #define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 768 #define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 769 #define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 770 #define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 771 772 /* 773 * Bits we care about when checking for DEVICE_TYPE_eDP 774 * Depending on the system, the other bits may or may not 775 * be set for eDP outputs. 776 */ 777 #define DEVICE_TYPE_eDP_BITS \ 778 (DEVICE_TYPE_INTERNAL_CONNECTOR | \ 779 DEVICE_TYPE_MIPI_OUTPUT | \ 780 DEVICE_TYPE_COMPOSITE_OUTPUT | \ 781 DEVICE_TYPE_DUAL_CHANNEL | \ 782 DEVICE_TYPE_LVDS_SINGALING | \ 783 DEVICE_TYPE_TMDS_DVI_SIGNALING | \ 784 DEVICE_TYPE_VIDEO_SIGNALING | \ 785 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ 786 DEVICE_TYPE_ANALOG_OUTPUT) 787 788 #define DEVICE_TYPE_DP_DUAL_MODE_BITS \ 789 (DEVICE_TYPE_INTERNAL_CONNECTOR | \ 790 DEVICE_TYPE_MIPI_OUTPUT | \ 791 DEVICE_TYPE_COMPOSITE_OUTPUT | \ 792 DEVICE_TYPE_LVDS_SINGALING | \ 793 DEVICE_TYPE_TMDS_DVI_SIGNALING | \ 794 DEVICE_TYPE_VIDEO_SIGNALING | \ 795 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ 796 DEVICE_TYPE_DIGITAL_OUTPUT | \ 797 DEVICE_TYPE_ANALOG_OUTPUT) 798 799 /* define the DVO port for HDMI output type */ 800 #define DVO_B 1 801 #define DVO_C 2 802 #define DVO_D 3 803 804 /* Possible values for the "DVO Port" field for versions >= 155: */ 805 #define DVO_PORT_HDMIA 0 806 #define DVO_PORT_HDMIB 1 807 #define DVO_PORT_HDMIC 2 808 #define DVO_PORT_HDMID 3 809 #define DVO_PORT_LVDS 4 810 #define DVO_PORT_TV 5 811 #define DVO_PORT_CRT 6 812 #define DVO_PORT_DPB 7 813 #define DVO_PORT_DPC 8 814 #define DVO_PORT_DPD 9 815 #define DVO_PORT_DPA 10 816 #define DVO_PORT_DPE 11 817 #define DVO_PORT_HDMIE 12 818 #define DVO_PORT_MIPIA 21 819 #define DVO_PORT_MIPIB 22 820 #define DVO_PORT_MIPIC 23 821 #define DVO_PORT_MIPID 24 822 823 /* Block 52 contains MIPI configuration block 824 * 6 * bdb_mipi_config, followed by 6 pps data block 825 * block below 826 */ 827 #define MAX_MIPI_CONFIGURATIONS 6 828 829 struct bdb_mipi_config { 830 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; 831 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; 832 } __packed; 833 834 /* Block 53 contains MIPI sequences as needed by the panel 835 * for enabling it. This block can be variable in size and 836 * can be maximum of 6 blocks 837 */ 838 struct bdb_mipi_sequence { 839 u8 version; 840 u8 data[0]; 841 } __packed; 842 843 enum mipi_gpio_pin_index { 844 MIPI_GPIO_UNDEFINED = 0, 845 MIPI_GPIO_PANEL_ENABLE, 846 MIPI_GPIO_BL_ENABLE, 847 MIPI_GPIO_PWM_ENABLE, 848 MIPI_GPIO_RESET_N, 849 MIPI_GPIO_PWR_DOWN_R, 850 MIPI_GPIO_STDBY_RST_N, 851 MIPI_GPIO_MAX 852 }; 853 854 #endif /* _INTEL_VBT_DEFS_H_ */ 855