1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/types.h> 27 #include <linux/i2c.h> 28 #include <linux/delay.h> 29 30 /* 31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 32 * DP and DPCD versions are independent. Differences from 1.0 are not noted, 33 * 1.0 devices basically don't exist in the wild. 34 * 35 * Abbreviations, in chronological order: 36 * 37 * eDP: Embedded DisplayPort version 1 38 * DPI: DisplayPort Interoperability Guideline v1.1a 39 * 1.2: DisplayPort 1.2 40 * MST: Multistream Transport - part of DP 1.2a 41 * 42 * 1.2 formally includes both eDP and DPI definitions. 43 */ 44 45 #define DP_AUX_MAX_PAYLOAD_BYTES 16 46 47 #define DP_AUX_I2C_WRITE 0x0 48 #define DP_AUX_I2C_READ 0x1 49 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 50 #define DP_AUX_I2C_MOT 0x4 51 #define DP_AUX_NATIVE_WRITE 0x8 52 #define DP_AUX_NATIVE_READ 0x9 53 54 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 55 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 56 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 57 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 58 59 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 60 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 61 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 62 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 63 64 /* AUX CH addresses */ 65 /* DPCD */ 66 #define DP_DPCD_REV 0x000 67 68 #define DP_MAX_LINK_RATE 0x001 69 70 #define DP_MAX_LANE_COUNT 0x002 71 # define DP_MAX_LANE_COUNT_MASK 0x1f 72 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 73 # define DP_ENHANCED_FRAME_CAP (1 << 7) 74 75 #define DP_MAX_DOWNSPREAD 0x003 76 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0) 77 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 78 79 #define DP_NORP 0x004 80 81 #define DP_DOWNSTREAMPORT_PRESENT 0x005 82 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 83 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 84 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) 85 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) 86 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) 87 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) 88 # define DP_FORMAT_CONVERSION (1 << 3) 89 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 90 91 #define DP_MAIN_LINK_CHANNEL_CODING 0x006 92 93 #define DP_DOWN_STREAM_PORT_COUNT 0x007 94 # define DP_PORT_COUNT_MASK 0x0f 95 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 96 # define DP_OUI_SUPPORT (1 << 7) 97 98 #define DP_RECEIVE_PORT_0_CAP_0 0x008 99 # define DP_LOCAL_EDID_PRESENT (1 << 1) 100 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) 101 102 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 103 104 #define DP_RECEIVE_PORT_1_CAP_0 0x00a 105 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b 106 107 #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 108 # define DP_I2C_SPEED_1K 0x01 109 # define DP_I2C_SPEED_5K 0x02 110 # define DP_I2C_SPEED_10K 0x04 111 # define DP_I2C_SPEED_100K 0x08 112 # define DP_I2C_SPEED_400K 0x10 113 # define DP_I2C_SPEED_1M 0x20 114 115 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 116 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) 117 # define DP_FRAMING_CHANGE_CAP (1 << 1) 118 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ 119 120 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 121 122 #define DP_ADAPTER_CAP 0x00f /* 1.2 */ 123 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) 124 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) 125 126 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ 127 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ 128 129 /* Multiple stream transport */ 130 #define DP_FAUX_CAP 0x020 /* 1.2 */ 131 # define DP_FAUX_CAP_1 (1 << 0) 132 133 #define DP_MSTM_CAP 0x021 /* 1.2 */ 134 # define DP_MST_CAP (1 << 0) 135 136 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ 137 138 /* AV_SYNC_DATA_BLOCK 1.2 */ 139 #define DP_AV_GRANULARITY 0x023 140 # define DP_AG_FACTOR_MASK (0xf << 0) 141 # define DP_AG_FACTOR_3MS (0 << 0) 142 # define DP_AG_FACTOR_2MS (1 << 0) 143 # define DP_AG_FACTOR_1MS (2 << 0) 144 # define DP_AG_FACTOR_500US (3 << 0) 145 # define DP_AG_FACTOR_200US (4 << 0) 146 # define DP_AG_FACTOR_100US (5 << 0) 147 # define DP_AG_FACTOR_10US (6 << 0) 148 # define DP_AG_FACTOR_1US (7 << 0) 149 # define DP_VG_FACTOR_MASK (0xf << 4) 150 # define DP_VG_FACTOR_3MS (0 << 4) 151 # define DP_VG_FACTOR_2MS (1 << 4) 152 # define DP_VG_FACTOR_1MS (2 << 4) 153 # define DP_VG_FACTOR_500US (3 << 4) 154 # define DP_VG_FACTOR_200US (4 << 4) 155 # define DP_VG_FACTOR_100US (5 << 4) 156 157 #define DP_AUD_DEC_LAT0 0x024 158 #define DP_AUD_DEC_LAT1 0x025 159 160 #define DP_AUD_PP_LAT0 0x026 161 #define DP_AUD_PP_LAT1 0x027 162 163 #define DP_VID_INTER_LAT 0x028 164 165 #define DP_VID_PROG_LAT 0x029 166 167 #define DP_REP_LAT 0x02a 168 169 #define DP_AUD_DEL_INS0 0x02b 170 #define DP_AUD_DEL_INS1 0x02c 171 #define DP_AUD_DEL_INS2 0x02d 172 /* End of AV_SYNC_DATA_BLOCK */ 173 174 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ 175 # define DP_ALPM_CAP (1 << 0) 176 177 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ 178 # define DP_AUX_FRAME_SYNC_CAP (1 << 0) 179 180 #define DP_GUID 0x030 /* 1.2 */ 181 182 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 183 # define DP_PSR_IS_SUPPORTED 1 184 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ 185 186 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 187 # define DP_PSR_NO_TRAIN_ON_EXIT 1 188 # define DP_PSR_SETUP_TIME_330 (0 << 1) 189 # define DP_PSR_SETUP_TIME_275 (1 << 1) 190 # define DP_PSR_SETUP_TIME_220 (2 << 1) 191 # define DP_PSR_SETUP_TIME_165 (3 << 1) 192 # define DP_PSR_SETUP_TIME_110 (4 << 1) 193 # define DP_PSR_SETUP_TIME_55 (5 << 1) 194 # define DP_PSR_SETUP_TIME_0 (6 << 1) 195 # define DP_PSR_SETUP_TIME_MASK (7 << 1) 196 # define DP_PSR_SETUP_TIME_SHIFT 1 197 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ 198 # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ 199 /* 200 * 0x80-0x8f describe downstream port capabilities, but there are two layouts 201 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 202 * each port's descriptor is one byte wide. If it was set, each port's is 203 * four bytes wide, starting with the one byte from the base info. As of 204 * DP interop v1.1a only VGA defines additional detail. 205 */ 206 207 /* offset 0 */ 208 #define DP_DOWNSTREAM_PORT_0 0x80 209 # define DP_DS_PORT_TYPE_MASK (7 << 0) 210 # define DP_DS_PORT_TYPE_DP 0 211 # define DP_DS_PORT_TYPE_VGA 1 212 # define DP_DS_PORT_TYPE_DVI 2 213 # define DP_DS_PORT_TYPE_HDMI 3 214 # define DP_DS_PORT_TYPE_NON_EDID 4 215 # define DP_DS_PORT_TYPE_DP_DUALMODE 5 216 # define DP_DS_PORT_TYPE_WIRELESS 6 217 # define DP_DS_PORT_HPD (1 << 3) 218 /* offset 1 for VGA is maximum megapixels per second / 8 */ 219 /* offset 2 */ 220 # define DP_DS_MAX_BPC_MASK (3 << 0) 221 # define DP_DS_8BPC 0 222 # define DP_DS_10BPC 1 223 # define DP_DS_12BPC 2 224 # define DP_DS_16BPC 3 225 226 /* link configuration */ 227 #define DP_LINK_BW_SET 0x100 228 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ 229 # define DP_LINK_BW_1_62 0x06 230 # define DP_LINK_BW_2_7 0x0a 231 # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 232 233 #define DP_LANE_COUNT_SET 0x101 234 # define DP_LANE_COUNT_MASK 0x0f 235 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 236 237 #define DP_TRAINING_PATTERN_SET 0x102 238 # define DP_TRAINING_PATTERN_DISABLE 0 239 # define DP_TRAINING_PATTERN_1 1 240 # define DP_TRAINING_PATTERN_2 2 241 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 242 # define DP_TRAINING_PATTERN_MASK 0x3 243 244 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ 245 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) 246 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) 247 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) 248 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) 249 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) 250 251 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 252 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 253 254 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 255 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 256 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 257 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 258 259 #define DP_TRAINING_LANE0_SET 0x103 260 #define DP_TRAINING_LANE1_SET 0x104 261 #define DP_TRAINING_LANE2_SET 0x105 262 #define DP_TRAINING_LANE3_SET 0x106 263 264 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 265 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 266 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 267 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) 268 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) 269 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) 270 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) 271 272 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 273 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) 274 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) 275 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) 276 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) 277 278 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 279 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 280 281 #define DP_DOWNSPREAD_CTRL 0x107 282 # define DP_SPREAD_AMP_0_5 (1 << 4) 283 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 284 285 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 286 # define DP_SET_ANSI_8B10B (1 << 0) 287 288 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 289 /* bitmask as for DP_I2C_SPEED_CAP */ 290 291 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 292 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) 293 # define DP_FRAMING_CHANGE_ENABLE (1 << 1) 294 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) 295 296 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ 297 #define DP_LINK_QUAL_LANE1_SET 0x10c 298 #define DP_LINK_QUAL_LANE2_SET 0x10d 299 #define DP_LINK_QUAL_LANE3_SET 0x10e 300 # define DP_LINK_QUAL_PATTERN_DISABLE 0 301 # define DP_LINK_QUAL_PATTERN_D10_2 1 302 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 303 # define DP_LINK_QUAL_PATTERN_PRBS7 3 304 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 305 # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 306 # define DP_LINK_QUAL_PATTERN_MASK 7 307 308 #define DP_TRAINING_LANE0_1_SET2 0x10f 309 #define DP_TRAINING_LANE2_3_SET2 0x110 310 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) 311 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) 312 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) 313 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) 314 315 #define DP_MSTM_CTRL 0x111 /* 1.2 */ 316 # define DP_MST_EN (1 << 0) 317 # define DP_UP_REQ_EN (1 << 1) 318 # define DP_UPSTREAM_IS_SRC (1 << 2) 319 320 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ 321 #define DP_AUDIO_DELAY1 0x113 322 #define DP_AUDIO_DELAY2 0x114 323 324 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ 325 # define DP_LINK_RATE_SET_SHIFT 0 326 # define DP_LINK_RATE_SET_MASK (7 << 0) 327 328 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ 329 # define DP_ALPM_ENABLE (1 << 0) 330 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) 331 332 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ 333 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) 334 # define DP_IRQ_HPD_ENABLE (1 << 1) 335 336 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ 337 # define DP_PWR_NOT_NEEDED (1 << 0) 338 339 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ 340 # define DP_AUX_FRAME_SYNC_VALID (1 << 0) 341 342 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 343 # define DP_PSR_ENABLE (1 << 0) 344 # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 345 # define DP_PSR_CRC_VERIFICATION (1 << 2) 346 # define DP_PSR_FRAME_CAPTURE (1 << 3) 347 # define DP_PSR_SELECTIVE_UPDATE (1 << 4) 348 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) 349 350 #define DP_ADAPTER_CTRL 0x1a0 351 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) 352 353 #define DP_BRANCH_DEVICE_CTRL 0x1a1 354 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) 355 356 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 357 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 358 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 359 360 #define DP_SINK_COUNT 0x200 361 /* prior to 1.2 bit 7 was reserved mbz */ 362 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 363 # define DP_SINK_CP_READY (1 << 6) 364 365 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 366 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 367 # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 368 # define DP_CP_IRQ (1 << 2) 369 # define DP_MCCS_IRQ (1 << 3) 370 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ 371 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ 372 # define DP_SINK_SPECIFIC_IRQ (1 << 6) 373 374 #define DP_LANE0_1_STATUS 0x202 375 #define DP_LANE2_3_STATUS 0x203 376 # define DP_LANE_CR_DONE (1 << 0) 377 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 378 # define DP_LANE_SYMBOL_LOCKED (1 << 2) 379 380 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 381 DP_LANE_CHANNEL_EQ_DONE | \ 382 DP_LANE_SYMBOL_LOCKED) 383 384 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 385 386 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 387 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 388 #define DP_LINK_STATUS_UPDATED (1 << 7) 389 390 #define DP_SINK_STATUS 0x205 391 392 #define DP_RECEIVE_PORT_0_STATUS (1 << 0) 393 #define DP_RECEIVE_PORT_1_STATUS (1 << 1) 394 395 #define DP_ADJUST_REQUEST_LANE0_1 0x206 396 #define DP_ADJUST_REQUEST_LANE2_3 0x207 397 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 398 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 399 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 400 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 401 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 402 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 403 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 404 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 405 406 #define DP_TEST_REQUEST 0x218 407 # define DP_TEST_LINK_TRAINING (1 << 0) 408 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) 409 # define DP_TEST_LINK_EDID_READ (1 << 2) 410 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 411 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ 412 413 #define DP_TEST_LINK_RATE 0x219 414 # define DP_LINK_RATE_162 (0x6) 415 # define DP_LINK_RATE_27 (0xa) 416 417 #define DP_TEST_LANE_COUNT 0x220 418 419 #define DP_TEST_PATTERN 0x221 420 # define DP_NO_TEST_PATTERN 0x0 421 # define DP_COLOR_RAMP 0x1 422 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 423 # define DP_COLOR_SQUARE 0x3 424 425 #define DP_TEST_H_TOTAL_HI 0x222 426 #define DP_TEST_H_TOTAL_LO 0x223 427 428 #define DP_TEST_V_TOTAL_HI 0x224 429 #define DP_TEST_V_TOTAL_LO 0x225 430 431 #define DP_TEST_H_START_HI 0x226 432 #define DP_TEST_H_START_LO 0x227 433 434 #define DP_TEST_V_START_HI 0x228 435 #define DP_TEST_V_START_LO 0x229 436 437 #define DP_TEST_HSYNC_HI 0x22A 438 # define DP_TEST_HSYNC_POLARITY (1 << 7) 439 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) 440 #define DP_TEST_HSYNC_WIDTH_LO 0x22B 441 442 #define DP_TEST_VSYNC_HI 0x22C 443 # define DP_TEST_VSYNC_POLARITY (1 << 7) 444 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) 445 #define DP_TEST_VSYNC_WIDTH_LO 0x22D 446 447 #define DP_TEST_H_WIDTH_HI 0x22E 448 #define DP_TEST_H_WIDTH_LO 0x22F 449 450 #define DP_TEST_V_HEIGHT_HI 0x230 451 #define DP_TEST_V_HEIGHT_LO 0x231 452 453 #define DP_TEST_MISC0 0x232 454 # define DP_TEST_SYNC_CLOCK (1 << 0) 455 # define DP_TEST_COLOR_FORMAT_MASK (3 << 1) 456 # define DP_TEST_COLOR_FORMAT_SHIFT 1 457 # define DP_COLOR_FORMAT_RGB (0 << 1) 458 # define DP_COLOR_FORMAT_YCbCr422 (1 << 1) 459 # define DP_COLOR_FORMAT_YCbCr444 (2 << 1) 460 # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) 461 # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) 462 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) 463 # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) 464 # define DP_TEST_BIT_DEPTH_MASK (7 << 5) 465 # define DP_TEST_BIT_DEPTH_SHIFT 5 466 # define DP_TEST_BIT_DEPTH_6 (0 << 5) 467 # define DP_TEST_BIT_DEPTH_8 (1 << 5) 468 # define DP_TEST_BIT_DEPTH_10 (2 << 5) 469 # define DP_TEST_BIT_DEPTH_12 (3 << 5) 470 # define DP_TEST_BIT_DEPTH_16 (4 << 5) 471 472 #define DP_TEST_MISC1 0x233 473 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0) 474 # define DP_TEST_INTERLACED (1 << 1) 475 476 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 477 478 #define DP_TEST_CRC_R_CR 0x240 479 #define DP_TEST_CRC_G_Y 0x242 480 #define DP_TEST_CRC_B_CB 0x244 481 482 #define DP_TEST_SINK_MISC 0x246 483 # define DP_TEST_CRC_SUPPORTED (1 << 5) 484 # define DP_TEST_COUNT_MASK 0xf 485 486 #define DP_TEST_RESPONSE 0x260 487 # define DP_TEST_ACK (1 << 0) 488 # define DP_TEST_NAK (1 << 1) 489 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 490 491 #define DP_TEST_EDID_CHECKSUM 0x261 492 493 #define DP_TEST_SINK 0x270 494 # define DP_TEST_SINK_START (1 << 0) 495 496 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ 497 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) 498 # define DP_PAYLOAD_ACT_HANDLED (1 << 1) 499 500 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ 501 /* up to ID_SLOT_63 at 0x2ff */ 502 503 #define DP_SOURCE_OUI 0x300 504 #define DP_SINK_OUI 0x400 505 #define DP_BRANCH_OUI 0x500 506 #define DP_BRANCH_ID 0x503 507 #define DP_BRANCH_HW_REV 0x509 508 #define DP_BRANCH_SW_REV 0x50A 509 510 #define DP_SET_POWER 0x600 511 # define DP_SET_POWER_D0 0x1 512 # define DP_SET_POWER_D3 0x2 513 # define DP_SET_POWER_MASK 0x3 514 515 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ 516 # define DP_EDP_11 0x00 517 # define DP_EDP_12 0x01 518 # define DP_EDP_13 0x02 519 # define DP_EDP_14 0x03 520 521 #define DP_EDP_GENERAL_CAP_1 0x701 522 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) 523 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) 524 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) 525 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) 526 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) 527 # define DP_EDP_FRC_ENABLE_CAP (1 << 5) 528 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6) 529 # define DP_EDP_SET_POWER_CAP (1 << 7) 530 531 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 532 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) 533 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) 534 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) 535 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) 536 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) 537 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) 538 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) 539 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) 540 541 #define DP_EDP_GENERAL_CAP_2 0x703 542 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) 543 544 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ 545 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0) 546 # define DP_EDP_X_REGION_CAP_SHIFT 0 547 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) 548 # define DP_EDP_Y_REGION_CAP_SHIFT 4 549 550 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 551 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0) 552 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) 553 # define DP_EDP_FRC_ENABLE (1 << 2) 554 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) 555 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) 556 557 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 558 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) 559 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) 560 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) 561 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) 562 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) 563 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) 564 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) 565 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) 566 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) 567 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ 568 569 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 570 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 571 572 #define DP_EDP_PWMGEN_BIT_COUNT 0x724 573 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 574 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 575 576 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 577 578 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 579 580 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a 581 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b 582 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c 583 584 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d 585 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e 586 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f 587 588 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 589 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 590 591 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ 592 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ 593 594 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 595 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 596 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 597 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ 598 599 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ 600 /* 0-5 sink count */ 601 # define DP_SINK_COUNT_CP_READY (1 << 6) 602 603 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ 604 605 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ 606 607 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ 608 609 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 610 # define DP_PSR_LINK_CRC_ERROR (1 << 0) 611 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 612 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ 613 614 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 615 # define DP_PSR_CAPS_CHANGE (1 << 0) 616 617 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 618 # define DP_PSR_SINK_INACTIVE 0 619 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 620 # define DP_PSR_SINK_ACTIVE_RFB 2 621 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 622 # define DP_PSR_SINK_ACTIVE_RESYNC 4 623 # define DP_PSR_SINK_INTERNAL_ERROR 7 624 # define DP_PSR_SINK_STATE_MASK 0x07 625 626 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ 627 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) 628 629 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ 630 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */ 631 # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ 632 # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ 633 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ 634 # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ 635 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ 636 # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ 637 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ 638 639 /* DP 1.2 Sideband message defines */ 640 /* peer device type - DP 1.2a Table 2-92 */ 641 #define DP_PEER_DEVICE_NONE 0x0 642 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 643 #define DP_PEER_DEVICE_MST_BRANCHING 0x2 644 #define DP_PEER_DEVICE_SST_SINK 0x3 645 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 646 647 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ 648 #define DP_LINK_ADDRESS 0x01 649 #define DP_CONNECTION_STATUS_NOTIFY 0x02 650 #define DP_ENUM_PATH_RESOURCES 0x10 651 #define DP_ALLOCATE_PAYLOAD 0x11 652 #define DP_QUERY_PAYLOAD 0x12 653 #define DP_RESOURCE_STATUS_NOTIFY 0x13 654 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 655 #define DP_REMOTE_DPCD_READ 0x20 656 #define DP_REMOTE_DPCD_WRITE 0x21 657 #define DP_REMOTE_I2C_READ 0x22 658 #define DP_REMOTE_I2C_WRITE 0x23 659 #define DP_POWER_UP_PHY 0x24 660 #define DP_POWER_DOWN_PHY 0x25 661 #define DP_SINK_EVENT_NOTIFY 0x30 662 #define DP_QUERY_STREAM_ENC_STATUS 0x38 663 664 /* DP 1.2 MST sideband nak reasons - table 2.84 */ 665 #define DP_NAK_WRITE_FAILURE 0x01 666 #define DP_NAK_INVALID_READ 0x02 667 #define DP_NAK_CRC_FAILURE 0x03 668 #define DP_NAK_BAD_PARAM 0x04 669 #define DP_NAK_DEFER 0x05 670 #define DP_NAK_LINK_FAILURE 0x06 671 #define DP_NAK_NO_RESOURCES 0x07 672 #define DP_NAK_DPCD_FAIL 0x08 673 #define DP_NAK_I2C_NAK 0x09 674 #define DP_NAK_ALLOCATE_FAIL 0x0a 675 676 #define MODE_I2C_START 1 677 #define MODE_I2C_WRITE 2 678 #define MODE_I2C_READ 4 679 #define MODE_I2C_STOP 8 680 681 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ 682 #define DP_MST_PHYSICAL_PORT_0 0 683 #define DP_MST_LOGICAL_PORT_0 8 684 685 #define DP_LINK_STATUS_SIZE 6 686 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 687 int lane_count); 688 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 689 int lane_count); 690 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 691 int lane); 692 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 693 int lane); 694 695 #define DP_BRANCH_OUI_HEADER_SIZE 0xc 696 #define DP_RECEIVER_CAP_SIZE 0xf 697 #define EDP_PSR_RECEIVER_CAP_SIZE 2 698 #define EDP_DISPLAY_CTL_CAP_SIZE 3 699 700 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 701 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 702 703 u8 drm_dp_link_rate_to_bw_code(int link_rate); 704 int drm_dp_bw_code_to_link_rate(u8 link_bw); 705 706 struct edp_sdp_header { 707 u8 HB0; /* Secondary Data Packet ID */ 708 u8 HB1; /* Secondary Data Packet Type */ 709 u8 HB2; /* 7:5 reserved, 4:0 revision number */ 710 u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ 711 } __packed; 712 713 #define EDP_SDP_HEADER_REVISION_MASK 0x1F 714 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F 715 716 struct edp_vsc_psr { 717 struct edp_sdp_header sdp_header; 718 u8 DB0; /* Stereo Interface */ 719 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ 720 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ 721 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ 722 u8 DB4; /* CRC value bits 7:0 of the G or Y component */ 723 u8 DB5; /* CRC value bits 15:8 of the G or Y component */ 724 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ 725 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ 726 u8 DB8_31[24]; /* Reserved */ 727 } __packed; 728 729 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) 730 #define EDP_VSC_PSR_UPDATE_RFB (1<<1) 731 #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) 732 733 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 734 735 static inline int 736 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 737 { 738 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 739 } 740 741 static inline u8 742 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 743 { 744 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 745 } 746 747 static inline bool 748 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 749 { 750 return dpcd[DP_DPCD_REV] >= 0x11 && 751 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 752 } 753 754 static inline bool 755 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 756 { 757 return dpcd[DP_DPCD_REV] >= 0x12 && 758 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 759 } 760 761 static inline bool 762 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 763 { 764 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 765 } 766 767 /* 768 * DisplayPort AUX channel 769 */ 770 771 /** 772 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 773 * @address: address of the (first) register to access 774 * @request: contains the type of transaction (see DP_AUX_* macros) 775 * @reply: upon completion, contains the reply type of the transaction 776 * @buffer: pointer to a transmission or reception buffer 777 * @size: size of @buffer 778 */ 779 struct drm_dp_aux_msg { 780 unsigned int address; 781 u8 request; 782 u8 reply; 783 void *buffer; 784 size_t size; 785 }; 786 787 /** 788 * struct drm_dp_aux - DisplayPort AUX channel 789 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter 790 * @ddc: I2C adapter that can be used for I2C-over-AUX communication 791 * @dev: pointer to struct device that is the parent for this AUX channel 792 * @crtc: backpointer to the crtc that is currently using this AUX channel 793 * @hw_mutex: internal mutex used for locking transfers 794 * @crc_work: worker that captures CRCs for each frame 795 * @crc_count: counter of captured frame CRCs 796 * @transfer: transfers a message representing a single AUX transaction 797 * 798 * The .dev field should be set to a pointer to the device that implements 799 * the AUX channel. 800 * 801 * The .name field may be used to specify the name of the I2C adapter. If set to 802 * NULL, dev_name() of .dev will be used. 803 * 804 * Drivers provide a hardware-specific implementation of how transactions 805 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg 806 * structure describing the transaction is passed into this function. Upon 807 * success, the implementation should return the number of payload bytes 808 * that were transferred, or a negative error-code on failure. Helpers 809 * propagate errors from the .transfer() function, with the exception of 810 * the -EBUSY error, which causes a transaction to be retried. On a short, 811 * helpers will return -EPROTO to make it simpler to check for failure. 812 * 813 * An AUX channel can also be used to transport I2C messages to a sink. A 814 * typical application of that is to access an EDID that's present in the 815 * sink device. The .transfer() function can also be used to execute such 816 * transactions. The drm_dp_aux_register() function registers an I2C 817 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers 818 * should call drm_dp_aux_unregister() to remove the I2C adapter. 819 * The I2C adapter uses long transfers by default; if a partial response is 820 * received, the adapter will drop down to the size given by the partial 821 * response for this transaction only. 822 * 823 * Note that the aux helper code assumes that the .transfer() function 824 * only modifies the reply field of the drm_dp_aux_msg structure. The 825 * retry logic and i2c helpers assume this is the case. 826 */ 827 struct drm_dp_aux { 828 const char *name; 829 struct i2c_adapter ddc; 830 struct device *dev; 831 struct drm_crtc *crtc; 832 struct lock hw_mutex; 833 struct work_struct crc_work; 834 u8 crc_count; 835 ssize_t (*transfer)(struct drm_dp_aux *aux, 836 struct drm_dp_aux_msg *msg); 837 /** 838 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 839 */ 840 unsigned i2c_nack_count; 841 /** 842 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 843 */ 844 unsigned i2c_defer_count; 845 }; 846 847 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 848 void *buffer, size_t size); 849 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 850 void *buffer, size_t size); 851 852 /** 853 * drm_dp_dpcd_readb() - read a single byte from the DPCD 854 * @aux: DisplayPort AUX channel 855 * @offset: address of the register to read 856 * @valuep: location where the value of the register will be stored 857 * 858 * Returns the number of bytes transferred (1) on success, or a negative 859 * error code on failure. 860 */ 861 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 862 unsigned int offset, u8 *valuep) 863 { 864 return drm_dp_dpcd_read(aux, offset, valuep, 1); 865 } 866 867 /** 868 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 869 * @aux: DisplayPort AUX channel 870 * @offset: address of the register to write 871 * @value: value to write to the register 872 * 873 * Returns the number of bytes transferred (1) on success, or a negative 874 * error code on failure. 875 */ 876 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 877 unsigned int offset, u8 value) 878 { 879 return drm_dp_dpcd_write(aux, offset, &value, 1); 880 } 881 882 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 883 u8 status[DP_LINK_STATUS_SIZE]); 884 885 /* 886 * DisplayPort link 887 */ 888 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) 889 890 struct drm_dp_link { 891 unsigned char revision; 892 unsigned int rate; 893 unsigned int num_lanes; 894 unsigned long capabilities; 895 }; 896 897 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); 898 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); 899 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); 900 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); 901 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 902 const u8 port_cap[4]); 903 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 904 const u8 port_cap[4]); 905 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 906 void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 907 const u8 port_cap[4], struct drm_dp_aux *aux); 908 909 void drm_dp_aux_init(struct drm_dp_aux *aux); 910 int drm_dp_aux_register(struct drm_dp_aux *aux); 911 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 912 913 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 914 int drm_dp_stop_crc(struct drm_dp_aux *aux); 915 916 struct drm_dp_dpcd_ident { 917 u8 oui[3]; 918 u8 device_id[6]; 919 u8 hw_rev; 920 u8 sw_major_rev; 921 u8 sw_minor_rev; 922 } __packed; 923 924 /** 925 * struct drm_dp_desc - DP branch/sink device descriptor 926 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 927 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 928 */ 929 struct drm_dp_desc { 930 struct drm_dp_dpcd_ident ident; 931 u32 quirks; 932 }; 933 934 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 935 bool is_branch); 936 937 /** 938 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 939 * 940 * Display Port sink and branch devices in the wild have a variety of bugs, try 941 * to collect them here. The quirks are shared, but it's up to the drivers to 942 * implement workarounds for them. 943 */ 944 enum drm_dp_quirk { 945 /** 946 * @DP_DPCD_QUIRK_LIMITED_M_N: 947 * 948 * The device requires main link attributes Mvid and Nvid to be limited 949 * to 16 bits. 950 */ 951 DP_DPCD_QUIRK_LIMITED_M_N, 952 }; 953 954 /** 955 * drm_dp_has_quirk() - does the DP device have a specific quirk 956 * @desc: Device decriptor filled by drm_dp_read_desc() 957 * @quirk: Quirk to query for 958 * 959 * Return true if DP device identified by @desc has @quirk. 960 */ 961 static inline bool 962 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 963 { 964 return desc->quirks & BIT(quirk); 965 } 966 967 #endif /* _DRM_DP_HELPER_H_ */ 968