1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/types.h> 27 #include <linux/i2c.h> 28 #include <linux/delay.h> 29 30 /* 31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 32 * DP and DPCD versions are independent. Differences from 1.0 are not noted, 33 * 1.0 devices basically don't exist in the wild. 34 * 35 * Abbreviations, in chronological order: 36 * 37 * eDP: Embedded DisplayPort version 1 38 * DPI: DisplayPort Interoperability Guideline v1.1a 39 * 1.2: DisplayPort 1.2 40 * MST: Multistream Transport - part of DP 1.2a 41 * 42 * 1.2 formally includes both eDP and DPI definitions. 43 */ 44 45 #define DP_AUX_MAX_PAYLOAD_BYTES 16 46 47 #define DP_AUX_I2C_WRITE 0x0 48 #define DP_AUX_I2C_READ 0x1 49 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 50 #define DP_AUX_I2C_MOT 0x4 51 #define DP_AUX_NATIVE_WRITE 0x8 52 #define DP_AUX_NATIVE_READ 0x9 53 54 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 55 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 56 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 57 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 58 59 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 60 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 61 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 62 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 63 64 /* AUX CH addresses */ 65 /* DPCD */ 66 #define DP_DPCD_REV 0x000 67 68 #define DP_MAX_LINK_RATE 0x001 69 70 #define DP_MAX_LANE_COUNT 0x002 71 # define DP_MAX_LANE_COUNT_MASK 0x1f 72 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 73 # define DP_ENHANCED_FRAME_CAP (1 << 7) 74 75 #define DP_MAX_DOWNSPREAD 0x003 76 # define DP_MAX_DOWNSPREAD_0_5 (1 << 0) 77 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 78 79 #define DP_NORP 0x004 80 81 #define DP_DOWNSTREAMPORT_PRESENT 0x005 82 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 83 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 84 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) 85 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) 86 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) 87 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) 88 # define DP_FORMAT_CONVERSION (1 << 3) 89 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 90 91 #define DP_MAIN_LINK_CHANNEL_CODING 0x006 92 93 #define DP_DOWN_STREAM_PORT_COUNT 0x007 94 # define DP_PORT_COUNT_MASK 0x0f 95 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 96 # define DP_OUI_SUPPORT (1 << 7) 97 98 #define DP_RECEIVE_PORT_0_CAP_0 0x008 99 # define DP_LOCAL_EDID_PRESENT (1 << 1) 100 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) 101 102 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 103 104 #define DP_RECEIVE_PORT_1_CAP_0 0x00a 105 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b 106 107 #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 108 # define DP_I2C_SPEED_1K 0x01 109 # define DP_I2C_SPEED_5K 0x02 110 # define DP_I2C_SPEED_10K 0x04 111 # define DP_I2C_SPEED_100K 0x08 112 # define DP_I2C_SPEED_400K 0x10 113 # define DP_I2C_SPEED_1M 0x20 114 115 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 116 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) 117 # define DP_FRAMING_CHANGE_CAP (1 << 1) 118 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ 119 120 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 121 122 #define DP_ADAPTER_CAP 0x00f /* 1.2 */ 123 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) 124 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) 125 126 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ 127 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ 128 129 /* Multiple stream transport */ 130 #define DP_FAUX_CAP 0x020 /* 1.2 */ 131 # define DP_FAUX_CAP_1 (1 << 0) 132 133 #define DP_MSTM_CAP 0x021 /* 1.2 */ 134 # define DP_MST_CAP (1 << 0) 135 136 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ 137 138 /* AV_SYNC_DATA_BLOCK 1.2 */ 139 #define DP_AV_GRANULARITY 0x023 140 # define DP_AG_FACTOR_MASK (0xf << 0) 141 # define DP_AG_FACTOR_3MS (0 << 0) 142 # define DP_AG_FACTOR_2MS (1 << 0) 143 # define DP_AG_FACTOR_1MS (2 << 0) 144 # define DP_AG_FACTOR_500US (3 << 0) 145 # define DP_AG_FACTOR_200US (4 << 0) 146 # define DP_AG_FACTOR_100US (5 << 0) 147 # define DP_AG_FACTOR_10US (6 << 0) 148 # define DP_AG_FACTOR_1US (7 << 0) 149 # define DP_VG_FACTOR_MASK (0xf << 4) 150 # define DP_VG_FACTOR_3MS (0 << 4) 151 # define DP_VG_FACTOR_2MS (1 << 4) 152 # define DP_VG_FACTOR_1MS (2 << 4) 153 # define DP_VG_FACTOR_500US (3 << 4) 154 # define DP_VG_FACTOR_200US (4 << 4) 155 # define DP_VG_FACTOR_100US (5 << 4) 156 157 #define DP_AUD_DEC_LAT0 0x024 158 #define DP_AUD_DEC_LAT1 0x025 159 160 #define DP_AUD_PP_LAT0 0x026 161 #define DP_AUD_PP_LAT1 0x027 162 163 #define DP_VID_INTER_LAT 0x028 164 165 #define DP_VID_PROG_LAT 0x029 166 167 #define DP_REP_LAT 0x02a 168 169 #define DP_AUD_DEL_INS0 0x02b 170 #define DP_AUD_DEL_INS1 0x02c 171 #define DP_AUD_DEL_INS2 0x02d 172 /* End of AV_SYNC_DATA_BLOCK */ 173 174 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ 175 # define DP_ALPM_CAP (1 << 0) 176 177 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ 178 # define DP_AUX_FRAME_SYNC_CAP (1 << 0) 179 180 #define DP_GUID 0x030 /* 1.2 */ 181 182 #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ 183 # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) 184 185 #define DP_DSC_REV 0x061 186 # define DP_DSC_MAJOR_MASK (0xf << 0) 187 # define DP_DSC_MINOR_MASK (0xf << 4) 188 # define DP_DSC_MAJOR_SHIFT 0 189 # define DP_DSC_MINOR_SHIFT 4 190 191 #define DP_DSC_RC_BUF_BLK_SIZE 0x062 192 # define DP_DSC_RC_BUF_BLK_SIZE_1 0x0 193 # define DP_DSC_RC_BUF_BLK_SIZE_4 0x1 194 # define DP_DSC_RC_BUF_BLK_SIZE_16 0x2 195 # define DP_DSC_RC_BUF_BLK_SIZE_64 0x3 196 197 #define DP_DSC_RC_BUF_SIZE 0x063 198 199 #define DP_DSC_SLICE_CAP_1 0x064 200 # define DP_DSC_1_PER_DP_DSC_SINK (1 << 0) 201 # define DP_DSC_2_PER_DP_DSC_SINK (1 << 1) 202 # define DP_DSC_4_PER_DP_DSC_SINK (1 << 3) 203 # define DP_DSC_6_PER_DP_DSC_SINK (1 << 4) 204 # define DP_DSC_8_PER_DP_DSC_SINK (1 << 5) 205 # define DP_DSC_10_PER_DP_DSC_SINK (1 << 6) 206 # define DP_DSC_12_PER_DP_DSC_SINK (1 << 7) 207 208 #define DP_DSC_LINE_BUF_BIT_DEPTH 0x065 209 # define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0) 210 # define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0 211 # define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1 212 # define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2 213 # define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3 214 # define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4 215 # define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5 216 # define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6 217 # define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7 218 # define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8 219 220 #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 221 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) 222 223 #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ 224 225 #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ 226 227 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 228 # define DP_DSC_RGB (1 << 0) 229 # define DP_DSC_YCbCr444 (1 << 1) 230 # define DP_DSC_YCbCr422_Simple (1 << 2) 231 # define DP_DSC_YCbCr422_Native (1 << 3) 232 # define DP_DSC_YCbCr420_Native (1 << 4) 233 234 #define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A 235 # define DP_DSC_8_BPC (1 << 1) 236 # define DP_DSC_10_BPC (1 << 2) 237 # define DP_DSC_12_BPC (1 << 3) 238 239 #define DP_DSC_PEAK_THROUGHPUT 0x06B 240 # define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0) 241 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0 242 # define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0) 243 # define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0) 244 # define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0) 245 # define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0) 246 # define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0) 247 # define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0) 248 # define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0) 249 # define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0) 250 # define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0) 251 # define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0) 252 # define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0) 253 # define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) 254 # define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) 255 # define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) 256 # define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) 257 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 258 # define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4) 259 # define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4) 260 # define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4) 261 # define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4) 262 # define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4) 263 # define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4) 264 # define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4) 265 # define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4) 266 # define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4) 267 # define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4) 268 # define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4) 269 # define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4) 270 # define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4) 271 # define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) 272 273 #define DP_DSC_MAX_SLICE_WIDTH 0x06C 274 275 #define DP_DSC_SLICE_CAP_2 0x06D 276 # define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) 277 # define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) 278 # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) 279 280 #define DP_DSC_BITS_PER_PIXEL_INC 0x06F 281 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 282 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 283 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 284 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 285 # define DP_DSC_BITS_PER_PIXEL_1 0x4 286 287 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 288 # define DP_PSR_IS_SUPPORTED 1 289 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ 290 291 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 292 # define DP_PSR_NO_TRAIN_ON_EXIT 1 293 # define DP_PSR_SETUP_TIME_330 (0 << 1) 294 # define DP_PSR_SETUP_TIME_275 (1 << 1) 295 # define DP_PSR_SETUP_TIME_220 (2 << 1) 296 # define DP_PSR_SETUP_TIME_165 (3 << 1) 297 # define DP_PSR_SETUP_TIME_110 (4 << 1) 298 # define DP_PSR_SETUP_TIME_55 (5 << 1) 299 # define DP_PSR_SETUP_TIME_0 (6 << 1) 300 # define DP_PSR_SETUP_TIME_MASK (7 << 1) 301 # define DP_PSR_SETUP_TIME_SHIFT 1 302 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ 303 # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ 304 /* 305 * 0x80-0x8f describe downstream port capabilities, but there are two layouts 306 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 307 * each port's descriptor is one byte wide. If it was set, each port's is 308 * four bytes wide, starting with the one byte from the base info. As of 309 * DP interop v1.1a only VGA defines additional detail. 310 */ 311 312 /* offset 0 */ 313 #define DP_DOWNSTREAM_PORT_0 0x80 314 # define DP_DS_PORT_TYPE_MASK (7 << 0) 315 # define DP_DS_PORT_TYPE_DP 0 316 # define DP_DS_PORT_TYPE_VGA 1 317 # define DP_DS_PORT_TYPE_DVI 2 318 # define DP_DS_PORT_TYPE_HDMI 3 319 # define DP_DS_PORT_TYPE_NON_EDID 4 320 # define DP_DS_PORT_TYPE_DP_DUALMODE 5 321 # define DP_DS_PORT_TYPE_WIRELESS 6 322 # define DP_DS_PORT_HPD (1 << 3) 323 /* offset 1 for VGA is maximum megapixels per second / 8 */ 324 /* offset 2 */ 325 # define DP_DS_MAX_BPC_MASK (3 << 0) 326 # define DP_DS_8BPC 0 327 # define DP_DS_10BPC 1 328 # define DP_DS_12BPC 2 329 # define DP_DS_16BPC 3 330 331 /* link configuration */ 332 #define DP_LINK_BW_SET 0x100 333 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ 334 # define DP_LINK_BW_1_62 0x06 335 # define DP_LINK_BW_2_7 0x0a 336 # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 337 338 #define DP_LANE_COUNT_SET 0x101 339 # define DP_LANE_COUNT_MASK 0x0f 340 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 341 342 #define DP_TRAINING_PATTERN_SET 0x102 343 # define DP_TRAINING_PATTERN_DISABLE 0 344 # define DP_TRAINING_PATTERN_1 1 345 # define DP_TRAINING_PATTERN_2 2 346 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 347 # define DP_TRAINING_PATTERN_MASK 0x3 348 349 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ 350 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) 351 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) 352 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) 353 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) 354 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) 355 356 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 357 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 358 359 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 360 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 361 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 362 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 363 364 #define DP_TRAINING_LANE0_SET 0x103 365 #define DP_TRAINING_LANE1_SET 0x104 366 #define DP_TRAINING_LANE2_SET 0x105 367 #define DP_TRAINING_LANE3_SET 0x106 368 369 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 370 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 371 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 372 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) 373 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) 374 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) 375 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) 376 377 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 378 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) 379 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) 380 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) 381 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) 382 383 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 384 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 385 386 #define DP_DOWNSPREAD_CTRL 0x107 387 # define DP_SPREAD_AMP_0_5 (1 << 4) 388 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 389 390 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 391 # define DP_SET_ANSI_8B10B (1 << 0) 392 393 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 394 /* bitmask as for DP_I2C_SPEED_CAP */ 395 396 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 397 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) 398 # define DP_FRAMING_CHANGE_ENABLE (1 << 1) 399 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) 400 401 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ 402 #define DP_LINK_QUAL_LANE1_SET 0x10c 403 #define DP_LINK_QUAL_LANE2_SET 0x10d 404 #define DP_LINK_QUAL_LANE3_SET 0x10e 405 # define DP_LINK_QUAL_PATTERN_DISABLE 0 406 # define DP_LINK_QUAL_PATTERN_D10_2 1 407 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 408 # define DP_LINK_QUAL_PATTERN_PRBS7 3 409 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 410 # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 411 # define DP_LINK_QUAL_PATTERN_MASK 7 412 413 #define DP_TRAINING_LANE0_1_SET2 0x10f 414 #define DP_TRAINING_LANE2_3_SET2 0x110 415 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) 416 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) 417 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) 418 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) 419 420 #define DP_MSTM_CTRL 0x111 /* 1.2 */ 421 # define DP_MST_EN (1 << 0) 422 # define DP_UP_REQ_EN (1 << 1) 423 # define DP_UPSTREAM_IS_SRC (1 << 2) 424 425 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ 426 #define DP_AUDIO_DELAY1 0x113 427 #define DP_AUDIO_DELAY2 0x114 428 429 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ 430 # define DP_LINK_RATE_SET_SHIFT 0 431 # define DP_LINK_RATE_SET_MASK (7 << 0) 432 433 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ 434 # define DP_ALPM_ENABLE (1 << 0) 435 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) 436 437 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ 438 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) 439 # define DP_IRQ_HPD_ENABLE (1 << 1) 440 441 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ 442 # define DP_PWR_NOT_NEEDED (1 << 0) 443 444 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ 445 # define DP_AUX_FRAME_SYNC_VALID (1 << 0) 446 447 #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ 448 449 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 450 # define DP_PSR_ENABLE (1 << 0) 451 # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 452 # define DP_PSR_CRC_VERIFICATION (1 << 2) 453 # define DP_PSR_FRAME_CAPTURE (1 << 3) 454 # define DP_PSR_SELECTIVE_UPDATE (1 << 4) 455 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) 456 457 #define DP_ADAPTER_CTRL 0x1a0 458 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) 459 460 #define DP_BRANCH_DEVICE_CTRL 0x1a1 461 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) 462 463 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 464 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 465 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 466 467 #define DP_SINK_COUNT 0x200 468 /* prior to 1.2 bit 7 was reserved mbz */ 469 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 470 # define DP_SINK_CP_READY (1 << 6) 471 472 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 473 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 474 # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 475 # define DP_CP_IRQ (1 << 2) 476 # define DP_MCCS_IRQ (1 << 3) 477 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ 478 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ 479 # define DP_SINK_SPECIFIC_IRQ (1 << 6) 480 481 #define DP_LANE0_1_STATUS 0x202 482 #define DP_LANE2_3_STATUS 0x203 483 # define DP_LANE_CR_DONE (1 << 0) 484 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 485 # define DP_LANE_SYMBOL_LOCKED (1 << 2) 486 487 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 488 DP_LANE_CHANNEL_EQ_DONE | \ 489 DP_LANE_SYMBOL_LOCKED) 490 491 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 492 493 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 494 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 495 #define DP_LINK_STATUS_UPDATED (1 << 7) 496 497 #define DP_SINK_STATUS 0x205 498 499 #define DP_RECEIVE_PORT_0_STATUS (1 << 0) 500 #define DP_RECEIVE_PORT_1_STATUS (1 << 1) 501 502 #define DP_ADJUST_REQUEST_LANE0_1 0x206 503 #define DP_ADJUST_REQUEST_LANE2_3 0x207 504 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 505 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 506 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 507 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 508 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 509 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 510 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 511 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 512 513 #define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c 514 515 #define DP_TEST_REQUEST 0x218 516 # define DP_TEST_LINK_TRAINING (1 << 0) 517 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) 518 # define DP_TEST_LINK_EDID_READ (1 << 2) 519 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 520 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ 521 522 #define DP_TEST_LINK_RATE 0x219 523 # define DP_LINK_RATE_162 (0x6) 524 # define DP_LINK_RATE_27 (0xa) 525 526 #define DP_TEST_LANE_COUNT 0x220 527 528 #define DP_TEST_PATTERN 0x221 529 # define DP_NO_TEST_PATTERN 0x0 530 # define DP_COLOR_RAMP 0x1 531 # define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 532 # define DP_COLOR_SQUARE 0x3 533 534 #define DP_TEST_H_TOTAL_HI 0x222 535 #define DP_TEST_H_TOTAL_LO 0x223 536 537 #define DP_TEST_V_TOTAL_HI 0x224 538 #define DP_TEST_V_TOTAL_LO 0x225 539 540 #define DP_TEST_H_START_HI 0x226 541 #define DP_TEST_H_START_LO 0x227 542 543 #define DP_TEST_V_START_HI 0x228 544 #define DP_TEST_V_START_LO 0x229 545 546 #define DP_TEST_HSYNC_HI 0x22A 547 # define DP_TEST_HSYNC_POLARITY (1 << 7) 548 # define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) 549 #define DP_TEST_HSYNC_WIDTH_LO 0x22B 550 551 #define DP_TEST_VSYNC_HI 0x22C 552 # define DP_TEST_VSYNC_POLARITY (1 << 7) 553 # define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) 554 #define DP_TEST_VSYNC_WIDTH_LO 0x22D 555 556 #define DP_TEST_H_WIDTH_HI 0x22E 557 #define DP_TEST_H_WIDTH_LO 0x22F 558 559 #define DP_TEST_V_HEIGHT_HI 0x230 560 #define DP_TEST_V_HEIGHT_LO 0x231 561 562 #define DP_TEST_MISC0 0x232 563 # define DP_TEST_SYNC_CLOCK (1 << 0) 564 # define DP_TEST_COLOR_FORMAT_MASK (3 << 1) 565 # define DP_TEST_COLOR_FORMAT_SHIFT 1 566 # define DP_COLOR_FORMAT_RGB (0 << 1) 567 # define DP_COLOR_FORMAT_YCbCr422 (1 << 1) 568 # define DP_COLOR_FORMAT_YCbCr444 (2 << 1) 569 # define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) 570 # define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) 571 # define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) 572 # define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) 573 # define DP_TEST_BIT_DEPTH_MASK (7 << 5) 574 # define DP_TEST_BIT_DEPTH_SHIFT 5 575 # define DP_TEST_BIT_DEPTH_6 (0 << 5) 576 # define DP_TEST_BIT_DEPTH_8 (1 << 5) 577 # define DP_TEST_BIT_DEPTH_10 (2 << 5) 578 # define DP_TEST_BIT_DEPTH_12 (3 << 5) 579 # define DP_TEST_BIT_DEPTH_16 (4 << 5) 580 581 #define DP_TEST_MISC1 0x233 582 # define DP_TEST_REFRESH_DENOMINATOR (1 << 0) 583 # define DP_TEST_INTERLACED (1 << 1) 584 585 #define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 586 587 #define DP_TEST_MISC0 0x232 588 589 #define DP_TEST_CRC_R_CR 0x240 590 #define DP_TEST_CRC_G_Y 0x242 591 #define DP_TEST_CRC_B_CB 0x244 592 593 #define DP_TEST_SINK_MISC 0x246 594 # define DP_TEST_CRC_SUPPORTED (1 << 5) 595 # define DP_TEST_COUNT_MASK 0xf 596 597 #define DP_TEST_PHY_PATTERN 0x248 598 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 599 #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 600 #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 601 #define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 602 #define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 603 #define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 604 #define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 605 #define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 606 #define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 607 #define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 608 609 #define DP_TEST_RESPONSE 0x260 610 # define DP_TEST_ACK (1 << 0) 611 # define DP_TEST_NAK (1 << 1) 612 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 613 614 #define DP_TEST_EDID_CHECKSUM 0x261 615 616 #define DP_TEST_SINK 0x270 617 # define DP_TEST_SINK_START (1 << 0) 618 619 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ 620 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) 621 # define DP_PAYLOAD_ACT_HANDLED (1 << 1) 622 623 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ 624 /* up to ID_SLOT_63 at 0x2ff */ 625 626 #define DP_SOURCE_OUI 0x300 627 #define DP_SINK_OUI 0x400 628 #define DP_BRANCH_OUI 0x500 629 #define DP_BRANCH_ID 0x503 630 #define DP_BRANCH_REVISION_START 0x509 631 #define DP_BRANCH_HW_REV 0x509 632 #define DP_BRANCH_SW_REV 0x50A 633 634 #define DP_SET_POWER 0x600 635 # define DP_SET_POWER_D0 0x1 636 # define DP_SET_POWER_D3 0x2 637 # define DP_SET_POWER_MASK 0x3 638 639 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ 640 # define DP_EDP_11 0x00 641 # define DP_EDP_12 0x01 642 # define DP_EDP_13 0x02 643 # define DP_EDP_14 0x03 644 645 #define DP_EDP_GENERAL_CAP_1 0x701 646 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) 647 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) 648 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) 649 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) 650 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) 651 # define DP_EDP_FRC_ENABLE_CAP (1 << 5) 652 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6) 653 # define DP_EDP_SET_POWER_CAP (1 << 7) 654 655 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 656 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) 657 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) 658 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) 659 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) 660 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) 661 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) 662 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) 663 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) 664 665 #define DP_EDP_GENERAL_CAP_2 0x703 666 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) 667 668 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ 669 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0) 670 # define DP_EDP_X_REGION_CAP_SHIFT 0 671 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) 672 # define DP_EDP_Y_REGION_CAP_SHIFT 4 673 674 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 675 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0) 676 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) 677 # define DP_EDP_FRC_ENABLE (1 << 2) 678 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) 679 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) 680 681 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 682 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) 683 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) 684 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) 685 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) 686 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) 687 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) 688 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) 689 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) 690 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) 691 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ 692 693 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 694 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 695 696 #define DP_EDP_PWMGEN_BIT_COUNT 0x724 697 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 698 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 699 # define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) 700 701 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 702 703 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 704 # define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 705 706 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a 707 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b 708 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c 709 710 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d 711 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e 712 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f 713 714 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 715 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 716 717 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ 718 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ 719 720 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 721 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 722 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 723 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ 724 725 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ 726 /* 0-5 sink count */ 727 # define DP_SINK_COUNT_CP_READY (1 << 6) 728 729 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ 730 731 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ 732 # define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0) 733 # define DP_LOCK_ACQUISITION_REQUEST (1 << 1) 734 # define DP_CEC_IRQ (1 << 2) 735 736 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ 737 738 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 739 # define DP_PSR_LINK_CRC_ERROR (1 << 0) 740 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 741 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ 742 743 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 744 # define DP_PSR_CAPS_CHANGE (1 << 0) 745 746 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 747 # define DP_PSR_SINK_INACTIVE 0 748 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 749 # define DP_PSR_SINK_ACTIVE_RFB 2 750 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 751 # define DP_PSR_SINK_ACTIVE_RESYNC 4 752 # define DP_PSR_SINK_INTERNAL_ERROR 7 753 # define DP_PSR_SINK_STATE_MASK 0x07 754 755 #define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */ 756 # define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0) 757 # define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0 758 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4) 759 # define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4 760 761 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ 762 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) 763 764 #define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ 765 #define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ 766 #define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ 767 #define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ 768 769 #define DP_DP13_DPCD_REV 0x2200 770 #define DP_DP13_MAX_LINK_RATE 0x2201 771 772 #define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ 773 # define DP_GTC_CAP (1 << 0) /* DP 1.3 */ 774 # define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ 775 # define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ 776 # define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ 777 # define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ 778 # define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ 779 # define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ 780 # define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ 781 782 /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ 783 #define DP_CEC_TUNNELING_CAPABILITY 0x3000 784 # define DP_CEC_TUNNELING_CAPABLE (1 << 0) 785 # define DP_CEC_SNOOPING_CAPABLE (1 << 1) 786 # define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2) 787 788 #define DP_CEC_TUNNELING_CONTROL 0x3001 789 # define DP_CEC_TUNNELING_ENABLE (1 << 0) 790 # define DP_CEC_SNOOPING_ENABLE (1 << 1) 791 792 #define DP_CEC_RX_MESSAGE_INFO 0x3002 793 # define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0) 794 # define DP_CEC_RX_MESSAGE_LEN_SHIFT 0 795 # define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4) 796 # define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5) 797 # define DP_CEC_RX_MESSAGE_ACKED (1 << 6) 798 # define DP_CEC_RX_MESSAGE_ENDED (1 << 7) 799 800 #define DP_CEC_TX_MESSAGE_INFO 0x3003 801 # define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0) 802 # define DP_CEC_TX_MESSAGE_LEN_SHIFT 0 803 # define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4) 804 # define DP_CEC_TX_RETRY_COUNT_SHIFT 4 805 # define DP_CEC_TX_MESSAGE_SEND (1 << 7) 806 807 #define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004 808 # define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0) 809 # define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1) 810 # define DP_CEC_TX_MESSAGE_SENT (1 << 4) 811 # define DP_CEC_TX_LINE_ERROR (1 << 5) 812 # define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6) 813 # define DP_CEC_TX_DATA_NACK_ERROR (1 << 7) 814 815 #define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */ 816 # define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0) 817 # define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1) 818 # define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2) 819 # define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3) 820 # define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4) 821 # define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5) 822 # define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6) 823 # define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7) 824 #define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */ 825 # define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0) 826 # define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1) 827 # define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2) 828 # define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3) 829 # define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4) 830 # define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5) 831 # define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6) 832 # define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7) 833 834 #define DP_CEC_RX_MESSAGE_BUFFER 0x3010 835 #define DP_CEC_TX_MESSAGE_BUFFER 0x3020 836 #define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 837 838 /* DP 1.2 Sideband message defines */ 839 /* peer device type - DP 1.2a Table 2-92 */ 840 #define DP_PEER_DEVICE_NONE 0x0 841 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 842 #define DP_PEER_DEVICE_MST_BRANCHING 0x2 843 #define DP_PEER_DEVICE_SST_SINK 0x3 844 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 845 846 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ 847 #define DP_LINK_ADDRESS 0x01 848 #define DP_CONNECTION_STATUS_NOTIFY 0x02 849 #define DP_ENUM_PATH_RESOURCES 0x10 850 #define DP_ALLOCATE_PAYLOAD 0x11 851 #define DP_QUERY_PAYLOAD 0x12 852 #define DP_RESOURCE_STATUS_NOTIFY 0x13 853 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 854 #define DP_REMOTE_DPCD_READ 0x20 855 #define DP_REMOTE_DPCD_WRITE 0x21 856 #define DP_REMOTE_I2C_READ 0x22 857 #define DP_REMOTE_I2C_WRITE 0x23 858 #define DP_POWER_UP_PHY 0x24 859 #define DP_POWER_DOWN_PHY 0x25 860 #define DP_SINK_EVENT_NOTIFY 0x30 861 #define DP_QUERY_STREAM_ENC_STATUS 0x38 862 863 /* DP 1.2 MST sideband nak reasons - table 2.84 */ 864 #define DP_NAK_WRITE_FAILURE 0x01 865 #define DP_NAK_INVALID_READ 0x02 866 #define DP_NAK_CRC_FAILURE 0x03 867 #define DP_NAK_BAD_PARAM 0x04 868 #define DP_NAK_DEFER 0x05 869 #define DP_NAK_LINK_FAILURE 0x06 870 #define DP_NAK_NO_RESOURCES 0x07 871 #define DP_NAK_DPCD_FAIL 0x08 872 #define DP_NAK_I2C_NAK 0x09 873 #define DP_NAK_ALLOCATE_FAIL 0x0a 874 875 #define MODE_I2C_START 1 876 #define MODE_I2C_WRITE 2 877 #define MODE_I2C_READ 4 878 #define MODE_I2C_STOP 8 879 880 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ 881 #define DP_MST_PHYSICAL_PORT_0 0 882 #define DP_MST_LOGICAL_PORT_0 8 883 884 #define DP_LINK_STATUS_SIZE 6 885 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 886 int lane_count); 887 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 888 int lane_count); 889 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 890 int lane); 891 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 892 int lane); 893 894 #define DP_BRANCH_OUI_HEADER_SIZE 0xc 895 #define DP_RECEIVER_CAP_SIZE 0xf 896 #define EDP_PSR_RECEIVER_CAP_SIZE 2 897 #define EDP_DISPLAY_CTL_CAP_SIZE 3 898 899 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 900 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 901 902 u8 drm_dp_link_rate_to_bw_code(int link_rate); 903 int drm_dp_bw_code_to_link_rate(u8 link_bw); 904 905 #define DP_SDP_AUDIO_TIMESTAMP 0x01 906 #define DP_SDP_AUDIO_STREAM 0x02 907 #define DP_SDP_EXTENSION 0x04 /* DP 1.1 */ 908 #define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ 909 #define DP_SDP_ISRC 0x06 /* DP 1.2 */ 910 #define DP_SDP_VSC 0x07 /* DP 1.2 */ 911 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ 912 #define DP_SDP_PPS 0x10 /* DP 1.4 */ 913 #define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ 914 #define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ 915 /* 0x80+ CEA-861 infoframe types */ 916 917 struct edp_sdp_header { 918 u8 HB0; /* Secondary Data Packet ID */ 919 u8 HB1; /* Secondary Data Packet Type */ 920 u8 HB2; /* 7:5 reserved, 4:0 revision number */ 921 u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ 922 } __packed; 923 924 #define EDP_SDP_HEADER_REVISION_MASK 0x1F 925 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F 926 927 struct edp_vsc_psr { 928 struct edp_sdp_header sdp_header; 929 u8 DB0; /* Stereo Interface */ 930 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ 931 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ 932 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ 933 u8 DB4; /* CRC value bits 7:0 of the G or Y component */ 934 u8 DB5; /* CRC value bits 15:8 of the G or Y component */ 935 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ 936 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ 937 u8 DB8_31[24]; /* Reserved */ 938 } __packed; 939 940 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) 941 #define EDP_VSC_PSR_UPDATE_RFB (1<<1) 942 #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) 943 944 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 945 946 static inline int 947 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 948 { 949 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 950 } 951 952 static inline u8 953 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 954 { 955 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 956 } 957 958 static inline bool 959 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 960 { 961 return dpcd[DP_DPCD_REV] >= 0x11 && 962 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 963 } 964 965 static inline bool 966 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 967 { 968 return dpcd[DP_DPCD_REV] >= 0x12 && 969 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 970 } 971 972 static inline bool 973 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 974 { 975 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 976 } 977 978 /* 979 * DisplayPort AUX channel 980 */ 981 982 /** 983 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 984 * @address: address of the (first) register to access 985 * @request: contains the type of transaction (see DP_AUX_* macros) 986 * @reply: upon completion, contains the reply type of the transaction 987 * @buffer: pointer to a transmission or reception buffer 988 * @size: size of @buffer 989 */ 990 struct drm_dp_aux_msg { 991 unsigned int address; 992 u8 request; 993 u8 reply; 994 void *buffer; 995 size_t size; 996 }; 997 998 /** 999 * struct drm_dp_aux - DisplayPort AUX channel 1000 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter 1001 * @ddc: I2C adapter that can be used for I2C-over-AUX communication 1002 * @dev: pointer to struct device that is the parent for this AUX channel 1003 * @crtc: backpointer to the crtc that is currently using this AUX channel 1004 * @hw_mutex: internal mutex used for locking transfers 1005 * @crc_work: worker that captures CRCs for each frame 1006 * @crc_count: counter of captured frame CRCs 1007 * @transfer: transfers a message representing a single AUX transaction 1008 * 1009 * The .dev field should be set to a pointer to the device that implements 1010 * the AUX channel. 1011 * 1012 * The .name field may be used to specify the name of the I2C adapter. If set to 1013 * NULL, dev_name() of .dev will be used. 1014 * 1015 * Drivers provide a hardware-specific implementation of how transactions 1016 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg 1017 * structure describing the transaction is passed into this function. Upon 1018 * success, the implementation should return the number of payload bytes 1019 * that were transferred, or a negative error-code on failure. Helpers 1020 * propagate errors from the .transfer() function, with the exception of 1021 * the -EBUSY error, which causes a transaction to be retried. On a short, 1022 * helpers will return -EPROTO to make it simpler to check for failure. 1023 * 1024 * An AUX channel can also be used to transport I2C messages to a sink. A 1025 * typical application of that is to access an EDID that's present in the 1026 * sink device. The .transfer() function can also be used to execute such 1027 * transactions. The drm_dp_aux_register() function registers an I2C 1028 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers 1029 * should call drm_dp_aux_unregister() to remove the I2C adapter. 1030 * The I2C adapter uses long transfers by default; if a partial response is 1031 * received, the adapter will drop down to the size given by the partial 1032 * response for this transaction only. 1033 * 1034 * Note that the aux helper code assumes that the .transfer() function 1035 * only modifies the reply field of the drm_dp_aux_msg structure. The 1036 * retry logic and i2c helpers assume this is the case. 1037 */ 1038 struct drm_dp_aux { 1039 const char *name; 1040 struct i2c_adapter ddc; 1041 struct device *dev; 1042 struct drm_crtc *crtc; 1043 struct lock hw_mutex; 1044 struct work_struct crc_work; 1045 u8 crc_count; 1046 ssize_t (*transfer)(struct drm_dp_aux *aux, 1047 struct drm_dp_aux_msg *msg); 1048 /** 1049 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 1050 */ 1051 unsigned i2c_nack_count; 1052 /** 1053 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 1054 */ 1055 unsigned i2c_defer_count; 1056 }; 1057 1058 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 1059 void *buffer, size_t size); 1060 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 1061 void *buffer, size_t size); 1062 1063 /** 1064 * drm_dp_dpcd_readb() - read a single byte from the DPCD 1065 * @aux: DisplayPort AUX channel 1066 * @offset: address of the register to read 1067 * @valuep: location where the value of the register will be stored 1068 * 1069 * Returns the number of bytes transferred (1) on success, or a negative 1070 * error code on failure. 1071 */ 1072 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 1073 unsigned int offset, u8 *valuep) 1074 { 1075 return drm_dp_dpcd_read(aux, offset, valuep, 1); 1076 } 1077 1078 /** 1079 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 1080 * @aux: DisplayPort AUX channel 1081 * @offset: address of the register to write 1082 * @value: value to write to the register 1083 * 1084 * Returns the number of bytes transferred (1) on success, or a negative 1085 * error code on failure. 1086 */ 1087 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 1088 unsigned int offset, u8 value) 1089 { 1090 return drm_dp_dpcd_write(aux, offset, &value, 1); 1091 } 1092 1093 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 1094 u8 status[DP_LINK_STATUS_SIZE]); 1095 1096 /* 1097 * DisplayPort link 1098 */ 1099 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) 1100 1101 struct drm_dp_link { 1102 unsigned char revision; 1103 unsigned int rate; 1104 unsigned int num_lanes; 1105 unsigned long capabilities; 1106 }; 1107 1108 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); 1109 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); 1110 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); 1111 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); 1112 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1113 const u8 port_cap[4]); 1114 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1115 const u8 port_cap[4]); 1116 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 1117 void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1118 const u8 port_cap[4], struct drm_dp_aux *aux); 1119 1120 void drm_dp_aux_init(struct drm_dp_aux *aux); 1121 int drm_dp_aux_register(struct drm_dp_aux *aux); 1122 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 1123 1124 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 1125 int drm_dp_stop_crc(struct drm_dp_aux *aux); 1126 1127 struct drm_dp_dpcd_ident { 1128 u8 oui[3]; 1129 u8 device_id[6]; 1130 u8 hw_rev; 1131 u8 sw_major_rev; 1132 u8 sw_minor_rev; 1133 } __packed; 1134 1135 /** 1136 * struct drm_dp_desc - DP branch/sink device descriptor 1137 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 1138 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 1139 */ 1140 struct drm_dp_desc { 1141 struct drm_dp_dpcd_ident ident; 1142 u32 quirks; 1143 }; 1144 1145 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 1146 bool is_branch); 1147 1148 /** 1149 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 1150 * 1151 * Display Port sink and branch devices in the wild have a variety of bugs, try 1152 * to collect them here. The quirks are shared, but it's up to the drivers to 1153 * implement workarounds for them. 1154 */ 1155 enum drm_dp_quirk { 1156 /** 1157 * @DP_DPCD_QUIRK_LIMITED_M_N: 1158 * 1159 * The device requires main link attributes Mvid and Nvid to be limited 1160 * to 16 bits. 1161 */ 1162 DP_DPCD_QUIRK_LIMITED_M_N, 1163 }; 1164 1165 /** 1166 * drm_dp_has_quirk() - does the DP device have a specific quirk 1167 * @desc: Device decriptor filled by drm_dp_read_desc() 1168 * @quirk: Quirk to query for 1169 * 1170 * Return true if DP device identified by @desc has @quirk. 1171 */ 1172 static inline bool 1173 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 1174 { 1175 return desc->quirks & BIT(quirk); 1176 } 1177 1178 #endif /* _DRM_DP_HELPER_H_ */ 1179