1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/types.h> 27 #include <linux/i2c.h> 28 #include <linux/delay.h> 29 30 /* 31 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that 32 * DP and DPCD versions are independent. Differences from 1.0 are not noted, 33 * 1.0 devices basically don't exist in the wild. 34 * 35 * Abbreviations, in chronological order: 36 * 37 * eDP: Embedded DisplayPort version 1 38 * DPI: DisplayPort Interoperability Guideline v1.1a 39 * 1.2: DisplayPort 1.2 40 * MST: Multistream Transport - part of DP 1.2a 41 * 42 * 1.2 formally includes both eDP and DPI definitions. 43 */ 44 45 #define DP_AUX_MAX_PAYLOAD_BYTES 16 46 47 #define DP_AUX_I2C_WRITE 0x0 48 #define DP_AUX_I2C_READ 0x1 49 #define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 50 #define DP_AUX_I2C_MOT 0x4 51 #define DP_AUX_NATIVE_WRITE 0x8 52 #define DP_AUX_NATIVE_READ 0x9 53 54 #define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) 55 #define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) 56 #define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) 57 #define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) 58 59 #define DP_AUX_I2C_REPLY_ACK (0x0 << 2) 60 #define DP_AUX_I2C_REPLY_NACK (0x1 << 2) 61 #define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) 62 #define DP_AUX_I2C_REPLY_MASK (0x3 << 2) 63 64 /* AUX CH addresses */ 65 /* DPCD */ 66 #define DP_DPCD_REV 0x000 67 68 #define DP_MAX_LINK_RATE 0x001 69 70 #define DP_MAX_LANE_COUNT 0x002 71 # define DP_MAX_LANE_COUNT_MASK 0x1f 72 # define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ 73 # define DP_ENHANCED_FRAME_CAP (1 << 7) 74 75 #define DP_MAX_DOWNSPREAD 0x003 76 # define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) 77 78 #define DP_NORP 0x004 79 80 #define DP_DOWNSTREAMPORT_PRESENT 0x005 81 # define DP_DWN_STRM_PORT_PRESENT (1 << 0) 82 # define DP_DWN_STRM_PORT_TYPE_MASK 0x06 83 # define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) 84 # define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) 85 # define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) 86 # define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) 87 # define DP_FORMAT_CONVERSION (1 << 3) 88 # define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ 89 90 #define DP_MAIN_LINK_CHANNEL_CODING 0x006 91 92 #define DP_DOWN_STREAM_PORT_COUNT 0x007 93 # define DP_PORT_COUNT_MASK 0x0f 94 # define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ 95 # define DP_OUI_SUPPORT (1 << 7) 96 97 #define DP_RECEIVE_PORT_0_CAP_0 0x008 98 # define DP_LOCAL_EDID_PRESENT (1 << 1) 99 # define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) 100 101 #define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 102 103 #define DP_RECEIVE_PORT_1_CAP_0 0x00a 104 #define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b 105 106 #define DP_I2C_SPEED_CAP 0x00c /* DPI */ 107 # define DP_I2C_SPEED_1K 0x01 108 # define DP_I2C_SPEED_5K 0x02 109 # define DP_I2C_SPEED_10K 0x04 110 # define DP_I2C_SPEED_100K 0x08 111 # define DP_I2C_SPEED_400K 0x10 112 # define DP_I2C_SPEED_1M 0x20 113 114 #define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ 115 # define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) 116 # define DP_FRAMING_CHANGE_CAP (1 << 1) 117 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ 118 119 #define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ 120 121 #define DP_ADAPTER_CAP 0x00f /* 1.2 */ 122 # define DP_FORCE_LOAD_SENSE_CAP (1 << 0) 123 # define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) 124 125 #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ 126 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ 127 128 /* Multiple stream transport */ 129 #define DP_FAUX_CAP 0x020 /* 1.2 */ 130 # define DP_FAUX_CAP_1 (1 << 0) 131 132 #define DP_MSTM_CAP 0x021 /* 1.2 */ 133 # define DP_MST_CAP (1 << 0) 134 135 #define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ 136 137 /* AV_SYNC_DATA_BLOCK 1.2 */ 138 #define DP_AV_GRANULARITY 0x023 139 # define DP_AG_FACTOR_MASK (0xf << 0) 140 # define DP_AG_FACTOR_3MS (0 << 0) 141 # define DP_AG_FACTOR_2MS (1 << 0) 142 # define DP_AG_FACTOR_1MS (2 << 0) 143 # define DP_AG_FACTOR_500US (3 << 0) 144 # define DP_AG_FACTOR_200US (4 << 0) 145 # define DP_AG_FACTOR_100US (5 << 0) 146 # define DP_AG_FACTOR_10US (6 << 0) 147 # define DP_AG_FACTOR_1US (7 << 0) 148 # define DP_VG_FACTOR_MASK (0xf << 4) 149 # define DP_VG_FACTOR_3MS (0 << 4) 150 # define DP_VG_FACTOR_2MS (1 << 4) 151 # define DP_VG_FACTOR_1MS (2 << 4) 152 # define DP_VG_FACTOR_500US (3 << 4) 153 # define DP_VG_FACTOR_200US (4 << 4) 154 # define DP_VG_FACTOR_100US (5 << 4) 155 156 #define DP_AUD_DEC_LAT0 0x024 157 #define DP_AUD_DEC_LAT1 0x025 158 159 #define DP_AUD_PP_LAT0 0x026 160 #define DP_AUD_PP_LAT1 0x027 161 162 #define DP_VID_INTER_LAT 0x028 163 164 #define DP_VID_PROG_LAT 0x029 165 166 #define DP_REP_LAT 0x02a 167 168 #define DP_AUD_DEL_INS0 0x02b 169 #define DP_AUD_DEL_INS1 0x02c 170 #define DP_AUD_DEL_INS2 0x02d 171 /* End of AV_SYNC_DATA_BLOCK */ 172 173 #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ 174 # define DP_ALPM_CAP (1 << 0) 175 176 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ 177 # define DP_AUX_FRAME_SYNC_CAP (1 << 0) 178 179 #define DP_GUID 0x030 /* 1.2 */ 180 181 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ 182 # define DP_PSR_IS_SUPPORTED 1 183 # define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ 184 185 #define DP_PSR_CAPS 0x071 /* XXX 1.2? */ 186 # define DP_PSR_NO_TRAIN_ON_EXIT 1 187 # define DP_PSR_SETUP_TIME_330 (0 << 1) 188 # define DP_PSR_SETUP_TIME_275 (1 << 1) 189 # define DP_PSR_SETUP_TIME_220 (2 << 1) 190 # define DP_PSR_SETUP_TIME_165 (3 << 1) 191 # define DP_PSR_SETUP_TIME_110 (4 << 1) 192 # define DP_PSR_SETUP_TIME_55 (5 << 1) 193 # define DP_PSR_SETUP_TIME_0 (6 << 1) 194 # define DP_PSR_SETUP_TIME_MASK (7 << 1) 195 # define DP_PSR_SETUP_TIME_SHIFT 1 196 197 /* 198 * 0x80-0x8f describe downstream port capabilities, but there are two layouts 199 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, 200 * each port's descriptor is one byte wide. If it was set, each port's is 201 * four bytes wide, starting with the one byte from the base info. As of 202 * DP interop v1.1a only VGA defines additional detail. 203 */ 204 205 /* offset 0 */ 206 #define DP_DOWNSTREAM_PORT_0 0x80 207 # define DP_DS_PORT_TYPE_MASK (7 << 0) 208 # define DP_DS_PORT_TYPE_DP 0 209 # define DP_DS_PORT_TYPE_VGA 1 210 # define DP_DS_PORT_TYPE_DVI 2 211 # define DP_DS_PORT_TYPE_HDMI 3 212 # define DP_DS_PORT_TYPE_NON_EDID 4 213 # define DP_DS_PORT_TYPE_DP_DUALMODE 5 214 # define DP_DS_PORT_TYPE_WIRELESS 6 215 # define DP_DS_PORT_HPD (1 << 3) 216 /* offset 1 for VGA is maximum megapixels per second / 8 */ 217 /* offset 2 */ 218 # define DP_DS_MAX_BPC_MASK (3 << 0) 219 # define DP_DS_8BPC 0 220 # define DP_DS_10BPC 1 221 # define DP_DS_12BPC 2 222 # define DP_DS_16BPC 3 223 224 /* link configuration */ 225 #define DP_LINK_BW_SET 0x100 226 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ 227 # define DP_LINK_BW_1_62 0x06 228 # define DP_LINK_BW_2_7 0x0a 229 # define DP_LINK_BW_5_4 0x14 /* 1.2 */ 230 231 #define DP_LANE_COUNT_SET 0x101 232 # define DP_LANE_COUNT_MASK 0x0f 233 # define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 234 235 #define DP_TRAINING_PATTERN_SET 0x102 236 # define DP_TRAINING_PATTERN_DISABLE 0 237 # define DP_TRAINING_PATTERN_1 1 238 # define DP_TRAINING_PATTERN_2 2 239 # define DP_TRAINING_PATTERN_3 3 /* 1.2 */ 240 # define DP_TRAINING_PATTERN_MASK 0x3 241 242 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ 243 # define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) 244 # define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) 245 # define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) 246 # define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) 247 # define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) 248 249 # define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) 250 # define DP_LINK_SCRAMBLING_DISABLE (1 << 5) 251 252 # define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) 253 # define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) 254 # define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) 255 # define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) 256 257 #define DP_TRAINING_LANE0_SET 0x103 258 #define DP_TRAINING_LANE1_SET 0x104 259 #define DP_TRAINING_LANE2_SET 0x105 260 #define DP_TRAINING_LANE3_SET 0x106 261 262 # define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 263 # define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 264 # define DP_TRAIN_MAX_SWING_REACHED (1 << 2) 265 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) 266 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) 267 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) 268 # define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) 269 270 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) 271 # define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) 272 # define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) 273 # define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) 274 # define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) 275 276 # define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 277 # define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) 278 279 #define DP_DOWNSPREAD_CTRL 0x107 280 # define DP_SPREAD_AMP_0_5 (1 << 4) 281 # define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ 282 283 #define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 284 # define DP_SET_ANSI_8B10B (1 << 0) 285 286 #define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ 287 /* bitmask as for DP_I2C_SPEED_CAP */ 288 289 #define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ 290 # define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) 291 # define DP_FRAMING_CHANGE_ENABLE (1 << 1) 292 # define DP_PANEL_SELF_TEST_ENABLE (1 << 7) 293 294 #define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ 295 #define DP_LINK_QUAL_LANE1_SET 0x10c 296 #define DP_LINK_QUAL_LANE2_SET 0x10d 297 #define DP_LINK_QUAL_LANE3_SET 0x10e 298 # define DP_LINK_QUAL_PATTERN_DISABLE 0 299 # define DP_LINK_QUAL_PATTERN_D10_2 1 300 # define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 301 # define DP_LINK_QUAL_PATTERN_PRBS7 3 302 # define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 303 # define DP_LINK_QUAL_PATTERN_HBR2_EYE 5 304 # define DP_LINK_QUAL_PATTERN_MASK 7 305 306 #define DP_TRAINING_LANE0_1_SET2 0x10f 307 #define DP_TRAINING_LANE2_3_SET2 0x110 308 # define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) 309 # define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) 310 # define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) 311 # define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) 312 313 #define DP_MSTM_CTRL 0x111 /* 1.2 */ 314 # define DP_MST_EN (1 << 0) 315 # define DP_UP_REQ_EN (1 << 1) 316 # define DP_UPSTREAM_IS_SRC (1 << 2) 317 318 #define DP_AUDIO_DELAY0 0x112 /* 1.2 */ 319 #define DP_AUDIO_DELAY1 0x113 320 #define DP_AUDIO_DELAY2 0x114 321 322 #define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ 323 # define DP_LINK_RATE_SET_SHIFT 0 324 # define DP_LINK_RATE_SET_MASK (7 << 0) 325 326 #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ 327 # define DP_ALPM_ENABLE (1 << 0) 328 # define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) 329 330 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ 331 # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) 332 # define DP_IRQ_HPD_ENABLE (1 << 1) 333 334 #define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ 335 # define DP_PWR_NOT_NEEDED (1 << 0) 336 337 #define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ 338 # define DP_AUX_FRAME_SYNC_VALID (1 << 0) 339 340 #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ 341 # define DP_PSR_ENABLE (1 << 0) 342 # define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 343 # define DP_PSR_CRC_VERIFICATION (1 << 2) 344 # define DP_PSR_FRAME_CAPTURE (1 << 3) 345 # define DP_PSR_SELECTIVE_UPDATE (1 << 4) 346 # define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS (1 << 5) 347 # define DP_PSR_ENABLE_PSR2 (1 << 6) /* eDP 1.4a */ 348 349 #define DP_ADAPTER_CTRL 0x1a0 350 # define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) 351 352 #define DP_BRANCH_DEVICE_CTRL 0x1a1 353 # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) 354 355 #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 356 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 357 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 358 359 #define DP_SINK_COUNT 0x200 360 /* prior to 1.2 bit 7 was reserved mbz */ 361 # define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) 362 # define DP_SINK_CP_READY (1 << 6) 363 364 #define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 365 # define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 366 # define DP_AUTOMATED_TEST_REQUEST (1 << 1) 367 # define DP_CP_IRQ (1 << 2) 368 # define DP_MCCS_IRQ (1 << 3) 369 # define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ 370 # define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ 371 # define DP_SINK_SPECIFIC_IRQ (1 << 6) 372 373 #define DP_LANE0_1_STATUS 0x202 374 #define DP_LANE2_3_STATUS 0x203 375 # define DP_LANE_CR_DONE (1 << 0) 376 # define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 377 # define DP_LANE_SYMBOL_LOCKED (1 << 2) 378 379 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ 380 DP_LANE_CHANNEL_EQ_DONE | \ 381 DP_LANE_SYMBOL_LOCKED) 382 383 #define DP_LANE_ALIGN_STATUS_UPDATED 0x204 384 385 #define DP_INTERLANE_ALIGN_DONE (1 << 0) 386 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) 387 #define DP_LINK_STATUS_UPDATED (1 << 7) 388 389 #define DP_SINK_STATUS 0x205 390 391 #define DP_RECEIVE_PORT_0_STATUS (1 << 0) 392 #define DP_RECEIVE_PORT_1_STATUS (1 << 1) 393 394 #define DP_ADJUST_REQUEST_LANE0_1 0x206 395 #define DP_ADJUST_REQUEST_LANE2_3 0x207 396 # define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 397 # define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 398 # define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 399 # define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 400 # define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 401 # define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 402 # define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 403 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 404 405 #define DP_TEST_REQUEST 0x218 406 # define DP_TEST_LINK_TRAINING (1 << 0) 407 # define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) 408 # define DP_TEST_LINK_EDID_READ (1 << 2) 409 # define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ 410 # define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ 411 412 #define DP_TEST_LINK_RATE 0x219 413 # define DP_LINK_RATE_162 (0x6) 414 # define DP_LINK_RATE_27 (0xa) 415 416 #define DP_TEST_LANE_COUNT 0x220 417 418 #define DP_TEST_PATTERN 0x221 419 420 #define DP_TEST_CRC_R_CR 0x240 421 #define DP_TEST_CRC_G_Y 0x242 422 #define DP_TEST_CRC_B_CB 0x244 423 424 #define DP_TEST_SINK_MISC 0x246 425 # define DP_TEST_CRC_SUPPORTED (1 << 5) 426 # define DP_TEST_COUNT_MASK 0xf 427 428 #define DP_TEST_RESPONSE 0x260 429 # define DP_TEST_ACK (1 << 0) 430 # define DP_TEST_NAK (1 << 1) 431 # define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) 432 433 #define DP_TEST_EDID_CHECKSUM 0x261 434 435 #define DP_TEST_SINK 0x270 436 # define DP_TEST_SINK_START (1 << 0) 437 438 #define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ 439 # define DP_PAYLOAD_TABLE_UPDATED (1 << 0) 440 # define DP_PAYLOAD_ACT_HANDLED (1 << 1) 441 442 #define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ 443 /* up to ID_SLOT_63 at 0x2ff */ 444 445 #define DP_SOURCE_OUI 0x300 446 #define DP_SINK_OUI 0x400 447 #define DP_BRANCH_OUI 0x500 448 #define DP_BRANCH_ID 0x503 449 #define DP_BRANCH_HW_REV 0x509 450 #define DP_BRANCH_SW_REV 0x50A 451 452 #define DP_SET_POWER 0x600 453 # define DP_SET_POWER_D0 0x1 454 # define DP_SET_POWER_D3 0x2 455 # define DP_SET_POWER_MASK 0x3 456 457 #define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ 458 # define DP_EDP_11 0x00 459 # define DP_EDP_12 0x01 460 # define DP_EDP_13 0x02 461 # define DP_EDP_14 0x03 462 463 #define DP_EDP_GENERAL_CAP_1 0x701 464 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) 465 # define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) 466 # define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) 467 # define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) 468 # define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) 469 # define DP_EDP_FRC_ENABLE_CAP (1 << 5) 470 # define DP_EDP_COLOR_ENGINE_CAP (1 << 6) 471 # define DP_EDP_SET_POWER_CAP (1 << 7) 472 473 #define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 474 # define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) 475 # define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) 476 # define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) 477 # define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) 478 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) 479 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) 480 # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) 481 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) 482 483 #define DP_EDP_GENERAL_CAP_2 0x703 484 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) 485 486 #define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ 487 # define DP_EDP_X_REGION_CAP_MASK (0xf << 0) 488 # define DP_EDP_X_REGION_CAP_SHIFT 0 489 # define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) 490 # define DP_EDP_Y_REGION_CAP_SHIFT 4 491 492 #define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 493 # define DP_EDP_BACKLIGHT_ENABLE (1 << 0) 494 # define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) 495 # define DP_EDP_FRC_ENABLE (1 << 2) 496 # define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) 497 # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) 498 499 #define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 500 # define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) 501 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) 502 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) 503 # define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) 504 # define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) 505 # define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) 506 # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) 507 # define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) 508 # define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) 509 # define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ 510 511 #define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 512 #define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 513 514 #define DP_EDP_PWMGEN_BIT_COUNT 0x724 515 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 516 #define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 517 518 #define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 519 520 #define DP_EDP_BACKLIGHT_FREQ_SET 0x728 521 522 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a 523 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b 524 #define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c 525 526 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d 527 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e 528 #define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f 529 530 #define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 531 #define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 532 533 #define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ 534 #define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ 535 536 #define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ 537 #define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ 538 #define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ 539 #define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ 540 541 #define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ 542 /* 0-5 sink count */ 543 # define DP_SINK_COUNT_CP_READY (1 << 6) 544 545 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ 546 547 #define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ 548 549 #define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ 550 551 #define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ 552 # define DP_PSR_LINK_CRC_ERROR (1 << 0) 553 # define DP_PSR_RFB_STORAGE_ERROR (1 << 1) 554 # define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ 555 556 #define DP_PSR_ESI 0x2007 /* XXX 1.2? */ 557 # define DP_PSR_CAPS_CHANGE (1 << 0) 558 559 #define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ 560 # define DP_PSR_SINK_INACTIVE 0 561 # define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 562 # define DP_PSR_SINK_ACTIVE_RFB 2 563 # define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 564 # define DP_PSR_SINK_ACTIVE_RESYNC 4 565 # define DP_PSR_SINK_INTERNAL_ERROR 7 566 # define DP_PSR_SINK_STATE_MASK 0x07 567 568 #define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ 569 # define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) 570 571 /* DP 1.2 Sideband message defines */ 572 /* peer device type - DP 1.2a Table 2-92 */ 573 #define DP_PEER_DEVICE_NONE 0x0 574 #define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 575 #define DP_PEER_DEVICE_MST_BRANCHING 0x2 576 #define DP_PEER_DEVICE_SST_SINK 0x3 577 #define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 578 579 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ 580 #define DP_LINK_ADDRESS 0x01 581 #define DP_CONNECTION_STATUS_NOTIFY 0x02 582 #define DP_ENUM_PATH_RESOURCES 0x10 583 #define DP_ALLOCATE_PAYLOAD 0x11 584 #define DP_QUERY_PAYLOAD 0x12 585 #define DP_RESOURCE_STATUS_NOTIFY 0x13 586 #define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 587 #define DP_REMOTE_DPCD_READ 0x20 588 #define DP_REMOTE_DPCD_WRITE 0x21 589 #define DP_REMOTE_I2C_READ 0x22 590 #define DP_REMOTE_I2C_WRITE 0x23 591 #define DP_POWER_UP_PHY 0x24 592 #define DP_POWER_DOWN_PHY 0x25 593 #define DP_SINK_EVENT_NOTIFY 0x30 594 #define DP_QUERY_STREAM_ENC_STATUS 0x38 595 596 /* DP 1.2 MST sideband nak reasons - table 2.84 */ 597 #define DP_NAK_WRITE_FAILURE 0x01 598 #define DP_NAK_INVALID_READ 0x02 599 #define DP_NAK_CRC_FAILURE 0x03 600 #define DP_NAK_BAD_PARAM 0x04 601 #define DP_NAK_DEFER 0x05 602 #define DP_NAK_LINK_FAILURE 0x06 603 #define DP_NAK_NO_RESOURCES 0x07 604 #define DP_NAK_DPCD_FAIL 0x08 605 #define DP_NAK_I2C_NAK 0x09 606 #define DP_NAK_ALLOCATE_FAIL 0x0a 607 608 #define MODE_I2C_START 1 609 #define MODE_I2C_WRITE 2 610 #define MODE_I2C_READ 4 611 #define MODE_I2C_STOP 8 612 613 /** 614 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp 615 * aux algorithm 616 * @running: set by the algo indicating whether an i2c is ongoing or whether 617 * the i2c bus is quiescent 618 * @address: i2c target address for the currently ongoing transfer 619 * @aux_ch: driver callback to transfer a single byte of the i2c payload 620 */ 621 struct i2c_algo_dp_aux_data { 622 bool running; 623 u16 address; 624 int (*aux_ch) (device_t adapter, 625 int mode, uint8_t write_byte, 626 uint8_t *read_byte); 627 void *priv; 628 device_t port; 629 }; 630 631 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ 632 #define DP_MST_PHYSICAL_PORT_0 0 633 #define DP_MST_LOGICAL_PORT_0 8 634 635 #define DP_LINK_STATUS_SIZE 6 636 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 637 int lane_count); 638 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 639 int lane_count); 640 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 641 int lane); 642 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 643 int lane); 644 645 #define DP_BRANCH_OUI_HEADER_SIZE 0xc 646 #define DP_RECEIVER_CAP_SIZE 0xf 647 #define EDP_PSR_RECEIVER_CAP_SIZE 2 648 #define EDP_DISPLAY_CTL_CAP_SIZE 3 649 650 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 651 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 652 653 u8 drm_dp_link_rate_to_bw_code(int link_rate); 654 int drm_dp_bw_code_to_link_rate(u8 link_bw); 655 656 struct edp_sdp_header { 657 u8 HB0; /* Secondary Data Packet ID */ 658 u8 HB1; /* Secondary Data Packet Type */ 659 u8 HB2; /* 7:5 reserved, 4:0 revision number */ 660 u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ 661 } __packed; 662 663 #define EDP_SDP_HEADER_REVISION_MASK 0x1F 664 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F 665 666 struct edp_vsc_psr { 667 struct edp_sdp_header sdp_header; 668 u8 DB0; /* Stereo Interface */ 669 u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ 670 u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ 671 u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ 672 u8 DB4; /* CRC value bits 7:0 of the G or Y component */ 673 u8 DB5; /* CRC value bits 15:8 of the G or Y component */ 674 u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ 675 u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ 676 u8 DB8_31[24]; /* Reserved */ 677 } __packed; 678 679 #define EDP_VSC_PSR_STATE_ACTIVE (1<<0) 680 #define EDP_VSC_PSR_UPDATE_RFB (1<<1) 681 #define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) 682 683 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 684 685 static inline int 686 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 687 { 688 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 689 } 690 691 static inline u8 692 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 693 { 694 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 695 } 696 697 static inline bool 698 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 699 { 700 return dpcd[DP_DPCD_REV] >= 0x11 && 701 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 702 } 703 704 static inline bool 705 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 706 { 707 return dpcd[DP_DPCD_REV] >= 0x12 && 708 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 709 } 710 711 /* 712 * DisplayPort AUX channel 713 */ 714 715 /** 716 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 717 * @address: address of the (first) register to access 718 * @request: contains the type of transaction (see DP_AUX_* macros) 719 * @reply: upon completion, contains the reply type of the transaction 720 * @buffer: pointer to a transmission or reception buffer 721 * @size: size of @buffer 722 */ 723 struct drm_dp_aux_msg { 724 unsigned int address; 725 u8 request; 726 u8 reply; 727 char *buffer; 728 size_t size; 729 }; 730 731 /** 732 * struct drm_dp_aux - DisplayPort AUX channel 733 * @name: user-visible name of this AUX channel and the I2C-over-AUX adapter 734 * @ddc: I2C adapter that can be used for I2C-over-AUX communication 735 * @dev: pointer to struct device that is the parent for this AUX channel 736 * @hw_mutex: internal mutex used for locking transfers 737 * @transfer: transfers a message representing a single AUX transaction 738 * 739 * The .dev field should be set to a pointer to the device that implements 740 * the AUX channel. 741 * 742 * The .name field may be used to specify the name of the I2C adapter. If set to 743 * NULL, dev_name() of .dev will be used. 744 * 745 * Drivers provide a hardware-specific implementation of how transactions 746 * are executed via the .transfer() function. A pointer to a drm_dp_aux_msg 747 * structure describing the transaction is passed into this function. Upon 748 * success, the implementation should return the number of payload bytes 749 * that were transferred, or a negative error-code on failure. Helpers 750 * propagate errors from the .transfer() function, with the exception of 751 * the -EBUSY error, which causes a transaction to be retried. On a short, 752 * helpers will return -EPROTO to make it simpler to check for failure. 753 * 754 * An AUX channel can also be used to transport I2C messages to a sink. A 755 * typical application of that is to access an EDID that's present in the 756 * sink device. The .transfer() function can also be used to execute such 757 * transactions. The drm_dp_aux_register() function registers an I2C 758 * adapter that can be passed to drm_probe_ddc(). Upon removal, drivers 759 * should call drm_dp_aux_unregister() to remove the I2C adapter. 760 * The I2C adapter uses long transfers by default; if a partial response is 761 * received, the adapter will drop down to the size given by the partial 762 * response for this transaction only. 763 * 764 * Note that the aux helper code assumes that the .transfer() function 765 * only modifies the reply field of the drm_dp_aux_msg structure. The 766 * retry logic and i2c helpers assume this is the case. 767 */ 768 struct drm_dp_aux { 769 char *name; 770 struct i2c_adapter ddc; 771 struct device *dev; 772 struct lock hw_mutex; 773 ssize_t (*transfer)(struct drm_dp_aux *aux, 774 struct drm_dp_aux_msg *msg); 775 /** 776 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 777 */ 778 unsigned i2c_nack_count; 779 /** 780 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 781 */ 782 unsigned i2c_defer_count; 783 }; 784 785 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 786 void *buffer, size_t size); 787 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 788 void *buffer, size_t size); 789 790 /** 791 * drm_dp_dpcd_readb() - read a single byte from the DPCD 792 * @aux: DisplayPort AUX channel 793 * @offset: address of the register to read 794 * @valuep: location where the value of the register will be stored 795 * 796 * Returns the number of bytes transferred (1) on success, or a negative 797 * error code on failure. 798 */ 799 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 800 unsigned int offset, u8 *valuep) 801 { 802 return drm_dp_dpcd_read(aux, offset, valuep, 1); 803 } 804 805 /** 806 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 807 * @aux: DisplayPort AUX channel 808 * @offset: address of the register to write 809 * @value: value to write to the register 810 * 811 * Returns the number of bytes transferred (1) on success, or a negative 812 * error code on failure. 813 */ 814 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 815 unsigned int offset, u8 value) 816 { 817 return drm_dp_dpcd_write(aux, offset, &value, 1); 818 } 819 820 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 821 u8 status[DP_LINK_STATUS_SIZE]); 822 823 /* 824 * DisplayPort link 825 */ 826 #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) 827 828 struct drm_dp_link { 829 unsigned char revision; 830 unsigned int rate; 831 unsigned int num_lanes; 832 unsigned long capabilities; 833 }; 834 835 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link); 836 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link); 837 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link); 838 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link); 839 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 840 const u8 port_cap[4]); 841 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 842 const u8 port_cap[4]); 843 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 844 void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 845 const u8 port_cap[4], struct drm_dp_aux *aux); 846 847 void drm_dp_aux_init(struct drm_dp_aux *aux); 848 int drm_dp_aux_register(struct drm_dp_aux *aux); 849 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 850 851 #endif /* _DRM_DP_HELPER_H_ */ 852