1 /* 2 * Copyright © 2007-2008 Intel Corporation 3 * Jesse Barnes <jesse.barnes@intel.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef __DRM_EDID_H__ 24 #define __DRM_EDID_H__ 25 26 #include <linux/types.h> 27 28 struct drm_device; 29 struct i2c_adapter; 30 31 #define EDID_LENGTH 128 32 #define DDC_ADDR 0x50 33 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ 34 35 #define CEA_EXT 0x02 36 #define VTB_EXT 0x10 37 #define DI_EXT 0x40 38 #define LS_EXT 0x50 39 #define MI_EXT 0x60 40 #define DISPLAYID_EXT 0x70 41 42 struct est_timings { 43 u8 t1; 44 u8 t2; 45 u8 mfg_rsvd; 46 } __attribute__((packed)); 47 48 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 49 #define EDID_TIMING_ASPECT_SHIFT 6 50 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 51 52 /* need to add 60 */ 53 #define EDID_TIMING_VFREQ_SHIFT 0 54 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 55 56 struct std_timing { 57 u8 hsize; /* need to multiply by 8 then add 248 */ 58 u8 vfreq_aspect; 59 } __attribute__((packed)); 60 61 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 62 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 63 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 64 #define DRM_EDID_PT_STEREO (1 << 5) 65 #define DRM_EDID_PT_INTERLACED (1 << 7) 66 67 /* If detailed data is pixel timing */ 68 struct detailed_pixel_timing { 69 u8 hactive_lo; 70 u8 hblank_lo; 71 u8 hactive_hblank_hi; 72 u8 vactive_lo; 73 u8 vblank_lo; 74 u8 vactive_vblank_hi; 75 u8 hsync_offset_lo; 76 u8 hsync_pulse_width_lo; 77 u8 vsync_offset_pulse_width_lo; 78 u8 hsync_vsync_offset_pulse_width_hi; 79 u8 width_mm_lo; 80 u8 height_mm_lo; 81 u8 width_height_mm_hi; 82 u8 hborder; 83 u8 vborder; 84 u8 misc; 85 } __attribute__((packed)); 86 87 /* If it's not pixel timing, it'll be one of the below */ 88 struct detailed_data_string { 89 u8 str[13]; 90 } __attribute__((packed)); 91 92 struct detailed_data_monitor_range { 93 u8 min_vfreq; 94 u8 max_vfreq; 95 u8 min_hfreq_khz; 96 u8 max_hfreq_khz; 97 u8 pixel_clock_mhz; /* need to multiply by 10 */ 98 u8 flags; 99 union { 100 struct { 101 u8 reserved; 102 u8 hfreq_start_khz; /* need to multiply by 2 */ 103 u8 c; /* need to divide by 2 */ 104 __le16 m; 105 u8 k; 106 u8 j; /* need to divide by 2 */ 107 } __attribute__((packed)) gtf2; 108 struct { 109 u8 version; 110 u8 data1; /* high 6 bits: extra clock resolution */ 111 u8 data2; /* plus low 2 of above: max hactive */ 112 u8 supported_aspects; 113 u8 flags; /* preferred aspect and blanking support */ 114 u8 supported_scalings; 115 u8 preferred_refresh; 116 } __attribute__((packed)) cvt; 117 } formula; 118 } __attribute__((packed)); 119 120 struct detailed_data_wpindex { 121 u8 white_yx_lo; /* Lower 2 bits each */ 122 u8 white_x_hi; 123 u8 white_y_hi; 124 u8 gamma; /* need to divide by 100 then add 1 */ 125 } __attribute__((packed)); 126 127 struct detailed_data_color_point { 128 u8 windex1; 129 u8 wpindex1[3]; 130 u8 windex2; 131 u8 wpindex2[3]; 132 } __attribute__((packed)); 133 134 struct cvt_timing { 135 u8 code[3]; 136 } __attribute__((packed)); 137 138 struct detailed_non_pixel { 139 u8 pad1; 140 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 141 fb=color point data, fa=standard timing data, 142 f9=undefined, f8=mfg. reserved */ 143 u8 pad2; 144 union { 145 struct detailed_data_string str; 146 struct detailed_data_monitor_range range; 147 struct detailed_data_wpindex color; 148 struct std_timing timings[6]; 149 struct cvt_timing cvt[4]; 150 } data; 151 } __attribute__((packed)); 152 153 #define EDID_DETAIL_EST_TIMINGS 0xf7 154 #define EDID_DETAIL_CVT_3BYTE 0xf8 155 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 156 #define EDID_DETAIL_STD_MODES 0xfa 157 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 158 #define EDID_DETAIL_MONITOR_NAME 0xfc 159 #define EDID_DETAIL_MONITOR_RANGE 0xfd 160 #define EDID_DETAIL_MONITOR_STRING 0xfe 161 #define EDID_DETAIL_MONITOR_SERIAL 0xff 162 163 struct detailed_timing { 164 __le16 pixel_clock; /* need to multiply by 10 KHz */ 165 union { 166 struct detailed_pixel_timing pixel_data; 167 struct detailed_non_pixel other_data; 168 } data; 169 } __attribute__((packed)); 170 171 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 172 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 173 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 174 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 175 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 176 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 177 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 178 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) 179 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) 180 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) 181 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) 182 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) 183 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) 184 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) 185 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) 186 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) 187 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0) 188 #define DRM_EDID_DIGITAL_TYPE_DVI (1) 189 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) 190 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) 191 #define DRM_EDID_DIGITAL_TYPE_MDDI (4) 192 #define DRM_EDID_DIGITAL_TYPE_DP (5) 193 194 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 195 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 196 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 197 /* If analog */ 198 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 199 /* If digital */ 200 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 201 #define DRM_EDID_FEATURE_RGB (0 << 3) 202 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 203 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 204 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 205 206 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 207 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 208 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 209 210 #define DRM_EDID_HDMI_DC_48 (1 << 6) 211 #define DRM_EDID_HDMI_DC_36 (1 << 5) 212 #define DRM_EDID_HDMI_DC_30 (1 << 4) 213 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 214 215 /* ELD Header Block */ 216 #define DRM_ELD_HEADER_BLOCK_SIZE 4 217 218 #define DRM_ELD_VER 0 219 # define DRM_ELD_VER_SHIFT 3 220 # define DRM_ELD_VER_MASK (0x1f << 3) 221 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ 222 # define DRM_ELD_VER_CANNED (0x1f << 3) 223 224 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ 225 226 /* ELD Baseline Block for ELD_Ver == 2 */ 227 #define DRM_ELD_CEA_EDID_VER_MNL 4 228 # define DRM_ELD_CEA_EDID_VER_SHIFT 5 229 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) 230 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) 231 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) 232 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) 233 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) 234 # define DRM_ELD_MNL_SHIFT 0 235 # define DRM_ELD_MNL_MASK (0x1f << 0) 236 237 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5 238 # define DRM_ELD_SAD_COUNT_SHIFT 4 239 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4) 240 # define DRM_ELD_CONN_TYPE_SHIFT 2 241 # define DRM_ELD_CONN_TYPE_MASK (3 << 2) 242 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2) 243 # define DRM_ELD_CONN_TYPE_DP (1 << 2) 244 # define DRM_ELD_SUPPORTS_AI (1 << 1) 245 # define DRM_ELD_SUPPORTS_HDCP (1 << 0) 246 247 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ 248 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ 249 250 #define DRM_ELD_SPEAKER 7 251 # define DRM_ELD_SPEAKER_RLRC (1 << 6) 252 # define DRM_ELD_SPEAKER_FLRC (1 << 5) 253 # define DRM_ELD_SPEAKER_RC (1 << 4) 254 # define DRM_ELD_SPEAKER_RLR (1 << 3) 255 # define DRM_ELD_SPEAKER_FC (1 << 2) 256 # define DRM_ELD_SPEAKER_LFE (1 << 1) 257 # define DRM_ELD_SPEAKER_FLR (1 << 0) 258 259 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ 260 # define DRM_ELD_PORT_ID_LEN 8 261 262 #define DRM_ELD_MANUFACTURER_NAME0 16 263 #define DRM_ELD_MANUFACTURER_NAME1 17 264 265 #define DRM_ELD_PRODUCT_CODE0 18 266 #define DRM_ELD_PRODUCT_CODE1 19 267 268 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ 269 270 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) 271 272 struct edid { 273 u8 header[8]; 274 /* Vendor & product info */ 275 u8 mfg_id[2]; 276 u8 prod_code[2]; 277 u32 serial; /* FIXME: byte order */ 278 u8 mfg_week; 279 u8 mfg_year; 280 /* EDID version */ 281 u8 version; 282 u8 revision; 283 /* Display info: */ 284 u8 input; 285 u8 width_cm; 286 u8 height_cm; 287 u8 gamma; 288 u8 features; 289 /* Color characteristics */ 290 u8 red_green_lo; 291 u8 black_white_lo; 292 u8 red_x; 293 u8 red_y; 294 u8 green_x; 295 u8 green_y; 296 u8 blue_x; 297 u8 blue_y; 298 u8 white_x; 299 u8 white_y; 300 /* Est. timings and mfg rsvd timings*/ 301 struct est_timings established_timings; 302 /* Standard timings 1-8*/ 303 struct std_timing standard_timings[8]; 304 /* Detailing timings 1-4 */ 305 struct detailed_timing detailed_timings[4]; 306 /* Number of 128 byte ext. blocks */ 307 u8 extensions; 308 /* Checksum */ 309 u8 checksum; 310 } __attribute__((packed)); 311 312 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 313 314 /* Short Audio Descriptor */ 315 struct cea_sad { 316 u8 format; 317 u8 channels; /* max number of channels - 1 */ 318 u8 freq; 319 u8 byte2; /* meaning depends on format */ 320 }; 321 322 struct drm_encoder; 323 struct drm_connector; 324 struct drm_display_mode; 325 struct hdmi_avi_infoframe; 326 struct hdmi_vendor_infoframe; 327 328 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); 329 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); 330 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); 331 int drm_av_sync_delay(struct drm_connector *connector, 332 const struct drm_display_mode *mode); 333 struct drm_connector *drm_select_eld(struct drm_encoder *encoder); 334 335 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE 336 int drm_load_edid_firmware(struct drm_connector *connector); 337 #else 338 static inline int drm_load_edid_firmware(struct drm_connector *connector) 339 { 340 return 0; 341 } 342 #endif 343 344 int 345 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 346 const struct drm_display_mode *mode); 347 int 348 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 349 const struct drm_display_mode *mode); 350 351 /** 352 * drm_eld_mnl - Get ELD monitor name length in bytes. 353 * @eld: pointer to an eld memory structure with mnl set 354 */ 355 static inline int drm_eld_mnl(const uint8_t *eld) 356 { 357 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; 358 } 359 360 /** 361 * drm_eld_sad - Get ELD SAD structures. 362 * @eld: pointer to an eld memory structure with sad_count set 363 */ 364 static inline const uint8_t *drm_eld_sad(const uint8_t *eld) 365 { 366 unsigned int ver, mnl; 367 368 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; 369 if (ver != 2 && ver != 31) 370 return NULL; 371 372 mnl = drm_eld_mnl(eld); 373 if (mnl > 16) 374 return NULL; 375 376 return eld + DRM_ELD_CEA_SAD(mnl, 0); 377 } 378 379 /** 380 * drm_eld_sad_count - Get ELD SAD count. 381 * @eld: pointer to an eld memory structure with sad_count set 382 */ 383 static inline int drm_eld_sad_count(const uint8_t *eld) 384 { 385 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> 386 DRM_ELD_SAD_COUNT_SHIFT; 387 } 388 389 /** 390 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes 391 * @eld: pointer to an eld memory structure with mnl and sad_count set 392 * 393 * This is a helper for determining the payload size of the baseline block, in 394 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. 395 */ 396 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) 397 { 398 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + 399 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; 400 } 401 402 /** 403 * drm_eld_size - Get ELD size in bytes 404 * @eld: pointer to a complete eld memory structure 405 * 406 * The returned value does not include the vendor block. It's vendor specific, 407 * and comprises of the remaining bytes in the ELD memory buffer after 408 * drm_eld_size() bytes of header and baseline block. 409 * 410 * The returned value is guaranteed to be a multiple of 4. 411 */ 412 static inline int drm_eld_size(const uint8_t *eld) 413 { 414 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; 415 } 416 417 /** 418 * drm_eld_get_conn_type - Get device type hdmi/dp connected 419 * @eld: pointer to an ELD memory structure 420 * 421 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to 422 * identify the display type connected. 423 */ 424 static inline u8 drm_eld_get_conn_type(const uint8_t *eld) 425 { 426 return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; 427 } 428 429 bool drm_probe_ddc(struct i2c_adapter *adapter); 430 struct edid *drm_do_get_edid(struct drm_connector *connector, 431 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 432 size_t len), 433 void *data); 434 struct edid *drm_get_edid(struct drm_connector *connector, 435 struct i2c_adapter *adapter); 436 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 437 struct i2c_adapter *adapter); 438 struct edid *drm_edid_duplicate(const struct edid *edid); 439 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); 440 441 u8 drm_match_cea_mode(const struct drm_display_mode *to_match); 442 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code); 443 bool drm_detect_hdmi_monitor(struct edid *edid); 444 bool drm_detect_monitor_audio(struct edid *edid); 445 bool drm_rgb_quant_range_selectable(struct edid *edid); 446 int drm_add_modes_noedid(struct drm_connector *connector, 447 int hdisplay, int vdisplay); 448 void drm_set_preferred_mode(struct drm_connector *connector, 449 int hpref, int vpref); 450 451 int drm_edid_header_is_valid(const u8 *raw_edid); 452 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 453 bool *edid_corrupt); 454 bool drm_edid_is_valid(struct edid *edid); 455 void drm_edid_get_monitor_name(struct edid *edid, char *name, 456 int buflen); 457 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 458 int hsize, int vsize, int fresh, 459 bool rb); 460 461 #endif /* __DRM_EDID_H__ */ 462