1 /* 2 * Copyright 2013 Intel Corporation 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 #ifndef _I915_PCIIDS_H 26 #define _I915_PCIIDS_H 27 28 /* 29 * A pci_device_id struct { 30 * __u32 vendor, device; 31 * __u32 subvendor, subdevice; 32 * __u32 class, class_mask; 33 * kernel_ulong_t driver_data; 34 * }; 35 * Don't use C99 here because "class" is reserved and we want to 36 * give userspace flexibility. 37 */ 38 #define INTEL_VGA_DEVICE(id, info) { \ 39 0x8086, id, \ 40 ~0, ~0, \ 41 0x030000, 0xff0000, \ 42 (unsigned long) info } 43 44 #define INTEL_QUANTA_VGA_DEVICE(info) { \ 45 0x8086, 0x16a, \ 46 0x152d, 0x8990, \ 47 0x030000, 0xff0000, \ 48 (unsigned long) info } 49 50 #define INTEL_I830_IDS(info) \ 51 INTEL_VGA_DEVICE(0x3577, info) 52 53 #define INTEL_I845G_IDS(info) \ 54 INTEL_VGA_DEVICE(0x2562, info) 55 56 #define INTEL_I85X_IDS(info) \ 57 INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \ 58 INTEL_VGA_DEVICE(0x358e, info) 59 60 #define INTEL_I865G_IDS(info) \ 61 INTEL_VGA_DEVICE(0x2572, info) /* I865_G */ 62 63 #define INTEL_I915G_IDS(info) \ 64 INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \ 65 INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */ 66 67 #define INTEL_I915GM_IDS(info) \ 68 INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */ 69 70 #define INTEL_I945G_IDS(info) \ 71 INTEL_VGA_DEVICE(0x2772, info) /* I945_G */ 72 73 #define INTEL_I945GM_IDS(info) \ 74 INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \ 75 INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */ 76 77 #define INTEL_I965G_IDS(info) \ 78 INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \ 79 INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \ 80 INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \ 81 INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */ 82 83 #define INTEL_G33_IDS(info) \ 84 INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \ 85 INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \ 86 INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */ 87 88 #define INTEL_I965GM_IDS(info) \ 89 INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \ 90 INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */ 91 92 #define INTEL_GM45_IDS(info) \ 93 INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */ 94 95 #define INTEL_G45_IDS(info) \ 96 INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \ 97 INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \ 98 INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \ 99 INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \ 100 INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \ 101 INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */ 102 103 #define INTEL_PINEVIEW_IDS(info) \ 104 INTEL_VGA_DEVICE(0xa001, info), \ 105 INTEL_VGA_DEVICE(0xa011, info) 106 107 #define INTEL_IRONLAKE_D_IDS(info) \ 108 INTEL_VGA_DEVICE(0x0042, info) 109 110 #define INTEL_IRONLAKE_M_IDS(info) \ 111 INTEL_VGA_DEVICE(0x0046, info) 112 113 #define INTEL_SNB_D_GT1_IDS(info) \ 114 INTEL_VGA_DEVICE(0x0102, info), \ 115 INTEL_VGA_DEVICE(0x010A, info) 116 117 #define INTEL_SNB_D_GT2_IDS(info) \ 118 INTEL_VGA_DEVICE(0x0112, info), \ 119 INTEL_VGA_DEVICE(0x0122, info) 120 121 #define INTEL_SNB_D_IDS(info) \ 122 INTEL_SNB_D_GT1_IDS(info), \ 123 INTEL_SNB_D_GT2_IDS(info) 124 125 #define INTEL_SNB_M_GT1_IDS(info) \ 126 INTEL_VGA_DEVICE(0x0106, info) 127 128 #define INTEL_SNB_M_GT2_IDS(info) \ 129 INTEL_VGA_DEVICE(0x0116, info), \ 130 INTEL_VGA_DEVICE(0x0126, info) 131 132 #define INTEL_SNB_M_IDS(info) \ 133 INTEL_SNB_M_GT1_IDS(info), \ 134 INTEL_SNB_M_GT2_IDS(info) 135 136 #define INTEL_IVB_M_GT1_IDS(info) \ 137 INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */ 138 139 #define INTEL_IVB_M_GT2_IDS(info) \ 140 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ 141 142 #define INTEL_IVB_M_IDS(info) \ 143 INTEL_IVB_M_GT1_IDS(info), \ 144 INTEL_IVB_M_GT2_IDS(info) 145 146 #define INTEL_IVB_D_GT1_IDS(info) \ 147 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ 148 INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */ 149 150 #define INTEL_IVB_D_GT2_IDS(info) \ 151 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ 152 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ 153 154 #define INTEL_IVB_D_IDS(info) \ 155 INTEL_IVB_D_GT1_IDS(info), \ 156 INTEL_IVB_D_GT2_IDS(info) 157 158 #define INTEL_IVB_Q_IDS(info) \ 159 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ 160 161 #define INTEL_HSW_GT1_IDS(info) \ 162 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ 163 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ 164 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ 165 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ 166 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ 167 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ 168 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ 169 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ 170 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ 171 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ 172 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ 173 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ 174 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ 175 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ 176 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ 177 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ 178 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ 179 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ 180 INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ 181 INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */ 182 183 #define INTEL_HSW_GT2_IDS(info) \ 184 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ 185 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ 186 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ 187 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ 188 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ 189 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ 190 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ 191 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ 192 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ 193 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ 194 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ 195 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ 196 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ 197 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ 198 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ 199 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ 200 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ 201 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ 202 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ 203 INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ 204 INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */ 205 206 #define INTEL_HSW_GT3_IDS(info) \ 207 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ 208 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ 209 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ 210 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ 211 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ 212 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ 213 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ 214 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ 215 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ 216 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ 217 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ 218 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ 219 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ 220 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ 221 INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \ 222 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ 223 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ 224 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ 225 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ 226 227 #define INTEL_HSW_IDS(info) \ 228 INTEL_HSW_GT1_IDS(info), \ 229 INTEL_HSW_GT2_IDS(info), \ 230 INTEL_HSW_GT3_IDS(info) 231 232 #define INTEL_VLV_IDS(info) \ 233 INTEL_VGA_DEVICE(0x0f30, info), \ 234 INTEL_VGA_DEVICE(0x0f31, info), \ 235 INTEL_VGA_DEVICE(0x0f32, info), \ 236 INTEL_VGA_DEVICE(0x0f33, info), \ 237 INTEL_VGA_DEVICE(0x0157, info), \ 238 INTEL_VGA_DEVICE(0x0155, info) 239 240 #define INTEL_BDW_GT1_IDS(info) \ 241 INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ 242 INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ 243 INTEL_VGA_DEVICE(0x160B, info), /* GT1 Iris */ \ 244 INTEL_VGA_DEVICE(0x160E, info), /* GT1 ULX */ \ 245 INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ 246 INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */ 247 248 #define INTEL_BDW_GT2_IDS(info) \ 249 INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ 250 INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ 251 INTEL_VGA_DEVICE(0x161B, info), /* GT2 ULT */ \ 252 INTEL_VGA_DEVICE(0x161E, info), /* GT2 ULX */ \ 253 INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ 254 INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ 255 256 #define INTEL_BDW_GT3_IDS(info) \ 257 INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ 258 INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ 259 INTEL_VGA_DEVICE(0x162B, info), /* Iris */ \ 260 INTEL_VGA_DEVICE(0x162E, info), /* ULX */\ 261 INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ 262 INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ 263 264 #define INTEL_BDW_RSVD_IDS(info) \ 265 INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \ 266 INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ 267 INTEL_VGA_DEVICE(0x163B, info), /* Iris */ \ 268 INTEL_VGA_DEVICE(0x163E, info), /* ULX */ \ 269 INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ 270 INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ 271 272 #define INTEL_BDW_IDS(info) \ 273 INTEL_BDW_GT1_IDS(info), \ 274 INTEL_BDW_GT2_IDS(info), \ 275 INTEL_BDW_GT3_IDS(info), \ 276 INTEL_BDW_RSVD_IDS(info) 277 278 #define INTEL_CHV_IDS(info) \ 279 INTEL_VGA_DEVICE(0x22b0, info), \ 280 INTEL_VGA_DEVICE(0x22b1, info), \ 281 INTEL_VGA_DEVICE(0x22b2, info), \ 282 INTEL_VGA_DEVICE(0x22b3, info) 283 284 #define INTEL_SKL_GT1_IDS(info) \ 285 INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ 286 INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ 287 INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ 288 INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ 289 INTEL_VGA_DEVICE(0x190A, info) /* SRV GT1 */ 290 291 #define INTEL_SKL_GT2_IDS(info) \ 292 INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ 293 INTEL_VGA_DEVICE(0x1921, info), /* ULT GT2F */ \ 294 INTEL_VGA_DEVICE(0x191E, info), /* ULX GT2 */ \ 295 INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ 296 INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ 297 INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ 298 INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ 299 300 #define INTEL_SKL_GT3_IDS(info) \ 301 INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ 302 INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3 */ \ 303 INTEL_VGA_DEVICE(0x1927, info), /* ULT GT3 */ \ 304 INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3 */ \ 305 INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3 */ 306 307 #define INTEL_SKL_GT4_IDS(info) \ 308 INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ 309 INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4 */ \ 310 INTEL_VGA_DEVICE(0x193D, info), /* WKS GT4 */ \ 311 INTEL_VGA_DEVICE(0x192A, info), /* SRV GT4 */ \ 312 INTEL_VGA_DEVICE(0x193A, info) /* SRV GT4e */ 313 314 #define INTEL_SKL_IDS(info) \ 315 INTEL_SKL_GT1_IDS(info), \ 316 INTEL_SKL_GT2_IDS(info), \ 317 INTEL_SKL_GT3_IDS(info), \ 318 INTEL_SKL_GT4_IDS(info) 319 320 #define INTEL_BXT_IDS(info) \ 321 INTEL_VGA_DEVICE(0x0A84, info), \ 322 INTEL_VGA_DEVICE(0x1A84, info), \ 323 INTEL_VGA_DEVICE(0x1A85, info), \ 324 INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \ 325 INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */ 326 327 #define INTEL_GLK_IDS(info) \ 328 INTEL_VGA_DEVICE(0x3184, info), \ 329 INTEL_VGA_DEVICE(0x3185, info) 330 331 #define INTEL_KBL_GT1_IDS(info) \ 332 INTEL_VGA_DEVICE(0x5913, info), /* ULT GT1.5 */ \ 333 INTEL_VGA_DEVICE(0x5915, info), /* ULX GT1.5 */ \ 334 INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ 335 INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ 336 INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ 337 INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \ 338 INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \ 339 INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */ 340 341 #define INTEL_KBL_GT2_IDS(info) \ 342 INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ 343 INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ 344 INTEL_VGA_DEVICE(0x5921, info), /* ULT GT2F */ \ 345 INTEL_VGA_DEVICE(0x591E, info), /* ULX GT2 */ \ 346 INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ 347 INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ 348 INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \ 349 INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ 350 351 #define INTEL_KBL_GT3_IDS(info) \ 352 INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ 353 INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \ 354 INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */ 355 356 #define INTEL_KBL_GT4_IDS(info) \ 357 INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */ 358 359 /* AML/KBL Y GT2 */ 360 #define INTEL_AML_KBL_GT2_IDS(info) \ 361 INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \ 362 INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */ 363 364 /* AML/CFL Y GT2 */ 365 #define INTEL_AML_CFL_GT2_IDS(info) \ 366 INTEL_VGA_DEVICE(0x87CA, info) 367 368 /* CML GT1 */ 369 #define INTEL_CML_GT1_IDS(info) \ 370 INTEL_VGA_DEVICE(0x9BA5, info), \ 371 INTEL_VGA_DEVICE(0x9BA8, info), \ 372 INTEL_VGA_DEVICE(0x9BA4, info), \ 373 INTEL_VGA_DEVICE(0x9BA2, info) 374 375 #define INTEL_CML_U_GT1_IDS(info) \ 376 INTEL_VGA_DEVICE(0x9B21, info), \ 377 INTEL_VGA_DEVICE(0x9BAA, info), \ 378 INTEL_VGA_DEVICE(0x9BAC, info) 379 380 /* CML GT2 */ 381 #define INTEL_CML_GT2_IDS(info) \ 382 INTEL_VGA_DEVICE(0x9BC5, info), \ 383 INTEL_VGA_DEVICE(0x9BC8, info), \ 384 INTEL_VGA_DEVICE(0x9BC4, info), \ 385 INTEL_VGA_DEVICE(0x9BC2, info), \ 386 INTEL_VGA_DEVICE(0x9BC6, info), \ 387 INTEL_VGA_DEVICE(0x9BE6, info), \ 388 INTEL_VGA_DEVICE(0x9BF6, info) 389 390 #define INTEL_CML_U_GT2_IDS(info) \ 391 INTEL_VGA_DEVICE(0x9B41, info), \ 392 INTEL_VGA_DEVICE(0x9BCA, info), \ 393 INTEL_VGA_DEVICE(0x9BCC, info) 394 395 #define INTEL_KBL_IDS(info) \ 396 INTEL_KBL_GT1_IDS(info), \ 397 INTEL_KBL_GT2_IDS(info), \ 398 INTEL_KBL_GT3_IDS(info), \ 399 INTEL_KBL_GT4_IDS(info) 400 401 /* CFL S */ 402 #define INTEL_CFL_S_GT1_IDS(info) \ 403 INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \ 404 INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \ 405 INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */ 406 407 #define INTEL_CFL_S_GT2_IDS(info) \ 408 INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \ 409 INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \ 410 INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \ 411 INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \ 412 INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */ 413 414 /* CFL H */ 415 #define INTEL_CFL_H_GT1_IDS(info) \ 416 INTEL_VGA_DEVICE(0x3E9C, info) 417 418 #define INTEL_CFL_H_GT2_IDS(info) \ 419 INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \ 420 INTEL_VGA_DEVICE(0x3E94, info) /* Halo GT2 */ 421 422 /* CFL U GT2 */ 423 #define INTEL_CFL_U_GT2_IDS(info) \ 424 INTEL_VGA_DEVICE(0x3EA9, info) 425 426 /* CFL U GT3 */ 427 #define INTEL_CFL_U_GT3_IDS(info) \ 428 INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \ 429 INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \ 430 INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ 431 INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */ 432 433 /* WHL/CFL U GT1 */ 434 #define INTEL_WHL_U_GT1_IDS(info) \ 435 INTEL_VGA_DEVICE(0x3EA1, info), \ 436 INTEL_VGA_DEVICE(0x3EA4, info) 437 438 /* WHL/CFL U GT2 */ 439 #define INTEL_WHL_U_GT2_IDS(info) \ 440 INTEL_VGA_DEVICE(0x3EA0, info), \ 441 INTEL_VGA_DEVICE(0x3EA3, info) 442 443 /* WHL/CFL U GT3 */ 444 #define INTEL_WHL_U_GT3_IDS(info) \ 445 INTEL_VGA_DEVICE(0x3EA2, info) 446 447 #define INTEL_CFL_IDS(info) \ 448 INTEL_CFL_S_GT1_IDS(info), \ 449 INTEL_CFL_S_GT2_IDS(info), \ 450 INTEL_CFL_H_GT1_IDS(info), \ 451 INTEL_CFL_H_GT2_IDS(info), \ 452 INTEL_CFL_U_GT2_IDS(info), \ 453 INTEL_CFL_U_GT3_IDS(info), \ 454 INTEL_WHL_U_GT1_IDS(info), \ 455 INTEL_WHL_U_GT2_IDS(info), \ 456 INTEL_WHL_U_GT3_IDS(info), \ 457 INTEL_AML_CFL_GT2_IDS(info), \ 458 INTEL_CML_GT1_IDS(info), \ 459 INTEL_CML_GT2_IDS(info), \ 460 INTEL_CML_U_GT1_IDS(info), \ 461 INTEL_CML_U_GT2_IDS(info) 462 463 /* CNL U 2+2 */ 464 #define INTEL_CNL_U_GT2_IDS(info) \ 465 INTEL_VGA_DEVICE(0x5A52, info), \ 466 INTEL_VGA_DEVICE(0x5A5A, info), \ 467 INTEL_VGA_DEVICE(0x5A42, info), \ 468 INTEL_VGA_DEVICE(0x5A4A, info) 469 470 /* CNL Y 2+2 */ 471 #define INTEL_CNL_Y_GT2_IDS(info) \ 472 INTEL_VGA_DEVICE(0x5A51, info), \ 473 INTEL_VGA_DEVICE(0x5A59, info), \ 474 INTEL_VGA_DEVICE(0x5A41, info), \ 475 INTEL_VGA_DEVICE(0x5A49, info), \ 476 INTEL_VGA_DEVICE(0x5A71, info), \ 477 INTEL_VGA_DEVICE(0x5A79, info) 478 479 #define INTEL_CNL_IDS(info) \ 480 INTEL_CNL_U_GT2_IDS(info), \ 481 INTEL_CNL_Y_GT2_IDS(info) 482 483 #endif /* _I915_PCIIDS_H */ 484