1 /* 2 * Copyright 2013 Intel Corporation 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 #ifndef _I915_PCIIDS_H 26 #define _I915_PCIIDS_H 27 28 /* 29 * A pci_device_id struct { 30 * __u32 vendor, device; 31 * __u32 subvendor, subdevice; 32 * __u32 class, class_mask; 33 * kernel_ulong_t driver_data; 34 * }; 35 * Don't use C99 here because "class" is reserved and we want to 36 * give userspace flexibility. 37 */ 38 #define INTEL_VGA_DEVICE(id, info) { \ 39 .class = PCI_BASE_CLASS_DISPLAY << 16, \ 40 .class_mask = 0xff0000, \ 41 .vendor = 0x8086, \ 42 .device = id, \ 43 .subvendor = PCI_ANY_ID, \ 44 .subdevice = PCI_ANY_ID, \ 45 .driver_data = (unsigned long) info } 46 47 #define INTEL_QUANTA_VGA_DEVICE(info) { \ 48 .class = PCI_BASE_CLASS_DISPLAY << 16, \ 49 .class_mask = 0xff0000, \ 50 .vendor = 0x8086, \ 51 .device = 0x16a, \ 52 .subvendor = 0x152d, \ 53 .subdevice = 0x8990, \ 54 .driver_data = (unsigned long) info } 55 56 #define INTEL_I830_IDS(info) \ 57 INTEL_VGA_DEVICE(0x3577, info) 58 59 #define INTEL_I845G_IDS(info) \ 60 INTEL_VGA_DEVICE(0x2562, info) 61 62 #define INTEL_I85X_IDS(info) \ 63 INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \ 64 INTEL_VGA_DEVICE(0x358e, info) 65 66 #define INTEL_I865G_IDS(info) \ 67 INTEL_VGA_DEVICE(0x2572, info) /* I865_G */ 68 69 #define INTEL_I915G_IDS(info) \ 70 INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \ 71 INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */ 72 73 #define INTEL_I915GM_IDS(info) \ 74 INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */ 75 76 #define INTEL_I945G_IDS(info) \ 77 INTEL_VGA_DEVICE(0x2772, info) /* I945_G */ 78 79 #define INTEL_I945GM_IDS(info) \ 80 INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \ 81 INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */ 82 83 #define INTEL_I965G_IDS(info) \ 84 INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \ 85 INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \ 86 INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \ 87 INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */ 88 89 #define INTEL_G33_IDS(info) \ 90 INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \ 91 INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \ 92 INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */ 93 94 #define INTEL_I965GM_IDS(info) \ 95 INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \ 96 INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */ 97 98 #define INTEL_GM45_IDS(info) \ 99 INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */ 100 101 #define INTEL_G45_IDS(info) \ 102 INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \ 103 INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \ 104 INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \ 105 INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \ 106 INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \ 107 INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */ 108 109 #define INTEL_PINEVIEW_IDS(info) \ 110 INTEL_VGA_DEVICE(0xa001, info), \ 111 INTEL_VGA_DEVICE(0xa011, info) 112 113 #define INTEL_IRONLAKE_D_IDS(info) \ 114 INTEL_VGA_DEVICE(0x0042, info) 115 116 #define INTEL_IRONLAKE_M_IDS(info) \ 117 INTEL_VGA_DEVICE(0x0046, info) 118 119 #define INTEL_SNB_D_IDS(info) \ 120 INTEL_VGA_DEVICE(0x0102, info), \ 121 INTEL_VGA_DEVICE(0x0112, info), \ 122 INTEL_VGA_DEVICE(0x0122, info), \ 123 INTEL_VGA_DEVICE(0x010A, info) 124 125 #define INTEL_SNB_M_IDS(info) \ 126 INTEL_VGA_DEVICE(0x0106, info), \ 127 INTEL_VGA_DEVICE(0x0116, info), \ 128 INTEL_VGA_DEVICE(0x0126, info) 129 130 #define INTEL_IVB_M_IDS(info) \ 131 INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \ 132 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ 133 134 #define INTEL_IVB_D_IDS(info) \ 135 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ 136 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ 137 INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \ 138 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ 139 140 #define INTEL_IVB_Q_IDS(info) \ 141 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ 142 143 #define INTEL_HSW_D_IDS(info) \ 144 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ 145 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ 146 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ 147 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \ 148 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \ 149 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \ 150 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ 151 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ 152 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ 153 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ 154 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ 155 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ 156 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ 157 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ 158 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ 159 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ 160 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ 161 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ 162 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ 163 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ 164 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ 165 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ 166 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ 167 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ 168 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ 169 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ 170 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ 171 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ 172 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ 173 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ 174 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \ 175 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \ 176 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ 177 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ 178 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ 179 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ 180 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ 181 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ 182 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ 183 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ 184 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ 185 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ 186 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \ 187 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \ 188 INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \ 189 190 #define INTEL_HSW_M_IDS(info) \ 191 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ 192 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ 193 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \ 194 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ 195 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ 196 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ 197 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ 198 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ 199 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ 200 INTEL_VGA_DEVICE(0x0A0E, info), /* ULX GT1 mobile */ \ 201 INTEL_VGA_DEVICE(0x0A1E, info), /* ULX GT2 mobile */ \ 202 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \ 203 INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ 204 INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ 205 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */ 206 207 #define INTEL_VLV_M_IDS(info) \ 208 INTEL_VGA_DEVICE(0x0f30, info), \ 209 INTEL_VGA_DEVICE(0x0f31, info), \ 210 INTEL_VGA_DEVICE(0x0f32, info), \ 211 INTEL_VGA_DEVICE(0x0f33, info), \ 212 INTEL_VGA_DEVICE(0x0157, info) 213 214 #define INTEL_VLV_D_IDS(info) \ 215 INTEL_VGA_DEVICE(0x0155, info) 216 217 #define _INTEL_BDW_M(gt, id, info) \ 218 INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info) 219 #define _INTEL_BDW_D(gt, id, info) \ 220 INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info) 221 222 #define _INTEL_BDW_M_IDS(gt, info) \ 223 _INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \ 224 _INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \ 225 _INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \ 226 _INTEL_BDW_M(gt, 0x160E, info) /* ULX */ 227 228 #define _INTEL_BDW_D_IDS(gt, info) \ 229 _INTEL_BDW_D(gt, 0x160A, info), /* Server */ \ 230 _INTEL_BDW_D(gt, 0x160D, info) /* Workstation */ 231 232 #define INTEL_BDW_GT12M_IDS(info) \ 233 _INTEL_BDW_M_IDS(1, info), \ 234 _INTEL_BDW_M_IDS(2, info) 235 236 #define INTEL_BDW_GT12D_IDS(info) \ 237 _INTEL_BDW_D_IDS(1, info), \ 238 _INTEL_BDW_D_IDS(2, info) 239 240 #define INTEL_BDW_GT3M_IDS(info) \ 241 _INTEL_BDW_M_IDS(3, info) 242 243 #define INTEL_BDW_GT3D_IDS(info) \ 244 _INTEL_BDW_D_IDS(3, info) 245 246 #define INTEL_BDW_RSVDM_IDS(info) \ 247 _INTEL_BDW_M_IDS(4, info) 248 249 #define INTEL_BDW_RSVDD_IDS(info) \ 250 _INTEL_BDW_D_IDS(4, info) 251 252 #define INTEL_BDW_M_IDS(info) \ 253 INTEL_BDW_GT12M_IDS(info), \ 254 INTEL_BDW_GT3M_IDS(info), \ 255 INTEL_BDW_RSVDM_IDS(info) 256 257 #define INTEL_BDW_D_IDS(info) \ 258 INTEL_BDW_GT12D_IDS(info), \ 259 INTEL_BDW_GT3D_IDS(info), \ 260 INTEL_BDW_RSVDD_IDS(info) 261 262 #define INTEL_CHV_IDS(info) \ 263 INTEL_VGA_DEVICE(0x22b0, info), \ 264 INTEL_VGA_DEVICE(0x22b1, info), \ 265 INTEL_VGA_DEVICE(0x22b2, info), \ 266 INTEL_VGA_DEVICE(0x22b3, info) 267 268 #endif /* _I915_PCIIDS_H */ 269