1 /* 2 * Copyright (c) 2014-2015 François Tigeot 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef LINUX_PCI_H 28 #define LINUX_PCI_H 29 30 #define PCI_ANY_ID (~0u) 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/pciio.h> 35 #include <sys/rman.h> 36 #include <bus/pci/pcivar.h> 37 #include <bus/pci/pcireg.h> 38 39 #include <linux/types.h> 40 #include <linux/device.h> 41 #include <linux/io.h> 42 43 #include <linux/pci_ids.h> 44 45 struct pci_bus; 46 47 struct pci_device_id { 48 uint32_t class; 49 uint32_t class_mask; 50 uint32_t vendor; 51 uint32_t device; 52 uint32_t subvendor; 53 uint32_t subdevice; 54 unsigned long driver_data; 55 }; 56 57 struct pci_dev { 58 struct pci_bus *bus; /* bus device is nailed to */ 59 struct device *dev; /* NOTE the star */ 60 61 unsigned short vendor; /* vendor ID */ 62 unsigned short device; /* device ID */ 63 unsigned short subsystem_vendor; 64 unsigned short subsystem_device; 65 }; 66 67 struct pci_bus { 68 struct pci_dev *self; /* handle to pdev self */ 69 struct device *dev; /* handle to dev */ 70 71 unsigned char number; /* bus addr number */ 72 // unsigned char max_bus_speed; /* max bus speed */ 73 }; 74 75 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 76 77 #define PCI_DMA_BIDIRECTIONAL 0 78 79 /* extracted from radeon/si.c radeon/cik.c */ 80 #define PCI_EXP_LNKCTL PCIER_LINKCTRL /* 16 */ 81 #define PCI_EXP_LNKCTL2 48 82 #define PCI_EXP_LNKCTL_HAWD PCIEM_LNKCTL_HAWD /* 0x0200 */ 83 #define PCI_EXP_DEVSTA PCIER_DEVSTS /* 10 */ 84 #define PCI_EXP_DEVSTA_TRPND 0x0020 85 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 86 87 static inline int 88 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 89 { 90 *val = (u16)pci_read_config(pdev->dev, where, 1); 91 return 0; 92 } 93 94 static inline int 95 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 96 { 97 *val = (u16)pci_read_config(pdev->dev, where, 2); 98 return 0; 99 } 100 101 static inline int 102 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 103 { 104 *val = (u32)pci_read_config(pdev->dev, where, 4); 105 return 0; 106 } 107 108 static inline int 109 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 110 { 111 pci_write_config(pdev->dev, where, val, 1); 112 return 0; 113 } 114 115 static inline int 116 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 117 { 118 pci_write_config(pdev->dev, where, val, 2); 119 return 0; 120 } 121 122 static inline int 123 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 124 { 125 pci_write_config(pdev->dev, where, val, 4); 126 return 0; 127 } 128 129 /* extracted from drm/radeon/evergreen.c */ 130 static inline int 131 pcie_get_readrq(struct pci_dev *pdev) 132 { 133 u16 ctl; 134 int err, cap; 135 136 err = pci_find_extcap(pdev->dev, PCIY_EXPRESS, &cap); 137 WARN_ON(err); 138 139 cap += PCIER_DEVCTRL; 140 141 ctl = pci_read_config(pdev->dev, cap, 2); 142 143 return 128 << ((ctl & PCIEM_DEVCTL_MAX_READRQ_MASK) >> 12); 144 } 145 146 /* valid rq sizes: 128, 256, 512, 1024, 2048, 4096 (^2N) */ 147 static inline int 148 pcie_set_readrq(struct pci_dev *pdev, int rq) 149 { 150 u16 ctl; 151 int err, cap; 152 153 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 154 return -EINVAL; 155 156 err = pci_find_extcap(pdev->dev, PCIY_EXPRESS, &cap); 157 if (err) 158 return (-1); 159 160 cap += PCIER_DEVCTRL; 161 162 ctl = pci_read_config(pdev->dev, cap, 2); 163 ctl &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; 164 ctl |= ((ffs(rq) - 8) << 12); 165 pci_write_config(pdev->dev, cap, ctl, 2); 166 return 0; 167 } 168 169 static inline struct pci_dev * 170 pci_dev_get(struct pci_dev *dev) 171 { 172 /* Linux increments a reference count here */ 173 return dev; 174 } 175 176 static inline struct pci_dev * 177 pci_dev_put(struct pci_dev *dev) 178 { 179 /* Linux decrements a reference count here */ 180 return dev; 181 } 182 183 184 static inline int 185 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 186 { 187 return -EIO; 188 } 189 190 static inline int 191 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 192 { 193 return -EIO; 194 } 195 196 typedef int pci_power_t; 197 198 #define PCI_D0 0 199 #define PCI_D1 1 200 #define PCI_D2 2 201 #define PCI_D3hot 3 202 #define PCI_D3cold 4 203 204 #include <asm/pci.h> 205 206 static inline struct resource_list_entry* 207 _pci_get_rle(struct pci_dev *pdev, int bar) 208 { 209 struct pci_devinfo *dinfo; 210 struct device *dev = pdev->dev; 211 struct resource_list_entry *rle; 212 213 dinfo = device_get_ivars(dev); 214 215 /* Some child devices don't have registered resources, they 216 * are only present in the parent */ 217 if (dinfo == NULL) { 218 kprintf("_pci_get_rle: dinfo was NULL, trying again with parent\n"); 219 dev = device_get_parent(dev); 220 } 221 dinfo = device_get_ivars(dev); 222 if (dinfo == NULL) 223 return NULL; 224 225 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, PCIR_BAR(bar)); 226 if (rle == NULL) { 227 rle = resource_list_find(&dinfo->resources, 228 SYS_RES_IOPORT, PCIR_BAR(bar)); 229 } 230 231 return rle; 232 } 233 234 /* 235 * Returns the first address (memory address or I/O port number) 236 * associated with one of the PCI I/O regions.The region is selected by 237 * the integer bar (the base address register), ranging from 0–5 (inclusive). 238 * The return value can be used by ioremap() 239 */ 240 static inline phys_addr_t 241 pci_resource_start(struct pci_dev *pdev, int bar) 242 { 243 struct resource_list_entry *rle; 244 245 rle = _pci_get_rle(pdev, bar); 246 if (rle == NULL) 247 return -1; 248 249 kprintf("pci_resource_start(0x%x, 0x%x) = 0x%lx\n", 250 pdev->device, PCIR_BAR(bar), rman_get_start(rle->res)); 251 252 return rman_get_start(rle->res); 253 } 254 255 static inline phys_addr_t 256 pci_resource_len(struct pci_dev *pdev, int bar) 257 { 258 struct resource_list_entry *rle; 259 260 rle = _pci_get_rle(pdev, bar); 261 if (rle == NULL) 262 return -1; 263 264 kprintf("pci_resource_len(0x%x, 0x%x) = 0x%lx\n", 265 pdev->device, PCIR_BAR(bar), rman_get_size(rle->res)); 266 267 return rman_get_size(rle->res); 268 } 269 270 #endif /* LINUX_PCI_H */ 271