1 /* 2 * Copyright (c) 2014-2019 François Tigeot <ftigeot@wolfpond.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef LINUX_PCI_H 28 #define LINUX_PCI_H 29 30 #include <linux/mod_devicetable.h> 31 32 #include <linux/types.h> 33 #include <linux/init.h> 34 #include <linux/list.h> 35 #include <linux/compiler.h> 36 #include <linux/errno.h> 37 #include <linux/kobject.h> 38 #include <linux/atomic.h> 39 #include <linux/device.h> 40 #include <linux/io.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <bus/pci/pcivar.h> 48 #include <bus/pci/pcireg.h> 49 50 #define PCI_ANY_ID (~0u) 51 52 struct pci_bus; 53 54 struct pci_device_id { 55 uint32_t vendor; 56 uint32_t device; 57 uint32_t subvendor; 58 uint32_t subdevice; 59 uint32_t class; 60 uint32_t class_mask; 61 unsigned long driver_data; 62 }; 63 64 struct pci_dev { 65 struct pci_bus *bus; /* bus device is nailed to */ 66 struct device dev; 67 68 uint32_t devfn; 69 uint16_t vendor; /* vendor ID */ 70 uint16_t device; /* device ID */ 71 uint16_t subsystem_vendor; 72 uint16_t subsystem_device; 73 74 uint8_t revision; /* revision ID */ 75 76 unsigned int irq; /* handle with care */ 77 void *pci_dev_data; 78 79 /* DragonFly-specific data */ 80 int _irq_type; 81 struct resource *_irqr; 82 int _irqrid; 83 }; 84 85 struct pci_bus { 86 struct pci_dev *self; /* handle to pdev self */ 87 struct device *dev; /* handle to dev */ 88 89 unsigned char number; /* bus addr number */ 90 }; 91 92 struct pci_driver { 93 }; 94 95 #define PCI_DMA_BIDIRECTIONAL 0 96 97 /* extracted from radeon/si.c radeon/cik.c */ 98 #define PCI_EXP_LNKCTL PCIER_LINKCTRL /* 16 */ 99 #define PCI_EXP_LNKCTL2 48 100 #define PCI_EXP_LNKCTL_HAWD PCIEM_LNKCTL_HAWD /* 0x0200 */ 101 #define PCI_EXP_DEVSTA PCIER_DEVSTS /* 10 */ 102 #define PCI_EXP_DEVSTA_TRPND 0x0020 103 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 104 105 static inline int 106 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 107 { 108 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 109 return 0; 110 } 111 112 static inline int 113 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 114 { 115 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 116 return 0; 117 } 118 119 static inline int 120 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 121 { 122 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 123 return 0; 124 } 125 126 static inline int 127 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 128 { 129 pci_write_config(pdev->dev.bsddev, where, val, 1); 130 return 0; 131 } 132 133 static inline int 134 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 135 { 136 pci_write_config(pdev->dev.bsddev, where, val, 2); 137 return 0; 138 } 139 140 static inline int 141 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 142 { 143 pci_write_config(pdev->dev.bsddev, where, val, 4); 144 return 0; 145 } 146 147 /* extracted from drm/radeon/evergreen.c */ 148 static inline int 149 pcie_get_readrq(struct pci_dev *pdev) 150 { 151 u16 ctl; 152 int err, cap; 153 154 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 155 156 cap += PCIER_DEVCTRL; 157 158 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 159 160 return 128 << ((ctl & PCIEM_DEVCTL_MAX_READRQ_MASK) >> 12); 161 } 162 163 /* valid rq sizes: 128, 256, 512, 1024, 2048, 4096 (^2N) */ 164 static inline int 165 pcie_set_readrq(struct pci_dev *pdev, int rq) 166 { 167 u16 ctl; 168 int err, cap; 169 170 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 171 return -EINVAL; 172 173 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 174 if (err) 175 return (-1); 176 177 cap += PCIER_DEVCTRL; 178 179 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 180 ctl &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; 181 ctl |= ((ffs(rq) - 8) << 12); 182 pci_write_config(pdev->dev.bsddev, cap, ctl, 2); 183 return 0; 184 } 185 186 static inline struct pci_dev * 187 pci_dev_get(struct pci_dev *dev) 188 { 189 /* Linux increments a reference count here */ 190 return dev; 191 } 192 193 static inline struct pci_dev * 194 pci_dev_put(struct pci_dev *dev) 195 { 196 /* Linux decrements a reference count here */ 197 return dev; 198 } 199 200 201 static inline int 202 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 203 { 204 return -EIO; 205 } 206 207 static inline int 208 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 209 { 210 return -EIO; 211 } 212 213 typedef int pci_power_t; 214 215 #define PCI_D0 0 216 #define PCI_D1 1 217 #define PCI_D2 2 218 #define PCI_D3hot 3 219 #define PCI_D3cold 4 220 221 #include <asm/pci.h> 222 223 static inline struct resource_list_entry* 224 _pci_get_rle(struct pci_dev *pdev, int bar) 225 { 226 struct pci_devinfo *dinfo; 227 device_t dev = pdev->dev.bsddev; 228 struct resource_list_entry *rle; 229 230 dinfo = device_get_ivars(dev); 231 232 /* Some child devices don't have registered resources, they 233 * are only present in the parent */ 234 if (dinfo == NULL) 235 dev = device_get_parent(dev); 236 dinfo = device_get_ivars(dev); 237 if (dinfo == NULL) 238 return NULL; 239 240 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, PCIR_BAR(bar)); 241 if (rle == NULL) { 242 rle = resource_list_find(&dinfo->resources, 243 SYS_RES_IOPORT, PCIR_BAR(bar)); 244 } 245 246 return rle; 247 } 248 249 /* 250 * Returns the first address (memory address or I/O port number) 251 * associated with one of the PCI I/O regions.The region is selected by 252 * the integer bar (the base address register), ranging from 0–5 (inclusive). 253 * The return value can be used by ioremap() 254 */ 255 static inline phys_addr_t 256 pci_resource_start(struct pci_dev *pdev, int bar) 257 { 258 struct resource *res; 259 int rid; 260 261 rid = PCIR_BAR(bar); 262 res = bus_alloc_resource_any(pdev->dev.bsddev, SYS_RES_MEMORY, &rid, RF_SHAREABLE); 263 if (res == NULL) { 264 kprintf("pci_resource_start(0x%p, 0x%x) failed\n", pdev, PCIR_BAR(bar)); 265 return -1; 266 } 267 268 return rman_get_start(res); 269 } 270 271 static inline phys_addr_t 272 pci_resource_len(struct pci_dev *pdev, int bar) 273 { 274 struct resource_list_entry *rle; 275 276 rle = _pci_get_rle(pdev, bar); 277 if (rle == NULL) 278 return -1; 279 280 return rman_get_size(rle->res); 281 } 282 283 static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 284 { 285 resource_size_t base, size; 286 287 base = pci_resource_start(dev, bar); 288 size = pci_resource_len(dev, bar); 289 290 if (base == 0) 291 return NULL; 292 293 if (maxlen && size > maxlen) 294 size = maxlen; 295 296 return ioremap(base, size); 297 } 298 299 static inline int 300 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val) 301 { 302 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 303 304 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 305 return 0; 306 } 307 308 static inline int 309 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val) 310 { 311 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 312 313 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 314 return 0; 315 } 316 317 static inline void * 318 pci_get_drvdata(struct pci_dev *pdev) 319 { 320 return pdev->pci_dev_data; 321 } 322 323 static inline void 324 pci_set_drvdata(struct pci_dev *pdev, void *data) 325 { 326 pdev->pci_dev_data = data; 327 } 328 329 static inline int 330 pci_register_driver(struct pci_driver *drv) 331 { 332 return 0; 333 } 334 335 static inline void 336 pci_clear_master(struct pci_dev *pdev) 337 { 338 pci_disable_busmaster(pdev->dev.bsddev); 339 } 340 341 static inline void 342 pci_set_master(struct pci_dev *pdev) 343 { 344 pci_enable_busmaster(pdev->dev.bsddev); 345 } 346 347 static inline int 348 pci_pcie_cap(struct pci_dev *pdev) 349 { 350 return pci_get_pciecap_ptr(pdev->dev.bsddev); 351 } 352 353 #endif /* LINUX_PCI_H */ 354