1 /* 2 * Copyright (c) 2014-2020 François Tigeot <ftigeot@wolfpond.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef LINUX_PCI_H 28 #define LINUX_PCI_H 29 30 #include <linux/mod_devicetable.h> 31 32 #include <linux/types.h> 33 #include <linux/init.h> 34 #include <linux/ioport.h> 35 #include <linux/list.h> 36 #include <linux/compiler.h> 37 #include <linux/errno.h> 38 #include <linux/kobject.h> 39 #include <linux/atomic.h> 40 #include <linux/device.h> 41 #include <linux/io.h> 42 #include <uapi/linux/pci.h> 43 44 #include <linux/pci_ids.h> 45 #include <linux/pci_regs.h> 46 47 #include <sys/pciio.h> 48 #include <sys/rman.h> 49 #include <bus/pci/pcivar.h> 50 #include <bus/pci/pcireg.h> 51 52 #define PCI_ANY_ID (~0u) 53 54 struct pci_bus; 55 struct device_node; 56 57 struct pci_device_id { 58 uint32_t vendor; 59 uint32_t device; 60 uint32_t subvendor; 61 uint32_t subdevice; 62 uint32_t class; 63 uint32_t class_mask; 64 unsigned long driver_data; 65 }; 66 67 typedef unsigned short pci_dev_flags_t; 68 69 #define PCI_DEV_FLAGS_NEEDS_RESUME (1 << 11) 70 71 struct pci_dev { 72 struct pci_bus *bus; /* bus device is nailed to */ 73 struct device dev; 74 75 uint32_t devfn; 76 uint16_t vendor; /* vendor ID */ 77 uint16_t device; /* device ID */ 78 uint16_t subsystem_vendor; 79 uint16_t subsystem_device; 80 81 uint8_t revision; /* revision ID */ 82 83 unsigned int irq; /* handle with care */ 84 void *pci_dev_data; 85 86 unsigned int no_64bit_msi:1; 87 pci_dev_flags_t dev_flags; 88 89 /* DragonFly-specific data */ 90 int _irq_type; 91 struct resource *_irqr; 92 int _irqrid; 93 }; 94 95 struct pci_bus { 96 struct pci_dev *self; /* handle to pdev self */ 97 struct device *dev; /* handle to dev */ 98 99 unsigned char number; /* bus addr number */ 100 101 unsigned char max_bus_speed; 102 }; 103 104 struct pci_driver { 105 const char *name; 106 const struct pci_device_id *id_table; 107 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 108 void (*remove)(struct pci_dev *dev); 109 }; 110 111 #define PCI_DMA_BIDIRECTIONAL 0 112 113 /* extracted from radeon/si.c radeon/cik.c */ 114 #define PCI_EXP_LNKCTL PCIER_LINKCTRL /* 16 */ 115 #define PCI_EXP_LNKCTL2 48 116 #define PCI_EXP_LNKCTL_HAWD PCIEM_LNKCTL_HAWD /* 0x0200 */ 117 #define PCI_EXP_DEVSTA PCIER_DEVSTS /* 10 */ 118 #define PCI_EXP_DEVSTA_TRPND 0x0020 119 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 120 121 static inline int 122 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 123 { 124 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 125 return 0; 126 } 127 128 static inline int 129 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 130 { 131 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 132 return 0; 133 } 134 135 static inline int 136 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 137 { 138 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 139 return 0; 140 } 141 142 static inline int 143 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 144 { 145 pci_write_config(pdev->dev.bsddev, where, val, 1); 146 return 0; 147 } 148 149 static inline int 150 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 151 { 152 pci_write_config(pdev->dev.bsddev, where, val, 2); 153 return 0; 154 } 155 156 static inline int 157 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 158 { 159 pci_write_config(pdev->dev.bsddev, where, val, 4); 160 return 0; 161 } 162 163 /* extracted from drm/radeon/evergreen.c */ 164 static inline int 165 pcie_get_readrq(struct pci_dev *pdev) 166 { 167 u16 ctl; 168 int err, cap; 169 170 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 171 172 cap += PCIER_DEVCTRL; 173 174 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 175 176 return 128 << ((ctl & PCIEM_DEVCTL_MAX_READRQ_MASK) >> 12); 177 } 178 179 /* valid rq sizes: 128, 256, 512, 1024, 2048, 4096 (^2N) */ 180 static inline int 181 pcie_set_readrq(struct pci_dev *pdev, int rq) 182 { 183 u16 ctl; 184 int err, cap; 185 186 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 187 return -EINVAL; 188 189 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 190 if (err) 191 return (-1); 192 193 cap += PCIER_DEVCTRL; 194 195 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 196 ctl &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; 197 ctl |= ((ffs(rq) - 8) << 12); 198 pci_write_config(pdev->dev.bsddev, cap, ctl, 2); 199 return 0; 200 } 201 202 static inline struct pci_dev * 203 pci_dev_get(struct pci_dev *dev) 204 { 205 /* Linux increments a reference count here */ 206 return dev; 207 } 208 209 static inline struct pci_dev * 210 pci_dev_put(struct pci_dev *dev) 211 { 212 /* Linux decrements a reference count here */ 213 return dev; 214 } 215 216 217 static inline int 218 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 219 { 220 return -EIO; 221 } 222 223 static inline int 224 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 225 { 226 return -EIO; 227 } 228 229 typedef int pci_power_t; 230 231 #define PCI_D0 0 232 #define PCI_D1 1 233 #define PCI_D2 2 234 #define PCI_D3hot 3 235 #define PCI_D3cold 4 236 237 #include <asm/pci.h> 238 239 static inline struct resource_list_entry* 240 _pci_get_rle(struct pci_dev *pdev, int bar) 241 { 242 struct pci_devinfo *dinfo; 243 device_t dev = pdev->dev.bsddev; 244 struct resource_list_entry *rle; 245 246 dinfo = device_get_ivars(dev); 247 248 /* Some child devices don't have registered resources, they 249 * are only present in the parent */ 250 if (dinfo == NULL) 251 dev = device_get_parent(dev); 252 dinfo = device_get_ivars(dev); 253 if (dinfo == NULL) 254 return NULL; 255 256 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, PCIR_BAR(bar)); 257 if (rle == NULL) { 258 rle = resource_list_find(&dinfo->resources, 259 SYS_RES_IOPORT, PCIR_BAR(bar)); 260 } 261 262 return rle; 263 } 264 265 /* 266 * Returns the first address (memory address or I/O port number) 267 * associated with one of the PCI I/O regions.The region is selected by 268 * the integer bar (the base address register), ranging from 0–5 (inclusive). 269 * The return value can be used by ioremap() 270 */ 271 static inline phys_addr_t 272 pci_resource_start(struct pci_dev *pdev, int bar) 273 { 274 struct resource *res; 275 int rid; 276 277 rid = PCIR_BAR(bar); 278 res = bus_alloc_resource_any(pdev->dev.bsddev, SYS_RES_MEMORY, &rid, RF_SHAREABLE); 279 if (res == NULL) { 280 kprintf("pci_resource_start(0x%p, 0x%x) failed\n", pdev, PCIR_BAR(bar)); 281 return -1; 282 } 283 284 return rman_get_start(res); 285 } 286 287 static inline phys_addr_t 288 pci_resource_len(struct pci_dev *pdev, int bar) 289 { 290 struct resource_list_entry *rle; 291 292 rle = _pci_get_rle(pdev, bar); 293 if (rle == NULL) 294 return -1; 295 296 return rman_get_size(rle->res); 297 } 298 299 static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 300 { 301 resource_size_t base, size; 302 303 base = pci_resource_start(dev, bar); 304 size = pci_resource_len(dev, bar); 305 306 if (base == 0) 307 return NULL; 308 309 if (maxlen && size > maxlen) 310 size = maxlen; 311 312 return ioremap(base, size); 313 } 314 315 static inline int 316 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val) 317 { 318 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 319 320 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 321 return 0; 322 } 323 324 static inline int 325 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val) 326 { 327 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 328 329 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 330 return 0; 331 } 332 333 static inline const char * 334 pci_name(struct pci_dev *pdev) 335 { 336 return device_get_desc(pdev->dev.bsddev); 337 } 338 339 static inline void * 340 pci_get_drvdata(struct pci_dev *pdev) 341 { 342 return pdev->pci_dev_data; 343 } 344 345 static inline void 346 pci_set_drvdata(struct pci_dev *pdev, void *data) 347 { 348 pdev->pci_dev_data = data; 349 } 350 351 static inline int 352 pci_register_driver(struct pci_driver *drv) 353 { 354 /* pci_register_driver not implemented */ 355 return 0; 356 } 357 358 static inline void 359 pci_unregister_driver(struct pci_driver *dev) 360 { 361 /* pci_unregister_driver not implemented */ 362 } 363 364 static inline void 365 pci_clear_master(struct pci_dev *pdev) 366 { 367 pci_disable_busmaster(pdev->dev.bsddev); 368 } 369 370 static inline void 371 pci_set_master(struct pci_dev *pdev) 372 { 373 pci_enable_busmaster(pdev->dev.bsddev); 374 } 375 376 static inline int 377 pci_pcie_cap(struct pci_dev *pdev) 378 { 379 return pci_get_pciecap_ptr(pdev->dev.bsddev); 380 } 381 382 /* DRM_MAX_PCI_RESOURCE */ 383 #define DEVICE_COUNT_RESOURCE 6 384 385 #include <uapi/linux/pci_regs.h> 386 387 /* From FreeBSD */ 388 389 static inline int 390 pci_enable_device(struct pci_dev *pdev) 391 { 392 393 pci_enable_io(pdev->dev.bsddev, SYS_RES_IOPORT); 394 pci_enable_io(pdev->dev.bsddev, SYS_RES_MEMORY); 395 return (0); 396 } 397 398 static inline void 399 pci_disable_device(struct pci_dev *pdev) 400 { 401 402 pci_disable_busmaster(pdev->dev.bsddev); 403 } 404 405 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 406 { 407 return true; 408 } 409 410 static inline int 411 pci_find_capability(struct pci_dev *pdev, int capid) 412 { 413 int reg; 414 415 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 416 return (0); 417 return (reg); 418 } 419 420 static inline u16 pcie_flags_reg(struct pci_dev *dev) 421 { 422 int pos; 423 u16 reg16; 424 425 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 426 if (!pos) 427 return 0; 428 429 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 430 431 return reg16; 432 } 433 434 static inline int pci_pcie_type(struct pci_dev *dev) 435 { 436 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 437 } 438 439 440 static inline int pcie_cap_version(struct pci_dev *dev) 441 { 442 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 443 } 444 445 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 446 { 447 int type = pci_pcie_type(dev); 448 449 return pcie_cap_version(dev) > 1 || 450 type == PCI_EXP_TYPE_ROOT_PORT || 451 type == PCI_EXP_TYPE_ENDPOINT || 452 type == PCI_EXP_TYPE_LEG_END; 453 } 454 455 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 456 { 457 int type = pci_pcie_type(dev); 458 459 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 460 (type == PCI_EXP_TYPE_DOWNSTREAM && 461 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 462 } 463 464 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 465 { 466 int type = pci_pcie_type(dev); 467 468 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 469 type == PCI_EXP_TYPE_RC_EC; 470 } 471 472 static inline bool 473 pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 474 { 475 if (!pci_is_pcie(dev->dev.bsddev)) 476 return false; 477 478 switch (pos) { 479 case PCI_EXP_FLAGS_TYPE: 480 return true; 481 case PCI_EXP_DEVCAP: 482 case PCI_EXP_DEVCTL: 483 case PCI_EXP_DEVSTA: 484 return pcie_cap_has_devctl(dev); 485 case PCI_EXP_LNKCAP: 486 case PCI_EXP_LNKCTL: 487 case PCI_EXP_LNKSTA: 488 return pcie_cap_has_lnkctl(dev); 489 case PCI_EXP_SLTCAP: 490 case PCI_EXP_SLTCTL: 491 case PCI_EXP_SLTSTA: 492 return pcie_cap_has_sltctl(dev); 493 case PCI_EXP_RTCTL: 494 case PCI_EXP_RTCAP: 495 case PCI_EXP_RTSTA: 496 return pcie_cap_has_rtctl(dev); 497 case PCI_EXP_DEVCAP2: 498 case PCI_EXP_DEVCTL2: 499 case PCI_EXP_LNKCAP2: 500 case PCI_EXP_LNKCTL2: 501 case PCI_EXP_LNKSTA2: 502 return pcie_cap_version(dev) > 1; 503 default: 504 return false; 505 } 506 } 507 508 static inline void __iomem __must_check * 509 pci_map_rom(struct pci_dev *pdev, size_t *size) 510 { 511 return vga_pci_map_bios(device_get_parent(pdev->dev.bsddev), size); 512 } 513 514 static inline void 515 pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom) 516 { 517 vga_pci_unmap_bios(device_get_parent(pdev->dev.bsddev), rom); 518 } 519 520 static inline int 521 pci_resource_flags(struct pci_dev *pdev, int bar) 522 { 523 /* Hardcoded to return only the type */ 524 if ((bar & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) { 525 kprintf("pci_resource_flags: pdev=%p bar=%d type=IO\n", pdev, bar); 526 return IORESOURCE_IO; 527 } else { 528 kprintf("pci_resource_flags: pdev=%p bar=%d type=MEM\n", pdev, bar); 529 return IORESOURCE_MEM; 530 } 531 } 532 533 enum pci_bus_speed { 534 PCIE_SPEED_2_5GT = 0x14, 535 PCIE_SPEED_5_0GT = 0x15, 536 PCIE_SPEED_8_0GT = 0x16, 537 PCIE_SPEED_16_0GT = 0x17, 538 PCI_SPEED_UNKNOWN = 0xff, 539 }; 540 541 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */ 542 enum pcie_link_width { 543 PCIE_LNK_WIDTH_RESRV = 0x00, 544 PCIE_LNK_X1 = 0x01, 545 PCIE_LNK_X2 = 0x02, 546 PCIE_LNK_X4 = 0x04, 547 PCIE_LNK_X8 = 0x08, 548 PCIE_LNK_X12 = 0x0c, 549 PCIE_LNK_X16 = 0x10, 550 PCIE_LNK_X32 = 0x20, 551 PCIE_LNK_WIDTH_UNKNOWN = 0xff, 552 }; 553 554 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 555 556 #define PCIER_LINK_CAP 0xc 557 558 static inline enum pci_bus_speed 559 pcie_get_speed_cap(struct pci_dev *dev) 560 { 561 device_t root; 562 uint32_t lnkcap, lnkcap2; 563 int error, pos; 564 565 root = device_get_parent(dev->dev.bsddev); 566 if (root == NULL) 567 return (PCI_SPEED_UNKNOWN); 568 root = device_get_parent(root); 569 if (root == NULL) 570 return (PCI_SPEED_UNKNOWN); 571 root = device_get_parent(root); 572 if (root == NULL) 573 return (PCI_SPEED_UNKNOWN); 574 575 if (pci_get_vendor(root) == PCI_VENDOR_ID_VIA || 576 pci_get_vendor(root) == PCI_VENDOR_ID_SERVERWORKS) 577 return (PCI_SPEED_UNKNOWN); 578 579 if ((error = pci_find_extcap(root, PCIY_EXPRESS, &pos)) != 0) 580 return (PCI_SPEED_UNKNOWN); 581 582 lnkcap2 = pci_read_config(root, pos + PCIER_LINK_CAP2, 4); 583 584 if (lnkcap2) { /* PCIe r3.0-compliant */ 585 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 586 return (PCIE_SPEED_2_5GT); 587 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 588 return (PCIE_SPEED_5_0GT); 589 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 590 return (PCIE_SPEED_8_0GT); 591 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) 592 return (PCIE_SPEED_16_0GT); 593 } else { /* pre-r3.0 */ 594 lnkcap = pci_read_config(root, pos + PCIER_LINK_CAP, 4); 595 if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) 596 return (PCIE_SPEED_2_5GT); 597 if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) 598 return (PCIE_SPEED_5_0GT); 599 if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) 600 return (PCIE_SPEED_8_0GT); 601 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) 602 return (PCIE_SPEED_16_0GT); 603 } 604 return (PCI_SPEED_UNKNOWN); 605 } 606 607 static inline enum pcie_link_width 608 pcie_get_width_cap(struct pci_dev *dev) 609 { 610 uint32_t lnkcap; 611 612 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 613 if (lnkcap) 614 return ((lnkcap & PCI_EXP_LNKCAP_MLW) >> 4); 615 616 return (PCIE_LNK_WIDTH_UNKNOWN); 617 } 618 619 #include <linux/pci-dma-compat.h> 620 621 #endif /* LINUX_PCI_H */ 622