1 /* 2 * Copyright (c) 2014-2020 François Tigeot <ftigeot@wolfpond.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef LINUX_PCI_H 28 #define LINUX_PCI_H 29 30 #include <linux/mod_devicetable.h> 31 32 #include <linux/types.h> 33 #include <linux/init.h> 34 #include <linux/ioport.h> 35 #include <linux/list.h> 36 #include <linux/compiler.h> 37 #include <linux/errno.h> 38 #include <linux/kobject.h> 39 #include <linux/atomic.h> 40 #include <linux/device.h> 41 #include <linux/io.h> 42 #include <uapi/linux/pci.h> 43 44 #include <linux/pci_ids.h> 45 46 #include <sys/pciio.h> 47 #include <sys/rman.h> 48 #include <bus/pci/pcivar.h> 49 #include <bus/pci/pcireg.h> 50 51 #define PCI_ANY_ID (~0u) 52 53 struct pci_bus; 54 struct device_node; 55 56 struct pci_device_id { 57 uint32_t vendor; 58 uint32_t device; 59 uint32_t subvendor; 60 uint32_t subdevice; 61 uint32_t class; 62 uint32_t class_mask; 63 unsigned long driver_data; 64 }; 65 66 typedef unsigned short pci_dev_flags_t; 67 68 #define PCI_DEV_FLAGS_NEEDS_RESUME (1 << 11) 69 70 struct pci_dev { 71 struct pci_bus *bus; /* bus device is nailed to */ 72 struct device dev; 73 74 uint32_t devfn; 75 uint16_t vendor; /* vendor ID */ 76 uint16_t device; /* device ID */ 77 uint16_t subsystem_vendor; 78 uint16_t subsystem_device; 79 80 uint8_t revision; /* revision ID */ 81 82 unsigned int irq; /* handle with care */ 83 void *pci_dev_data; 84 85 unsigned int no_64bit_msi:1; 86 pci_dev_flags_t dev_flags; 87 88 /* DragonFly-specific data */ 89 int _irq_type; 90 struct resource *_irqr; 91 int _irqrid; 92 }; 93 94 struct pci_bus { 95 struct pci_dev *self; /* handle to pdev self */ 96 struct device *dev; /* handle to dev */ 97 98 unsigned char number; /* bus addr number */ 99 100 unsigned char max_bus_speed; 101 }; 102 103 struct pci_driver { 104 const char *name; 105 const struct pci_device_id *id_table; 106 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); 107 void (*remove)(struct pci_dev *dev); 108 }; 109 110 #define PCI_DMA_BIDIRECTIONAL 0 111 112 /* extracted from radeon/si.c radeon/cik.c */ 113 #define PCI_EXP_LNKCTL PCIER_LINKCTRL /* 16 */ 114 #define PCI_EXP_LNKCTL2 48 115 #define PCI_EXP_LNKCTL_HAWD PCIEM_LNKCTL_HAWD /* 0x0200 */ 116 #define PCI_EXP_DEVSTA PCIER_DEVSTS /* 10 */ 117 #define PCI_EXP_DEVSTA_TRPND 0x0020 118 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 119 120 static inline int 121 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 122 { 123 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 124 return 0; 125 } 126 127 static inline int 128 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 129 { 130 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 131 return 0; 132 } 133 134 static inline int 135 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 136 { 137 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 138 return 0; 139 } 140 141 static inline int 142 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 143 { 144 pci_write_config(pdev->dev.bsddev, where, val, 1); 145 return 0; 146 } 147 148 static inline int 149 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 150 { 151 pci_write_config(pdev->dev.bsddev, where, val, 2); 152 return 0; 153 } 154 155 static inline int 156 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 157 { 158 pci_write_config(pdev->dev.bsddev, where, val, 4); 159 return 0; 160 } 161 162 /* extracted from drm/radeon/evergreen.c */ 163 static inline int 164 pcie_get_readrq(struct pci_dev *pdev) 165 { 166 u16 ctl; 167 int err, cap; 168 169 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 170 171 cap += PCIER_DEVCTRL; 172 173 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 174 175 return 128 << ((ctl & PCIEM_DEVCTL_MAX_READRQ_MASK) >> 12); 176 } 177 178 /* valid rq sizes: 128, 256, 512, 1024, 2048, 4096 (^2N) */ 179 static inline int 180 pcie_set_readrq(struct pci_dev *pdev, int rq) 181 { 182 u16 ctl; 183 int err, cap; 184 185 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 186 return -EINVAL; 187 188 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 189 if (err) 190 return (-1); 191 192 cap += PCIER_DEVCTRL; 193 194 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 195 ctl &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; 196 ctl |= ((ffs(rq) - 8) << 12); 197 pci_write_config(pdev->dev.bsddev, cap, ctl, 2); 198 return 0; 199 } 200 201 static inline struct pci_dev * 202 pci_dev_get(struct pci_dev *dev) 203 { 204 /* Linux increments a reference count here */ 205 return dev; 206 } 207 208 static inline struct pci_dev * 209 pci_dev_put(struct pci_dev *dev) 210 { 211 /* Linux decrements a reference count here */ 212 return dev; 213 } 214 215 216 static inline int 217 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 218 { 219 return -EIO; 220 } 221 222 static inline int 223 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 224 { 225 return -EIO; 226 } 227 228 typedef int pci_power_t; 229 230 #define PCI_D0 0 231 #define PCI_D1 1 232 #define PCI_D2 2 233 #define PCI_D3hot 3 234 #define PCI_D3cold 4 235 236 #include <asm/pci.h> 237 238 static inline struct resource_list_entry* 239 _pci_get_rle(struct pci_dev *pdev, int bar) 240 { 241 struct pci_devinfo *dinfo; 242 device_t dev = pdev->dev.bsddev; 243 struct resource_list_entry *rle; 244 245 dinfo = device_get_ivars(dev); 246 247 /* Some child devices don't have registered resources, they 248 * are only present in the parent */ 249 if (dinfo == NULL) 250 dev = device_get_parent(dev); 251 dinfo = device_get_ivars(dev); 252 if (dinfo == NULL) 253 return NULL; 254 255 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, PCIR_BAR(bar)); 256 if (rle == NULL) { 257 rle = resource_list_find(&dinfo->resources, 258 SYS_RES_IOPORT, PCIR_BAR(bar)); 259 } 260 261 return rle; 262 } 263 264 /* 265 * Returns the first address (memory address or I/O port number) 266 * associated with one of the PCI I/O regions.The region is selected by 267 * the integer bar (the base address register), ranging from 0–5 (inclusive). 268 * The return value can be used by ioremap() 269 */ 270 static inline phys_addr_t 271 pci_resource_start(struct pci_dev *pdev, int bar) 272 { 273 struct resource *res; 274 int rid; 275 276 rid = PCIR_BAR(bar); 277 res = bus_alloc_resource_any(pdev->dev.bsddev, SYS_RES_MEMORY, &rid, RF_SHAREABLE); 278 if (res == NULL) { 279 kprintf("pci_resource_start(0x%p, 0x%x) failed\n", pdev, PCIR_BAR(bar)); 280 return -1; 281 } 282 283 return rman_get_start(res); 284 } 285 286 static inline phys_addr_t 287 pci_resource_len(struct pci_dev *pdev, int bar) 288 { 289 struct resource_list_entry *rle; 290 291 rle = _pci_get_rle(pdev, bar); 292 if (rle == NULL) 293 return -1; 294 295 return rman_get_size(rle->res); 296 } 297 298 static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 299 { 300 resource_size_t base, size; 301 302 base = pci_resource_start(dev, bar); 303 size = pci_resource_len(dev, bar); 304 305 if (base == 0) 306 return NULL; 307 308 if (maxlen && size > maxlen) 309 size = maxlen; 310 311 return ioremap(base, size); 312 } 313 314 static inline int 315 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val) 316 { 317 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 318 319 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 320 return 0; 321 } 322 323 static inline int 324 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val) 325 { 326 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 327 328 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 329 return 0; 330 } 331 332 static inline const char * 333 pci_name(struct pci_dev *pdev) 334 { 335 return device_get_desc(pdev->dev.bsddev); 336 } 337 338 static inline void * 339 pci_get_drvdata(struct pci_dev *pdev) 340 { 341 return pdev->pci_dev_data; 342 } 343 344 static inline void 345 pci_set_drvdata(struct pci_dev *pdev, void *data) 346 { 347 pdev->pci_dev_data = data; 348 } 349 350 static inline int 351 pci_register_driver(struct pci_driver *drv) 352 { 353 /* pci_register_driver not implemented */ 354 return 0; 355 } 356 357 static inline void 358 pci_unregister_driver(struct pci_driver *dev) 359 { 360 /* pci_unregister_driver not implemented */ 361 } 362 363 static inline void 364 pci_clear_master(struct pci_dev *pdev) 365 { 366 pci_disable_busmaster(pdev->dev.bsddev); 367 } 368 369 static inline void 370 pci_set_master(struct pci_dev *pdev) 371 { 372 pci_enable_busmaster(pdev->dev.bsddev); 373 } 374 375 static inline int 376 pci_pcie_cap(struct pci_dev *pdev) 377 { 378 return pci_get_pciecap_ptr(pdev->dev.bsddev); 379 } 380 381 /* DRM_MAX_PCI_RESOURCE */ 382 #define DEVICE_COUNT_RESOURCE 6 383 384 #include <uapi/linux/pci_regs.h> 385 386 /* From FreeBSD */ 387 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 388 { 389 return true; 390 } 391 392 static inline int 393 pci_find_capability(struct pci_dev *pdev, int capid) 394 { 395 int reg; 396 397 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 398 return (0); 399 return (reg); 400 } 401 402 static inline u16 pcie_flags_reg(struct pci_dev *dev) 403 { 404 int pos; 405 u16 reg16; 406 407 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 408 if (!pos) 409 return 0; 410 411 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 412 413 return reg16; 414 } 415 416 static inline int pci_pcie_type(struct pci_dev *dev) 417 { 418 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 419 } 420 421 422 static inline int pcie_cap_version(struct pci_dev *dev) 423 { 424 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 425 } 426 427 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 428 { 429 int type = pci_pcie_type(dev); 430 431 return pcie_cap_version(dev) > 1 || 432 type == PCI_EXP_TYPE_ROOT_PORT || 433 type == PCI_EXP_TYPE_ENDPOINT || 434 type == PCI_EXP_TYPE_LEG_END; 435 } 436 437 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 438 { 439 int type = pci_pcie_type(dev); 440 441 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 442 (type == PCI_EXP_TYPE_DOWNSTREAM && 443 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 444 } 445 446 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 447 { 448 int type = pci_pcie_type(dev); 449 450 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 451 type == PCI_EXP_TYPE_RC_EC; 452 } 453 454 static inline bool 455 pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 456 { 457 if (!pci_is_pcie(dev->dev.bsddev)) 458 return false; 459 460 switch (pos) { 461 case PCI_EXP_FLAGS_TYPE: 462 return true; 463 case PCI_EXP_DEVCAP: 464 case PCI_EXP_DEVCTL: 465 case PCI_EXP_DEVSTA: 466 return pcie_cap_has_devctl(dev); 467 case PCI_EXP_LNKCAP: 468 case PCI_EXP_LNKCTL: 469 case PCI_EXP_LNKSTA: 470 return pcie_cap_has_lnkctl(dev); 471 case PCI_EXP_SLTCAP: 472 case PCI_EXP_SLTCTL: 473 case PCI_EXP_SLTSTA: 474 return pcie_cap_has_sltctl(dev); 475 case PCI_EXP_RTCTL: 476 case PCI_EXP_RTCAP: 477 case PCI_EXP_RTSTA: 478 return pcie_cap_has_rtctl(dev); 479 case PCI_EXP_DEVCAP2: 480 case PCI_EXP_DEVCTL2: 481 case PCI_EXP_LNKCAP2: 482 case PCI_EXP_LNKCTL2: 483 case PCI_EXP_LNKSTA2: 484 return pcie_cap_version(dev) > 1; 485 default: 486 return false; 487 } 488 } 489 490 static inline void __iomem __must_check * 491 pci_map_rom(struct pci_dev *pdev, size_t *size) 492 { 493 return vga_pci_map_bios(device_get_parent(pdev->dev.bsddev), size); 494 } 495 496 static inline void 497 pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom) 498 { 499 vga_pci_unmap_bios(device_get_parent(pdev->dev.bsddev), rom); 500 } 501 502 static inline int 503 pci_resource_flags(struct pci_dev *pdev, int bar) 504 { 505 /* Hardcoded to return only the type */ 506 if ((bar & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) { 507 kprintf("pci_resource_flags: pdev=%p bar=%d type=IO\n", pdev, bar); 508 return IORESOURCE_IO; 509 } else { 510 kprintf("pci_resource_flags: pdev=%p bar=%d type=MEM\n", pdev, bar); 511 return IORESOURCE_MEM; 512 } 513 } 514 515 enum pci_bus_speed { 516 PCIE_SPEED_2_5GT = 0x14, 517 PCIE_SPEED_5_0GT = 0x15, 518 PCIE_SPEED_8_0GT = 0x16, 519 PCI_SPEED_UNKNOWN = 0xff, 520 }; 521 522 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val); 523 524 #include <linux/pci-dma-compat.h> 525 526 #endif /* LINUX_PCI_H */ 527