1 /* 2 * Copyright (c) 2014-2019 François Tigeot <ftigeot@wolfpond.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef LINUX_PCI_H 28 #define LINUX_PCI_H 29 30 #include <linux/mod_devicetable.h> 31 32 #include <linux/types.h> 33 #include <linux/init.h> 34 #include <linux/list.h> 35 #include <linux/compiler.h> 36 #include <linux/errno.h> 37 #include <linux/kobject.h> 38 #include <linux/atomic.h> 39 #include <linux/device.h> 40 #include <linux/io.h> 41 #include <uapi/linux/pci.h> 42 43 #include <linux/pci_ids.h> 44 45 #include <sys/pciio.h> 46 #include <sys/rman.h> 47 #include <bus/pci/pcivar.h> 48 #include <bus/pci/pcireg.h> 49 50 #define PCI_ANY_ID (~0u) 51 52 struct pci_bus; 53 54 struct pci_device_id { 55 uint32_t vendor; 56 uint32_t device; 57 uint32_t subvendor; 58 uint32_t subdevice; 59 uint32_t class; 60 uint32_t class_mask; 61 unsigned long driver_data; 62 }; 63 64 struct pci_dev { 65 struct pci_bus *bus; /* bus device is nailed to */ 66 struct device dev; 67 68 uint32_t devfn; 69 uint16_t vendor; /* vendor ID */ 70 uint16_t device; /* device ID */ 71 uint16_t subsystem_vendor; 72 uint16_t subsystem_device; 73 74 uint8_t revision; /* revision ID */ 75 76 unsigned int irq; /* handle with care */ 77 void *pci_dev_data; 78 79 unsigned int no_64bit_msi:1; 80 81 /* DragonFly-specific data */ 82 int _irq_type; 83 struct resource *_irqr; 84 int _irqrid; 85 }; 86 87 struct pci_bus { 88 struct pci_dev *self; /* handle to pdev self */ 89 struct device *dev; /* handle to dev */ 90 91 unsigned char number; /* bus addr number */ 92 }; 93 94 struct pci_driver { 95 }; 96 97 #define PCI_DMA_BIDIRECTIONAL 0 98 99 /* extracted from radeon/si.c radeon/cik.c */ 100 #define PCI_EXP_LNKCTL PCIER_LINKCTRL /* 16 */ 101 #define PCI_EXP_LNKCTL2 48 102 #define PCI_EXP_LNKCTL_HAWD PCIEM_LNKCTL_HAWD /* 0x0200 */ 103 #define PCI_EXP_DEVSTA PCIER_DEVSTS /* 10 */ 104 #define PCI_EXP_DEVSTA_TRPND 0x0020 105 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 106 107 static inline int 108 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 109 { 110 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 111 return 0; 112 } 113 114 static inline int 115 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 116 { 117 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 118 return 0; 119 } 120 121 static inline int 122 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 123 { 124 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 125 return 0; 126 } 127 128 static inline int 129 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 130 { 131 pci_write_config(pdev->dev.bsddev, where, val, 1); 132 return 0; 133 } 134 135 static inline int 136 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 137 { 138 pci_write_config(pdev->dev.bsddev, where, val, 2); 139 return 0; 140 } 141 142 static inline int 143 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 144 { 145 pci_write_config(pdev->dev.bsddev, where, val, 4); 146 return 0; 147 } 148 149 /* extracted from drm/radeon/evergreen.c */ 150 static inline int 151 pcie_get_readrq(struct pci_dev *pdev) 152 { 153 u16 ctl; 154 int err, cap; 155 156 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 157 158 cap += PCIER_DEVCTRL; 159 160 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 161 162 return 128 << ((ctl & PCIEM_DEVCTL_MAX_READRQ_MASK) >> 12); 163 } 164 165 /* valid rq sizes: 128, 256, 512, 1024, 2048, 4096 (^2N) */ 166 static inline int 167 pcie_set_readrq(struct pci_dev *pdev, int rq) 168 { 169 u16 ctl; 170 int err, cap; 171 172 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 173 return -EINVAL; 174 175 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 176 if (err) 177 return (-1); 178 179 cap += PCIER_DEVCTRL; 180 181 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 182 ctl &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; 183 ctl |= ((ffs(rq) - 8) << 12); 184 pci_write_config(pdev->dev.bsddev, cap, ctl, 2); 185 return 0; 186 } 187 188 static inline struct pci_dev * 189 pci_dev_get(struct pci_dev *dev) 190 { 191 /* Linux increments a reference count here */ 192 return dev; 193 } 194 195 static inline struct pci_dev * 196 pci_dev_put(struct pci_dev *dev) 197 { 198 /* Linux decrements a reference count here */ 199 return dev; 200 } 201 202 203 static inline int 204 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 205 { 206 return -EIO; 207 } 208 209 static inline int 210 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 211 { 212 return -EIO; 213 } 214 215 typedef int pci_power_t; 216 217 #define PCI_D0 0 218 #define PCI_D1 1 219 #define PCI_D2 2 220 #define PCI_D3hot 3 221 #define PCI_D3cold 4 222 223 #include <asm/pci.h> 224 225 static inline struct resource_list_entry* 226 _pci_get_rle(struct pci_dev *pdev, int bar) 227 { 228 struct pci_devinfo *dinfo; 229 device_t dev = pdev->dev.bsddev; 230 struct resource_list_entry *rle; 231 232 dinfo = device_get_ivars(dev); 233 234 /* Some child devices don't have registered resources, they 235 * are only present in the parent */ 236 if (dinfo == NULL) 237 dev = device_get_parent(dev); 238 dinfo = device_get_ivars(dev); 239 if (dinfo == NULL) 240 return NULL; 241 242 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, PCIR_BAR(bar)); 243 if (rle == NULL) { 244 rle = resource_list_find(&dinfo->resources, 245 SYS_RES_IOPORT, PCIR_BAR(bar)); 246 } 247 248 return rle; 249 } 250 251 /* 252 * Returns the first address (memory address or I/O port number) 253 * associated with one of the PCI I/O regions.The region is selected by 254 * the integer bar (the base address register), ranging from 0–5 (inclusive). 255 * The return value can be used by ioremap() 256 */ 257 static inline phys_addr_t 258 pci_resource_start(struct pci_dev *pdev, int bar) 259 { 260 struct resource *res; 261 int rid; 262 263 rid = PCIR_BAR(bar); 264 res = bus_alloc_resource_any(pdev->dev.bsddev, SYS_RES_MEMORY, &rid, RF_SHAREABLE); 265 if (res == NULL) { 266 kprintf("pci_resource_start(0x%p, 0x%x) failed\n", pdev, PCIR_BAR(bar)); 267 return -1; 268 } 269 270 return rman_get_start(res); 271 } 272 273 static inline phys_addr_t 274 pci_resource_len(struct pci_dev *pdev, int bar) 275 { 276 struct resource_list_entry *rle; 277 278 rle = _pci_get_rle(pdev, bar); 279 if (rle == NULL) 280 return -1; 281 282 return rman_get_size(rle->res); 283 } 284 285 static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 286 { 287 resource_size_t base, size; 288 289 base = pci_resource_start(dev, bar); 290 size = pci_resource_len(dev, bar); 291 292 if (base == 0) 293 return NULL; 294 295 if (maxlen && size > maxlen) 296 size = maxlen; 297 298 return ioremap(base, size); 299 } 300 301 static inline int 302 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val) 303 { 304 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 305 306 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 307 return 0; 308 } 309 310 static inline int 311 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val) 312 { 313 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 314 315 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 316 return 0; 317 } 318 319 static inline const char * 320 pci_name(struct pci_dev *pdev) 321 { 322 return device_get_desc(pdev->dev.bsddev); 323 } 324 325 static inline void * 326 pci_get_drvdata(struct pci_dev *pdev) 327 { 328 return pdev->pci_dev_data; 329 } 330 331 static inline void 332 pci_set_drvdata(struct pci_dev *pdev, void *data) 333 { 334 pdev->pci_dev_data = data; 335 } 336 337 static inline int 338 pci_register_driver(struct pci_driver *drv) 339 { 340 return 0; 341 } 342 343 static inline void 344 pci_clear_master(struct pci_dev *pdev) 345 { 346 pci_disable_busmaster(pdev->dev.bsddev); 347 } 348 349 static inline void 350 pci_set_master(struct pci_dev *pdev) 351 { 352 pci_enable_busmaster(pdev->dev.bsddev); 353 } 354 355 static inline int 356 pci_pcie_cap(struct pci_dev *pdev) 357 { 358 return pci_get_pciecap_ptr(pdev->dev.bsddev); 359 } 360 361 /* DRM_MAX_PCI_RESOURCE */ 362 #define DEVICE_COUNT_RESOURCE 6 363 364 #include <uapi/linux/pci_regs.h> 365 366 /* From FreeBSD */ 367 static inline bool pcie_cap_has_devctl(const struct pci_dev *dev) 368 { 369 return true; 370 } 371 372 static inline int 373 pci_find_capability(struct pci_dev *pdev, int capid) 374 { 375 int reg; 376 377 if (pci_find_extcap(pdev->dev.bsddev, capid, ®)) 378 return (0); 379 return (reg); 380 } 381 382 static inline u16 pcie_flags_reg(struct pci_dev *dev) 383 { 384 int pos; 385 u16 reg16; 386 387 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 388 if (!pos) 389 return 0; 390 391 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, ®16); 392 393 return reg16; 394 } 395 396 static inline int pci_pcie_type(struct pci_dev *dev) 397 { 398 return (pcie_flags_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4; 399 } 400 401 402 static inline int pcie_cap_version(struct pci_dev *dev) 403 { 404 return pcie_flags_reg(dev) & PCI_EXP_FLAGS_VERS; 405 } 406 407 static inline bool pcie_cap_has_lnkctl(struct pci_dev *dev) 408 { 409 int type = pci_pcie_type(dev); 410 411 return pcie_cap_version(dev) > 1 || 412 type == PCI_EXP_TYPE_ROOT_PORT || 413 type == PCI_EXP_TYPE_ENDPOINT || 414 type == PCI_EXP_TYPE_LEG_END; 415 } 416 417 static inline bool pcie_cap_has_sltctl(struct pci_dev *dev) 418 { 419 int type = pci_pcie_type(dev); 420 421 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 422 (type == PCI_EXP_TYPE_DOWNSTREAM && 423 pcie_flags_reg(dev) & PCI_EXP_FLAGS_SLOT); 424 } 425 426 static inline bool pcie_cap_has_rtctl(struct pci_dev *dev) 427 { 428 int type = pci_pcie_type(dev); 429 430 return pcie_cap_version(dev) > 1 || type == PCI_EXP_TYPE_ROOT_PORT || 431 type == PCI_EXP_TYPE_RC_EC; 432 } 433 434 static inline bool 435 pcie_capability_reg_implemented(struct pci_dev *dev, int pos) 436 { 437 if (!pci_is_pcie(dev->dev.bsddev)) 438 return false; 439 440 switch (pos) { 441 case PCI_EXP_FLAGS_TYPE: 442 return true; 443 case PCI_EXP_DEVCAP: 444 case PCI_EXP_DEVCTL: 445 case PCI_EXP_DEVSTA: 446 return pcie_cap_has_devctl(dev); 447 case PCI_EXP_LNKCAP: 448 case PCI_EXP_LNKCTL: 449 case PCI_EXP_LNKSTA: 450 return pcie_cap_has_lnkctl(dev); 451 case PCI_EXP_SLTCAP: 452 case PCI_EXP_SLTCTL: 453 case PCI_EXP_SLTSTA: 454 return pcie_cap_has_sltctl(dev); 455 case PCI_EXP_RTCTL: 456 case PCI_EXP_RTCAP: 457 case PCI_EXP_RTSTA: 458 return pcie_cap_has_rtctl(dev); 459 case PCI_EXP_DEVCAP2: 460 case PCI_EXP_DEVCTL2: 461 case PCI_EXP_LNKCAP2: 462 case PCI_EXP_LNKCTL2: 463 case PCI_EXP_LNKSTA2: 464 return pcie_cap_version(dev) > 1; 465 default: 466 return false; 467 } 468 } 469 470 #endif /* LINUX_PCI_H */ 471