1 /* 2 * Copyright (c) 2014-2017 François Tigeot 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef LINUX_PCI_H 28 #define LINUX_PCI_H 29 30 #define PCI_ANY_ID (~0u) 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/pciio.h> 35 #include <sys/rman.h> 36 #include <bus/pci/pcivar.h> 37 #include <bus/pci/pcireg.h> 38 39 #include <linux/types.h> 40 #include <linux/list.h> 41 #include <linux/compiler.h> 42 #include <linux/errno.h> 43 #include <linux/kobject.h> 44 #include <linux/atomic.h> 45 #include <linux/device.h> 46 #include <linux/io.h> 47 48 #include <linux/pci_ids.h> 49 50 struct pci_bus; 51 52 struct pci_device_id { 53 uint32_t vendor; 54 uint32_t device; 55 uint32_t subvendor; 56 uint32_t subdevice; 57 uint32_t class; 58 uint32_t class_mask; 59 unsigned long driver_data; 60 }; 61 62 struct pci_dev { 63 struct pci_bus *bus; /* bus device is nailed to */ 64 struct device dev; 65 66 uint16_t vendor; /* vendor ID */ 67 uint16_t device; /* device ID */ 68 uint16_t subsystem_vendor; 69 uint16_t subsystem_device; 70 71 uint8_t revision; /* revision ID */ 72 73 unsigned int irq; /* handle with care */ 74 }; 75 76 struct pci_bus { 77 struct pci_dev *self; /* handle to pdev self */ 78 struct device *dev; /* handle to dev */ 79 80 unsigned char number; /* bus addr number */ 81 }; 82 83 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 84 85 #define PCI_DMA_BIDIRECTIONAL 0 86 87 /* extracted from radeon/si.c radeon/cik.c */ 88 #define PCI_EXP_LNKCTL PCIER_LINKCTRL /* 16 */ 89 #define PCI_EXP_LNKCTL2 48 90 #define PCI_EXP_LNKCTL_HAWD PCIEM_LNKCTL_HAWD /* 0x0200 */ 91 #define PCI_EXP_DEVSTA PCIER_DEVSTS /* 10 */ 92 #define PCI_EXP_DEVSTA_TRPND 0x0020 93 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 94 95 static inline int 96 pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) 97 { 98 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 99 return 0; 100 } 101 102 static inline int 103 pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) 104 { 105 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 106 return 0; 107 } 108 109 static inline int 110 pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) 111 { 112 *val = (u32)pci_read_config(pdev->dev.bsddev, where, 4); 113 return 0; 114 } 115 116 static inline int 117 pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) 118 { 119 pci_write_config(pdev->dev.bsddev, where, val, 1); 120 return 0; 121 } 122 123 static inline int 124 pci_write_config_word(struct pci_dev *pdev, int where, u16 val) 125 { 126 pci_write_config(pdev->dev.bsddev, where, val, 2); 127 return 0; 128 } 129 130 static inline int 131 pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) 132 { 133 pci_write_config(pdev->dev.bsddev, where, val, 4); 134 return 0; 135 } 136 137 /* extracted from drm/radeon/evergreen.c */ 138 static inline int 139 pcie_get_readrq(struct pci_dev *pdev) 140 { 141 u16 ctl; 142 int err, cap; 143 144 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 145 146 cap += PCIER_DEVCTRL; 147 148 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 149 150 return 128 << ((ctl & PCIEM_DEVCTL_MAX_READRQ_MASK) >> 12); 151 } 152 153 /* valid rq sizes: 128, 256, 512, 1024, 2048, 4096 (^2N) */ 154 static inline int 155 pcie_set_readrq(struct pci_dev *pdev, int rq) 156 { 157 u16 ctl; 158 int err, cap; 159 160 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 161 return -EINVAL; 162 163 err = pci_find_extcap(pdev->dev.bsddev, PCIY_EXPRESS, &cap); 164 if (err) 165 return (-1); 166 167 cap += PCIER_DEVCTRL; 168 169 ctl = pci_read_config(pdev->dev.bsddev, cap, 2); 170 ctl &= ~PCIEM_DEVCTL_MAX_READRQ_MASK; 171 ctl |= ((ffs(rq) - 8) << 12); 172 pci_write_config(pdev->dev.bsddev, cap, ctl, 2); 173 return 0; 174 } 175 176 static inline struct pci_dev * 177 pci_dev_get(struct pci_dev *dev) 178 { 179 /* Linux increments a reference count here */ 180 return dev; 181 } 182 183 static inline struct pci_dev * 184 pci_dev_put(struct pci_dev *dev) 185 { 186 /* Linux decrements a reference count here */ 187 return dev; 188 } 189 190 191 static inline int 192 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 193 { 194 return -EIO; 195 } 196 197 static inline int 198 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 199 { 200 return -EIO; 201 } 202 203 typedef int pci_power_t; 204 205 #define PCI_D0 0 206 #define PCI_D1 1 207 #define PCI_D2 2 208 #define PCI_D3hot 3 209 #define PCI_D3cold 4 210 211 #include <asm/pci.h> 212 213 static inline struct resource_list_entry* 214 _pci_get_rle(struct pci_dev *pdev, int bar) 215 { 216 struct pci_devinfo *dinfo; 217 device_t dev = pdev->dev.bsddev; 218 struct resource_list_entry *rle; 219 220 dinfo = device_get_ivars(dev); 221 222 /* Some child devices don't have registered resources, they 223 * are only present in the parent */ 224 if (dinfo == NULL) { 225 kprintf("_pci_get_rle: dinfo was NULL, trying again with parent\n"); 226 dev = device_get_parent(dev); 227 } 228 dinfo = device_get_ivars(dev); 229 if (dinfo == NULL) 230 return NULL; 231 232 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY, PCIR_BAR(bar)); 233 if (rle == NULL) { 234 rle = resource_list_find(&dinfo->resources, 235 SYS_RES_IOPORT, PCIR_BAR(bar)); 236 } 237 238 return rle; 239 } 240 241 /* 242 * Returns the first address (memory address or I/O port number) 243 * associated with one of the PCI I/O regions.The region is selected by 244 * the integer bar (the base address register), ranging from 0–5 (inclusive). 245 * The return value can be used by ioremap() 246 */ 247 static inline phys_addr_t 248 pci_resource_start(struct pci_dev *pdev, int bar) 249 { 250 struct resource *res; 251 int rid; 252 253 rid = PCIR_BAR(bar); 254 res = bus_alloc_resource_any(pdev->dev.bsddev, SYS_RES_MEMORY, &rid, RF_SHAREABLE); 255 if (res == NULL) { 256 kprintf("pci_resource_start(0x%p, 0x%x) failed\n", pdev, PCIR_BAR(bar)); 257 return -1; 258 } 259 260 return rman_get_start(res); 261 } 262 263 static inline phys_addr_t 264 pci_resource_len(struct pci_dev *pdev, int bar) 265 { 266 struct resource_list_entry *rle; 267 268 rle = _pci_get_rle(pdev, bar); 269 if (rle == NULL) 270 return -1; 271 272 kprintf("pci_resource_len(0x%x, 0x%x) = 0x%lx\n", 273 pdev->device, PCIR_BAR(bar), rman_get_size(rle->res)); 274 275 return rman_get_size(rle->res); 276 } 277 278 static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 279 { 280 resource_size_t base, size; 281 282 base = pci_resource_start(dev, bar); 283 size = pci_resource_len(dev, bar); 284 285 if (base == 0) 286 return NULL; 287 288 if (maxlen && size > maxlen) 289 size = maxlen; 290 291 return ioremap(base, size); 292 } 293 294 static inline int 295 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val) 296 { 297 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 298 299 *val = (u8)pci_read_config(pdev->dev.bsddev, where, 1); 300 return 0; 301 } 302 303 static inline int 304 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val) 305 { 306 const struct pci_dev *pdev = container_of(&bus, struct pci_dev, bus); 307 308 *val = (u16)pci_read_config(pdev->dev.bsddev, where, 2); 309 return 0; 310 } 311 312 #endif /* LINUX_PCI_H */ 313